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From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Oleksandr Ocheretnyi <oocheret@cisco.com>
Cc: tudor.ambarus@microchip.com, miquel.raynal@bootlin.com,
	p.yadav@ti.com, michael@walle.cc, richard@nod.at,
	vigneshr@ti.com, broonie@kernel.org,
	linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
	mauro.lima@eclypsium.com, lee.jones@linaro.org,
	linux-kernel@vger.kernel.org, xe-linux-external@cisco.com
Subject: Re: [PATCH v2] mtd: spi-nor: handle unsupported FSR opcodes properly
Date: Thu, 16 Jun 2022 08:31:04 +0300	[thread overview]
Message-ID: <YqrAGKLUazeNH1XK@lahna> (raw)
In-Reply-To: <20220615191153.3017939-1-oocheret@cisco.com>

On Wed, Jun 15, 2022 at 12:11:53PM -0700, Oleksandr Ocheretnyi wrote:
> Originally commit 094d3b9 ("mtd: spi-nor: Add USE_FSR flag for n25q*
> entries") and following one 8f93826 ("mtd: spi-nor: micron-st: convert
> USE_FSR to a manufacturer flag") enabled SPINOR_OP_RDFSR opcode handling
> ability, however some controller drivers still cannot handle it properly
> in the micron_st_nor_ready() call what breaks some mtd callbacks with
> next error logs:
> 
> mtdblock: erase of region [address1, size1] on "BIOS" failed
> mtdblock: erase of region [address2, size2] on "BIOS" failed
> 
> The Intel SPI controller does not support low level operations, like
> reading the flag status register (FSR). It only exposes a set of high
> level operations for software to use. For this reason check the return
> value of micron_st_nor_read_fsr() and if the operation was not
> supported, use the status register value only. This allows the chip to
> work even when attached to Intel SPI controller (there are such systems
> out there).
> 
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>

I don't think I signed this off.

> Signed-off-by: Oleksandr Ocheretnyi <oocheret@cisco.com>
> Link: https://lore.kernel.org/lkml/YmZUCIE%2FND82BlNh@lahna/
> ---

What changed between v1 and v2? And did you take into consideration the
comments I gave?

______________________________________________________
Linux MTD discussion mailing list
http://lists.infradead.org/mailman/listinfo/linux-mtd/

WARNING: multiple messages have this Message-ID (diff)
From: Mika Westerberg <mika.westerberg@linux.intel.com>
To: Oleksandr Ocheretnyi <oocheret@cisco.com>
Cc: tudor.ambarus@microchip.com, miquel.raynal@bootlin.com,
	p.yadav@ti.com, michael@walle.cc, richard@nod.at,
	vigneshr@ti.com, broonie@kernel.org,
	linux-mtd@lists.infradead.org, linux-spi@vger.kernel.org,
	mauro.lima@eclypsium.com, lee.jones@linaro.org,
	linux-kernel@vger.kernel.org, xe-linux-external@cisco.com
Subject: Re: [PATCH v2] mtd: spi-nor: handle unsupported FSR opcodes properly
Date: Thu, 16 Jun 2022 08:31:04 +0300	[thread overview]
Message-ID: <YqrAGKLUazeNH1XK@lahna> (raw)
In-Reply-To: <20220615191153.3017939-1-oocheret@cisco.com>

On Wed, Jun 15, 2022 at 12:11:53PM -0700, Oleksandr Ocheretnyi wrote:
> Originally commit 094d3b9 ("mtd: spi-nor: Add USE_FSR flag for n25q*
> entries") and following one 8f93826 ("mtd: spi-nor: micron-st: convert
> USE_FSR to a manufacturer flag") enabled SPINOR_OP_RDFSR opcode handling
> ability, however some controller drivers still cannot handle it properly
> in the micron_st_nor_ready() call what breaks some mtd callbacks with
> next error logs:
> 
> mtdblock: erase of region [address1, size1] on "BIOS" failed
> mtdblock: erase of region [address2, size2] on "BIOS" failed
> 
> The Intel SPI controller does not support low level operations, like
> reading the flag status register (FSR). It only exposes a set of high
> level operations for software to use. For this reason check the return
> value of micron_st_nor_read_fsr() and if the operation was not
> supported, use the status register value only. This allows the chip to
> work even when attached to Intel SPI controller (there are such systems
> out there).
> 
> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>

I don't think I signed this off.

> Signed-off-by: Oleksandr Ocheretnyi <oocheret@cisco.com>
> Link: https://lore.kernel.org/lkml/YmZUCIE%2FND82BlNh@lahna/
> ---

What changed between v1 and v2? And did you take into consideration the
comments I gave?

  parent reply	other threads:[~2022-06-16  5:31 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <BYAPR11MB27570C5DC510D0F37FC106E4CDF69@BYAPR11MB2757.namprd11.prod.outlook.com>
2022-04-25  7:55 ` mtd: spi-nor: fatal issue during the mtd_erase() calls mika.westerberg
2022-04-25  7:55   ` mika.westerberg
2022-06-10 19:15   ` [PATCH] mtd: spi-nor: handle unsupported FSR opcodes properly Oleksandr Ocheretnyi
2022-06-10 19:15     ` Oleksandr Ocheretnyi
2022-06-13  6:18     ` Mika Westerberg
2022-06-13  6:18       ` Mika Westerberg
     [not found]       ` <BYAPR11MB27570F2863F7BCDFE629B3DFCDAA9@BYAPR11MB2757.namprd11.prod.outlook.com>
2022-06-15  9:49         ` Mika Westerberg
2022-06-15  9:49           ` Mika Westerberg
2022-06-15 18:10           ` Michael Walle
2022-06-15 18:10             ` Michael Walle
2022-06-15 19:11             ` [PATCH v2] " Oleksandr Ocheretnyi
2022-06-15 19:11               ` Oleksandr Ocheretnyi
2022-06-15 19:25               ` Mark Brown
2022-06-15 19:25                 ` Mark Brown
2022-06-16  5:31               ` Mika Westerberg [this message]
2022-06-16  5:31                 ` Mika Westerberg
     [not found]                 ` <BYAPR11MB2757B1146457E3860389F4D1CDAC9@BYAPR11MB2757.namprd11.prod.outlook.com>
2022-06-16 10:35                   ` Mika Westerberg
2022-06-16 10:35                     ` Mika Westerberg
2022-06-16 12:14                     ` Oleksandr Ocheretnyi
2022-06-16 12:14                       ` Oleksandr Ocheretnyi
2022-06-16 12:33                       ` Mika Westerberg
2022-06-16 12:33                         ` Mika Westerberg
     [not found]                         ` <BYAPR11MB2757CEBE99C3A0861928CD43CDAC9@BYAPR11MB2757.namprd11.prod.outlook.com>
2022-06-16 12:59                           ` Mika Westerberg
2022-06-16 12:59                             ` Mika Westerberg
     [not found]                             ` <BYAPR11MB2757BD90C63B9F6A31E0600ACDAC9@BYAPR11MB2757.namprd11.prod.outlook.com>
2022-06-17  5:04                               ` Mika Westerberg
2022-06-17  5:04                                 ` Mika Westerberg
2022-07-19  9:12                     ` Tudor.Ambarus
2022-07-19  9:12                       ` Tudor.Ambarus
2022-06-16  5:29             ` [PATCH] " Mika Westerberg
2022-06-16  5:29               ` Mika Westerberg

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