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From: Andi Shyti <andi.shyti@linux.intel.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: mauro.chehab@linux.intel.com,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	"David Airlie" <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	"Chris Wilson" <chris.p.wilson@intel.com>,
	"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Dave Airlie" <airlied@redhat.com>,
	stable@vger.kernel.org, intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH 4/6] drm/i915/gt: Only invalidate TLBs exposed to user manipulation
Date: Thu, 23 Jun 2022 13:13:56 +0200	[thread overview]
Message-ID: <YrRK9Gaf/G4AXwYn@intel.intel> (raw)
In-Reply-To: <387b9a8d3e719ad2db4fce56c0bfc0f909fd6df6.1655306128.git.mchehab@kernel.org>

Hi Mauro,

On Wed, Jun 15, 2022 at 04:27:38PM +0100, Mauro Carvalho Chehab wrote:
> From: Chris Wilson <chris.p.wilson@intel.com>
> 
> Don't flush TLBs when the buffer is only used in the GGTT under full
> control of the kernel, as there's no risk of of concurrent access
> and stale access from prefetch.
> 
> We only need to invalidate the TLB if they are accessible by the user.
> 
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
> 
> Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
> Cc: Fei Yang <fei.yang@intel.com>
> Cc: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: stable@vger.kernel.org
> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Thanks,
Andi

WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "Chris Wilson" <chris.p.wilson@intel.com>,
	"Fei Yang" <fei.yang@intel.com>,
	"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
	"Daniel Vetter" <daniel@ffwll.ch>,
	"Dave Airlie" <airlied@redhat.com>,
	"David Airlie" <airlied@linux.ie>,
	"Jani Nikula" <jani.nikula@linux.intel.com>,
	"Joonas Lahtinen" <joonas.lahtinen@linux.intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
	dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
	linux-kernel@vger.kernel.org, mauro.chehab@linux.intel.com,
	"Andi Shyti" <andi.shyti@linux.intel.com>,
	stable@vger.kernel.org,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>
Subject: Re: [PATCH 4/6] drm/i915/gt: Only invalidate TLBs exposed to user manipulation
Date: Thu, 23 Jun 2022 13:13:56 +0200	[thread overview]
Message-ID: <YrRK9Gaf/G4AXwYn@intel.intel> (raw)
In-Reply-To: <387b9a8d3e719ad2db4fce56c0bfc0f909fd6df6.1655306128.git.mchehab@kernel.org>

Hi Mauro,

On Wed, Jun 15, 2022 at 04:27:38PM +0100, Mauro Carvalho Chehab wrote:
> From: Chris Wilson <chris.p.wilson@intel.com>
> 
> Don't flush TLBs when the buffer is only used in the GGTT under full
> control of the kernel, as there's no risk of of concurrent access
> and stale access from prefetch.
> 
> We only need to invalidate the TLB if they are accessible by the user.
> 
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
> 
> Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
> Cc: Fei Yang <fei.yang@intel.com>
> Cc: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: stable@vger.kernel.org
> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Thanks,
Andi

WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Mauro Carvalho Chehab <mchehab@kernel.org>
Cc: "Tvrtko Ursulin" <tvrtko.ursulin@linux.intel.com>,
	mauro.chehab@linux.intel.com, "Fei Yang" <fei.yang@intel.com>,
	"Thomas Hellström" <thomas.hellstrom@linux.intel.com>,
	"David Airlie" <airlied@linux.ie>,
	dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
	"Chris Wilson" <chris.p.wilson@intel.com>,
	"Thomas Hellstrom" <thomas.hellstrom@intel.com>,
	"Rodrigo Vivi" <rodrigo.vivi@intel.com>,
	"Andi Shyti" <andi.shyti@linux.intel.com>,
	"Dave Airlie" <airlied@redhat.com>,
	stable@vger.kernel.org, intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH 4/6] drm/i915/gt: Only invalidate TLBs exposed to user manipulation
Date: Thu, 23 Jun 2022 13:13:56 +0200	[thread overview]
Message-ID: <YrRK9Gaf/G4AXwYn@intel.intel> (raw)
In-Reply-To: <387b9a8d3e719ad2db4fce56c0bfc0f909fd6df6.1655306128.git.mchehab@kernel.org>

Hi Mauro,

On Wed, Jun 15, 2022 at 04:27:38PM +0100, Mauro Carvalho Chehab wrote:
> From: Chris Wilson <chris.p.wilson@intel.com>
> 
> Don't flush TLBs when the buffer is only used in the GGTT under full
> control of the kernel, as there's no risk of of concurrent access
> and stale access from prefetch.
> 
> We only need to invalidate the TLB if they are accessible by the user.
> 
> Fixes: 7938d61591d3 ("drm/i915: Flush TLBs before releasing backing store")
> 
> Signed-off-by: Chris Wilson <chris.p.wilson@intel.com>
> Cc: Fei Yang <fei.yang@intel.com>
> Cc: Andi Shyti <andi.shyti@linux.intel.com>
> Cc: stable@vger.kernel.org
> Acked-by: Thomas Hellström <thomas.hellstrom@linux.intel.com>
> Signed-off-by: Mauro Carvalho Chehab <mchehab@kernel.org>

Reviewed-by: Andi Shyti <andi.shyti@linux.intel.com>

Thanks,
Andi

  parent reply	other threads:[~2022-06-23 11:14 UTC|newest]

Thread overview: 87+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-06-15 15:27 [Intel-gfx] [PATCH 0/6] Fix TLB invalidate issues with Broadwell Mauro Carvalho Chehab
2022-06-15 15:27 ` Mauro Carvalho Chehab
2022-06-15 15:27 ` Mauro Carvalho Chehab
2022-06-15 15:27 ` [Intel-gfx] [PATCH 1/6] drm/i915/gt: Ignore TLB invalidations on idle engines Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-16  7:21   ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:21     ` Tvrtko Ursulin
2022-06-16  7:21     ` Tvrtko Ursulin
2022-06-23 11:04   ` [Intel-gfx] " Andi Shyti
2022-06-23 11:04     ` Andi Shyti
2022-06-23 11:04     ` Andi Shyti
2022-06-15 15:27 ` [Intel-gfx] [PATCH 2/6] drm/i915/gt: Invalidate TLB of the OA unit at TLB invalidations Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 17:03   ` [Intel-gfx] " Umesh Nerlige Ramappa
2022-06-15 17:03     ` Umesh Nerlige Ramappa
2022-06-23 11:07   ` Andi Shyti
2022-06-23 11:07     ` Andi Shyti
2022-06-23 11:07     ` Andi Shyti
2022-06-15 15:27 ` [Intel-gfx] [PATCH 3/6] drm/i915/gt: Skip TLB invalidations once wedged Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-16  7:25   ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:25     ` Tvrtko Ursulin
2022-06-16  7:25     ` Tvrtko Ursulin
2022-06-23 11:08   ` [Intel-gfx] " Andi Shyti
2022-06-23 11:08     ` Andi Shyti
2022-06-23 11:08     ` Andi Shyti
2022-06-15 15:27 ` [Intel-gfx] [PATCH 4/6] drm/i915/gt: Only invalidate TLBs exposed to user manipulation Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-16  7:33   ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:33     ` Tvrtko Ursulin
2022-06-16  7:33     ` Tvrtko Ursulin
2022-06-23 11:13   ` Andi Shyti [this message]
2022-06-23 11:13     ` Andi Shyti
2022-06-23 11:13     ` Andi Shyti
2022-06-15 15:27 ` [Intel-gfx] [PATCH 5/6] drm/i915/gt: Serialize GRDOM access between multiple engine resets Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-16  7:35   ` [Intel-gfx] " Tvrtko Ursulin
2022-06-16  7:35     ` Tvrtko Ursulin
2022-06-16  7:35     ` Tvrtko Ursulin
2022-06-23 11:17   ` [Intel-gfx] " Andi Shyti
2022-06-23 11:17     ` Andi Shyti
2022-06-23 11:17     ` Andi Shyti
2022-06-24  8:34     ` [Intel-gfx] " Tvrtko Ursulin
2022-06-24  8:34       ` Tvrtko Ursulin
2022-06-24  8:34       ` Tvrtko Ursulin
2022-06-27  9:00       ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-27  9:00         ` Mauro Carvalho Chehab
2022-06-27  9:00         ` Mauro Carvalho Chehab
2022-06-28 15:49         ` [Intel-gfx] " Tvrtko Ursulin
2022-06-28 15:49           ` Tvrtko Ursulin
2022-06-28 15:49           ` Tvrtko Ursulin
2022-06-29 15:30           ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-29 15:30             ` Mauro Carvalho Chehab
2022-06-29 15:30             ` Mauro Carvalho Chehab
2022-06-29 16:02             ` [Intel-gfx] " Tvrtko Ursulin
2022-06-29 16:02               ` Tvrtko Ursulin
2022-06-29 16:02               ` Tvrtko Ursulin
2022-06-30  7:32               ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-30  7:32                 ` Mauro Carvalho Chehab
2022-06-30  7:32                 ` Mauro Carvalho Chehab
2022-06-30  8:12                 ` [Intel-gfx] " Tvrtko Ursulin
2022-06-30  8:12                   ` Tvrtko Ursulin
2022-06-30  8:12                   ` Tvrtko Ursulin
2022-06-30 16:01                   ` [Intel-gfx] " Mauro Carvalho Chehab
2022-06-30 16:01                     ` Mauro Carvalho Chehab
2022-06-30 16:01                     ` Mauro Carvalho Chehab
2022-07-01  7:56                     ` [Intel-gfx] " Tvrtko Ursulin
2022-07-01  7:56                       ` Tvrtko Ursulin
2022-07-01  7:56                       ` Tvrtko Ursulin
2022-07-04  8:42                       ` [Intel-gfx] " Mauro Carvalho Chehab
2022-07-04  8:42                         ` Mauro Carvalho Chehab
2022-07-04  8:42                         ` Mauro Carvalho Chehab
2022-06-15 15:27 ` [Intel-gfx] [PATCH 6/6] drm/i915/gt: Serialize TLB invalidates with GT resets Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-15 15:27   ` Mauro Carvalho Chehab
2022-06-23 11:18   ` [Intel-gfx] " Andi Shyti
2022-06-23 11:18     ` Andi Shyti
2022-06-23 11:18     ` Andi Shyti
2022-06-15 17:26 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Fix TLB invalidate issues with Broadwell Patchwork
2022-06-15 17:26 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-06-15 17:48 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-06-15 23:45 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork

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