From: Greg KH <gregkh@linuxfoundation.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>,
Conor Dooley <Conor.Dooley@microchip.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Daire.McNamara@microchip.com,
Niklas Cassel <niklas.cassel@wdc.com>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>,
Zong Li <zong.li@sifive.com>,
Emil Renner Berthing <kernel@esmil.dk>,
hahnjo@hahnjo.de, Guo Ren <guoren@kernel.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
changbin.du@intel.com, Heiko Stuebner <heiko@sntech.de>,
philipp.tomsich@vrull.eu, Rob Herring <robh@kernel.org>,
Marc Zyngier <maz@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Brice.Goglin@inria.fr
Subject: Re: [RFC 2/4] arch-topology: add a default implementation of store_cpu_topology()
Date: Fri, 8 Jul 2022 12:03:41 +0200 [thread overview]
Message-ID: <YsgA/eycDF9TgCIT@kroah.com> (raw)
In-Reply-To: <20220708094710.rxk6flrueegdsggr@bogus>
On Fri, Jul 08, 2022 at 10:47:10AM +0100, Sudeep Holla wrote:
> On Fri, Jul 08, 2022 at 11:28:19AM +0200, Geert Uytterhoeven wrote:
> > Hi Sudeep,
> >
> > On Fri, Jul 8, 2022 at 11:22 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
> > > On Fri, Jul 08, 2022 at 08:35:57AM +0000, Conor.Dooley@microchip.com wrote:
> > > > On 08/07/2022 09:24, Sudeep Holla wrote:
> > > > > On Thu, Jul 07, 2022 at 11:04:35PM +0100, Conor Dooley wrote:
> > > > >> From: Conor Dooley <conor.dooley@microchip.com>
> > > > >>
> > > > >> RISC-V & arm64 both use an almost identical method of filling in
> > > > >> default vales for arch topology. Create a weakly defined default
> > > > >> implementation with the intent of migrating both archs to use it.
> > > > >>
> > > > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > > > >> ---
> > > > >> drivers/base/arch_topology.c | 19 +++++++++++++++++++
> > > > >> include/linux/arch_topology.h | 1 +
> > > > >> 2 files changed, 20 insertions(+)
> > > > >>
> > > > >> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> > > > >> index 441e14ac33a4..07e84c6ac5c2 100644
> > > > >> --- a/drivers/base/arch_topology.c
> > > > >> +++ b/drivers/base/arch_topology.c
> > > > >> @@ -765,6 +765,25 @@ void update_siblings_masks(unsigned int cpuid)
> > > > >> }
> > > > >> }
> > > > >>
> > > > >> +void __weak store_cpu_topology(unsigned int cpuid)
> > > >
> > > > Does using __weak here make sense to you?
> > > >
> > >
> > > I don't want any weak definition and arch to override as we know only
> > > arm64 and RISC-V are the only users and they are aligned to have same
> > > implementation. So weak definition doesn't make sense to me.
> > >
> > > > >
> > > > > I prefer to have this as default implementation. So just get the risc-v
> > > > > one pushed to upstream first(for v5.20) and get all the backports if required.
> > > > > Next cycle(i.e. v5.21), you can move both RISC-V and arm64.
> > > > >
> > > >
> > > > Yeah, that was my intention. I meant to label patch 1/4 as "PATCH"
> > > > and (2,3,4)/4 as RFC but forgot. I talked with Palmer about doing
> > > > the risc-v impl. and then migrate both on IRC & he seemed happy with
> > > > it.
> > > >
> > >
> > > Ah OK, good.
> > >
> > > > If you're okay with patch 1/4, I'll resubmit it as a standalone v2.
> > > >
> > >
> > > That would be great, thanks. You can most the code to move to generic from
> > > both arm64 and risc-v once we have this in v5.20-rc1
> >
> > Why not ignore risc-v for now, and move the arm64 implementation to
> > the generic code for v5.20, so every arch will have it at once?
> >
>
> We could but,
> 1. This arch_topology is new and has been going through lot of changes
> recently and having code there might make it difficult to backport
> changes that are required for RISC-V(my guess)
Worry about future issues in the future. Make it simple now as you know
what you are dealing with at the moment.
thanks,
greg k-h
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Greg KH <gregkh@linuxfoundation.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>,
Conor Dooley <Conor.Dooley@microchip.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Daire.McNamara@microchip.com,
Niklas Cassel <niklas.cassel@wdc.com>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>,
Zong Li <zong.li@sifive.com>,
Emil Renner Berthing <kernel@esmil.dk>,
hahnjo@hahnjo.de, Guo Ren <guoren@kernel.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
changbin.du@intel.com, Heiko Stuebner <heiko@sntech.de>,
philipp.tomsich@vrull.eu, Rob Herring <robh@kernel.org>,
Marc Zyngier <maz@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Brice.Goglin@inria.fr
Subject: Re: [RFC 2/4] arch-topology: add a default implementation of store_cpu_topology()
Date: Fri, 8 Jul 2022 12:03:41 +0200 [thread overview]
Message-ID: <YsgA/eycDF9TgCIT@kroah.com> (raw)
In-Reply-To: <20220708094710.rxk6flrueegdsggr@bogus>
On Fri, Jul 08, 2022 at 10:47:10AM +0100, Sudeep Holla wrote:
> On Fri, Jul 08, 2022 at 11:28:19AM +0200, Geert Uytterhoeven wrote:
> > Hi Sudeep,
> >
> > On Fri, Jul 8, 2022 at 11:22 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
> > > On Fri, Jul 08, 2022 at 08:35:57AM +0000, Conor.Dooley@microchip.com wrote:
> > > > On 08/07/2022 09:24, Sudeep Holla wrote:
> > > > > On Thu, Jul 07, 2022 at 11:04:35PM +0100, Conor Dooley wrote:
> > > > >> From: Conor Dooley <conor.dooley@microchip.com>
> > > > >>
> > > > >> RISC-V & arm64 both use an almost identical method of filling in
> > > > >> default vales for arch topology. Create a weakly defined default
> > > > >> implementation with the intent of migrating both archs to use it.
> > > > >>
> > > > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > > > >> ---
> > > > >> drivers/base/arch_topology.c | 19 +++++++++++++++++++
> > > > >> include/linux/arch_topology.h | 1 +
> > > > >> 2 files changed, 20 insertions(+)
> > > > >>
> > > > >> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> > > > >> index 441e14ac33a4..07e84c6ac5c2 100644
> > > > >> --- a/drivers/base/arch_topology.c
> > > > >> +++ b/drivers/base/arch_topology.c
> > > > >> @@ -765,6 +765,25 @@ void update_siblings_masks(unsigned int cpuid)
> > > > >> }
> > > > >> }
> > > > >>
> > > > >> +void __weak store_cpu_topology(unsigned int cpuid)
> > > >
> > > > Does using __weak here make sense to you?
> > > >
> > >
> > > I don't want any weak definition and arch to override as we know only
> > > arm64 and RISC-V are the only users and they are aligned to have same
> > > implementation. So weak definition doesn't make sense to me.
> > >
> > > > >
> > > > > I prefer to have this as default implementation. So just get the risc-v
> > > > > one pushed to upstream first(for v5.20) and get all the backports if required.
> > > > > Next cycle(i.e. v5.21), you can move both RISC-V and arm64.
> > > > >
> > > >
> > > > Yeah, that was my intention. I meant to label patch 1/4 as "PATCH"
> > > > and (2,3,4)/4 as RFC but forgot. I talked with Palmer about doing
> > > > the risc-v impl. and then migrate both on IRC & he seemed happy with
> > > > it.
> > > >
> > >
> > > Ah OK, good.
> > >
> > > > If you're okay with patch 1/4, I'll resubmit it as a standalone v2.
> > > >
> > >
> > > That would be great, thanks. You can most the code to move to generic from
> > > both arm64 and risc-v once we have this in v5.20-rc1
> >
> > Why not ignore risc-v for now, and move the arm64 implementation to
> > the generic code for v5.20, so every arch will have it at once?
> >
>
> We could but,
> 1. This arch_topology is new and has been going through lot of changes
> recently and having code there might make it difficult to backport
> changes that are required for RISC-V(my guess)
Worry about future issues in the future. Make it simple now as you know
what you are dealing with at the moment.
thanks,
greg k-h
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
WARNING: multiple messages have this Message-ID (diff)
From: Greg KH <gregkh@linuxfoundation.org>
To: Sudeep Holla <sudeep.holla@arm.com>
Cc: Geert Uytterhoeven <geert@linux-m68k.org>,
Conor Dooley <Conor.Dooley@microchip.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Palmer Dabbelt <palmer@rivosinc.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Daire.McNamara@microchip.com,
Niklas Cassel <niklas.cassel@wdc.com>,
Damien Le Moal <damien.lemoal@opensource.wdc.com>,
Zong Li <zong.li@sifive.com>,
Emil Renner Berthing <kernel@esmil.dk>,
hahnjo@hahnjo.de, Guo Ren <guoren@kernel.org>,
Anup Patel <anup@brainfault.org>,
Atish Patra <atishp@atishpatra.org>,
changbin.du@intel.com, Heiko Stuebner <heiko@sntech.de>,
philipp.tomsich@vrull.eu, Rob Herring <robh@kernel.org>,
Marc Zyngier <maz@kernel.org>,
Viresh Kumar <viresh.kumar@linaro.org>,
linux-riscv <linux-riscv@lists.infradead.org>,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
Linux ARM <linux-arm-kernel@lists.infradead.org>,
Brice.Goglin@inria.fr
Subject: Re: [RFC 2/4] arch-topology: add a default implementation of store_cpu_topology()
Date: Fri, 8 Jul 2022 12:03:41 +0200 [thread overview]
Message-ID: <YsgA/eycDF9TgCIT@kroah.com> (raw)
In-Reply-To: <20220708094710.rxk6flrueegdsggr@bogus>
On Fri, Jul 08, 2022 at 10:47:10AM +0100, Sudeep Holla wrote:
> On Fri, Jul 08, 2022 at 11:28:19AM +0200, Geert Uytterhoeven wrote:
> > Hi Sudeep,
> >
> > On Fri, Jul 8, 2022 at 11:22 AM Sudeep Holla <sudeep.holla@arm.com> wrote:
> > > On Fri, Jul 08, 2022 at 08:35:57AM +0000, Conor.Dooley@microchip.com wrote:
> > > > On 08/07/2022 09:24, Sudeep Holla wrote:
> > > > > On Thu, Jul 07, 2022 at 11:04:35PM +0100, Conor Dooley wrote:
> > > > >> From: Conor Dooley <conor.dooley@microchip.com>
> > > > >>
> > > > >> RISC-V & arm64 both use an almost identical method of filling in
> > > > >> default vales for arch topology. Create a weakly defined default
> > > > >> implementation with the intent of migrating both archs to use it.
> > > > >>
> > > > >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > > > >> ---
> > > > >> drivers/base/arch_topology.c | 19 +++++++++++++++++++
> > > > >> include/linux/arch_topology.h | 1 +
> > > > >> 2 files changed, 20 insertions(+)
> > > > >>
> > > > >> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> > > > >> index 441e14ac33a4..07e84c6ac5c2 100644
> > > > >> --- a/drivers/base/arch_topology.c
> > > > >> +++ b/drivers/base/arch_topology.c
> > > > >> @@ -765,6 +765,25 @@ void update_siblings_masks(unsigned int cpuid)
> > > > >> }
> > > > >> }
> > > > >>
> > > > >> +void __weak store_cpu_topology(unsigned int cpuid)
> > > >
> > > > Does using __weak here make sense to you?
> > > >
> > >
> > > I don't want any weak definition and arch to override as we know only
> > > arm64 and RISC-V are the only users and they are aligned to have same
> > > implementation. So weak definition doesn't make sense to me.
> > >
> > > > >
> > > > > I prefer to have this as default implementation. So just get the risc-v
> > > > > one pushed to upstream first(for v5.20) and get all the backports if required.
> > > > > Next cycle(i.e. v5.21), you can move both RISC-V and arm64.
> > > > >
> > > >
> > > > Yeah, that was my intention. I meant to label patch 1/4 as "PATCH"
> > > > and (2,3,4)/4 as RFC but forgot. I talked with Palmer about doing
> > > > the risc-v impl. and then migrate both on IRC & he seemed happy with
> > > > it.
> > > >
> > >
> > > Ah OK, good.
> > >
> > > > If you're okay with patch 1/4, I'll resubmit it as a standalone v2.
> > > >
> > >
> > > That would be great, thanks. You can most the code to move to generic from
> > > both arm64 and risc-v once we have this in v5.20-rc1
> >
> > Why not ignore risc-v for now, and move the arm64 implementation to
> > the generic code for v5.20, so every arch will have it at once?
> >
>
> We could but,
> 1. This arch_topology is new and has been going through lot of changes
> recently and having code there might make it difficult to backport
> changes that are required for RISC-V(my guess)
Worry about future issues in the future. Make it simple now as you know
what you are dealing with at the moment.
thanks,
greg k-h
next prev parent reply other threads:[~2022-07-08 10:04 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-07-07 22:04 [PATCH/RFC 0/4] Fix RISC-V's arch-topology reporting Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-07 22:04 ` [RFC 1/4] riscv: arch-topology: fix default topology reporting Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-07 22:04 ` [RFC 2/4] arch-topology: add a default implementation of store_cpu_topology() Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-08 8:24 ` Sudeep Holla
2022-07-08 8:24 ` Sudeep Holla
2022-07-08 8:24 ` Sudeep Holla
2022-07-08 8:35 ` Conor.Dooley
2022-07-08 8:35 ` Conor.Dooley
2022-07-08 8:35 ` Conor.Dooley
2022-07-08 9:21 ` Sudeep Holla
2022-07-08 9:21 ` Sudeep Holla
2022-07-08 9:21 ` Sudeep Holla
2022-07-08 9:28 ` Geert Uytterhoeven
2022-07-08 9:28 ` Geert Uytterhoeven
2022-07-08 9:28 ` Geert Uytterhoeven
2022-07-08 9:47 ` Sudeep Holla
2022-07-08 9:47 ` Sudeep Holla
2022-07-08 9:47 ` Sudeep Holla
2022-07-08 10:03 ` Greg KH [this message]
2022-07-08 10:03 ` Greg KH
2022-07-08 10:03 ` Greg KH
2022-07-08 11:39 ` Sudeep Holla
2022-07-08 11:39 ` Sudeep Holla
2022-07-08 11:39 ` Sudeep Holla
2022-07-08 11:57 ` Conor.Dooley
2022-07-08 11:57 ` Conor.Dooley
2022-07-08 11:57 ` Conor.Dooley
2022-07-08 13:59 ` Sudeep Holla
2022-07-08 13:59 ` Sudeep Holla
2022-07-08 13:59 ` Sudeep Holla
2022-07-08 10:02 ` Conor.Dooley
2022-07-08 10:02 ` Conor.Dooley
2022-07-08 10:02 ` Conor.Dooley
2022-07-07 22:04 ` [RFC 3/4] riscv: arch-topology: move riscv to the generic store_cpu_topology() Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-07 22:04 ` [RFC 4/4] arm64: arch-topology move arm64 " Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-07 22:04 ` Conor Dooley
2022-07-07 22:06 ` [PATCH/RFC 0/4] Fix RISC-V's arch-topology reporting Conor.Dooley
2022-07-07 22:06 ` Conor.Dooley
2022-07-07 22:06 ` Conor.Dooley
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