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From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Conor.Dooley@microchip.com
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	palmer@rivosinc.com, aou@eecs.berkeley.edu, sudeep.holla@arm.com,
	catalin.marinas@arm.com, will@kernel.org,
	gregkh@linuxfoundation.org, rafael@kernel.org, arnd@arndb.de,
	Daire.McNamara@microchip.com, niklas.cassel@wdc.com,
	damien.lemoal@opensource.wdc.com, geert@linux-m68k.org,
	zong.li@sifive.com, kernel@esmil.dk, hahnjo@hahnjo.de,
	guoren@kernel.org, anup@brainfault.org, atishp@atishpatra.org,
	heiko@sntech.de, philipp.tomsich@vrull.eu, robh@kernel.org,
	maz@kernel.org, viresh.kumar@linaro.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, Brice.Goglin@inria.fr
Subject: Re: [PATCH v2 1/2] arm64: topology: move store_cpu_topology() to shared code
Date: Sat, 9 Jul 2022 20:50:17 +0100	[thread overview]
Message-ID: <Ysnb+VNniRBF1Hh0@shell.armlinux.org.uk> (raw)
In-Reply-To: <efa89122-b428-7691-49d3-f5867206f05a@microchip.com>

On Sat, Jul 09, 2022 at 12:58:57PM +0000, Conor.Dooley@microchip.com wrote:
> +CC Russel, Arnd
> 
> On 08/07/2022 21:45, Conor Dooley - M52691 wrote:
> > On 08/07/2022 21:33, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> arm64's method of defining a default cpu topology requires only minimal
> >> changes to apply to RISC-V also. The current arm64 implementation exits
> >> early in a uniprocessor configuration by reading MPIDR & claiming that
> >> uniprocessor can rely on the default values.
> >>
> >> This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64:
> >> topology: Stop using MPIDR for topology information")', because the
> >> current code just assigns default values for multiprocessor systems.
> >>
> >> With the MPIDR references removed, store_cpu_topolgy() can be moved to
> >> the common arch_topology code.
> >>
> >> CC: stable@vger.kernel.org
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> ---8<---
> >>  #ifdef CONFIG_ACPI
> >>  static bool __init acpi_cpu_is_threaded(int cpu)
> >>  {
> >> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> >> index 441e14ac33a4..07e84c6ac5c2 100644
> >> --- a/drivers/base/arch_topology.c
> >> +++ b/drivers/base/arch_topology.c
> >> @@ -765,6 +765,25 @@ void update_siblings_masks(unsigned int cpuid)
> >>  	}
> >>  }
> >>  
> >> +void __weak store_cpu_topology(unsigned int cpuid)
> > 
> > Ahh crap, I forgot to remove the __weak.
> > I won't immediately respin since it is minor. I've pushed it (without
> > the __weak) to https://git.kernel.org/conor/h/arch-topo so it'll get
> > the lkp coverage.
> 
> And build failure for arm32:
> 
> > tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git arch-topo
> > branch HEAD: df379c4b12f6b22fb8c07c2be16fd821a4fcbfc5  riscv: topology: fix default topology reporting
> > 
> > Error/Warning: (recently discovered and may have been fixed)
> > 
> > arch_topology.c:(.text+0xbac): multiple definition of `store_cpu_topology'; arch/arm/kernel/topology.o:topology.c:(.text+0x0): first defined here
> > 
> > Error/Warning ids grouped by kconfigs:
> > 
> > gcc_recent_errors
> > `-- arm-defconfig
> >     `-- multiple-definition-of-store_cpu_topology-arch-arm-kernel-topology.o:topology.c:(.text):first-defined-here
> > 
> > elapsed time: 721m
> 
> Looking at the arm32 implementation - it appears to be mostly the sort of MPIDR
> stuff that was removed from the arm64 implementation in 3102bc0e6ac7 ("arm64:
> topology: Stop using MPIDR for topology information"). Could arm32 benefit from
> the same shared implemenation too, or is usage of MPIDR only invalid for arm64?

Don't look at me... this code was contributed by Linaro, presumably for
systems they have. I've never had anything that would require this so
the code never interested me, so I never took much notice of it.

Sorry, I can't be of more help.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Conor.Dooley@microchip.com
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	palmer@rivosinc.com, aou@eecs.berkeley.edu, sudeep.holla@arm.com,
	catalin.marinas@arm.com, will@kernel.org,
	gregkh@linuxfoundation.org, rafael@kernel.org, arnd@arndb.de,
	Daire.McNamara@microchip.com, niklas.cassel@wdc.com,
	damien.lemoal@opensource.wdc.com, geert@linux-m68k.org,
	zong.li@sifive.com, kernel@esmil.dk, hahnjo@hahnjo.de,
	guoren@kernel.org, anup@brainfault.org, atishp@atishpatra.org,
	heiko@sntech.de, philipp.tomsich@vrull.eu, robh@kernel.org,
	maz@kernel.org, viresh.kumar@linaro.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, Brice.Goglin@inria.fr
Subject: Re: [PATCH v2 1/2] arm64: topology: move store_cpu_topology() to shared code
Date: Sat, 9 Jul 2022 20:50:17 +0100	[thread overview]
Message-ID: <Ysnb+VNniRBF1Hh0@shell.armlinux.org.uk> (raw)
In-Reply-To: <efa89122-b428-7691-49d3-f5867206f05a@microchip.com>

On Sat, Jul 09, 2022 at 12:58:57PM +0000, Conor.Dooley@microchip.com wrote:
> +CC Russel, Arnd
> 
> On 08/07/2022 21:45, Conor Dooley - M52691 wrote:
> > On 08/07/2022 21:33, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> arm64's method of defining a default cpu topology requires only minimal
> >> changes to apply to RISC-V also. The current arm64 implementation exits
> >> early in a uniprocessor configuration by reading MPIDR & claiming that
> >> uniprocessor can rely on the default values.
> >>
> >> This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64:
> >> topology: Stop using MPIDR for topology information")', because the
> >> current code just assigns default values for multiprocessor systems.
> >>
> >> With the MPIDR references removed, store_cpu_topolgy() can be moved to
> >> the common arch_topology code.
> >>
> >> CC: stable@vger.kernel.org
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> ---8<---
> >>  #ifdef CONFIG_ACPI
> >>  static bool __init acpi_cpu_is_threaded(int cpu)
> >>  {
> >> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> >> index 441e14ac33a4..07e84c6ac5c2 100644
> >> --- a/drivers/base/arch_topology.c
> >> +++ b/drivers/base/arch_topology.c
> >> @@ -765,6 +765,25 @@ void update_siblings_masks(unsigned int cpuid)
> >>  	}
> >>  }
> >>  
> >> +void __weak store_cpu_topology(unsigned int cpuid)
> > 
> > Ahh crap, I forgot to remove the __weak.
> > I won't immediately respin since it is minor. I've pushed it (without
> > the __weak) to https://git.kernel.org/conor/h/arch-topo so it'll get
> > the lkp coverage.
> 
> And build failure for arm32:
> 
> > tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git arch-topo
> > branch HEAD: df379c4b12f6b22fb8c07c2be16fd821a4fcbfc5  riscv: topology: fix default topology reporting
> > 
> > Error/Warning: (recently discovered and may have been fixed)
> > 
> > arch_topology.c:(.text+0xbac): multiple definition of `store_cpu_topology'; arch/arm/kernel/topology.o:topology.c:(.text+0x0): first defined here
> > 
> > Error/Warning ids grouped by kconfigs:
> > 
> > gcc_recent_errors
> > `-- arm-defconfig
> >     `-- multiple-definition-of-store_cpu_topology-arch-arm-kernel-topology.o:topology.c:(.text):first-defined-here
> > 
> > elapsed time: 721m
> 
> Looking at the arm32 implementation - it appears to be mostly the sort of MPIDR
> stuff that was removed from the arm64 implementation in 3102bc0e6ac7 ("arm64:
> topology: Stop using MPIDR for topology information"). Could arm32 benefit from
> the same shared implemenation too, or is usage of MPIDR only invalid for arm64?

Don't look at me... this code was contributed by Linaro, presumably for
systems they have. I've never had anything that would require this so
the code never interested me, so I never took much notice of it.

Sorry, I can't be of more help.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

WARNING: multiple messages have this Message-ID (diff)
From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Conor.Dooley@microchip.com
Cc: paul.walmsley@sifive.com, palmer@dabbelt.com,
	palmer@rivosinc.com, aou@eecs.berkeley.edu, sudeep.holla@arm.com,
	catalin.marinas@arm.com, will@kernel.org,
	gregkh@linuxfoundation.org, rafael@kernel.org, arnd@arndb.de,
	Daire.McNamara@microchip.com, niklas.cassel@wdc.com,
	damien.lemoal@opensource.wdc.com, geert@linux-m68k.org,
	zong.li@sifive.com, kernel@esmil.dk, hahnjo@hahnjo.de,
	guoren@kernel.org, anup@brainfault.org, atishp@atishpatra.org,
	heiko@sntech.de, philipp.tomsich@vrull.eu, robh@kernel.org,
	maz@kernel.org, viresh.kumar@linaro.org,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, Brice.Goglin@inria.fr
Subject: Re: [PATCH v2 1/2] arm64: topology: move store_cpu_topology() to shared code
Date: Sat, 9 Jul 2022 20:50:17 +0100	[thread overview]
Message-ID: <Ysnb+VNniRBF1Hh0@shell.armlinux.org.uk> (raw)
In-Reply-To: <efa89122-b428-7691-49d3-f5867206f05a@microchip.com>

On Sat, Jul 09, 2022 at 12:58:57PM +0000, Conor.Dooley@microchip.com wrote:
> +CC Russel, Arnd
> 
> On 08/07/2022 21:45, Conor Dooley - M52691 wrote:
> > On 08/07/2022 21:33, Conor Dooley wrote:
> >> From: Conor Dooley <conor.dooley@microchip.com>
> >>
> >> arm64's method of defining a default cpu topology requires only minimal
> >> changes to apply to RISC-V also. The current arm64 implementation exits
> >> early in a uniprocessor configuration by reading MPIDR & claiming that
> >> uniprocessor can rely on the default values.
> >>
> >> This is appears to be a hangover from prior to '3102bc0e6ac7 ("arm64:
> >> topology: Stop using MPIDR for topology information")', because the
> >> current code just assigns default values for multiprocessor systems.
> >>
> >> With the MPIDR references removed, store_cpu_topolgy() can be moved to
> >> the common arch_topology code.
> >>
> >> CC: stable@vger.kernel.org
> >> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> >> ---
> ---8<---
> >>  #ifdef CONFIG_ACPI
> >>  static bool __init acpi_cpu_is_threaded(int cpu)
> >>  {
> >> diff --git a/drivers/base/arch_topology.c b/drivers/base/arch_topology.c
> >> index 441e14ac33a4..07e84c6ac5c2 100644
> >> --- a/drivers/base/arch_topology.c
> >> +++ b/drivers/base/arch_topology.c
> >> @@ -765,6 +765,25 @@ void update_siblings_masks(unsigned int cpuid)
> >>  	}
> >>  }
> >>  
> >> +void __weak store_cpu_topology(unsigned int cpuid)
> > 
> > Ahh crap, I forgot to remove the __weak.
> > I won't immediately respin since it is minor. I've pushed it (without
> > the __weak) to https://git.kernel.org/conor/h/arch-topo so it'll get
> > the lkp coverage.
> 
> And build failure for arm32:
> 
> > tree/branch: https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git arch-topo
> > branch HEAD: df379c4b12f6b22fb8c07c2be16fd821a4fcbfc5  riscv: topology: fix default topology reporting
> > 
> > Error/Warning: (recently discovered and may have been fixed)
> > 
> > arch_topology.c:(.text+0xbac): multiple definition of `store_cpu_topology'; arch/arm/kernel/topology.o:topology.c:(.text+0x0): first defined here
> > 
> > Error/Warning ids grouped by kconfigs:
> > 
> > gcc_recent_errors
> > `-- arm-defconfig
> >     `-- multiple-definition-of-store_cpu_topology-arch-arm-kernel-topology.o:topology.c:(.text):first-defined-here
> > 
> > elapsed time: 721m
> 
> Looking at the arm32 implementation - it appears to be mostly the sort of MPIDR
> stuff that was removed from the arm64 implementation in 3102bc0e6ac7 ("arm64:
> topology: Stop using MPIDR for topology information"). Could arm32 benefit from
> the same shared implemenation too, or is usage of MPIDR only invalid for arm64?

Don't look at me... this code was contributed by Linaro, presumably for
systems they have. I've never had anything that would require this so
the code never interested me, so I never took much notice of it.

Sorry, I can't be of more help.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

  reply	other threads:[~2022-07-09 19:53 UTC|newest]

Thread overview: 24+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-07-08 20:33 [PATCH v2 0/2] Fix RISC-V's arch-topology reporting Conor Dooley
2022-07-08 20:33 ` Conor Dooley
2022-07-08 20:33 ` Conor Dooley
2022-07-08 20:33 ` [PATCH v2 1/2] arm64: topology: move store_cpu_topology() to shared code Conor Dooley
2022-07-08 20:33   ` Conor Dooley
2022-07-08 20:33   ` Conor Dooley
2022-07-08 20:45   ` Conor.Dooley
2022-07-08 20:45     ` Conor.Dooley
2022-07-08 20:45     ` Conor.Dooley
2022-07-09 12:58     ` Conor.Dooley
2022-07-09 12:58       ` Conor.Dooley
2022-07-09 12:58       ` Conor.Dooley
2022-07-09 19:50       ` Russell King (Oracle) [this message]
2022-07-09 19:50         ` Russell King (Oracle)
2022-07-09 19:50         ` Russell King (Oracle)
2022-07-11 10:02       ` Sudeep Holla
2022-07-11 10:02         ` Sudeep Holla
2022-07-11 10:02         ` Sudeep Holla
2022-07-11 10:24         ` Conor.Dooley
2022-07-11 10:24           ` Conor.Dooley
2022-07-11 10:24           ` Conor.Dooley
2022-07-08 20:33 ` [PATCH v2 2/2] riscv: topology: fix default topology reporting Conor Dooley
2022-07-08 20:33   ` Conor Dooley
2022-07-08 20:33   ` Conor Dooley

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