From: Andi Shyti <andi.shyti@linux.intel.com>
To: Randy Dunlap <rdunlap@infradead.org>
Cc: Maxime Ripard <mripard@kernel.org>,
Jonathan Corbet <corbet@lwn.net>, David Airlie <airlied@linux.ie>,
Thomas Zimmermann <tzimmermann@suse.de>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Chris Wilson <chris.p.wilson@intel.com>,
linux-doc@vger.kernel.org, Rodrigo Vivi <rodrigo.vivi@intel.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
intel-gfx@lists.freedesktop.org
Subject: Re: [Intel-gfx] [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions
Date: Fri, 5 Aug 2022 11:08:05 +0200 [thread overview]
Message-ID: <Yuzd9Ysc3BDQHuSW@alfio.lan> (raw)
In-Reply-To: <0698c5a5-3bf2-daa4-e10e-2715f9b0d080@infradead.org>
Hi Randy,
> > +/**
> > + * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
> > + * @gt: GT structure
>
> In multiple places (here and below) it would be nice to know what a
> GT structure is. I looked thru multiple C and header files yesterday
> and didn't find any comments about it.
>
> Just saying that @gt is a GT structure isn't very helpful, other
> than making kernel-doc shut up.
the 'gt' belongs to the drivers/gpu/drm/i915/gt/ subsystem and
it's widely used a throughout i915.
I think it's inappropriate to describe it just here. On the other
hand I agree that a better documentation is required for the GT
itself where other parts can point to.
Andi
WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Randy Dunlap <rdunlap@infradead.org>
Cc: Mauro Carvalho Chehab <mchehab@kernel.org>,
Jonathan Corbet <corbet@lwn.net>,
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>,
Andi Shyti <andi.shyti@linux.intel.com>,
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
Chris Wilson <chris.p.wilson@intel.com>,
Daniel Vetter <daniel@ffwll.ch>, David Airlie <airlied@linux.ie>,
Jani Nikula <jani.nikula@linux.intel.com>,
Joonas Lahtinen <joonas.lahtinen@linux.intel.com>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <mripard@kernel.org>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Thomas Zimmermann <tzimmermann@suse.de>,
dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org,
linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions
Date: Fri, 5 Aug 2022 11:08:05 +0200 [thread overview]
Message-ID: <Yuzd9Ysc3BDQHuSW@alfio.lan> (raw)
In-Reply-To: <0698c5a5-3bf2-daa4-e10e-2715f9b0d080@infradead.org>
Hi Randy,
> > +/**
> > + * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
> > + * @gt: GT structure
>
> In multiple places (here and below) it would be nice to know what a
> GT structure is. I looked thru multiple C and header files yesterday
> and didn't find any comments about it.
>
> Just saying that @gt is a GT structure isn't very helpful, other
> than making kernel-doc shut up.
the 'gt' belongs to the drivers/gpu/drm/i915/gt/ subsystem and
it's widely used a throughout i915.
I think it's inappropriate to describe it just here. On the other
hand I agree that a better documentation is required for the GT
itself where other parts can point to.
Andi
WARNING: multiple messages have this Message-ID (diff)
From: Andi Shyti <andi.shyti@linux.intel.com>
To: Randy Dunlap <rdunlap@infradead.org>
Cc: Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com>,
Jonathan Corbet <corbet@lwn.net>, David Airlie <airlied@linux.ie>,
Thomas Zimmermann <tzimmermann@suse.de>,
dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org,
Chris Wilson <chris.p.wilson@intel.com>,
linux-doc@vger.kernel.org,
Andi Shyti <andi.shyti@linux.intel.com>,
Rodrigo Vivi <rodrigo.vivi@intel.com>,
Niranjana Vishwanathapura <niranjana.vishwanathapura@intel.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
intel-gfx@lists.freedesktop.org
Subject: Re: [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions
Date: Fri, 5 Aug 2022 11:08:05 +0200 [thread overview]
Message-ID: <Yuzd9Ysc3BDQHuSW@alfio.lan> (raw)
In-Reply-To: <0698c5a5-3bf2-daa4-e10e-2715f9b0d080@infradead.org>
Hi Randy,
> > +/**
> > + * intel_gt_invalidate_tlb_full - do full TLB cache invalidation
> > + * @gt: GT structure
>
> In multiple places (here and below) it would be nice to know what a
> GT structure is. I looked thru multiple C and header files yesterday
> and didn't find any comments about it.
>
> Just saying that @gt is a GT structure isn't very helpful, other
> than making kernel-doc shut up.
the 'gt' belongs to the drivers/gpu/drm/i915/gt/ subsystem and
it's widely used a throughout i915.
I think it's inappropriate to describe it just here. On the other
hand I agree that a better documentation is required for the GT
itself where other parts can point to.
Andi
next prev parent reply other threads:[~2022-08-05 9:08 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-08-04 7:37 [Intel-gfx] [PATCH v3 0/3] Move TLB invalidation code for its own file and document it Mauro Carvalho Chehab
2022-08-04 7:37 ` Mauro Carvalho Chehab
2022-08-04 7:37 ` Mauro Carvalho Chehab
2022-08-04 7:37 ` [Intel-gfx] [PATCH v3 1/3] drm/i915: pass a pointer for tlb seqno at vma_invalidate_tlb() Mauro Carvalho Chehab
2022-08-04 7:37 ` Mauro Carvalho Chehab
2022-08-04 8:18 ` [Intel-gfx] " Tvrtko Ursulin
2022-08-04 8:18 ` Tvrtko Ursulin
2022-08-08 16:37 ` [Intel-gfx] " Andi Shyti
2022-08-08 16:37 ` Andi Shyti
2022-08-08 19:04 ` [Intel-gfx] " Rodrigo Vivi
2022-08-08 19:04 ` Rodrigo Vivi
2022-08-08 23:09 ` Andi Shyti
2022-08-08 23:09 ` Andi Shyti
2022-08-09 0:15 ` Vivi, Rodrigo
2022-08-09 0:15 ` Vivi, Rodrigo
2022-08-09 6:29 ` Mauro Carvalho Chehab
2022-08-09 6:29 ` Mauro Carvalho Chehab
2022-08-04 7:37 ` [Intel-gfx] [PATCH v3 2/3] drm/i915/gt: Move TLB invalidation to its own file Mauro Carvalho Chehab
2022-08-04 7:37 ` Mauro Carvalho Chehab
2022-08-04 7:37 ` [Intel-gfx] [PATCH v3 3/3] drm/i915/gt: document TLB cache invalidation functions Mauro Carvalho Chehab
2022-08-04 7:37 ` Mauro Carvalho Chehab
2022-08-04 7:37 ` Mauro Carvalho Chehab
2022-08-04 19:00 ` [Intel-gfx] " Randy Dunlap
2022-08-04 19:00 ` Randy Dunlap
2022-08-04 19:00 ` Randy Dunlap
2022-08-05 9:08 ` Andi Shyti [this message]
2022-08-05 9:08 ` Andi Shyti
2022-08-05 9:08 ` Andi Shyti
2022-08-05 9:24 ` [Intel-gfx] " Tvrtko Ursulin
2022-08-05 9:24 ` Tvrtko Ursulin
2022-08-05 9:24 ` Tvrtko Ursulin
2022-08-05 10:30 ` [Intel-gfx] " Mauro Carvalho Chehab
2022-08-05 10:30 ` Mauro Carvalho Chehab
2022-08-05 10:30 ` Mauro Carvalho Chehab
2022-08-08 16:58 ` Andi Shyti
2022-08-08 16:58 ` Andi Shyti
2022-08-08 16:58 ` Andi Shyti
2022-08-04 8:12 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Move TLB invalidation code for its own file and document it (rev4) Patchwork
2022-08-04 8:12 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2022-08-04 8:34 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-08-04 10:09 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork
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