Re: [PATCH] arm64/cache: Fix cache_type_cwg() for register generation

From: Mark Rutland <mark.rutland@arm.com>
To: Mark Brown <broonie@kernel.org>
Cc: Will Deacon <will@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Ard Biesheuvel <ardb@kernel.org>
Subject: Re: [PATCH] arm64/cache: Fix cache_type_cwg() for register generation
Date: Thu, 18 Aug 2022 14:20:18 +0100	[thread overview]
Message-ID: <Yv48c92AukRk0VTM@FVFF77S0Q05N.cambridge.arm.com> (raw)
In-Reply-To: <Yv0x4l8GqnC3uNyY@sirena.org.uk>

On Wed, Aug 17, 2022 at 07:22:26PM +0100, Mark Brown wrote:
> On Wed, Aug 17, 2022 at 05:56:24PM +0100, Mark Rutland wrote:
> 
> >   5b345e39d3ebc213 ("arm64/sysreg: Standardise naming for CTR_EL0 fields")
> 
> > ... and instead have:
> 
> > | #define CTR_CWG(ctr)          SYS_FIELD_GET(CTR_EL0, CWG, ctr)
> 
> I think if we're going to define that sort of per bitfield accessor
> macro (which is certainly a valid and reasonable thing to do) we should
> be having the script generate them rather than open coding them but
> that's getting out of scope for a fix and should be done separately.

I'm not asking for us to do that for *every* bitfield accessor, I'm just asking
for us to be locally consistent within cache.h.

I'm also happy to use SYS_FIELD_GET() directly within cache_type_cwg(), and not
define CTR_CWG().

Thanks,
Mark.

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