* [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies
@ 2022-08-01 23:48 Taylor, Clinton A
2022-08-02 0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) Patchwork
` (3 more replies)
0 siblings, 4 replies; 5+ messages in thread
From: Taylor, Clinton A @ 2022-08-01 23:48 UTC (permalink / raw)
To: Intel-gfx
Using the BSPEC algorithm add addition HDMI pixel clocks to the existing
table.
v2: remove 297000 unused entry
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Taylor, Clinton A <clinton.a.taylor@intel.com>
---
drivers/gpu/drm/i915/display/intel_snps_phy.c | 1115 +++++++++++++++++
1 file changed, 1115 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c
index 0bdbedc67d7d..f75808e0c95e 100644
--- a/drivers/gpu/drm/i915/display/intel_snps_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c
@@ -518,6 +518,1085 @@ static const struct intel_mpllb_state dg2_hdmi_148_5 = {
};
/* values in the below table are calculted using the algo */
+static const struct intel_mpllb_state dg2_hdmi_25200 = {
+ .clock = 25200,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_27027 = {
+ .clock = 27027,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_28320 = {
+ .clock = 28320,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_30240 = {
+ .clock = 30240,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_31500 = {
+ .clock = 31500,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_36000 = {
+ .clock = 36000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_40000 = {
+ .clock = 40000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_49500 = {
+ .clock = 49500,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_50000 = {
+ .clock = 50000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_57284 = {
+ .clock = 57284,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_58000 = {
+ .clock = 58000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_65000 = {
+ .clock = 65000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+static const struct intel_mpllb_state dg2_hdmi_71000 = {
+ .clock = 71000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_74176 = {
+ .clock = 74176,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_75000 = {
+ .clock = 75000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_78750 = {
+ .clock = 78750,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_85500 = {
+ .clock = 85500,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_88750 = {
+ .clock = 88750,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_106500 = {
+ .clock = 106500,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_108000 = {
+ .clock = 108000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_115500 = {
+ .clock = 115500,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_119000 = {
+ .clock = 119000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_135000 = {
+ .clock = 135000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_138500 = {
+ .clock = 138500,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_147160 = {
+ .clock = 147160,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_148352 = {
+ .clock = 148352,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_154000 = {
+ .clock = 154000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_162000 = {
+ .clock = 162000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_209800 = {
+ .clock = 209800,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_262750 = {
+ .clock = 262750,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_268500 = {
+ .clock = 268500,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_296703 = {
+ .clock = 296703,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_241500 = {
+ .clock = 241500,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_497750 = {
+ .clock = 497750,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_592000 = {
+ .clock = 592000,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
+static const struct intel_mpllb_state dg2_hdmi_593407 = {
+ .clock = 593407,
+ .ref_control =
+ REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3),
+ .mpllb_cp =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124),
+ .mpllb_div =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3),
+ .mpllb_div2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1),
+ .mpllb_fracn1 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535),
+ .mpllb_fracn2 =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) |
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549),
+ .mpllb_sscen =
+ REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1),
+};
+
static const struct intel_mpllb_state dg2_hdmi_297 = {
.clock = 297000,
.ref_control =
@@ -584,6 +1663,42 @@ static const struct intel_mpllb_state * const dg2_hdmi_tables[] = {
&dg2_hdmi_148_5,
&dg2_hdmi_297,
&dg2_hdmi_594,
+ &dg2_hdmi_25200,
+ &dg2_hdmi_27027,
+ &dg2_hdmi_28320,
+ &dg2_hdmi_30240,
+ &dg2_hdmi_31500,
+ &dg2_hdmi_36000,
+ &dg2_hdmi_40000,
+ &dg2_hdmi_49500,
+ &dg2_hdmi_50000,
+ &dg2_hdmi_57284,
+ &dg2_hdmi_58000,
+ &dg2_hdmi_65000,
+ &dg2_hdmi_71000,
+ &dg2_hdmi_74176,
+ &dg2_hdmi_75000,
+ &dg2_hdmi_78750,
+ &dg2_hdmi_85500,
+ &dg2_hdmi_88750,
+ &dg2_hdmi_106500,
+ &dg2_hdmi_108000,
+ &dg2_hdmi_115500,
+ &dg2_hdmi_119000,
+ &dg2_hdmi_135000,
+ &dg2_hdmi_138500,
+ &dg2_hdmi_147160,
+ &dg2_hdmi_148352,
+ &dg2_hdmi_154000,
+ &dg2_hdmi_162000,
+ &dg2_hdmi_209800,
+ &dg2_hdmi_241500,
+ &dg2_hdmi_262750,
+ &dg2_hdmi_268500,
+ &dg2_hdmi_296703,
+ &dg2_hdmi_497750,
+ &dg2_hdmi_592000,
+ &dg2_hdmi_593407,
NULL,
};
--
2.25.1
^ permalink raw reply related [flat|nested] 5+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) 2022-08-01 23:48 [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies Taylor, Clinton A @ 2022-08-02 0:13 ` Patchwork 2022-08-02 0:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork ` (2 subsequent siblings) 3 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2022-08-02 0:13 UTC (permalink / raw) To: Taylor, Clinton A; +Cc: intel-gfx == Series Details == Series: drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) URL : https://patchwork.freedesktop.org/series/106891/ State : warning == Summary == Error: dim checkpatch failed 64ed0b830d10 drm/i915/dg2: Add additional HDMI pixel clock frequencies -:382: CHECK:LINE_SPACING: Please use a blank line after function/struct/union/enum declarations #382: FILE: drivers/gpu/drm/i915/display/intel_snps_phy.c:880: +}; +static const struct intel_mpllb_state dg2_hdmi_71000 = { total: 0 errors, 0 warnings, 1 checks, 1127 lines checked ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) 2022-08-01 23:48 [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies Taylor, Clinton A 2022-08-02 0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) Patchwork @ 2022-08-02 0:32 ` Patchwork 2022-08-02 11:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-08-11 16:57 ` [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies Balasubramani Vivekanandan 3 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2022-08-02 0:32 UTC (permalink / raw) To: Taylor, Clinton A; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 7950 bytes --] == Series Details == Series: drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) URL : https://patchwork.freedesktop.org/series/106891/ State : success == Summary == CI Bug Log - changes from CI_DRM_11961 -> Patchwork_106891v2 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/index.html Participating hosts (43 -> 38) ------------------------------ Additional (1): fi-rkl-11600 Missing (6): fi-hsw-4200u fi-bsw-n3050 fi-glk-dsi fi-ctg-p8600 fi-bsw-kefka fi-bsw-nick Known issues ------------ Here are the changes found in Patchwork_106891v2 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_huc_copy@huc-copy: - fi-rkl-11600: NOTRUN -> [SKIP][1] ([i915#2190]) [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html * igt@gem_lmem_swapping@basic: - fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#4613]) +3 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@gem_lmem_swapping@basic.html * igt@gem_tiled_pread_basic: - fi-rkl-11600: NOTRUN -> [SKIP][3] ([i915#3282]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - fi-rkl-11600: NOTRUN -> [SKIP][4] ([i915#3012]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html * igt@i915_selftest@live@hangcheck: - bat-dg1-6: [PASS][5] -> [DMESG-FAIL][6] ([i915#4494] / [i915#4957]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/bat-dg1-6/igt@i915_selftest@live@hangcheck.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/bat-dg1-6/igt@i915_selftest@live@hangcheck.html * igt@i915_suspend@basic-s3-without-i915: - fi-rkl-11600: NOTRUN -> [INCOMPLETE][7] ([i915#5982]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@i915_suspend@basic-s3-without-i915.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-hsw-4770: NOTRUN -> [SKIP][8] ([fdo#109271] / [fdo#111827]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@hdmi-edid-read: - fi-rkl-11600: NOTRUN -> [SKIP][9] ([fdo#111827]) +7 similar issues [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor: - fi-rkl-11600: NOTRUN -> [SKIP][10] ([i915#4103]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor.html * igt@kms_force_connector_basic@force-load-detect: - fi-rkl-11600: NOTRUN -> [SKIP][11] ([fdo#109285] / [i915#4098]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_psr@primary_page_flip: - fi-rkl-11600: NOTRUN -> [SKIP][12] ([i915#1072]) +3 similar issues [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@kms_psr@primary_page_flip.html * igt@kms_setmode@basic-clone-single-crtc: - fi-rkl-11600: NOTRUN -> [SKIP][13] ([i915#3555] / [i915#4098]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-read: - fi-rkl-11600: NOTRUN -> [SKIP][14] ([fdo#109295] / [i915#3291] / [i915#3708]) +2 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@prime_vgem@basic-read.html * igt@prime_vgem@basic-userptr: - fi-rkl-11600: NOTRUN -> [SKIP][15] ([fdo#109295] / [i915#3301] / [i915#3708]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-rkl-11600/igt@prime_vgem@basic-userptr.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s0@smem: - {bat-adlm-1}: [DMESG-WARN][16] ([i915#2867]) -> [PASS][17] [16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/bat-adlm-1/igt@gem_exec_suspend@basic-s0@smem.html * igt@i915_selftest@live@guc: - {bat-dg2-9}: [DMESG-WARN][18] ([i915#5763]) -> [PASS][19] +6 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/bat-dg2-9/igt@i915_selftest@live@guc.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/bat-dg2-9/igt@i915_selftest@live@guc.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770: [INCOMPLETE][20] ([i915#4785]) -> [PASS][21] [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 [i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087 [i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270 [i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354 [i915#5537]: https://gitlab.freedesktop.org/drm/intel/issues/5537 [i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763 [i915#5903]: https://gitlab.freedesktop.org/drm/intel/issues/5903 [i915#5950]: https://gitlab.freedesktop.org/drm/intel/issues/5950 [i915#5982]: https://gitlab.freedesktop.org/drm/intel/issues/5982 [i915#6257]: https://gitlab.freedesktop.org/drm/intel/issues/6257 Build changes ------------- * Linux: CI_DRM_11961 -> Patchwork_106891v2 CI-20190529: 20190529 CI_DRM_11961: 7c6c0dca085a0589c6b9d56db454655def59ec48 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6606: 70465d8cc0ea657dba56b1c1e6f70df98f3db851 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_106891v2: 7c6c0dca085a0589c6b9d56db454655def59ec48 @ git://anongit.freedesktop.org/gfx-ci/linux ### Linux commits 5282827e8a5d drm/i915/dg2: Add additional HDMI pixel clock frequencies == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/index.html [-- Attachment #2: Type: text/html, Size: 8769 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) 2022-08-01 23:48 [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies Taylor, Clinton A 2022-08-02 0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) Patchwork 2022-08-02 0:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork @ 2022-08-02 11:38 ` Patchwork 2022-08-11 16:57 ` [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies Balasubramani Vivekanandan 3 siblings, 0 replies; 5+ messages in thread From: Patchwork @ 2022-08-02 11:38 UTC (permalink / raw) To: Taylor, Clinton A; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 42610 bytes --] == Series Details == Series: drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) URL : https://patchwork.freedesktop.org/series/106891/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11961_full -> Patchwork_106891v2_full ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_106891v2_full absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_106891v2_full, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. Participating hosts (13 -> 13) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_106891v2_full: ### IGT changes ### #### Possible regressions #### * igt@syncobj_timeline@signal-point-0: - shard-iclb: [PASS][1] -> [INCOMPLETE][2] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb3/igt@syncobj_timeline@signal-point-0.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb4/igt@syncobj_timeline@signal-point-0.html #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@i915_pm_rps@fence-order: - {shard-rkl}: [PASS][3] -> [TIMEOUT][4] [3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@i915_pm_rps@fence-order.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@i915_pm_rps@fence-order.html New tests --------- New tests have been introduced between CI_DRM_11961_full and Patchwork_106891v2_full: ### New IGT tests (4) ### * igt@kms_cursor_crc@cursor-dpms@pipe-a-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.89] s * igt@kms_cursor_crc@cursor-dpms@pipe-b-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.75] s * igt@kms_cursor_crc@cursor-dpms@pipe-c-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.73] s * igt@kms_cursor_crc@cursor-dpms@pipe-d-hdmi-a-4: - Statuses : 1 pass(s) - Exec time: [0.74] s Known issues ------------ Here are the changes found in Patchwork_106891v2_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_balancer@parallel-keep-submit-fence: - shard-iclb: [PASS][5] -> [SKIP][6] ([i915#4525]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb1/igt@gem_exec_balancer@parallel-keep-submit-fence.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb6/igt@gem_exec_balancer@parallel-keep-submit-fence.html * igt@gem_exec_fair@basic-deadline: - shard-glk: [PASS][7] -> [FAIL][8] ([i915#2846]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-glk3/igt@gem_exec_fair@basic-deadline.html [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk2/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-share@rcs0: - shard-tglb: [PASS][9] -> [FAIL][10] ([i915#2842]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-tglb5/igt@gem_exec_fair@basic-none-share@rcs0.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-tglb7/igt@gem_exec_fair@basic-none-share@rcs0.html - shard-iclb: [PASS][11] -> [FAIL][12] ([i915#2842]) [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb5/igt@gem_exec_fair@basic-none-share@rcs0.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb2/igt@gem_exec_fair@basic-none-share@rcs0.html * igt@gem_exec_fair@basic-none@rcs0: - shard-glk: [PASS][13] -> [FAIL][14] ([i915#2842]) +3 similar issues [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-glk5/igt@gem_exec_fair@basic-none@rcs0.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk2/igt@gem_exec_fair@basic-none@rcs0.html * igt@gem_lmem_swapping@heavy-multi: - shard-glk: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#4613]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk1/igt@gem_lmem_swapping@heavy-multi.html * igt@gem_lmem_swapping@heavy-verify-random: - shard-kbl: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#4613]) [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl4/igt@gem_lmem_swapping@heavy-verify-random.html * igt@gem_lmem_swapping@parallel-random-verify: - shard-skl: NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +3 similar issues [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl10/igt@gem_lmem_swapping@parallel-random-verify.html * igt@gem_workarounds@suspend-resume: - shard-apl: [PASS][18] -> [DMESG-WARN][19] ([i915#180]) +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-apl7/igt@gem_workarounds@suspend-resume.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl6/igt@gem_workarounds@suspend-resume.html - shard-kbl: [PASS][20] -> [DMESG-WARN][21] ([i915#180]) +1 similar issue [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-kbl1/igt@gem_workarounds@suspend-resume.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl7/igt@gem_workarounds@suspend-resume.html * igt@i915_pm_dc@dc6-dpms: - shard-iclb: [PASS][22] -> [FAIL][23] ([i915#454]) [22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb8/igt@i915_pm_dc@dc6-dpms.html [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb3/igt@i915_pm_dc@dc6-dpms.html * igt@i915_suspend@forcewake: - shard-skl: [PASS][24] -> [INCOMPLETE][25] ([i915#4817]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-skl4/igt@i915_suspend@forcewake.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl7/igt@i915_suspend@forcewake.html * igt@kms_big_fb@linear-64bpp-rotate-270: - shard-skl: NOTRUN -> [SKIP][26] ([fdo#109271]) +218 similar issues [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl1/igt@kms_big_fb@linear-64bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-32bpp-rotate-90: - shard-skl: NOTRUN -> [TIMEOUT][27] ([i915#6371]) [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl1/igt@kms_big_fb@yf-tiled-32bpp-rotate-90.html * igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3886]) +15 similar issues [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl2/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][29] ([fdo#109271] / [i915#3886]) +1 similar issue [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl4/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html * igt@kms_chamelium@hdmi-crc-multiple: - shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [fdo#111827]) +17 similar issues [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl2/igt@kms_chamelium@hdmi-crc-multiple.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-glk: NOTRUN -> [SKIP][31] ([fdo#109271] / [fdo#111827]) +2 similar issues [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk1/igt@kms_color_chamelium@pipe-b-ctm-max.html * igt@kms_color_chamelium@pipe-c-ctm-0-75: - shard-kbl: NOTRUN -> [SKIP][32] ([fdo#109271] / [fdo#111827]) +6 similar issues [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl4/igt@kms_color_chamelium@pipe-c-ctm-0-75.html * igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size: - shard-glk: [PASS][33] -> [FAIL][34] ([i915#2346]) [33]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor@atomic-transitions-varying-size.html * igt@kms_cursor_legacy@flip-vs-cursor@varying-size: - shard-skl: [PASS][35] -> [FAIL][36] ([i915#2346]) [35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl4/igt@kms_cursor_legacy@flip-vs-cursor@varying-size.html * igt@kms_fbcon_fbt@psr-suspend: - shard-skl: [PASS][37] -> [FAIL][38] ([i915#4767]) [37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-skl10/igt@kms_fbcon_fbt@psr-suspend.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl1/igt@kms_fbcon_fbt@psr-suspend.html * igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2: - shard-glk: [PASS][39] -> [FAIL][40] ([i915#2122]) [39]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-glk5/igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2.html [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk2/igt@kms_flip@2x-plain-flip-fb-recreate@ac-hdmi-a1-hdmi-a2.html * igt@kms_flip@blocking-wf_vblank@c-edp1: - shard-skl: [PASS][41] -> [FAIL][42] ([i915#2122]) [41]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-skl7/igt@kms_flip@blocking-wf_vblank@c-edp1.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl9/igt@kms_flip@blocking-wf_vblank@c-edp1.html * igt@kms_flip@flip-vs-expired-vblank@c-edp1: - shard-skl: [PASS][43] -> [FAIL][44] ([i915#79]) +1 similar issue [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl6/igt@kms_flip@flip-vs-expired-vblank@c-edp1.html * igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode: - shard-iclb: NOTRUN -> [SKIP][45] ([i915#2672]) +6 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb3/igt@kms_flip_scaled_crc@flip-32bpp-4tile-to-32bpp-4tiledg2rcccs-downscaling@pipe-a-default-mode.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode: - shard-iclb: NOTRUN -> [SKIP][46] ([i915#2672] / [i915#3555]) [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilegen12rcccs-upscaling@pipe-a-valid-mode.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt: - shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271]) +65 similar issues [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl4/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite: - shard-glk: NOTRUN -> [SKIP][48] ([fdo#109271]) +11 similar issues [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite.html * igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1: - shard-kbl: NOTRUN -> [FAIL][49] ([i915#1188]) [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl7/igt@kms_hdr@bpc-switch-dpms@pipe-a-dp-1.html * igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1: - shard-kbl: [PASS][50] -> [FAIL][51] ([i915#1188]) [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-kbl1/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl4/igt@kms_hdr@bpc-switch-suspend@pipe-a-dp-1.html * igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes: - shard-kbl: NOTRUN -> [DMESG-WARN][52] ([i915#180]) +1 similar issue [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl7/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-a-planes.html * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb: - shard-skl: NOTRUN -> [FAIL][53] ([i915#265]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html * igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max: - shard-skl: NOTRUN -> [FAIL][54] ([fdo#108145] / [i915#265]) [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-constant-alpha-max.html * igt@kms_psr2_su@frontbuffer-xrgb8888: - shard-iclb: [PASS][55] -> [SKIP][56] ([fdo#109642] / [fdo#111068] / [i915#658]) [55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html * igt@kms_psr2_su@page_flip-xrgb8888: - shard-skl: NOTRUN -> [SKIP][57] ([fdo#109271] / [i915#658]) +5 similar issues [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl1/igt@kms_psr2_su@page_flip-xrgb8888.html * igt@kms_psr@psr2_sprite_mmap_gtt: - shard-iclb: [PASS][58] -> [SKIP][59] ([fdo#109441]) +1 similar issue [58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_gtt.html [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_gtt.html * igt@kms_psr_stress_test@invalidate-primary-flip-overlay: - shard-tglb: [PASS][60] -> [SKIP][61] ([i915#5519]) [60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-tglb1/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html [61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-tglb2/igt@kms_psr_stress_test@invalidate-primary-flip-overlay.html * igt@kms_sysfs_edid_timing: - shard-skl: NOTRUN -> [FAIL][62] ([i915#6493]) [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl1/igt@kms_sysfs_edid_timing.html * igt@kms_writeback@writeback-invalid-parameters: - shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2437]) [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl10/igt@kms_writeback@writeback-invalid-parameters.html * igt@perf@polling-parameterized: - shard-apl: [PASS][64] -> [FAIL][65] ([i915#5639]) [64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-apl4/igt@perf@polling-parameterized.html [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl7/igt@perf@polling-parameterized.html * igt@sysfs_clients@fair-1: - shard-glk: NOTRUN -> [SKIP][66] ([fdo#109271] / [i915#2994]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk1/igt@sysfs_clients@fair-1.html * igt@sysfs_clients@split-10: - shard-skl: NOTRUN -> [SKIP][67] ([fdo#109271] / [i915#2994]) +1 similar issue [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl7/igt@sysfs_clients@split-10.html * igt@sysfs_clients@split-50: - shard-kbl: NOTRUN -> [SKIP][68] ([fdo#109271] / [i915#2994]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl7/igt@sysfs_clients@split-50.html #### Possible fixes #### * igt@fbdev@info: - {shard-rkl}: [SKIP][69] ([i915#2582]) -> [PASS][70] [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@fbdev@info.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@fbdev@info.html * igt@gem_ctx_exec@basic-nohangcheck: - shard-tglb: [FAIL][71] ([i915#6268]) -> [PASS][72] [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-tglb1/igt@gem_ctx_exec@basic-nohangcheck.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-tglb2/igt@gem_ctx_exec@basic-nohangcheck.html * igt@gem_ctx_persistence@engines-hang@rcs0: - {shard-dg1}: [FAIL][73] ([i915#4883]) -> [PASS][74] +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-dg1-15/igt@gem_ctx_persistence@engines-hang@rcs0.html [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-dg1-18/igt@gem_ctx_persistence@engines-hang@rcs0.html * igt@gem_exec_balancer@parallel-contexts: - shard-iclb: [SKIP][75] ([i915#4525]) -> [PASS][76] +2 similar issues [75]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb5/igt@gem_exec_balancer@parallel-contexts.html [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html * igt@gem_exec_fair@basic-deadline: - shard-kbl: [FAIL][77] ([i915#2846]) -> [PASS][78] [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-kbl1/igt@gem_exec_fair@basic-deadline.html [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl7/igt@gem_exec_fair@basic-deadline.html * igt@gem_exec_fair@basic-none-solo@rcs0: - shard-apl: [FAIL][79] ([i915#2842]) -> [PASS][80] +1 similar issue [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl1/igt@gem_exec_fair@basic-none-solo@rcs0.html * igt@gem_exec_fair@basic-none-vip@rcs0: - shard-glk: [FAIL][81] ([i915#2842]) -> [PASS][82] +1 similar issue [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-glk6/igt@gem_exec_fair@basic-none-vip@rcs0.html [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk5/igt@gem_exec_fair@basic-none-vip@rcs0.html * igt@gem_exec_fair@basic-none@vcs1: - shard-kbl: [FAIL][83] ([i915#2842]) -> [PASS][84] +2 similar issues [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-kbl7/igt@gem_exec_fair@basic-none@vcs1.html [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl7/igt@gem_exec_fair@basic-none@vcs1.html * igt@gem_exec_fair@basic-pace-share@rcs0: - {shard-tglu}: [FAIL][85] ([i915#2842]) -> [PASS][86] [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html - shard-tglb: [FAIL][87] ([i915#2842]) -> [PASS][88] [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-tglb6/igt@gem_exec_fair@basic-pace-share@rcs0.html [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-tglb1/igt@gem_exec_fair@basic-pace-share@rcs0.html * igt@gem_exec_fence@basic-busy@bcs0: - {shard-rkl}: [SKIP][89] ([i915#6251]) -> [PASS][90] [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@gem_exec_fence@basic-busy@bcs0.html [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-1/igt@gem_exec_fence@basic-busy@bcs0.html * igt@gem_exec_reloc@basic-write-read: - {shard-rkl}: [SKIP][91] ([i915#3281]) -> [PASS][92] +19 similar issues [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-6/igt@gem_exec_reloc@basic-write-read.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-5/igt@gem_exec_reloc@basic-write-read.html * igt@gem_pread@snoop: - {shard-rkl}: [SKIP][93] ([i915#3282]) -> [PASS][94] +8 similar issues [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-2/igt@gem_pread@snoop.html [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-5/igt@gem_pread@snoop.html * igt@gem_userptr_blits@huge-split: - shard-iclb: [FAIL][95] ([i915#3376]) -> [PASS][96] [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb1/igt@gem_userptr_blits@huge-split.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb6/igt@gem_userptr_blits@huge-split.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [DMESG-WARN][97] ([i915#180]) -> [PASS][98] +4 similar issues [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-kbl7/igt@gem_workarounds@suspend-resume-fd.html * igt@gen9_exec_parse@allowed-single: - shard-glk: [DMESG-WARN][99] ([i915#5566] / [i915#716]) -> [PASS][100] [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-glk5/igt@gen9_exec_parse@allowed-single.html [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-glk1/igt@gen9_exec_parse@allowed-single.html * igt@gen9_exec_parse@valid-registers: - {shard-rkl}: [SKIP][101] ([i915#2527]) -> [PASS][102] +2 similar issues [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-2/igt@gen9_exec_parse@valid-registers.html [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-5/igt@gen9_exec_parse@valid-registers.html * igt@i915_pm_dc@dc6-dpms: - {shard-rkl}: [SKIP][103] ([i915#3361]) -> [PASS][104] [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@i915_pm_dc@dc6-dpms.html [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-1/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_dc@dc6-psr: - shard-iclb: [FAIL][105] ([i915#454]) -> [PASS][106] [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb3/igt@i915_pm_dc@dc6-psr.html [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb5/igt@i915_pm_dc@dc6-psr.html * igt@i915_pm_rpm@dpms-mode-unset-lpsp: - {shard-dg1}: [SKIP][107] ([i915#1397]) -> [PASS][108] [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-dg1-15/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-dg1-18/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html * igt@i915_pm_rpm@fences: - {shard-rkl}: [SKIP][109] ([i915#1849]) -> [PASS][110] +1 similar issue [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-1/igt@i915_pm_rpm@fences.html [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@i915_pm_rpm@fences.html * igt@i915_pm_rpm@modeset-lpsp-stress-no-wait: - {shard-rkl}: [SKIP][111] ([i915#1397]) -> [PASS][112] [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@i915_pm_rpm@modeset-lpsp-stress-no-wait.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip: - {shard-rkl}: [SKIP][113] ([i915#1845] / [i915#4098]) -> [PASS][114] +33 similar issues [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip.html * igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy: - shard-skl: [FAIL][115] ([i915#2346]) -> [PASS][116] [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-busy-crc-legacy.html * igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled: - {shard-rkl}: [SKIP][117] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][118] +7 similar issues [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-gtt-untiled.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt: - {shard-rkl}: [SKIP][119] ([i915#1849] / [i915#4098]) -> [PASS][120] +19 similar issues [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc: - shard-skl: [DMESG-WARN][121] ([i915#1982]) -> [PASS][122] [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-skl2/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl9/igt@kms_frontbuffer_tracking@psr-1p-primscrn-cur-indfb-draw-mmap-wc.html * igt@kms_plane@pixel-format-source-clamping@pipe-b-planes: - {shard-rkl}: [SKIP][123] ([i915#1849] / [i915#3558]) -> [PASS][124] +1 similar issue [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb: - {shard-rkl}: [SKIP][125] ([i915#1849] / [i915#3546] / [i915#4070] / [i915#4098]) -> [PASS][126] +1 similar issue [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-2/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - shard-skl: [FAIL][127] ([fdo#108145] / [i915#265]) -> [PASS][128] [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-skl7/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-coverage-7efc: - {shard-rkl}: [SKIP][129] ([i915#1849] / [i915#3546] / [i915#4098]) -> [PASS][130] [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html * igt@kms_plane_multiple@atomic-pipe-a-tiling-y: - {shard-rkl}: [SKIP][131] ([i915#3558] / [i915#4070]) -> [PASS][132] [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-1/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-a-tiling-y.html * igt@kms_psr@cursor_mmap_cpu: - {shard-rkl}: [SKIP][133] ([i915#1072]) -> [PASS][134] +3 similar issues [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-1/igt@kms_psr@cursor_mmap_cpu.html [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@kms_psr@cursor_mmap_cpu.html * igt@kms_psr@psr2_sprite_plane_move: - shard-iclb: [SKIP][135] ([fdo#109441]) -> [PASS][136] +1 similar issue [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb5/igt@kms_psr@psr2_sprite_plane_move.html [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb2/igt@kms_psr@psr2_sprite_plane_move.html * igt@kms_universal_plane@universal-plane-pipe-b-sanity: - {shard-rkl}: [SKIP][137] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][138] [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-1/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html * igt@perf@gen12-unprivileged-single-ctx-counters: - {shard-rkl}: [SKIP][139] ([fdo#109289]) -> [PASS][140] [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@perf@gen12-unprivileged-single-ctx-counters.html [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-1/igt@perf@gen12-unprivileged-single-ctx-counters.html * igt@perf@short-reads: - shard-skl: [FAIL][141] ([i915#51]) -> [PASS][142] [141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-skl7/igt@perf@short-reads.html [142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-skl2/igt@perf@short-reads.html * igt@prime_vgem@basic-fence-read: - {shard-rkl}: [SKIP][143] ([fdo#109295] / [i915#3291] / [i915#3708]) -> [PASS][144] +1 similar issue [143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-2/igt@prime_vgem@basic-fence-read.html [144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-5/igt@prime_vgem@basic-fence-read.html * igt@sysfs_timeslice_duration@timeout@vecs0: - {shard-rkl}: [FAIL][145] ([i915#1755]) -> [PASS][146] [145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-rkl-5/igt@sysfs_timeslice_duration@timeout@vecs0.html [146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-rkl-6/igt@sysfs_timeslice_duration@timeout@vecs0.html #### Warnings #### * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: [FAIL][147] ([i915#2842]) -> [FAIL][148] ([i915#2849]) [147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb7/igt@gem_exec_fair@basic-throttle@rcs0.html [148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb6/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area: - shard-iclb: [SKIP][149] ([i915#2920]) -> [SKIP][150] ([fdo#111068] / [i915#658]) +1 similar issue [149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html [150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html * igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb: - shard-iclb: [SKIP][151] ([i915#658]) -> [SKIP][152] ([i915#2920]) +1 similar issue [151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb7/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html [152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area-big-fb.html * igt@kms_psr2_su@page_flip-p010: - shard-iclb: [SKIP][153] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [FAIL][154] ([i915#5939]) [153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-iclb5/igt@kms_psr2_su@page_flip-p010.html [154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-iclb2/igt@kms_psr2_su@page_flip-p010.html * igt@runner@aborted: - shard-apl: ([FAIL][155], [FAIL][156], [FAIL][157]) ([fdo#109271] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163], [FAIL][164]) ([fdo#109271] / [i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) [155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-apl7/igt@runner@aborted.html [156]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-apl7/igt@runner@aborted.html [157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11961/shard-apl8/igt@runner@aborted.html [158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl8/igt@runner@aborted.html [159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl6/igt@runner@aborted.html [160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl8/igt@runner@aborted.html [161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl6/igt@runner@aborted.html [162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl1/igt@runner@aborted.html [163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl6/igt@runner@aborted.html [164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/shard-apl4/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145 [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289 [fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291 [fdo#109295]: https://bugs.freedesktop.org/show_bug.cgi?id=109295 [fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#109314]: https://bugs.freedesktop.org/show_bug.cgi?id=109314 [fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441 [fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506 [fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642 [fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723 [fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068 [fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314 [fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614 [fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1188]: https://gitlab.freedesktop.org/drm/intel/issues/1188 [i915#1257]: https://gitlab.freedesktop.org/drm/intel/issues/1257 [i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132 [i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397 [i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755 [i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180 [i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825 [i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#1911]: https://gitlab.freedesktop.org/drm/intel/issues/1911 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122 [i915#2232]: https://gitlab.freedesktop.org/drm/intel/issues/2232 [i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346 [i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437 [i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527 [i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265 [i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672 [i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280 [i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842 [i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846 [i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849 [i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920 [i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994 [i915#3002]: https://gitlab.freedesktop.org/drm/intel/issues/3002 [i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116 [i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291 [i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297 [i915#3361]: https://gitlab.freedesktop.org/drm/intel/issues/3361 [i915#3376]: https://gitlab.freedesktop.org/drm/intel/issues/3376 [i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458 [i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539 [i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638 [i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734 [i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742 [i915#3828]: https://gitlab.freedesktop.org/drm/intel/issues/3828 [i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886 [i915#3963]: https://gitlab.freedesktop.org/drm/intel/issues/3963 [i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032 [i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4171]: https://gitlab.freedesktop.org/drm/intel/issues/4171 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369 [i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525 [i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538 [i915#454]: https://gitlab.freedesktop.org/drm/intel/issues/454 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4767]: https://gitlab.freedesktop.org/drm/intel/issues/4767 [i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812 [i915#4817]: https://gitlab.freedesktop.org/drm/intel/issues/4817 [i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833 [i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853 [i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855 [i915#4883]: https://gitlab.freedesktop.org/drm/intel/issues/4883 [i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893 [i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941 [i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991 [i915#51]: https://gitlab.freedesktop.org/drm/intel/issues/51 [i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176 [i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286 [i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287 [i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439 [i915#5519]: https://gitlab.freedesktop.org/drm/intel/issues/5519 [i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563 [i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566 [i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639 [i915#5939]: https://gitlab.freedesktop.org/drm/intel/issues/5939 [i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095 [i915#6248]: https://gitlab.freedesktop.org/drm/intel/issues/6248 [i915#6251]: https://gitlab.freedesktop.org/drm/intel/issues/6251 [i915#6259]: https://gitlab.freedesktop.org/drm/intel/issues/6259 [i915#6268]: https://gitlab.freedesktop.org/drm/intel/issues/6268 [i915#6355]: https://gitlab.freedesktop.org/drm/intel/issues/6355 [i915#6371]: https://gitlab.freedesktop.org/drm/intel/issues/6371 [i915#6493]: https://gitlab.freedesktop.org/drm/intel/issues/6493 [i915#6497]: https://gitlab.freedesktop.org/drm/intel/issues/6497 [i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658 [i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716 [i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79 Build changes ------------- * Linux: CI_DRM_11961 -> Patchwork_106891v2 CI-20190529: 20190529 CI_DRM_11961: 7c6c0dca085a0589c6b9d56db454655def59ec48 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6606: 70465d8cc0ea657dba56b1c1e6f70df98f3db851 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_106891v2: 7c6c0dca085a0589c6b9d56db454655def59ec48 @ git://anongit.freedesktop.org/gfx-ci/linux piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_106891v2/index.html [-- Attachment #2: Type: text/html, Size: 47032 bytes --] ^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies 2022-08-01 23:48 [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies Taylor, Clinton A ` (2 preceding siblings ...) 2022-08-02 11:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork @ 2022-08-11 16:57 ` Balasubramani Vivekanandan 3 siblings, 0 replies; 5+ messages in thread From: Balasubramani Vivekanandan @ 2022-08-11 16:57 UTC (permalink / raw) To: Taylor, Clinton A, Intel-gfx On 01.08.2022 16:48, Taylor, Clinton A wrote: > Using the BSPEC algorithm add addition HDMI pixel clocks to the existing > table. > > v2: remove 297000 unused entry > > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com> > Signed-off-by: Taylor, Clinton A <clinton.a.taylor@intel.com> Reviewed-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> > --- > drivers/gpu/drm/i915/display/intel_snps_phy.c | 1115 +++++++++++++++++ > 1 file changed, 1115 insertions(+) > > diff --git a/drivers/gpu/drm/i915/display/intel_snps_phy.c b/drivers/gpu/drm/i915/display/intel_snps_phy.c > index 0bdbedc67d7d..f75808e0c95e 100644 > --- a/drivers/gpu/drm/i915/display/intel_snps_phy.c > +++ b/drivers/gpu/drm/i915/display/intel_snps_phy.c > @@ -518,6 +518,1085 @@ static const struct intel_mpllb_state dg2_hdmi_148_5 = { > }; > > /* values in the below table are calculted using the algo */ > +static const struct intel_mpllb_state dg2_hdmi_25200 = { > + .clock = 25200, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 41943) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 2621), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_27027 = { > + .clock = 27027, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 31876) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 46555), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_28320 = { > + .clock = 28320, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 148) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 40894) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 30408), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_30240 = { > + .clock = 30240, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 5) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 50331) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 42466), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_31500 = { > + .clock = 31500, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 68) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_36000 = { > + .clock = 36000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 82) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_40000 = { > + .clock = 40000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_49500 = { > + .clock = 49500, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 126) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_50000 = { > + .clock = 50000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 128) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_57284 = { > + .clock = 57284, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 150) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 42886) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 49701), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_58000 = { > + .clock = 58000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 4) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_65000 = { > + .clock = 65000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > +static const struct intel_mpllb_state dg2_hdmi_71000 = { > + .clock = 71000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 80) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_74176 = { > + .clock = 74176, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_75000 = { > + .clock = 75000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 88) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_78750 = { > + .clock = 78750, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 94) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_85500 = { > + .clock = 85500, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 104) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_88750 = { > + .clock = 88750, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 1), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 110) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_106500 = { > + .clock = 106500, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 138) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_108000 = { > + .clock = 108000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 140) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_115500 = { > + .clock = 115500, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 152) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_119000 = { > + .clock = 119000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 3) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 158) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_135000 = { > + .clock = 135000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 76) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 0), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_138500 = { > + .clock = 138500, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 78) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 26214) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 26214), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_147160 = { > + .clock = 147160, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 84) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 56623) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 6815), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_148352 = { > + .clock = 148352, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22334) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 43829), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_154000 = { > + .clock = 154000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 13) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 90) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_162000 = { > + .clock = 162000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 2), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 96) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 52428) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_209800 = { > + .clock = 209800, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 134) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 60293) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7864), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_262750 = { > + .clock = 262750, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 72) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_268500 = { > + .clock = 268500, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 7) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 74) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 45875) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_296703 = { > + .clock = 296703, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22321) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 36804), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_241500 = { > + .clock = 241500, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 160) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 39321) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 39320), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_497750 = { > + .clock = 497750, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 15) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 0), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 166) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 36044) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 52427), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_592000 = { > + .clock = 592000, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 13107) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 13107), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > +static const struct intel_mpllb_state dg2_hdmi_593407 = { > + .clock = 593407, > + .ref_control = > + REG_FIELD_PREP(SNPS_PHY_REF_CONTROL_REF_RANGE, 3), > + .mpllb_cp = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT, 6) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP, 14) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_INT_GS, 64) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_CP_PROP_GS, 124), > + .mpllb_div = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_DIV5_CLK_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_TX_CLK_DIV, 0) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_PMIX_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_V2I, 2) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FREQ_VCO, 3), > + .mpllb_div2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_REF_CLK_DIV, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_MULTIPLIER, 86) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_HDMI_DIV, 1), > + .mpllb_fracn1 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_CGG_UPDATE_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_EN, 1) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_DEN, 65535), > + .mpllb_fracn2 = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_QUOT, 22328) | > + REG_FIELD_PREP(SNPS_PHY_MPLLB_FRACN_REM, 7549), > + .mpllb_sscen = > + REG_FIELD_PREP(SNPS_PHY_MPLLB_SSC_UP_SPREAD, 1), > +}; > + > static const struct intel_mpllb_state dg2_hdmi_297 = { > .clock = 297000, > .ref_control = > @@ -584,6 +1663,42 @@ static const struct intel_mpllb_state * const dg2_hdmi_tables[] = { > &dg2_hdmi_148_5, > &dg2_hdmi_297, > &dg2_hdmi_594, > + &dg2_hdmi_25200, > + &dg2_hdmi_27027, > + &dg2_hdmi_28320, > + &dg2_hdmi_30240, > + &dg2_hdmi_31500, > + &dg2_hdmi_36000, > + &dg2_hdmi_40000, > + &dg2_hdmi_49500, > + &dg2_hdmi_50000, > + &dg2_hdmi_57284, > + &dg2_hdmi_58000, > + &dg2_hdmi_65000, > + &dg2_hdmi_71000, > + &dg2_hdmi_74176, > + &dg2_hdmi_75000, > + &dg2_hdmi_78750, > + &dg2_hdmi_85500, > + &dg2_hdmi_88750, > + &dg2_hdmi_106500, > + &dg2_hdmi_108000, > + &dg2_hdmi_115500, > + &dg2_hdmi_119000, > + &dg2_hdmi_135000, > + &dg2_hdmi_138500, > + &dg2_hdmi_147160, > + &dg2_hdmi_148352, > + &dg2_hdmi_154000, > + &dg2_hdmi_162000, > + &dg2_hdmi_209800, > + &dg2_hdmi_241500, > + &dg2_hdmi_262750, > + &dg2_hdmi_268500, > + &dg2_hdmi_296703, > + &dg2_hdmi_497750, > + &dg2_hdmi_592000, > + &dg2_hdmi_593407, > NULL, > }; > > -- > 2.25.1 > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-08-11 16:57 UTC | newest] Thread overview: 5+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2022-08-01 23:48 [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies Taylor, Clinton A 2022-08-02 0:13 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/dg2: Add additional HDMI pixel clock frequencies (rev2) Patchwork 2022-08-02 0:32 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-08-02 11:38 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork 2022-08-11 16:57 ` [Intel-gfx] [PATCH v2] drm/i915/dg2: Add additional HDMI pixel clock frequencies Balasubramani Vivekanandan
This is an external index of several public inboxes, see mirroring instructions on how to clone and mirror all data and code used by this external index.