From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Nikita Shubin <nikita.shubin@maquefel.me>
Cc: "Mayuresh Chitale" <mchitale@ventanamicro.com>,
linux@yadro.com,
"Genevieve Chan" <genevieve.chan@starfivetech.com>,
"João Mário Domingos" <joao.mario@tecnico.ulisboa.pt>,
"Nikita Shubin" <n.shubin@yadro.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Ingo Molnar" <mingo@redhat.com>,
"Mark Rutland" <mark.rutland@arm.com>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Jiri Olsa" <jolsa@kernel.org>,
"Namhyung Kim" <namhyung@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
"Kautuk Consul" <kconsul@ventanamicro.com>
Subject: Re: [PATCH v5] perf arch events: riscv sbi firmware std event files
Date: Fri, 12 Aug 2022 16:41:31 -0300 [thread overview]
Message-ID: <Yvas60duFUkSzuz+@kernel.org> (raw)
In-Reply-To: <20220811112303.4e5f0566@redslave.neermore.group>
Em Thu, Aug 11, 2022 at 11:23:03AM +0300, Nikita Shubin escreveu:
> Hello Mayuresh!
>
> On Wed, 10 Aug 2022 20:26:18 +0530
> Mayuresh Chitale <mchitale@ventanamicro.com> wrote:
>
> > On Tue, 2022-06-28 at 14:45 +0300, Nikita Shubin wrote:
> > > From: Nikita Shubin <n.shubin@yadro.com>
> > >
> > > Firmware events are defined by "RISC-V Supervisor Binary Interface
> > > Specification", which means they should be always available as long
> > > as
> > > firmware supports >= 0.3.0 SBI.
> > >
> > > Expose them to arch std events, so they can be reused by particular
> > > PMU bindings.
> > >
> > > Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
> > > ---
> > > v4->v5:
> > > - changed EventCode to ConfigCode, as 63 bit exceeds event code
> > > format
> > > ---
> > > .../arch/riscv/riscv-sbi-firmware.json | 134
> > > ++++++++++++++++++
> > > 1 file changed, 134 insertions(+)
> > > create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-
> > > firmware.json
> > >
> > > diff --git
> > > a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> > > b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json new file
> > > mode 100644 index 000000000000..b9d305f1ada8
> > > --- /dev/null
> > > +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> > > @@ -0,0 +1,134 @@
> > > +[
> > > + {
> > > + "PublicDescription": "Misaligned load trap",
> > > + "ConfigCode": "0x8000000000000000",
> > > + "EventName": "FW_MISALIGNED_LOAD",
> > > + "BriefDescription": "Misaligned load trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Misaligned store trap",
> > > + "ConfigCode": "0x8000000000000001",
> > > + "EventName": "FW_MISALIGNED_STORE",
> > > + "BriefDescription": "Misaligned store trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Load access trap",
> > > + "ConfigCode": "0x8000000000000002",
> > > + "EventName": "FW_ACCESS_LOAD",
> > > + "BriefDescription": "Load access trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Store access trap",
> > > + "ConfigCode": "0x8000000000000003",
> > > + "EventName": "FW_ACCESS_STORE",
> > > + "BriefDescription": "Store access trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Illegal instruction trap",
> > > + "ConfigCode": "0x8000000000000004",
> > > + "EventName": "FW_ILLEGAL_INSN",
> > > + "BriefDescription": "Illegal instruction trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Set timer event",
> > > + "ConfigCode": "0x8000000000000005",
> > > + "EventName": "FW_SET_TIMER",
> > > + "BriefDescription": "Set timer event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent IPI to other HART event",
> > > + "ConfigCode": "0x8000000000000006",
> > > + "EventName": "FW_IPI_SENT",
> > > + "BriefDescription": "Sent IPI to other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received IPI from other HART event",
> > > + "ConfigCode": "0x8000000000000007",
> > > + "EventName": "FW_IPI_RECEIVED",
> > > + "BriefDescription": "Received IPI from other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent FENCE.I request to other HART
> > > event",
> > > + "ConfigCode": "0x8000000000000008",
> > > + "EventName": "FW_FENCE_I_SENT",
> > > + "BriefDescription": "Sent FENCE.I request to other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received FENCE.I request from other HART
> > > event",
> > > + "ConfigCode": "0x8000000000000009",
> > > + "EventName": "FW_FENCE_I_RECEIVED",
> > > + "BriefDescription": "Received FENCE.I request from other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent SFENCE.VMA request to other HART
> > > event",
> > > + "ConfigCode": "0x80000000000000a",
> > > + "EventName": "FW_SFENCE_VMA_SENT",
> > > + "BriefDescription": "Sent SFENCE.VMA request to other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received SFENCE.VMA request from other
> > > HART event",
> > > + "ConfigCode": "0x800000000000000b",
> > > + "EventName": "FW_SFENCE_VMA_RECEIVED",
> > > + "BriefDescription": "Received SFENCE.VMA request from other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent SFENCE.VMA with ASID request to
> > > other HART event",
> > > + "ConfigCode": "0x800000000000000c",
> > > + "EventName": "FW_SFENCE_VMA_RECEIVED",
> > > + "BriefDescription": "Sent SFENCE.VMA with ASID request to other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received SFENCE.VMA with ASID request
> > > from other HART event",
> > > + "ConfigCode": "0x800000000000000d",
> > > + "EventName": "FW_SFENCE_VMA_ASID_RECEIVED",
> > > + "BriefDescription": "Received SFENCE.VMA with ASID request from
> > > other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.GVMA request to other HART
> > > event",
> > > + "ConfigCode": "0x800000000000000e",
> > > + "EventName": "FW_HFENCE_GVMA_SENT",
> > > + "BriefDescription": "Sent HFENCE.GVMA request to other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.GVMA request from other
> > > HART event",
> > > + "ConfigCode": "0x800000000000000f",
> > > + "EventName": "FW_HFENCE_GVMA_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.GVMA request from other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.GVMA with VMID request to
> > > other HART event",
> > > + "ConfigCode": "0x8000000000000010",
> > > + "EventName": "FW_HFENCE_GVMA_VMID_SENT",
> > > + "BriefDescription": "Sent HFENCE.GVMA with VMID request to
> > > other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.GVMA with VMID request
> > > from other HART event",
> > > + "ConfigCode": "0x8000000000000011",
> > > + "EventName": "FW_HFENCE_GVMA_VMID_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.GVMA with VMID request
> > > from other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.VVMA request to other HART
> > > event",
> > > + "ConfigCode": "0x8000000000000012",
> > > + "EventName": "FW_HFENCE_VVMA_SENT",
> > > + "BriefDescription": "Sent HFENCE.VVMA request to other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.VVMA request from other
> > > HART event",
> > > + "ConfigCode": "0x8000000000000013",
> > > + "EventName": "FW_HFENCE_VVMA_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.VVMA request from other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.VVMA with ASID request to
> > > other HART event",
> > > + "ConfigCode": "0x8000000000000014",
> > > + "EventName": "FW_HFENCE_VVMA_ASID_SENT",
> > > + "BriefDescription": "Sent HFENCE.VVMA with ASID request to
> > > other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.VVMA with ASID request
> > > from other HART event",
> > > + "ConfigCode": "0x8000000000000015",
> > > + "EventName": "FW_HFENCE_VVMA_ASID_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.VVMA with ASID request
> > > from other HART event"
> > > + }
> > > +]
> >
> > When testing with perf using firmware events we saw this error:
> > WARNING: event 'N/A' not valid (bits 59 of config '80000000000000a'
> > not supported by kernel)!
> >
> > It looks it is due to a typo and applying the below patch resolved the
> > issue for us.
>
> Thanks for catching this - indeed this is a correct fix.
>
> >
> > Tested-by: Kautuk Consul <kconsul@ventanamicro.com>
>
> Thank you for testing!
Can you please resubmit with the fixes, rebased to the current
acme/perf/core branch?
If I get this today it may even get into v6.0. :-)
Thanks,
- Arnaldo
WARNING: multiple messages have this Message-ID (diff)
From: Arnaldo Carvalho de Melo <acme@kernel.org>
To: Nikita Shubin <nikita.shubin@maquefel.me>
Cc: "Mayuresh Chitale" <mchitale@ventanamicro.com>,
linux@yadro.com,
"Genevieve Chan" <genevieve.chan@starfivetech.com>,
"João Mário Domingos" <joao.mario@tecnico.ulisboa.pt>,
"Nikita Shubin" <n.shubin@yadro.com>,
"Peter Zijlstra" <peterz@infradead.org>,
"Ingo Molnar" <mingo@redhat.com>,
"Mark Rutland" <mark.rutland@arm.com>,
"Alexander Shishkin" <alexander.shishkin@linux.intel.com>,
"Jiri Olsa" <jolsa@kernel.org>,
"Namhyung Kim" <namhyung@kernel.org>,
"Paul Walmsley" <paul.walmsley@sifive.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Albert Ou" <aou@eecs.berkeley.edu>,
linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org,
linux-riscv@lists.infradead.org,
"Kautuk Consul" <kconsul@ventanamicro.com>
Subject: Re: [PATCH v5] perf arch events: riscv sbi firmware std event files
Date: Fri, 12 Aug 2022 16:41:31 -0300 [thread overview]
Message-ID: <Yvas60duFUkSzuz+@kernel.org> (raw)
In-Reply-To: <20220811112303.4e5f0566@redslave.neermore.group>
Em Thu, Aug 11, 2022 at 11:23:03AM +0300, Nikita Shubin escreveu:
> Hello Mayuresh!
>
> On Wed, 10 Aug 2022 20:26:18 +0530
> Mayuresh Chitale <mchitale@ventanamicro.com> wrote:
>
> > On Tue, 2022-06-28 at 14:45 +0300, Nikita Shubin wrote:
> > > From: Nikita Shubin <n.shubin@yadro.com>
> > >
> > > Firmware events are defined by "RISC-V Supervisor Binary Interface
> > > Specification", which means they should be always available as long
> > > as
> > > firmware supports >= 0.3.0 SBI.
> > >
> > > Expose them to arch std events, so they can be reused by particular
> > > PMU bindings.
> > >
> > > Signed-off-by: Nikita Shubin <n.shubin@yadro.com>
> > > ---
> > > v4->v5:
> > > - changed EventCode to ConfigCode, as 63 bit exceeds event code
> > > format
> > > ---
> > > .../arch/riscv/riscv-sbi-firmware.json | 134
> > > ++++++++++++++++++
> > > 1 file changed, 134 insertions(+)
> > > create mode 100644 tools/perf/pmu-events/arch/riscv/riscv-sbi-
> > > firmware.json
> > >
> > > diff --git
> > > a/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> > > b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json new file
> > > mode 100644 index 000000000000..b9d305f1ada8
> > > --- /dev/null
> > > +++ b/tools/perf/pmu-events/arch/riscv/riscv-sbi-firmware.json
> > > @@ -0,0 +1,134 @@
> > > +[
> > > + {
> > > + "PublicDescription": "Misaligned load trap",
> > > + "ConfigCode": "0x8000000000000000",
> > > + "EventName": "FW_MISALIGNED_LOAD",
> > > + "BriefDescription": "Misaligned load trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Misaligned store trap",
> > > + "ConfigCode": "0x8000000000000001",
> > > + "EventName": "FW_MISALIGNED_STORE",
> > > + "BriefDescription": "Misaligned store trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Load access trap",
> > > + "ConfigCode": "0x8000000000000002",
> > > + "EventName": "FW_ACCESS_LOAD",
> > > + "BriefDescription": "Load access trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Store access trap",
> > > + "ConfigCode": "0x8000000000000003",
> > > + "EventName": "FW_ACCESS_STORE",
> > > + "BriefDescription": "Store access trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Illegal instruction trap",
> > > + "ConfigCode": "0x8000000000000004",
> > > + "EventName": "FW_ILLEGAL_INSN",
> > > + "BriefDescription": "Illegal instruction trap event"
> > > + },
> > > + {
> > > + "PublicDescription": "Set timer event",
> > > + "ConfigCode": "0x8000000000000005",
> > > + "EventName": "FW_SET_TIMER",
> > > + "BriefDescription": "Set timer event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent IPI to other HART event",
> > > + "ConfigCode": "0x8000000000000006",
> > > + "EventName": "FW_IPI_SENT",
> > > + "BriefDescription": "Sent IPI to other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received IPI from other HART event",
> > > + "ConfigCode": "0x8000000000000007",
> > > + "EventName": "FW_IPI_RECEIVED",
> > > + "BriefDescription": "Received IPI from other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent FENCE.I request to other HART
> > > event",
> > > + "ConfigCode": "0x8000000000000008",
> > > + "EventName": "FW_FENCE_I_SENT",
> > > + "BriefDescription": "Sent FENCE.I request to other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received FENCE.I request from other HART
> > > event",
> > > + "ConfigCode": "0x8000000000000009",
> > > + "EventName": "FW_FENCE_I_RECEIVED",
> > > + "BriefDescription": "Received FENCE.I request from other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent SFENCE.VMA request to other HART
> > > event",
> > > + "ConfigCode": "0x80000000000000a",
> > > + "EventName": "FW_SFENCE_VMA_SENT",
> > > + "BriefDescription": "Sent SFENCE.VMA request to other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received SFENCE.VMA request from other
> > > HART event",
> > > + "ConfigCode": "0x800000000000000b",
> > > + "EventName": "FW_SFENCE_VMA_RECEIVED",
> > > + "BriefDescription": "Received SFENCE.VMA request from other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent SFENCE.VMA with ASID request to
> > > other HART event",
> > > + "ConfigCode": "0x800000000000000c",
> > > + "EventName": "FW_SFENCE_VMA_RECEIVED",
> > > + "BriefDescription": "Sent SFENCE.VMA with ASID request to other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received SFENCE.VMA with ASID request
> > > from other HART event",
> > > + "ConfigCode": "0x800000000000000d",
> > > + "EventName": "FW_SFENCE_VMA_ASID_RECEIVED",
> > > + "BriefDescription": "Received SFENCE.VMA with ASID request from
> > > other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.GVMA request to other HART
> > > event",
> > > + "ConfigCode": "0x800000000000000e",
> > > + "EventName": "FW_HFENCE_GVMA_SENT",
> > > + "BriefDescription": "Sent HFENCE.GVMA request to other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.GVMA request from other
> > > HART event",
> > > + "ConfigCode": "0x800000000000000f",
> > > + "EventName": "FW_HFENCE_GVMA_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.GVMA request from other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.GVMA with VMID request to
> > > other HART event",
> > > + "ConfigCode": "0x8000000000000010",
> > > + "EventName": "FW_HFENCE_GVMA_VMID_SENT",
> > > + "BriefDescription": "Sent HFENCE.GVMA with VMID request to
> > > other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.GVMA with VMID request
> > > from other HART event",
> > > + "ConfigCode": "0x8000000000000011",
> > > + "EventName": "FW_HFENCE_GVMA_VMID_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.GVMA with VMID request
> > > from other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.VVMA request to other HART
> > > event",
> > > + "ConfigCode": "0x8000000000000012",
> > > + "EventName": "FW_HFENCE_VVMA_SENT",
> > > + "BriefDescription": "Sent HFENCE.VVMA request to other HART
> > > event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.VVMA request from other
> > > HART event",
> > > + "ConfigCode": "0x8000000000000013",
> > > + "EventName": "FW_HFENCE_VVMA_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.VVMA request from other
> > > HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Sent HFENCE.VVMA with ASID request to
> > > other HART event",
> > > + "ConfigCode": "0x8000000000000014",
> > > + "EventName": "FW_HFENCE_VVMA_ASID_SENT",
> > > + "BriefDescription": "Sent HFENCE.VVMA with ASID request to
> > > other HART event"
> > > + },
> > > + {
> > > + "PublicDescription": "Received HFENCE.VVMA with ASID request
> > > from other HART event",
> > > + "ConfigCode": "0x8000000000000015",
> > > + "EventName": "FW_HFENCE_VVMA_ASID_RECEIVED",
> > > + "BriefDescription": "Received HFENCE.VVMA with ASID request
> > > from other HART event"
> > > + }
> > > +]
> >
> > When testing with perf using firmware events we saw this error:
> > WARNING: event 'N/A' not valid (bits 59 of config '80000000000000a'
> > not supported by kernel)!
> >
> > It looks it is due to a typo and applying the below patch resolved the
> > issue for us.
>
> Thanks for catching this - indeed this is a correct fix.
>
> >
> > Tested-by: Kautuk Consul <kconsul@ventanamicro.com>
>
> Thank you for testing!
Can you please resubmit with the fixes, rebased to the current
acme/perf/core branch?
If I get this today it may even get into v6.0. :-)
Thanks,
- Arnaldo
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-08-12 19:41 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-28 11:45 [PATCH v5 0/4] RISC-V: Create unique identification for SoC PMU Nikita Shubin
2022-06-28 11:45 ` Nikita Shubin
2022-06-28 11:45 ` Nikita Shubin
2022-06-28 11:45 ` [PATCH v5 1/4] drivers/perf: riscv_pmu_sbi: perf format Nikita Shubin
2022-06-28 11:45 ` Nikita Shubin
2022-06-28 11:45 ` Nikita Shubin
2022-06-28 11:45 ` [PATCH v5] perf tools riscv: Add support for get_cpuid_str function Nikita Shubin
2022-06-28 11:45 ` Nikita Shubin
2022-06-28 11:45 ` [PATCH v5] perf arch events: riscv sbi firmware std event files Nikita Shubin
2022-06-28 11:45 ` Nikita Shubin
2022-08-10 14:56 ` Mayuresh Chitale
2022-08-10 14:56 ` Mayuresh Chitale
2022-08-11 8:23 ` Nikita Shubin
2022-08-11 8:23 ` Nikita Shubin
2022-08-12 19:41 ` Arnaldo Carvalho de Melo [this message]
2022-08-12 19:41 ` Arnaldo Carvalho de Melo
2022-08-15 13:27 ` Nikita Shubin
2022-08-15 13:27 ` Nikita Shubin
2022-08-16 19:25 ` Arnaldo Carvalho de Melo
2022-08-16 19:25 ` Arnaldo Carvalho de Melo
2022-06-28 11:45 ` [PATCH v5 4/4] perf vendor events riscv: add Sifive U74 JSON file Nikita Shubin
2022-06-28 11:45 ` Nikita Shubin
2022-07-06 16:50 ` [PATCH v5 0/4] RISC-V: Create unique identification for SoC PMU Will Deacon
2022-07-06 16:50 ` Will Deacon
2022-07-06 16:50 ` Will Deacon
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=Yvas60duFUkSzuz+@kernel.org \
--to=acme@kernel.org \
--cc=alexander.shishkin@linux.intel.com \
--cc=aou@eecs.berkeley.edu \
--cc=genevieve.chan@starfivetech.com \
--cc=joao.mario@tecnico.ulisboa.pt \
--cc=jolsa@kernel.org \
--cc=kconsul@ventanamicro.com \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux@yadro.com \
--cc=mark.rutland@arm.com \
--cc=mchitale@ventanamicro.com \
--cc=mingo@redhat.com \
--cc=n.shubin@yadro.com \
--cc=namhyung@kernel.org \
--cc=nikita.shubin@maquefel.me \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=peterz@infradead.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.