[PATCH 0/4] r8a779f0: enable MSIOF

[PATCH 0/4] r8a779f0: enable MSIOF

[Wolfram Sang]

Here are the clk and DTS patches to enable MSIOF on R-Car S4-8 and the
Spider board.

I could only test MSIOF0 and 2 which worked fine. MSIOF1 and 3 are in
parallel with the FTDIs for the debug consoles. So, likely because of
that, reading data always results in zeroes.

There are questions left in patch 1+2.

Looking forward to comments,

   Wolfram

Duc Nguyen (1):
  arm64: dts: renesas: r8a779f0: Add MSIOF nodes

Wolfram Sang (3):
  clk: renesas: r8a779f0: Add MSIOF clocks
  arm64: dts: renesas: spider-cpu: Add MSIOF node
  TEST: arm64: dts: renesas: spider: Add MSIOF node

 .../boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 12 ++++
 .../boot/dts/renesas/r8a779f0-spider.dts      |  8 +++
 arch/arm64/boot/dts/renesas/r8a779f0.dtsi     | 72 +++++++++++++++++++
 drivers/clk/renesas/r8a779f0-cpg-mssr.c       |  4 ++
 4 files changed, 96 insertions(+)

-- 
2.35.1

[PATCH 1/4] clk: renesas: r8a779f0: Add MSIOF clocks

[Wolfram Sang]

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

For V3U, we also used "msiX" as clock names, so I followed that. I
wonder, though, if we shouldn't keep using "msiofX" and rename V3U as
well?

 drivers/clk/renesas/r8a779f0-cpg-mssr.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/renesas/r8a779f0-cpg-mssr.c b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
index 0faf13060ce8..adaed73097d7 100644
--- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
+++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
@@ -131,6 +131,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
 	DEF_MOD("i2c3",		521,	R8A779F0_CLK_S0D6_PER),
 	DEF_MOD("i2c4",		522,	R8A779F0_CLK_S0D6_PER),
 	DEF_MOD("i2c5",		523,	R8A779F0_CLK_S0D6_PER),
+	DEF_MOD("msi0",		618,	R8A779F0_CLK_MSO),
+	DEF_MOD("msi1",		619,	R8A779F0_CLK_MSO),
+	DEF_MOD("msi2",		620,	R8A779F0_CLK_MSO),
+	DEF_MOD("msi3",		621,	R8A779F0_CLK_MSO),
 	DEF_MOD("pcie0",	624,	R8A779F0_CLK_S0D2),
 	DEF_MOD("pcie1",	625,	R8A779F0_CLK_S0D2),
 	DEF_MOD("scif0",	702,	R8A779F0_CLK_S0D12_PER),
-- 
2.35.1

Re: [PATCH 1/4] clk: renesas: r8a779f0: Add MSIOF clocks

[Geert Uytterhoeven]

Hi Wolfram,

On Wed, Aug 24, 2022 at 12:36 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> ---
> For V3U, we also used "msiX" as clock names, so I followed that. I
> wonder, though, if we shouldn't keep using "msiofX" and rename V3U as
> well?

I think we should use "msiofX" for R-Car S4, as that's what's used
in the documentation.  I can fix that while applying.
On R-Car V3U we used "msiX", to follow the documentation.

> --- a/drivers/clk/renesas/r8a779f0-cpg-mssr.c
> +++ b/drivers/clk/renesas/r8a779f0-cpg-mssr.c
> @@ -131,6 +131,10 @@ static const struct mssr_mod_clk r8a779f0_mod_clks[] __initconst = {
>         DEF_MOD("i2c3",         521,    R8A779F0_CLK_S0D6_PER),
>         DEF_MOD("i2c4",         522,    R8A779F0_CLK_S0D6_PER),
>         DEF_MOD("i2c5",         523,    R8A779F0_CLK_S0D6_PER),
> +       DEF_MOD("msi0",         618,    R8A779F0_CLK_MSO),
> +       DEF_MOD("msi1",         619,    R8A779F0_CLK_MSO),
> +       DEF_MOD("msi2",         620,    R8A779F0_CLK_MSO),
> +       DEF_MOD("msi3",         621,    R8A779F0_CLK_MSO),
>         DEF_MOD("pcie0",        624,    R8A779F0_CLK_S0D2),
>         DEF_MOD("pcie1",        625,    R8A779F0_CLK_S0D2),
>         DEF_MOD("scif0",        702,    R8A779F0_CLK_S0D12_PER),

Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v6.1, with the clock names fixed.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 1/4] clk: renesas: r8a779f0: Add MSIOF clocks

[Wolfram Sang]

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Hi Geert,

> > For V3U, we also used "msiX" as clock names, so I followed that. I
> > wonder, though, if we shouldn't keep using "msiofX" and rename V3U as
> > well?
> 
> I think we should use "msiofX" for R-Car S4, as that's what's used
> in the documentation.  I can fix that while applying.
> On R-Car V3U we used "msiX", to follow the documentation.

Ok. Thank you for the clarification and the assistance!

Happy hacking,

   Wolfram

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[PATCH 2/4] arm64: dts: renesas: r8a779f0: Add MSIOF nodes

[Wolfram Sang]

From: Duc Nguyen <duc.nguyen.ub@renesas.com>

Add MSIOF nodes for R-Car S4-8.

Signed-off-by: Duc Nguyen <duc.nguyen.ub@renesas.com>
[thanh: added DMA and assigned-clock-rates]
Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
[wsa: removed mso clock from clocks-property]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---

Do we want the "assigned-clocks" here?

 arch/arm64/boot/dts/renesas/r8a779f0.dtsi | 72 +++++++++++++++++++++++
 1 file changed, 72 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
index 5aff5a23cf06..3a8e052be64b 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0.dtsi
@@ -654,6 +654,78 @@ scif4: serial@e6c40000 {
 			status = "disabled";
 		};
 
+		msiof0: spi@e6e90000 {
+			compatible = "renesas,msiof-r8a779f0",
+				     "renesas,rcar-gen4-msiof";
+			reg = <0 0xe6e90000 0 0x0064>;
+			interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 618>;
+			assigned-clocks = <&cpg CPG_CORE R8A779F0_CLK_MSO>;
+			assigned-clock-rates = <20000000>;
+			dmas = <&dmac0 0x41>, <&dmac0 0x40>,
+			       <&dmac1 0x41>, <&dmac1 0x40>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 618>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof1: spi@e6ea0000 {
+			compatible = "renesas,msiof-r8a779f0",
+				     "renesas,rcar-gen4-msiof";
+			reg = <0 0xe6ea0000 0 0x0064>;
+			interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 619>;
+			assigned-clocks = <&cpg CPG_CORE R8A779F0_CLK_MSO>;
+			assigned-clock-rates = <20000000>;
+			dmas = <&dmac0 0x43>, <&dmac0 0x42>,
+			       <&dmac1 0x43>, <&dmac1 0x42>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 619>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof2: spi@e6c00000 {
+			compatible = "renesas,msiof-r8a779f0",
+				     "renesas,rcar-gen4-msiof";
+			reg = <0 0xe6c00000 0 0x0064>;
+			interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 620>;
+			assigned-clocks = <&cpg CPG_CORE R8A779F0_CLK_MSO>;
+			assigned-clock-rates = <20000000>;
+			dmas = <&dmac0 0x45>, <&dmac0 0x44>,
+			       <&dmac1 0x45>, <&dmac1 0x44>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 620>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		msiof3: spi@e6c10000 {
+			compatible = "renesas,msiof-r8a779f0",
+				     "renesas,rcar-gen4-msiof";
+			reg = <0 0xe6c10000 0 0x0064>;
+			interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+			clocks = <&cpg CPG_MOD 621>;
+			assigned-clocks = <&cpg CPG_CORE R8A779F0_CLK_MSO>;
+			assigned-clock-rates = <20000000>;
+			dmas = <&dmac0 0x47>, <&dmac0 0x46>,
+			       <&dmac1 0x47>, <&dmac1 0x46>;
+			dma-names = "tx", "rx", "tx", "rx";
+			power-domains = <&sysc R8A779F0_PD_ALWAYS_ON>;
+			resets = <&cpg 621>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
 		dmac0: dma-controller@e7350000 {
 			compatible = "renesas,dmac-r8a779f0",
 				     "renesas,rcar-gen4-dmac";
-- 
2.35.1

Re: [PATCH 2/4] arm64: dts: renesas: r8a779f0: Add MSIOF nodes

[Geert Uytterhoeven]

Hi Wolfram,

On Wed, Aug 24, 2022 at 12:36 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> From: Duc Nguyen <duc.nguyen.ub@renesas.com>
>
> Add MSIOF nodes for R-Car S4-8.
>
> Signed-off-by: Duc Nguyen <duc.nguyen.ub@renesas.com>
> [thanh: added DMA and assigned-clock-rates]
> Signed-off-by: Thanh Quan <thanh.quan.xn@renesas.com>
> [wsa: removed mso clock from clocks-property]
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> Do we want the "assigned-clocks" here?

No we do not, as these are board-specific.

With these removed:
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 3/4] arm64: dts: renesas: spider-cpu: Add MSIOF node

[Wolfram Sang]

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
index 8075959cccee..f4428a35a548 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
@@ -101,6 +101,12 @@ &mmc0 {
 	status = "okay";
 };
 
+&msiof0 {
+	pinctrl-0 = <&msiof0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &pfc {
 	pinctrl-0 = <&scif_clk_pins>;
 	pinctrl-names = "default";
@@ -116,6 +122,12 @@ mmc_pins: mmc {
 		power-source = <1800>;
 	};
 
+	msiof0_pins: msiof0 {
+		groups = "msiof0_clk", "msiof0_sync", "msiof0_rxd",
+			 "msiof0_txd", "msiof0_ss1", "msiof0_ss2";
+		function = "msiof0";
+	};
+
 	scif0_pins: scif0 {
 		groups = "scif0_data", "scif0_ctrl";
 		function = "scif0";
-- 
2.35.1

Re: [PATCH 3/4] arm64: dts: renesas: spider-cpu: Add MSIOF node

[Geert Uytterhoeven]

Hi Wolfram,

On Wed, Aug 24, 2022 at 12:36 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>

Thanks for your patch!

> --- a/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider-cpu.dtsi
> @@ -101,6 +101,12 @@ &mmc0 {
>         status = "okay";
>  };
>
> +&msiof0 {
> +       pinctrl-0 = <&msiof0_pins>;
> +       pinctrl-names = "default";
> +       status = "okay";
> +};

I assume you added this becomes Spider has an MSIOF pin header?

> +
>  &pfc {
>         pinctrl-0 = <&scif_clk_pins>;
>         pinctrl-names = "default";
> @@ -116,6 +122,12 @@ mmc_pins: mmc {
>                 power-source = <1800>;
>         };
>
> +       msiof0_pins: msiof0 {
> +               groups = "msiof0_clk", "msiof0_sync", "msiof0_rxd",
> +                        "msiof0_txd", "msiof0_ss1", "msiof0_ss2";

MSIOF0_SS2 is also used as the VDDQ18_33_SPI voltage selector, which
is used as the power source for various components (but not available
on the MSIOF0 pin header?), so I'm a but reluctant to add this patch...

> +               function = "msiof0";
> +       };
> +
>         scif0_pins: scif0 {
>                 groups = "scif0_data", "scif0_ctrl";
>                 function = "scif0";

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/4] arm64: dts: renesas: spider-cpu: Add MSIOF node

[Wolfram Sang]

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Hi Geert,

> > +&msiof0 {
> > +       pinctrl-0 = <&msiof0_pins>;
> > +       pinctrl-names = "default";
> > +       status = "okay";
> > +};
> 
> I assume you added this becomes Spider has an MSIOF pin header?

Yes, that is one reason. It has it on the extension board. On the CPU
board, MSIOF0 is also connected to the CPLD.

> > +
> >  &pfc {
> >         pinctrl-0 = <&scif_clk_pins>;
> >         pinctrl-names = "default";
> > @@ -116,6 +122,12 @@ mmc_pins: mmc {
> >                 power-source = <1800>;
> >         };
> >
> > +       msiof0_pins: msiof0 {
> > +               groups = "msiof0_clk", "msiof0_sync", "msiof0_rxd",
> > +                        "msiof0_txd", "msiof0_ss1", "msiof0_ss2";
> 
> MSIOF0_SS2 is also used as the VDDQ18_33_SPI voltage selector, which
> is used as the power source for various components (but not available
> on the MSIOF0 pin header?), so I'm a but reluctant to add this patch...

Uh, you are right with the voltage selector. I missed that, sorry.
However, it is present on the MSIOF0 connector at pin 1. My suggestion
is to remove SS2 from the PFC node and add a comment describing the
situation?

All the best,

   Wolfram


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Re: [PATCH 3/4] arm64: dts: renesas: spider-cpu: Add MSIOF node

[Geert Uytterhoeven]

Hi Wolfram,

On Mon, Aug 29, 2022 at 1:11 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> > > +&msiof0 {
> > > +       pinctrl-0 = <&msiof0_pins>;
> > > +       pinctrl-names = "default";
> > > +       status = "okay";
> > > +};
> >
> > I assume you added this becomes Spider has an MSIOF pin header?
>
> Yes, that is one reason. It has it on the extension board. On the CPU
> board, MSIOF0 is also connected to the CPLD.
>
> > > +
> > >  &pfc {
> > >         pinctrl-0 = <&scif_clk_pins>;
> > >         pinctrl-names = "default";
> > > @@ -116,6 +122,12 @@ mmc_pins: mmc {
> > >                 power-source = <1800>;
> > >         };
> > >
> > > +       msiof0_pins: msiof0 {
> > > +               groups = "msiof0_clk", "msiof0_sync", "msiof0_rxd",
> > > +                        "msiof0_txd", "msiof0_ss1", "msiof0_ss2";
> >
> > MSIOF0_SS2 is also used as the VDDQ18_33_SPI voltage selector, which
> > is used as the power source for various components (but not available
> > on the MSIOF0 pin header?), so I'm a but reluctant to add this patch...
>
> Uh, you are right with the voltage selector. I missed that, sorry.
> However, it is present on the MSIOF0 connector at pin 1. My suggestion
> is to remove SS2 from the PFC node and add a comment describing the
> situation?

SS2 is available on the connector, but the power source (VDDQ18_33_SPI)
is not.

So my preference is to leave MSIOF0 alone.

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH 3/4] arm64: dts: renesas: spider-cpu: Add MSIOF node

[Wolfram Sang]

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> So my preference is to leave MSIOF0 alone.

So, I just resend patch2 with assigned-clocks removed?


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Re: [PATCH 3/4] arm64: dts: renesas: spider-cpu: Add MSIOF node

[Geert Uytterhoeven]

Hi Wolfram,

On Mon, Aug 29, 2022 at 1:51 PM Wolfram Sang
<wsa+renesas@sang-engineering.com> wrote:
> > So my preference is to leave MSIOF0 alone.
>
> So, I just resend patch2 with assigned-clocks removed?

I think that's the best approach to take. Thanks!

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

[PATCH 4/4] TEST: arm64: dts: renesas: spider: Add MSIOF node

[Wolfram Sang]

Activate spidev on the MSIOF0 connector on the breakout board.
Not for upstream!

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
---
 arch/arm64/boot/dts/renesas/r8a779f0-spider.dts | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
index 7a7c8ffba711..20803dcf73dc 100644
--- a/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
+++ b/arch/arm64/boot/dts/renesas/r8a779f0-spider.dts
@@ -31,3 +31,11 @@ eeprom@51 {
 		pagesize = <8>;
 	};
 };
+
+&msiof0 {
+	spidev@0  {
+		compatible = "rohm,dh2228fv";
+		reg = <0>;
+		spi-max-frequency = <400000>;
+	};
+};
-- 
2.35.1