From: Oliver Upton <oliver.upton@linux.dev>
To: Andrew Jones <andrew.jones@linux.dev>
Cc: kvm@vger.kernel.org, Marc Zyngier <maz@kernel.org>,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org,
Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>,
kvmarm@lists.cs.columbia.edu,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v2 7/7] KVM: selftests: Add test for RAZ/WI AArch32 ID registers
Date: Tue, 6 Sep 2022 05:54:40 +0100 [thread overview]
Message-ID: <YxbSkCMxZdwKGqQM@google.com> (raw)
In-Reply-To: <20220905073140.lrsrbyu2zhkiki5a@kamzik>
Hi Drew,
On Mon, Sep 05, 2022 at 09:31:40AM +0200, Andrew Jones wrote:
[...]
> > +static uint64_t reg_ids[] = {
> > + KVM_ARM64_SYS_REG(SYS_ID_PFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_PFR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR3_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR3_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR4_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR5_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR4_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR6_EL1),
> > + KVM_ARM64_SYS_REG(SYS_MVFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_MVFR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_MVFR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_PFR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR5_EL1),
>
> Hi Oliver,
>
> I see all the hidden and unallocated registers have been filtered out of
> the test lists. They should also behave as RAZ, right? Maybe we should
> keep them in the lists here for consistency and to test them as well.
Sure, can do. The reason I only tested these registers is because they
have RAZ/WI behavior with this series, whereas the rest are RAZ +
invariant. Should be easy enough to cover the whole range, though.
--
Thanks,
Oliver
_______________________________________________
kvmarm mailing list
kvmarm@lists.cs.columbia.edu
https://lists.cs.columbia.edu/mailman/listinfo/kvmarm
WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oliver.upton@linux.dev>
To: Andrew Jones <andrew.jones@linux.dev>
Cc: Marc Zyngier <maz@kernel.org>, James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
Reiji Watanabe <reijiw@google.com>,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 7/7] KVM: selftests: Add test for RAZ/WI AArch32 ID registers
Date: Tue, 6 Sep 2022 05:54:40 +0100 [thread overview]
Message-ID: <YxbSkCMxZdwKGqQM@google.com> (raw)
In-Reply-To: <20220905073140.lrsrbyu2zhkiki5a@kamzik>
Hi Drew,
On Mon, Sep 05, 2022 at 09:31:40AM +0200, Andrew Jones wrote:
[...]
> > +static uint64_t reg_ids[] = {
> > + KVM_ARM64_SYS_REG(SYS_ID_PFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_PFR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR3_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR3_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR4_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR5_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR4_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR6_EL1),
> > + KVM_ARM64_SYS_REG(SYS_MVFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_MVFR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_MVFR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_PFR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR5_EL1),
>
> Hi Oliver,
>
> I see all the hidden and unallocated registers have been filtered out of
> the test lists. They should also behave as RAZ, right? Maybe we should
> keep them in the lists here for consistency and to test them as well.
Sure, can do. The reason I only tested these registers is because they
have RAZ/WI behavior with this series, whereas the rest are RAZ +
invariant. Should be easy enough to cover the whole range, though.
--
Thanks,
Oliver
WARNING: multiple messages have this Message-ID (diff)
From: Oliver Upton <oliver.upton@linux.dev>
To: Andrew Jones <andrew.jones@linux.dev>
Cc: Marc Zyngier <maz@kernel.org>, James Morse <james.morse@arm.com>,
Alexandru Elisei <alexandru.elisei@arm.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Shuah Khan <shuah@kernel.org>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
linux-arm-kernel@lists.infradead.org,
kvmarm@lists.cs.columbia.edu, kvm@vger.kernel.org,
Reiji Watanabe <reijiw@google.com>,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org
Subject: Re: [PATCH v2 7/7] KVM: selftests: Add test for RAZ/WI AArch32 ID registers
Date: Tue, 6 Sep 2022 05:54:40 +0100 [thread overview]
Message-ID: <YxbSkCMxZdwKGqQM@google.com> (raw)
In-Reply-To: <20220905073140.lrsrbyu2zhkiki5a@kamzik>
Hi Drew,
On Mon, Sep 05, 2022 at 09:31:40AM +0200, Andrew Jones wrote:
[...]
> > +static uint64_t reg_ids[] = {
> > + KVM_ARM64_SYS_REG(SYS_ID_PFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_PFR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_DFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR3_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR3_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR4_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR5_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR4_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_ISAR6_EL1),
> > + KVM_ARM64_SYS_REG(SYS_MVFR0_EL1),
> > + KVM_ARM64_SYS_REG(SYS_MVFR1_EL1),
> > + KVM_ARM64_SYS_REG(SYS_MVFR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_PFR2_EL1),
> > + KVM_ARM64_SYS_REG(SYS_ID_MMFR5_EL1),
>
> Hi Oliver,
>
> I see all the hidden and unallocated registers have been filtered out of
> the test lists. They should also behave as RAZ, right? Maybe we should
> keep them in the lists here for consistency and to test them as well.
Sure, can do. The reason I only tested these registers is because they
have RAZ/WI behavior with this series, whereas the rest are RAZ +
invariant. Should be easy enough to cover the whole range, though.
--
Thanks,
Oliver
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
next prev parent reply other threads:[~2022-09-06 4:54 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-02 15:47 [PATCH v2 0/7] KVM: arm64: Use visibility hook to treat ID regs as RAZ Oliver Upton
2022-09-02 15:47 ` Oliver Upton
2022-09-02 15:47 ` Oliver Upton
2022-09-02 15:47 ` [PATCH v2 1/7] " Oliver Upton
2022-09-02 15:47 ` Oliver Upton
2022-09-02 15:47 ` Oliver Upton
2022-09-02 15:47 ` [PATCH v2 2/7] KVM: arm64: Remove internal accessor helpers for id regs Oliver Upton
2022-09-02 15:47 ` Oliver Upton
2022-09-02 15:47 ` Oliver Upton
2022-09-07 2:00 ` Reiji Watanabe
2022-09-07 2:00 ` Reiji Watanabe
2022-09-07 2:00 ` Reiji Watanabe
2022-09-02 15:47 ` [PATCH v2 3/7] KVM: arm64: Drop raz parameter from read_id_reg() Oliver Upton
2022-09-02 15:47 ` Oliver Upton
2022-09-02 15:47 ` Oliver Upton
2022-09-07 2:26 ` Reiji Watanabe
2022-09-07 2:26 ` Reiji Watanabe
2022-09-07 2:26 ` Reiji Watanabe
2022-09-02 15:48 ` [PATCH v2 4/7] KVM: arm64: Spin off helper for calling visibility hook Oliver Upton
2022-09-02 15:48 ` Oliver Upton
2022-09-02 15:48 ` Oliver Upton
2022-09-02 15:48 ` [PATCH v2 5/7] KVM: arm64: Add a visibility bit to ignore user writes Oliver Upton
2022-09-02 15:48 ` Oliver Upton
2022-09-02 15:48 ` Oliver Upton
2022-09-07 2:40 ` Reiji Watanabe
2022-09-07 2:40 ` Reiji Watanabe
2022-09-07 2:40 ` Reiji Watanabe
2022-09-02 15:48 ` [PATCH v2 6/7] KVM: arm64: Treat 32bit ID registers as RAZ/WI on 64bit-only system Oliver Upton
2022-09-02 15:48 ` Oliver Upton
2022-09-02 15:48 ` Oliver Upton
2022-09-07 4:52 ` Reiji Watanabe
2022-09-07 4:52 ` Reiji Watanabe
2022-09-07 4:52 ` Reiji Watanabe
2022-09-09 10:15 ` Oliver Upton
2022-09-09 10:15 ` Oliver Upton
2022-09-09 10:15 ` Oliver Upton
2022-09-02 15:48 ` [PATCH v2 7/7] KVM: selftests: Add test for RAZ/WI AArch32 ID registers Oliver Upton
2022-09-02 15:48 ` Oliver Upton
2022-09-02 15:48 ` Oliver Upton
2022-09-05 7:31 ` Andrew Jones
2022-09-05 7:31 ` Andrew Jones
2022-09-05 7:31 ` Andrew Jones
2022-09-06 4:54 ` Oliver Upton [this message]
2022-09-06 4:54 ` Oliver Upton
2022-09-06 4:54 ` Oliver Upton
2022-09-02 15:52 ` [PATCH v2 0/7] KVM: arm64: Use visibility hook to treat ID regs as RAZ Oliver Upton
2022-09-02 15:52 ` Oliver Upton
2022-09-02 15:52 ` Oliver Upton
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=YxbSkCMxZdwKGqQM@google.com \
--to=oliver.upton@linux.dev \
--cc=andrew.jones@linux.dev \
--cc=kvm@vger.kernel.org \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-kselftest@vger.kernel.org \
--cc=maz@kernel.org \
--cc=pbonzini@redhat.com \
--cc=shuah@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.