From: Conor Dooley <conor@kernel.org>
To: kvm-riscv@lists.infradead.org
Subject: [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension
Date: Wed, 21 Sep 2022 22:33:46 +0100 [thread overview]
Message-ID: <YyuDOr5dMospSNzF@spud> (raw)
In-Reply-To: <YytwBzdgCSWSPRNB@spud>
On Wed, Sep 21, 2022 at 09:11:56PM +0100, Conor Dooley wrote:
> On Wed, Sep 21, 2022 at 12:46:14PM -0700, Chris Stillson wrote:
>
> Hey Chris,
>
> Looks like this only partially made it to the list. The cover letter is
> missing as are a bunch of the patches in the middle, see:
> https://lore.kernel.org/linux-riscv/20220921194629.1480202-3-stillson at rivosinc.com/T/#t
nvm, rest of it seems to have finally made it through now.
> Also, when you run format-patch to generate the patches, please add the
> `-v` flag with a number so that the patchset gets the version number
> added to it.
>
> Ohh, and Palmer's non-rivos email looks wrong?
Rest still applies though & rerolling as v12 would be nice so that the
tools don't get confused about which version is which since you've now
sent a pair of v1s.
Your SoB is still missing from the individual patches too.
Getting there though, this one is at least threaded & the patches are
not whitespace damaged/line wrapped anymore AFAICT.
Thanks,
Conor.
WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor@kernel.org>
To: Chris Stillson <stillson@rivosinc.com>
Cc: linux-riscv@lists.infradead.org, palmer@dabbelt.com,
kvm-riscv@lists.infradead.org, Guo Ren <ren_guo@c-sky.com>,
Guo Ren <guoren@linux.alibaba.com>,
Anup Patel <anup@brainfault.org>,
Greentime Hu <greentime.hu@sifive.com>,
Palmer Dabbelt <palmer@rivosinc.com>
Subject: Re: [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension
Date: Wed, 21 Sep 2022 22:33:46 +0100 [thread overview]
Message-ID: <YyuDOr5dMospSNzF@spud> (raw)
In-Reply-To: <YytwBzdgCSWSPRNB@spud>
On Wed, Sep 21, 2022 at 09:11:56PM +0100, Conor Dooley wrote:
> On Wed, Sep 21, 2022 at 12:46:14PM -0700, Chris Stillson wrote:
>
> Hey Chris,
>
> Looks like this only partially made it to the list. The cover letter is
> missing as are a bunch of the patches in the middle, see:
> https://lore.kernel.org/linux-riscv/20220921194629.1480202-3-stillson@rivosinc.com/T/#t
nvm, rest of it seems to have finally made it through now.
> Also, when you run format-patch to generate the patches, please add the
> `-v` flag with a number so that the patchset gets the version number
> added to it.
>
> Ohh, and Palmer's non-rivos email looks wrong?
Rest still applies though & rerolling as v12 would be nice so that the
tools don't get confused about which version is which since you've now
sent a pair of v1s.
Your SoB is still missing from the individual patches too.
Getting there though, this one is at least threaded & the patches are
not whitespace damaged/line wrapped anymore AFAICT.
Thanks,
Conor.
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linux-riscv@lists.infradead.org
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next prev parent reply other threads:[~2022-09-21 21:33 UTC|newest]
Thread overview: 41+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-21 19:46 [PATCH 00/17] Prctl to enable vector commands, previous vector patches rebased Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 01/17] riscv: Rename __switch_to_aux -> fpu Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 20:11 ` Conor Dooley
2022-09-21 20:11 ` Conor Dooley
2022-09-21 21:33 ` Conor Dooley [this message]
2022-09-21 21:33 ` Conor Dooley
2022-09-21 19:46 ` [PATCH 03/17] riscv: Add new csr defines related to vector extension Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 04/17] riscv: Add vector feature to compile Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 05/17] riscv: Add has_vector/riscv_vsize to save vector features Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 06/17] riscv: Reset vector register Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 07/17] riscv: Add vector struct and assembler definitions Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 08/17] riscv: Add task switch support for vector Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 09/17] riscv: Add ptrace vector support Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 10/17] riscv: Add sigcontext save/restore for vector Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 11/17] riscv: signal: Report signal frame size to userspace via auxv Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 12/17] riscv: Add support for kernel mode vector Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 13/17] riscv: Add vector extension XOR implementation Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 14/17] riscv: Fix a kernel panic issue if $s2 is set to a specific value before entering Linux Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 15/17] riscv: Add V extension to KVM ISA allow list Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 16/17] riscv: KVM: Add vector lazy save/restore support Chris Stillson
2022-09-21 19:46 ` Chris Stillson
2022-09-21 19:46 ` [PATCH 17/17] riscv: prctl to enable vector commands Chris Stillson
2022-09-21 19:46 ` Chris Stillson
-- strict thread matches above, loose matches on Subject: below --
2022-09-21 16:46 [PATCH 02/17] riscv: Extending cpufeature.c to detect V-extension Chris Stillson
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