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From: Jisheng Zhang <jszhang@kernel.org>
To: Guo Ren <guoren@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Nathan Chancellor <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	llvm@lists.linux.dev
Subject: Re: [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp
Date: Fri, 30 Sep 2022 00:01:42 +0800	[thread overview]
Message-ID: <YzXBZnGXQdEGR1LW@xhacker> (raw)
In-Reply-To: <CAJF2gTTADq-JpUtitSr0nw1aDPZrsB6f1jA-04WmOVcrxYeakw@mail.gmail.com>

On Thu, Sep 29, 2022 at 11:59:00AM +0800, Guo Ren wrote:
> On Thu, Sep 29, 2022 at 12:29 AM Jisheng Zhang <jszhang@kernel.org> wrote:
> >
> > Consolidate the saving/restoring GPs(except ra, sp and tp) into
> > save_gp/restore_gp macro.
> >
> > No functional change intended.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/include/asm/asm.h   | 65 +++++++++++++++++++++++++
> >  arch/riscv/kernel/entry.S      | 87 ++--------------------------------
> >  arch/riscv/kernel/mcount-dyn.S | 58 +----------------------
> >  3 files changed, 70 insertions(+), 140 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
> > index 1b471ff73178..2f3b49536e9d 100644
> > --- a/arch/riscv/include/asm/asm.h
> > +++ b/arch/riscv/include/asm/asm.h
> > @@ -68,6 +68,7 @@
> >  #endif
> >
> >  #ifdef __ASSEMBLY__
> > +#include <asm/asm-offsets.h>
> >
> >  /* Common assembly source macros */
> >
> > @@ -80,6 +81,70 @@
> >         .endr
> >  .endm
> >
> > +       /* save all GPs except ra, sp and tp */
> > +       .macro save_gp
> How about leave x3(gp) out of the macro, and define:
> .marco save_from_x5_to_x31
> .marco restore_from_x5_to_x31

Good idea, will do in next version.

Thanks

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Guo Ren <guoren@kernel.org>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Nathan Chancellor <nathan@kernel.org>,
	Nick Desaulniers <ndesaulniers@google.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	llvm@lists.linux.dev
Subject: Re: [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp
Date: Fri, 30 Sep 2022 00:01:42 +0800	[thread overview]
Message-ID: <YzXBZnGXQdEGR1LW@xhacker> (raw)
In-Reply-To: <CAJF2gTTADq-JpUtitSr0nw1aDPZrsB6f1jA-04WmOVcrxYeakw@mail.gmail.com>

On Thu, Sep 29, 2022 at 11:59:00AM +0800, Guo Ren wrote:
> On Thu, Sep 29, 2022 at 12:29 AM Jisheng Zhang <jszhang@kernel.org> wrote:
> >
> > Consolidate the saving/restoring GPs(except ra, sp and tp) into
> > save_gp/restore_gp macro.
> >
> > No functional change intended.
> >
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > ---
> >  arch/riscv/include/asm/asm.h   | 65 +++++++++++++++++++++++++
> >  arch/riscv/kernel/entry.S      | 87 ++--------------------------------
> >  arch/riscv/kernel/mcount-dyn.S | 58 +----------------------
> >  3 files changed, 70 insertions(+), 140 deletions(-)
> >
> > diff --git a/arch/riscv/include/asm/asm.h b/arch/riscv/include/asm/asm.h
> > index 1b471ff73178..2f3b49536e9d 100644
> > --- a/arch/riscv/include/asm/asm.h
> > +++ b/arch/riscv/include/asm/asm.h
> > @@ -68,6 +68,7 @@
> >  #endif
> >
> >  #ifdef __ASSEMBLY__
> > +#include <asm/asm-offsets.h>
> >
> >  /* Common assembly source macros */
> >
> > @@ -80,6 +81,70 @@
> >         .endr
> >  .endm
> >
> > +       /* save all GPs except ra, sp and tp */
> > +       .macro save_gp
> How about leave x3(gp) out of the macro, and define:
> .marco save_from_x5_to_x31
> .marco restore_from_x5_to_x31

Good idea, will do in next version.

Thanks

  reply	other threads:[~2022-09-29 16:11 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-28 16:20 [PATCH v2 0/4] riscv: entry: further clean up and VMAP_STACK fix Jisheng Zhang
2022-09-28 16:20 ` Jisheng Zhang
2022-09-28 16:20 ` [PATCH v2 1/4] riscv: remove extra level wrappers of trace_hardirqs_{on,off} Jisheng Zhang
2022-09-28 16:20   ` Jisheng Zhang
2022-09-28 16:20 ` [PATCH v2 2/4] riscv: consolidate ret_from_kernel_thread into ret_from_fork Jisheng Zhang
2022-09-28 16:20   ` Jisheng Zhang
2022-10-19  3:37   ` Guo Ren
2022-10-19  3:37     ` Guo Ren
2022-09-28 16:20 ` [PATCH v2 3/4] riscv: fix race when vmap stack overflow and remove shadow_stack Jisheng Zhang
2022-09-28 16:20   ` Jisheng Zhang
2022-09-28 16:54   ` Jisheng Zhang
2022-09-28 16:54     ` Jisheng Zhang
2022-09-29  5:54     ` Guo Ren
2022-09-29  5:54       ` Guo Ren
2022-09-29  6:58       ` Guo Ren
2022-09-29  6:58         ` Guo Ren
2022-09-29 16:18       ` Jisheng Zhang
2022-09-29 16:18         ` Jisheng Zhang
2022-09-30  3:35         ` Guo Ren
2022-09-30  3:35           ` Guo Ren
2022-10-19  2:52       ` Guo Ren
2022-10-19  2:52         ` Guo Ren
2022-10-19 13:05         ` Jisheng Zhang
2022-10-19 13:05           ` Jisheng Zhang
2022-10-20  1:00           ` Guo Ren
2022-10-20  1:00             ` Guo Ren
2022-09-28 16:20 ` [PATCH v2 4/4] riscv: entry: consolidate general regs saving into save_gp Jisheng Zhang
2022-09-28 16:20   ` Jisheng Zhang
2022-09-29  3:59   ` Guo Ren
2022-09-29  3:59     ` Guo Ren
2022-09-29 16:01     ` Jisheng Zhang [this message]
2022-09-29 16:01       ` Jisheng Zhang
2022-10-19  2:55       ` Guo Ren
2022-10-19  2:55         ` Guo Ren
2022-10-19 13:01         ` Jisheng Zhang
2022-10-19 13:01           ` Jisheng Zhang

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