Re: [PATCH v6 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support

From: Vinod Koul <vkoul@kernel.org>
To: Wenbin Yao <quic_wenbyao@quicinc.com>
Cc: kishon@kernel.org, p.zabel@pengutronix.de,
	dmitry.baryshkov@linaro.org, abel.vesa@linaro.org,
	quic_qianyu@quicinc.com, neil.armstrong@linaro.org,
	manivannan.sadhasivam@linaro.org, quic_devipriy@quicinc.com,
	konrad.dybcio@oss.qualcomm.com, linux-arm-msm@vger.kernel.org,
	linux-phy@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v6 0/2] phy: qcom: qmp-pcie: Add PCIe PHY no_csr reset support
Date: Fri, 11 Apr 2025 12:59:44 +0530	[thread overview]
Message-ID: <Z/jE6FzW4MM98hgv@vaman> (raw)
In-Reply-To: <20250319094544.3980357-1-quic_wenbyao@quicinc.com>

On 19-03-25, 17:45, Wenbin Yao wrote:
> The series aims to skip phy register programming and drive PCIe PHY with
> register setting programmed in bootloader by simply toggling no_csr reset,
> which once togglled, PHY hardware will be reset while PHY registers are
> retained.
> 
> First, determine whether PHY setting can be skipped by checking
> QPHY_START_CTRL register and the existence of nocsr reset. If it is
> programmed and no_csr reset is supported, do no_csr reset and skip BCR
> reset which will reset entire PHY.
> 
> This series also remove has_nocsr_reset flag in qmp_phy_cfg structure and
> decide whether the PHY supports nocsr reset by checking the existence of
> nocsr reset in device tree.
> 
> The series are tested on X1E80100-QCP and HDK8550.
> 
> The commit messages of this patchset have been modified based on comments
> and suggestions.

This does not apply for me on phy/next, pls rebase and resend

-- 
~Vinod