From: Tommaso Merciai <tommaso.merciai.xr@bp.renesas.com>
To: Pavel Machek <pavel@denx.de>
Cc: cip-dev@lists.cip-project.org,
Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>,
Biju Das <biju.das.jz@bp.renesas.com>,
Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>,
tomm.merciai@gmail.com
Subject: Re: [PATCH 6.1.y-cip 00/21] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform
Date: Mon, 24 Mar 2025 10:03:51 +0100 [thread overview]
Message-ID: <Z-Ef99PHhg9P9kWP@tom-desktop> (raw)
In-Reply-To: <Z93ILAaLP1+LR2gP@duo.ucw.cz>
Hi Pavel,
Thanks for your comment.
On Fri, Mar 21, 2025 at 09:12:28PM +0100, Pavel Machek wrote:
> Hi!
>
> > This patch series adds initial support for the Renesas RZ/G3E SoC and
> > RZ/G3E SMARC EVK platform to linux-6.1.y-cip kernel. The RZ/G3E device is a
> > general-purpose microprocessor with a quad-core CA-55, single core CM-33,
> > Ethos-U55 NPU, Mali-G52 3-D Graphics and other peripherals.
> >
> > All patches are cherry-picked from mainline kernel.
>
> Ok, thanks for the series, it looks good to me.
>
> Should I simply try to apply it to both 6.1 and 6.12? I guess I can do
> that if there are no other comments.
I tested on my side and I can share that the following patches are needed
to boot the board on top of be95b49207284 (linux-6.12.y-cip):
abf61442f5523 (HEAD) arm64: defconfig: Enable R9A09G047 SoC
5fe2ef2536b4b soc: renesas: Add RZ/G3E (R9A09G047) config option
0b2bbca0cccdc arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board
b39f424adff45 arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM
b1f6a3f53e512 arm64: dts: renesas: r9a09g047: Add OPP table
a89ab4d1d72ad arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC
0545748b50260 clk: renesas: r9a09g047: Add CA55 core clocks
53902b5dba919 clk: renesas: rzv2h: Add support for RZ/G3E SoC
a1721e1ab4092 clk: renesas: rzv2h: Add MSTOP support
c5e58c15e5b02 clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets
6e9acef8a72fd clk: renesas: r9a09g057: Add clock and reset entries for ICU
13f8ef8afecea clk: renesas: r9a09g057: Add CA55 core clocks
f53d5c3439ebf clk: renesas: rzv2h: Add selective Runtime PM support for clocks
510f8e3823b22 dt-bindings: clock: renesas: Document RZ/G3E SoC CPG
bcb927d43ed05 dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK
541305514cdf5 dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants
Patches need some really small rework, (just moving up/down things to be
applied).
Test log:
root@smarc-rzg3e:~# uname -r
6.12.19-00045-gabf61442f552
root@smarc-rzg3e:~# cat /proc/cpuinfo
processor : 0
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 1
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 2
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
processor : 3
BogoMIPS : 48.00
Features : fp asimd evtstrm aes pmull sha1 sha2 crc32 atomics fphp asimdhp cpuid asimdrdm lrcpc dcpop asimddp
CPU implementer : 0x41
CPU architecture: 8
CPU variant : 0x2
CPU part : 0xd05
CPU revision : 0
root@smarc-rzg3e:~# cat /proc/meminfo
MemTotal: 3883788 kB
MemFree: 3569016 kB
MemAvailable: 3503672 kB
root@smarc-rzg3e:~# cat /proc/interrupts
CPU0 CPU1 CPU2 CPU3
11: 5442 5213 7158 10565 GICv3 27 Level arch_timer
14: 0 0 0 0 GICv3 561 Level 11c01400.serial:rx err
15: 1 0 0 0 GICv3 564 Level 11c01400.serial:rx full
16: 1668 0 0 0 GICv3 565 Level 11c01400.serial:tx empty
17: 0 0 0 0 GICv3 562 Level 11c01400.serial:break
18: 116 0 0 0 GICv3 566 Level 11c01400.serial:rx ready
19: 0 0 0 0 GICv3 563 Level 11c01400.serial:tx end
IPI0: 403 479 131 286 Rescheduling interrupts
IPI1: 4293 4511 1482 4291 Function call interrupts
IPI2: 0 0 0 0 CPU stop interrupts
IPI3: 0 0 0 0 CPU stop NMIs
IPI4: 0 0 0 0 Timer broadcast interrupts
IPI5: 447 524 272 565 IRQ work interrupts
IPI6: 0 0 0 0 CPU backtrace interrupts
IPI7: 0 0 0 0 KGDB roundup interrupts
Err: 0
>
> Best regards,
> Pavel
> --
> DENX Software Engineering GmbH, Managing Director: Erika Unter
> HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Thanks & Regards,
Tommaso
next prev parent reply other threads:[~2025-03-24 9:04 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-03-21 11:00 [PATCH 6.1.y-cip 00/21] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 01/21] dt-bindings: soc: renesas: Document Renesas RZ/G3E SoC variants Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 02/21] dt-bindings: soc: renesas: Document RZ/G3E SMARC SoM and Carrier-II EVK Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 03/21] dt-bindings: clock: renesas: Document RZ/V2H(P) SoC CPG Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 04/21] dt-bindings: clock: renesas: Document RZ/G3E " Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 05/21] clk: renesas: Add family-specific clock driver for RZ/V2H(P) Tommaso Merciai
2025-03-21 20:08 ` Pavel Machek
2025-03-21 11:00 ` [PATCH 6.1.y-cip 06/21] clk: renesas: Add RZ/V2H(P) CPG driver Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 07/21] clk: renesas: rzv2h: Add support for dynamic switching divider clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 08/21] clk: renesas: rzv2h: Add selective Runtime PM support for clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 09/21] clk: renesas: r9a09g057: Add clock and reset entries for GTM/RIIC/SDHI/WDT Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 10/21] clk: renesas: r9a09g057: Add CA55 core clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 11/21] clk: renesas: r9a09g057: Add clock and reset entries for ICU Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 12/21] clk: renesas: r9a09g057: Add support for PLLVDO, CRU clocks, and resets Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 13/21] clk: renesas: rzv2h: Add MSTOP support Tommaso Merciai
2025-03-21 20:10 ` Pavel Machek
2025-03-21 11:00 ` [PATCH 6.1.y-cip 14/21] clk: renesas: rzv2h: Add support for RZ/G3E SoC Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 15/21] clk: renesas: r9a09g047: Add CA55 core clocks Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 16/21] arm64: dts: renesas: Add initial DTSI for RZ/G3E SoC Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 17/21] arm64: dts: renesas: r9a09g047: Add OPP table Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 18/21] arm64: dts: renesas: Add initial support for RZ/G3E SMARC SoM Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 19/21] arm64: dts: renesas: Add initial device tree for RZ/G3E SMARC EVK board Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 20/21] soc: renesas: Add RZ/G3E (R9A09G047) config option Tommaso Merciai
2025-03-21 11:00 ` [PATCH 6.1.y-cip 21/21] arm64: defconfig: Enable R9A09G047 SoC Tommaso Merciai
2025-03-21 20:12 ` [PATCH 6.1.y-cip 00/21] Add support for Renesas RZ/G3E SoC and SMARC-EVK platform Pavel Machek
2025-03-24 9:03 ` Tommaso Merciai [this message]
2025-03-24 9:15 ` Pavel Machek
2025-03-26 12:54 ` Pavel Machek
2025-03-26 13:43 ` Tommaso Merciai
2025-03-31 9:07 ` Pavel Machek
2025-03-31 9:54 ` Tommaso Merciai
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