Re: Reset on Beaglebone Black has become unreliable/broken

[Konstantin Kletschke <konstantin.kletschke@inside-m2m.de>]

On Tue, Dec 03, 2024 at 07:46:56PM +0100, Ahmad Fatoum wrote:

> > I can simulate this with "mw 0x44e00f00 0x1" which shows the freeze 
> > I see (upon restart) on affected BBBs.
> 
> This happens without Linux first starting, right? So that invalidates
> my theory of Linux reconfiguring the PMIC to something invalid.

Yesthis is all reproducible without linux being involved.
Applies to S1 connected to NRESET_INOUT (warm restart) and barebox too
(reste cmd, watchdog triggering).

> Nice. Do you know about https://barebox.org/doc/latest/user/system-reset.html ?
> 
> TL;DR: Cold reset is usually the preferred way to reset as it comes
> with the least amount of surprises.

No, not yet. I will investigate.
One could change this for BBB, but the ugly part is, the Hardware on
the BBB forreset, S1, triggers warm restart. Hardwired, if I read
correct.

> What does a cold reset do on an electrical level? Does it tell the PMIC
> to do a reset?

I am not shure, I will investigate.
There is a circle CPU PMIC_PWR_EN connected to PMIC and PMIC WAKEUP
connected to CPU. PMIC's reset input is not connected.

> Anther thing, I wonder about is what configuration the PMIC has on affected
> boards and boards not affected. Can you use the I2C commands in barebox
> to read the PMIC register set and compare it between the affected and
> unaffected boards? Maybe they have different mask defaults?

This is a good idea, I will do this tomorrow. Have to get used to read
that out of the PMIC. May be a difference to u-boot is from interest in
a second step too, but the idea about differen mask defaults is
interesting since the error is so darn hitting 100% on affected boards
and 0% on not affected ones.
Could it be different RAM chips, whichsettings causes them to be on the edge?

Regards
Konsti


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