* [PATCH v2 01/11] x86/Kconfig: Geode CPU has cmpxchg8b
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 16:00 ` Brian Gerst
2024-12-10 14:49 ` [PATCH v2 02/11] x86: drop 32-bit "bigsmp" machine support Arnd Bergmann
` (10 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox, stable
From: Arnd Bergmann <arnd@arndb.de>
An older cleanup of mine inadvertently removed geode-gx1 and geode-lx
from the list of CPUs that are known to support a working cmpxchg8b.
Fixes: 88a2b4edda3d ("x86/Kconfig: Rework CONFIG_X86_PAE dependency")
Cc: stable@vger.kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/x86/Kconfig.cpu | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 2a7279d80460..42e6a40876ea 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -368,7 +368,7 @@ config X86_HAVE_PAE
config X86_CMPXCHG64
def_bool y
- depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7
+ depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 || MGEODEGX1 || MGEODE_LX
# this should be set for all -march=.. options where the compiler
# generates cmov.
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v2 01/11] x86/Kconfig: Geode CPU has cmpxchg8b
2024-12-10 14:49 ` [PATCH v2 01/11] x86/Kconfig: Geode CPU has cmpxchg8b Arnd Bergmann
@ 2024-12-10 16:00 ` Brian Gerst
0 siblings, 0 replies; 21+ messages in thread
From: Brian Gerst @ 2024-12-10 16:00 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-kernel, x86, Arnd Bergmann, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin, Linus Torvalds,
Andy Shevchenko, Matthew Wilcox, stable
On Tue, Dec 10, 2024 at 9:50 AM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> An older cleanup of mine inadvertently removed geode-gx1 and geode-lx
> from the list of CPUs that are known to support a working cmpxchg8b.
>
> Fixes: 88a2b4edda3d ("x86/Kconfig: Rework CONFIG_X86_PAE dependency")
> Cc: stable@vger.kernel.org
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
> ---
> arch/x86/Kconfig.cpu | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
> index 2a7279d80460..42e6a40876ea 100644
> --- a/arch/x86/Kconfig.cpu
> +++ b/arch/x86/Kconfig.cpu
> @@ -368,7 +368,7 @@ config X86_HAVE_PAE
>
> config X86_CMPXCHG64
> def_bool y
> - depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7
> + depends on X86_HAVE_PAE || M586TSC || M586MMX || MK6 || MK7 || MGEODEGX1 || MGEODE_LX
>
> # this should be set for all -march=.. options where the compiler
> # generates cmov.
> --
> 2.39.5
>
>
An idea for a future cleanup would be to change lists like this to
select statements. That would make it easier to see what each CPU
option enables.
Brian Gerst
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 02/11] x86: drop 32-bit "bigsmp" machine support
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
2024-12-10 14:49 ` [PATCH v2 01/11] x86/Kconfig: Geode CPU has cmpxchg8b Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 14:49 ` [PATCH v2 03/11] x86: rework CONFIG_GENERIC_CPU compiler flags Arnd Bergmann
` (9 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
From: Arnd Bergmann <arnd@arndb.de>
The x86-32 kernel used to support multiple platforms with more than eight
logical CPUs, from the 1999-2003 timeframe: Sequent NUMA-Q, IBM Summit,
Unisys ES7000 and HP F8. Support for all except the latter was dropped
back in 2014, leaving only the F8 based DL740 and DL760 G2 machines in
this catery, with up to eight single-core Socket-603 Xeon-MP processors
with hyperthreading.
Like the already removed machines, the HP F8 servers at the cost upwards
of $100k in typical configurations, but were quickly obsoleted by
their 64-bit Socket-604 cousins and the AMD Opteron.
Earlier servers with up to 8 Pentium Pro or Xeon processors remain
fully supported as they had no hyperthreading. Similarly, the more
common 4-socket Xeon-MP machines with hyperthreading using Intel
or ServerWorks chipsets continue to work without this, and all the
multi-core Xeon processors also run 64-bit kernels.
While the "bigsmp" support can also be used to run on later 64-bit
machines (including VM guests), it seems best to discourage that
and get any remaining users to update their kernels to 64-bit builds
on these. As a side-effect of this, there is also no more need to
support NUMA configurations on 32-bit x86, as all true 32-bit
NUMA platforms are already gone.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
.../admin-guide/kernel-parameters.txt | 4 -
arch/x86/Kconfig | 20 +---
arch/x86/kernel/apic/Makefile | 3 -
arch/x86/kernel/apic/apic.c | 3 -
arch/x86/kernel/apic/bigsmp_32.c | 105 ------------------
arch/x86/kernel/apic/local.h | 13 ---
arch/x86/kernel/apic/probe_32.c | 29 -----
7 files changed, 4 insertions(+), 173 deletions(-)
delete mode 100644 arch/x86/kernel/apic/bigsmp_32.c
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index dc663c0ca670..eca370e99844 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -410,10 +410,6 @@
Format: { quiet (default) | verbose | debug }
Change the amount of debugging information output
when initialising the APIC and IO-APIC components.
- For X86-32, this can also be used to specify an APIC
- driver name.
- Format: apic=driver_name
- Examples: apic=bigsmp
apic_extnmi= [APIC,X86,EARLY] External NMI delivery setting
Format: { bsp (default) | all | none }
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 9d7bd0ae48c4..42494739344d 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -526,12 +526,6 @@ config X86_FRED
ring transitions and exception/interrupt handling if the
system supports it.
-config X86_BIGSMP
- bool "Support for big SMP systems with more than 8 CPUs"
- depends on SMP && X86_32
- help
- This option is needed for the systems that have more than 8 CPUs.
-
config X86_EXTENDED_PLATFORM
bool "Support for extended (non-PC) x86 platforms"
default y
@@ -730,8 +724,8 @@ config X86_32_NON_STANDARD
depends on X86_32 && SMP
depends on X86_EXTENDED_PLATFORM
help
- This option compiles in the bigsmp and STA2X11 default
- subarchitectures. It is intended for a generic binary
+ This option compiles in the STA2X11 default
+ subarchitecture. It is intended for a generic binary
kernel. If you select them all, kernel will probe it one by
one and will fallback to default.
@@ -1008,8 +1002,7 @@ config NR_CPUS_RANGE_BEGIN
config NR_CPUS_RANGE_END
int
depends on X86_32
- default 64 if SMP && X86_BIGSMP
- default 8 if SMP && !X86_BIGSMP
+ default 8 if SMP
default 1 if !SMP
config NR_CPUS_RANGE_END
@@ -1022,7 +1015,6 @@ config NR_CPUS_RANGE_END
config NR_CPUS_DEFAULT
int
depends on X86_32
- default 32 if X86_BIGSMP
default 8 if SMP
default 1 if !SMP
@@ -1568,8 +1560,7 @@ config AMD_MEM_ENCRYPT
config NUMA
bool "NUMA Memory Allocation and Scheduler Support"
depends on SMP
- depends on X86_64 || (X86_32 && HIGHMEM64G && X86_BIGSMP)
- default y if X86_BIGSMP
+ depends on X86_64
select USE_PERCPU_NUMA_NODE_ID
select OF_NUMA if OF
help
@@ -1582,9 +1573,6 @@ config NUMA
For 64-bit this is recommended if the system is Intel Core i7
(or later), AMD Opteron, or EM64T NUMA.
- For 32-bit this is only needed if you boot a 32-bit
- kernel on a 64-bit NUMA platform.
-
Otherwise, you should say N.
config AMD_NUMA
diff --git a/arch/x86/kernel/apic/Makefile b/arch/x86/kernel/apic/Makefile
index 3bf0487cf3b7..52d1808ee360 100644
--- a/arch/x86/kernel/apic/Makefile
+++ b/arch/x86/kernel/apic/Makefile
@@ -23,8 +23,5 @@ obj-$(CONFIG_X86_X2APIC) += x2apic_cluster.o
obj-y += apic_flat_64.o
endif
-# APIC probe will depend on the listing order here
-obj-$(CONFIG_X86_BIGSMP) += bigsmp_32.o
-
# For 32bit, probe_32 need to be listed last
obj-$(CONFIG_X86_LOCAL_APIC) += probe_$(BITS).o
diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index c5fb28e6451a..cb453bacf281 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -1371,8 +1371,6 @@ void __init apic_intr_mode_init(void)
x86_64_probe_apic();
- x86_32_install_bigsmp();
-
if (x86_platform.apic_post_init)
x86_platform.apic_post_init();
@@ -1674,7 +1672,6 @@ static __init void apic_read_boot_cpu_id(bool x2apic)
boot_cpu_apic_version = GET_APIC_VERSION(apic_read(APIC_LVR));
}
topology_register_boot_apic(boot_cpu_physical_apicid);
- x86_32_probe_bigsmp_early();
}
#ifdef CONFIG_X86_X2APIC
diff --git a/arch/x86/kernel/apic/bigsmp_32.c b/arch/x86/kernel/apic/bigsmp_32.c
deleted file mode 100644
index 9285d500d5b4..000000000000
--- a/arch/x86/kernel/apic/bigsmp_32.c
+++ /dev/null
@@ -1,105 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0
-/*
- * APIC driver for "bigsmp" xAPIC machines with more than 8 virtual CPUs.
- *
- * Drives the local APIC in "clustered mode".
- */
-#include <linux/cpumask.h>
-#include <linux/dmi.h>
-#include <linux/smp.h>
-
-#include <asm/apic.h>
-#include <asm/io_apic.h>
-
-#include "local.h"
-
-static u32 bigsmp_get_apic_id(u32 x)
-{
- return (x >> 24) & 0xFF;
-}
-
-static void bigsmp_send_IPI_allbutself(int vector)
-{
- default_send_IPI_mask_allbutself_phys(cpu_online_mask, vector);
-}
-
-static void bigsmp_send_IPI_all(int vector)
-{
- default_send_IPI_mask_sequence_phys(cpu_online_mask, vector);
-}
-
-static int dmi_bigsmp; /* can be set by dmi scanners */
-
-static int hp_ht_bigsmp(const struct dmi_system_id *d)
-{
- printk(KERN_NOTICE "%s detected: force use of apic=bigsmp\n", d->ident);
- dmi_bigsmp = 1;
-
- return 0;
-}
-
-
-static const struct dmi_system_id bigsmp_dmi_table[] = {
- { hp_ht_bigsmp, "HP ProLiant DL760 G2",
- { DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
- DMI_MATCH(DMI_BIOS_VERSION, "P44-"),
- }
- },
-
- { hp_ht_bigsmp, "HP ProLiant DL740",
- { DMI_MATCH(DMI_BIOS_VENDOR, "HP"),
- DMI_MATCH(DMI_BIOS_VERSION, "P47-"),
- }
- },
- { } /* NULL entry stops DMI scanning */
-};
-
-static int probe_bigsmp(void)
-{
- return dmi_check_system(bigsmp_dmi_table);
-}
-
-static struct apic apic_bigsmp __ro_after_init = {
-
- .name = "bigsmp",
- .probe = probe_bigsmp,
-
- .dest_mode_logical = false,
-
- .disable_esr = 1,
-
- .cpu_present_to_apicid = default_cpu_present_to_apicid,
-
- .max_apic_id = 0xFE,
- .get_apic_id = bigsmp_get_apic_id,
-
- .calc_dest_apicid = apic_default_calc_apicid,
-
- .send_IPI = default_send_IPI_single_phys,
- .send_IPI_mask = default_send_IPI_mask_sequence_phys,
- .send_IPI_mask_allbutself = NULL,
- .send_IPI_allbutself = bigsmp_send_IPI_allbutself,
- .send_IPI_all = bigsmp_send_IPI_all,
- .send_IPI_self = default_send_IPI_self,
-
- .read = native_apic_mem_read,
- .write = native_apic_mem_write,
- .eoi = native_apic_mem_eoi,
- .icr_read = native_apic_icr_read,
- .icr_write = native_apic_icr_write,
- .wait_icr_idle = apic_mem_wait_icr_idle,
- .safe_wait_icr_idle = apic_mem_wait_icr_idle_timeout,
-};
-
-bool __init apic_bigsmp_possible(bool cmdline_override)
-{
- return apic == &apic_bigsmp || !cmdline_override;
-}
-
-void __init apic_bigsmp_force(void)
-{
- if (apic != &apic_bigsmp)
- apic_install_driver(&apic_bigsmp);
-}
-
-apic_driver(apic_bigsmp);
diff --git a/arch/x86/kernel/apic/local.h b/arch/x86/kernel/apic/local.h
index 842fe28496be..bdcf609eb283 100644
--- a/arch/x86/kernel/apic/local.h
+++ b/arch/x86/kernel/apic/local.h
@@ -65,17 +65,4 @@ void default_send_IPI_self(int vector);
void default_send_IPI_mask_sequence_logical(const struct cpumask *mask, int vector);
void default_send_IPI_mask_allbutself_logical(const struct cpumask *mask, int vector);
void default_send_IPI_mask_logical(const struct cpumask *mask, int vector);
-void x86_32_probe_bigsmp_early(void);
-void x86_32_install_bigsmp(void);
-#else
-static inline void x86_32_probe_bigsmp_early(void) { }
-static inline void x86_32_install_bigsmp(void) { }
-#endif
-
-#ifdef CONFIG_X86_BIGSMP
-bool apic_bigsmp_possible(bool cmdline_selected);
-void apic_bigsmp_force(void);
-#else
-static inline bool apic_bigsmp_possible(bool cmdline_selected) { return false; };
-static inline void apic_bigsmp_force(void) { }
#endif
diff --git a/arch/x86/kernel/apic/probe_32.c b/arch/x86/kernel/apic/probe_32.c
index f75ee345c02d..87bc9e7ca5d6 100644
--- a/arch/x86/kernel/apic/probe_32.c
+++ b/arch/x86/kernel/apic/probe_32.c
@@ -93,35 +93,6 @@ static int __init parse_apic(char *arg)
}
early_param("apic", parse_apic);
-void __init x86_32_probe_bigsmp_early(void)
-{
- if (nr_cpu_ids <= 8 || xen_pv_domain())
- return;
-
- if (IS_ENABLED(CONFIG_X86_BIGSMP)) {
- switch (boot_cpu_data.x86_vendor) {
- case X86_VENDOR_INTEL:
- if (!APIC_XAPIC(boot_cpu_apic_version))
- break;
- /* P4 and above */
- fallthrough;
- case X86_VENDOR_HYGON:
- case X86_VENDOR_AMD:
- if (apic_bigsmp_possible(cmdline_apic))
- return;
- break;
- }
- }
- pr_info("Limiting to 8 possible CPUs\n");
- set_nr_cpu_ids(8);
-}
-
-void __init x86_32_install_bigsmp(void)
-{
- if (nr_cpu_ids > 8 && !xen_pv_domain())
- apic_bigsmp_force();
-}
-
void __init x86_32_probe_apic(void)
{
if (!cmdline_apic) {
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v2 03/11] x86: rework CONFIG_GENERIC_CPU compiler flags
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
2024-12-10 14:49 ` [PATCH v2 01/11] x86/Kconfig: Geode CPU has cmpxchg8b Arnd Bergmann
2024-12-10 14:49 ` [PATCH v2 02/11] x86: drop 32-bit "bigsmp" machine support Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 14:49 ` [PATCH v2 04/11] x86: drop configuration options for early 64-bit CPUs Arnd Bergmann
` (8 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
From: Arnd Bergmann <arnd@arndb.de>
Building an x86-64 kernel with CONFIG_GENERIC_CPU is documented to
run on all CPUs, but the Makefile does not actually pass an -march=
argument, instead relying on the default that was used to configure
the toolchain.
In many cases, gcc will be configured to -march=x86-64 or -march=k8
for maximum compatibility, but in other cases a distribution default
may be either raised to a more recent ISA, or set to -march=native
to build for the CPU used for compilation. This still works in the
case of building a custom kernel for the local machine.
The point where it breaks down is building a kernel for another
machine that is older the the default target. Changing the default
to -march=x86-64 would make it work reliable, but possibly produce
worse code on distros that intentionally default to a newer ISA.
To allow reliably building a kernel for either the oldest x86-64
CPUs, pass the -march=x86-64 flag to the compiler. This was not
possible in early versions of x86-64 gcc, but works on all currently
supported versions down to at least gcc-5.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/x86/Makefile | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 5b773b34768d..5af3172fd51c 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -183,14 +183,14 @@ else
cflags-$(CONFIG_MPSC) += -march=nocona
cflags-$(CONFIG_MCORE2) += -march=core2
cflags-$(CONFIG_MATOM) += -march=atom
- cflags-$(CONFIG_GENERIC_CPU) += -mtune=generic
+ cflags-$(CONFIG_GENERIC_CPU) += -march=x86-64 -mtune=generic
KBUILD_CFLAGS += $(cflags-y)
rustflags-$(CONFIG_MK8) += -Ctarget-cpu=k8
rustflags-$(CONFIG_MPSC) += -Ctarget-cpu=nocona
rustflags-$(CONFIG_MCORE2) += -Ctarget-cpu=core2
rustflags-$(CONFIG_MATOM) += -Ctarget-cpu=atom
- rustflags-$(CONFIG_GENERIC_CPU) += -Ztune-cpu=generic
+ rustflags-$(CONFIG_GENERIC_CPU) += -Ctarget-cpu=x86-64 -Ztune-cpu=generic
KBUILD_RUSTFLAGS += $(rustflags-y)
KBUILD_CFLAGS += -mno-red-zone
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v2 04/11] x86: drop configuration options for early 64-bit CPUs
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
` (2 preceding siblings ...)
2024-12-10 14:49 ` [PATCH v2 03/11] x86: rework CONFIG_GENERIC_CPU compiler flags Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 14:49 ` [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option Arnd Bergmann
` (7 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
From: Arnd Bergmann <arnd@arndb.de>
The x86 CPU selection menu is confusing for a number of reasons:
When configuring 32-bit kernels, it shows a small number of early 64-bit
microarchitectures (K8, Core 2) but not the regular generic 64-bit target
that is the normal default. There is no longer a reason to run 32-bit
kernels on production 64-bit systems, so only actual 32-bit CPUs need
to be shown here.
When configuring 64-bit kernels, the options also pointless as there is
no way to pick any CPU from the past 15 years, leaving GENERIC_CPU as
the only sensible choice.
Address both of the above by removing the obsolete options and making
all 64-bit kernels run on both Intel and AMD CPUs from any generation.
Testing generic 32-bit kernels on 64-bit hardware remains possible,
just not building a 32-bit kernel that requires a 64-bit CPU.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/x86/Kconfig.cpu | 95 +++++----------------------------
arch/x86/Makefile | 16 +-----
arch/x86/Makefile_32.cpu | 5 +-
arch/x86/include/asm/vermagic.h | 4 --
drivers/misc/mei/Kconfig | 2 +-
5 files changed, 18 insertions(+), 104 deletions(-)
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 42e6a40876ea..8fcb8ccee44b 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -1,9 +1,9 @@
# SPDX-License-Identifier: GPL-2.0
# Put here option for CPU selection and depending optimization
choice
- prompt "Processor family"
- default M686 if X86_32
- default GENERIC_CPU if X86_64
+ prompt "x86-32 Processor family"
+ depends on X86_32
+ default M686
help
This is the processor type of your CPU. This information is
used for optimizing purposes. In order to compile a kernel
@@ -31,7 +31,6 @@ choice
- "Pentium-4" for the Intel Pentium 4 or P4-based Celeron.
- "K6" for the AMD K6, K6-II and K6-III (aka K6-3D).
- "Athlon" for the AMD K7 family (Athlon/Duron/Thunderbird).
- - "Opteron/Athlon64/Hammer/K8" for all K8 and newer AMD CPUs.
- "Crusoe" for the Transmeta Crusoe series.
- "Efficeon" for the Transmeta Efficeon series.
- "Winchip-C6" for original IDT Winchip.
@@ -42,13 +41,10 @@ choice
- "CyrixIII/VIA C3" for VIA Cyrix III or VIA C3.
- "VIA C3-2" for VIA C3-2 "Nehemiah" (model 9 and above).
- "VIA C7" for VIA C7.
- - "Intel P4" for the Pentium 4/Netburst microarchitecture.
- - "Core 2/newer Xeon" for all core2 and newer Intel CPUs.
- "Intel Atom" for the Atom-microarchitecture CPUs.
- - "Generic-x86-64" for a kernel which runs on any x86-64 CPU.
See each option's help text for additional details. If you don't know
- what to do, choose "486".
+ what to do, choose "Pentium-Pro".
config M486SX
bool "486SX"
@@ -114,11 +110,11 @@ config MPENTIUMIII
extensions.
config MPENTIUMM
- bool "Pentium M"
+ bool "Pentium M/Pentium Dual Core/Core Solo/Core Duo"
depends on X86_32
help
Select this for Intel Pentium M (not Pentium-4 M)
- notebook chips.
+ "Merom" Core Solo/Duo notebook chips
config MPENTIUM4
bool "Pentium-4/Celeron(P4-based)/Pentium-4 M/older Xeon"
@@ -139,22 +135,10 @@ config MPENTIUM4
-Mobile Pentium 4
-Mobile Pentium 4 M
-Extreme Edition (Gallatin)
- -Prescott
- -Prescott 2M
- -Cedar Mill
- -Presler
- -Smithfiled
Xeons (Intel Xeon, Xeon MP, Xeon LV, Xeon MV) corename:
-Foster
-Prestonia
-Gallatin
- -Nocona
- -Irwindale
- -Cranford
- -Potomac
- -Paxville
- -Dempsey
-
config MK6
bool "K6/K6-II/K6-III"
@@ -172,13 +156,6 @@ config MK7
some extended instructions, and passes appropriate optimization
flags to GCC.
-config MK8
- bool "Opteron/Athlon64/Hammer/K8"
- help
- Select this for an AMD Opteron or Athlon64 Hammer-family processor.
- Enables use of some extended instructions, and passes appropriate
- optimization flags to GCC.
-
config MCRUSOE
bool "Crusoe"
depends on X86_32
@@ -258,42 +235,14 @@ config MVIAC7
Select this for a VIA C7. Selecting this uses the correct cache
shift and tells gcc to treat the CPU as a 686.
-config MPSC
- bool "Intel P4 / older Netburst based Xeon"
- depends on X86_64
- help
- Optimize for Intel Pentium 4, Pentium D and older Nocona/Dempsey
- Xeon CPUs with Intel 64bit which is compatible with x86-64.
- Note that the latest Xeons (Xeon 51xx and 53xx) are not based on the
- Netburst core and shouldn't use this option. You can distinguish them
- using the cpu family field
- in /proc/cpuinfo. Family 15 is an older Xeon, Family 6 a newer one.
-
-config MCORE2
- bool "Core 2/newer Xeon"
- help
-
- Select this for Intel Core 2 and newer Core 2 Xeons (Xeon 51xx and
- 53xx) CPUs. You can distinguish newer from older Xeons by the CPU
- family in /proc/cpuinfo. Newer ones have 6 and older ones 15
- (not a typo)
-
config MATOM
bool "Intel Atom"
help
-
Select this for the Intel Atom platform. Intel Atom CPUs have an
in-order pipelining architecture and thus can benefit from
accordingly optimized code. Use a recent GCC with specific Atom
support in order to fully benefit from selecting this option.
-config GENERIC_CPU
- bool "Generic-x86-64"
- depends on X86_64
- help
- Generic x86-64 CPU.
- Run equally well on all x86-64 CPUs.
-
endchoice
config X86_GENERIC
@@ -317,8 +266,8 @@ config X86_INTERNODE_CACHE_SHIFT
config X86_L1_CACHE_SHIFT
int
- default "7" if MPENTIUM4 || MPSC
- default "6" if MK7 || MK8 || MPENTIUMM || MCORE2 || MATOM || MVIAC7 || X86_GENERIC || GENERIC_CPU
+ default "7" if MPENTIUM4
+ default "6" if MK7 || MPENTIUMM || MATOM || MVIAC7 || X86_GENERIC || X86_64
default "4" if MELAN || M486SX || M486 || MGEODEGX1
default "5" if MWINCHIP3D || MWINCHIPC6 || MCRUSOE || MEFFICEON || MCYRIXIII || MK6 || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || M586 || MVIAC3_2 || MGEODE_LX
@@ -336,35 +285,19 @@ config X86_ALIGNMENT_16
config X86_INTEL_USERCOPY
def_bool y
- depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK8 || MK7 || MEFFICEON || MCORE2
+ depends on MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M586MMX || X86_GENERIC || MK7 || MEFFICEON
config X86_USE_PPRO_CHECKSUM
def_bool y
- depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MCORE2 || MATOM
-
-#
-# P6_NOPs are a relatively minor optimization that require a family >=
-# 6 processor, except that it is broken on certain VIA chips.
-# Furthermore, AMD chips prefer a totally different sequence of NOPs
-# (which work on all CPUs). In addition, it looks like Virtual PC
-# does not understand them.
-#
-# As a result, disallow these if we're not compiling for X86_64 (these
-# NOPs do work on all x86-64 capable chips); the list of processors in
-# the right-hand clause are the cores that benefit from this optimization.
-#
-config X86_P6_NOP
- def_bool y
- depends on X86_64
- depends on (MCORE2 || MPENTIUM4 || MPSC)
+ depends on MWINCHIP3D || MWINCHIPC6 || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MGEODE_LX || MATOM
config X86_TSC
def_bool y
- depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MK8 || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MCORE2 || MATOM) || X86_64
+ depends on (MWINCHIP3D || MCRUSOE || MEFFICEON || MCYRIXIII || MK7 || MK6 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || M586MMX || M586TSC || MVIAC3_2 || MVIAC7 || MGEODEGX1 || MGEODE_LX || MATOM) || X86_64
config X86_HAVE_PAE
def_bool y
- depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MK8 || MVIAC7 || MCORE2 || MATOM || X86_64
+ depends on MCRUSOE || MEFFICEON || MCYRIXIII || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC7 || MATOM || X86_64
config X86_CMPXCHG64
def_bool y
@@ -374,12 +307,12 @@ config X86_CMPXCHG64
# generates cmov.
config X86_CMOV
def_bool y
- depends on (MK8 || MK7 || MCORE2 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || X86_64 || MATOM || MGEODE_LX)
+ depends on (MK7 || MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MCRUSOE || MEFFICEON || MATOM || MGEODE_LX || X86_64)
config X86_MINIMUM_CPU_FAMILY
int
default "64" if X86_64
- default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MCORE2 || MK7 || MK8)
+ default "6" if X86_32 && (MPENTIUM4 || MPENTIUMM || MPENTIUMIII || MPENTIUMII || M686 || MVIAC3_2 || MVIAC7 || MEFFICEON || MATOM || MK7)
default "5" if X86_32 && X86_CMPXCHG64
default "4"
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 5af3172fd51c..8120085b00a4 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -178,20 +178,8 @@ else
# Use -mskip-rax-setup if supported.
KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup)
- # FIXME - should be integrated in Makefile.cpu (Makefile_32.cpu)
- cflags-$(CONFIG_MK8) += -march=k8
- cflags-$(CONFIG_MPSC) += -march=nocona
- cflags-$(CONFIG_MCORE2) += -march=core2
- cflags-$(CONFIG_MATOM) += -march=atom
- cflags-$(CONFIG_GENERIC_CPU) += -march=x86-64 -mtune=generic
- KBUILD_CFLAGS += $(cflags-y)
-
- rustflags-$(CONFIG_MK8) += -Ctarget-cpu=k8
- rustflags-$(CONFIG_MPSC) += -Ctarget-cpu=nocona
- rustflags-$(CONFIG_MCORE2) += -Ctarget-cpu=core2
- rustflags-$(CONFIG_MATOM) += -Ctarget-cpu=atom
- rustflags-$(CONFIG_GENERIC_CPU) += -Ctarget-cpu=x86-64 -Ztune-cpu=generic
- KBUILD_RUSTFLAGS += $(rustflags-y)
+ KBUILD_CFLAGS += -march=x86-64 -mtune=generic
+ KBUILD_RUSTFLAGS += -Ctarget-cpu=x86-64 -Ztune-cpu=generic
KBUILD_CFLAGS += -mno-red-zone
KBUILD_CFLAGS += -mcmodel=kernel
diff --git a/arch/x86/Makefile_32.cpu b/arch/x86/Makefile_32.cpu
index 94834c4b5e5e..af7de9a42752 100644
--- a/arch/x86/Makefile_32.cpu
+++ b/arch/x86/Makefile_32.cpu
@@ -24,7 +24,6 @@ cflags-$(CONFIG_MK6) += -march=k6
# Please note, that patches that add -march=athlon-xp and friends are pointless.
# They make zero difference whatsosever to performance at this time.
cflags-$(CONFIG_MK7) += -march=athlon
-cflags-$(CONFIG_MK8) += $(call cc-option,-march=k8,-march=athlon)
cflags-$(CONFIG_MCRUSOE) += -march=i686 $(align)
cflags-$(CONFIG_MEFFICEON) += -march=i686 $(call tune,pentium3) $(align)
cflags-$(CONFIG_MWINCHIPC6) += $(call cc-option,-march=winchip-c6,-march=i586)
@@ -32,9 +31,7 @@ cflags-$(CONFIG_MWINCHIP3D) += $(call cc-option,-march=winchip2,-march=i586)
cflags-$(CONFIG_MCYRIXIII) += $(call cc-option,-march=c3,-march=i486) $(align)
cflags-$(CONFIG_MVIAC3_2) += $(call cc-option,-march=c3-2,-march=i686)
cflags-$(CONFIG_MVIAC7) += -march=i686
-cflags-$(CONFIG_MCORE2) += -march=i686 $(call tune,core2)
-cflags-$(CONFIG_MATOM) += $(call cc-option,-march=atom,$(call cc-option,-march=core2,-march=i686)) \
- $(call cc-option,-mtune=atom,$(call cc-option,-mtune=generic))
+cflags-$(CONFIG_MATOM) += -march=atom
# AMD Elan support
cflags-$(CONFIG_MELAN) += -march=i486
diff --git a/arch/x86/include/asm/vermagic.h b/arch/x86/include/asm/vermagic.h
index 75884d2cdec3..5d471253c755 100644
--- a/arch/x86/include/asm/vermagic.h
+++ b/arch/x86/include/asm/vermagic.h
@@ -15,8 +15,6 @@
#define MODULE_PROC_FAMILY "586TSC "
#elif defined CONFIG_M586MMX
#define MODULE_PROC_FAMILY "586MMX "
-#elif defined CONFIG_MCORE2
-#define MODULE_PROC_FAMILY "CORE2 "
#elif defined CONFIG_MATOM
#define MODULE_PROC_FAMILY "ATOM "
#elif defined CONFIG_M686
@@ -33,8 +31,6 @@
#define MODULE_PROC_FAMILY "K6 "
#elif defined CONFIG_MK7
#define MODULE_PROC_FAMILY "K7 "
-#elif defined CONFIG_MK8
-#define MODULE_PROC_FAMILY "K8 "
#elif defined CONFIG_MELAN
#define MODULE_PROC_FAMILY "ELAN "
#elif defined CONFIG_MCRUSOE
diff --git a/drivers/misc/mei/Kconfig b/drivers/misc/mei/Kconfig
index 67d9391f1855..7575fee96cc6 100644
--- a/drivers/misc/mei/Kconfig
+++ b/drivers/misc/mei/Kconfig
@@ -3,7 +3,7 @@
config INTEL_MEI
tristate "Intel Management Engine Interface"
depends on X86 && PCI
- default GENERIC_CPU || MCORE2 || MATOM || X86_GENERIC
+ default X86_64 || MATOM
help
The Intel Management Engine (Intel ME) provides Manageability,
Security and Media services for system containing Intel chipsets.
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
` (3 preceding siblings ...)
2024-12-10 14:49 ` [PATCH v2 04/11] x86: drop configuration options for early 64-bit CPUs Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 19:05 ` irecca.kun
2024-12-10 21:02 ` Josh Triplett
2024-12-10 14:49 ` [PATCH v2 06/11] x86: remove HIGHMEM64G support Arnd Bergmann
` (6 subsequent siblings)
11 siblings, 2 replies; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
From: Arnd Bergmann <arnd@arndb.de>
As a replacement for the obsole MK8/MPSC/MCORE2 configuration options,
allow building a specialized kernel for the local CPU, which is useful
for users building their own kernels, and does not require maintaining
a list of possible CPU options.
Between -march=native and -mtune=native, I pick the former in order
to give the best performance through the use of extra instructions,
but at the cost of not being able to run on older CPUs at all. This
creates a small risk of running into illegal instruction faults when
the resulting binary ends up being run on a machine other than the
one it was built on.
Link: https://lore.kernel.org/lkml/CAHk-=wji1sV93yKbc==Z7OSSHBiDE=LAdG_d5Y-zPBrnSs0k2A@mail.gmail.com/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/x86/Kconfig.cpu | 14 ++++++++++++++
arch/x86/Makefile | 5 +++++
2 files changed, 19 insertions(+)
diff --git a/arch/x86/Kconfig.cpu b/arch/x86/Kconfig.cpu
index 8fcb8ccee44b..d634b163e913 100644
--- a/arch/x86/Kconfig.cpu
+++ b/arch/x86/Kconfig.cpu
@@ -257,6 +257,20 @@ config X86_GENERIC
This is really intended for distributors who need more
generic optimizations.
+config X86_64_NATIVE
+ bool "Build with -march=native optimization"
+ depends on X86_64
+ help
+ Make it possible to have a slightly better optimized kernel for
+ the machine it is built on, by passing -march=native instead
+ the more generic -march=x86-64 option. This lets compilers
+ use extensions to the x86-64 instruction set that were not
+ present in the original AMD Opteron and Intel Pentium4 CPUs,
+ and schedule instructions for the pipeline model.
+
+ Select this option only when building a kernel to run locally,
+ as it may be incompatible with any other processor.
+
#
# Define implied options from the CPU selection here
config X86_INTERNODE_CACHE_SHIFT
diff --git a/arch/x86/Makefile b/arch/x86/Makefile
index 8120085b00a4..bf45b84c138f 100644
--- a/arch/x86/Makefile
+++ b/arch/x86/Makefile
@@ -178,8 +178,13 @@ else
# Use -mskip-rax-setup if supported.
KBUILD_CFLAGS += $(call cc-option,-mskip-rax-setup)
+ifdef CONFIG_X86_64_NATIVE
+ KBUILD_CFLAGS += -march=native
+ KBUILD_RUSTFLAGS += -Ctarget-cpu=native
+else
KBUILD_CFLAGS += -march=x86-64 -mtune=generic
KBUILD_RUSTFLAGS += -Ctarget-cpu=x86-64 -Ztune-cpu=generic
+endif
KBUILD_CFLAGS += -mno-red-zone
KBUILD_CFLAGS += -mcmodel=kernel
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option
2024-12-10 14:49 ` [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option Arnd Bergmann
@ 2024-12-10 19:05 ` irecca.kun
2024-12-10 20:56 ` Arnd Bergmann
2024-12-10 21:02 ` Josh Triplett
1 sibling, 1 reply; 21+ messages in thread
From: irecca.kun @ 2024-12-10 19:05 UTC (permalink / raw)
To: Arnd Bergmann, linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
Hello.
On 12/10/24 14:49, Arnd Bergmann wrote:
> As a replacement for the obsole MK8/MPSC/MCORE2 configuration options,
> allow building a specialized kernel for the local CPU, which is useful
> for users building their own kernels, and does not require maintaining
> a list of possible CPU options.
That potentially introduces problems. Namely compilers could apply auto-vectorization, which currently breaks the kernel.
We probably need an additional patch like this: https://github.com/zen-kernel/zen-kernel/commit/95b7981ba2e5c86529de0e895c2d9e428aa3f7dc
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option
2024-12-10 19:05 ` irecca.kun
@ 2024-12-10 20:56 ` Arnd Bergmann
2024-12-10 21:08 ` irecca.kun
0 siblings, 1 reply; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 20:56 UTC (permalink / raw)
To: irecca.kun, Arnd Bergmann, linux-kernel, x86
Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin, Linus Torvalds, Andy Shevchenko, Matthew Wilcox
On Tue, Dec 10, 2024, at 20:05, irecca.kun@gmail.com wrote:
> Hello.
>
> On 12/10/24 14:49, Arnd Bergmann wrote:
>> As a replacement for the obsole MK8/MPSC/MCORE2 configuration options,
>> allow building a specialized kernel for the local CPU, which is useful
>> for users building their own kernels, and does not require maintaining
>> a list of possible CPU options.
>
> That potentially introduces problems. Namely compilers could apply
> auto-vectorization, which currently breaks the kernel.
> We probably need an additional patch like this:
> https://github.com/zen-kernel/zen-kernel/commit/95b7981ba2e5c86529de0e895c2d9e428aa3f7dc
I don't see how either -mno-avx2 or -fno-tree-vectorize would be
needed here: avx2 is already turned off because of -mno-avx,
and -ftree-vectorize is only enabled by default at -O3 level,
which we don't use (and which doesn't add any instructions).
There may be other flags that need to be disabled though.
With the flags we currently pass to the kernel, this is the
difference in the gcc-14 -Q --help=target output between the
x86-64 baseline and the -march=emeraldrapids, which is currently
the most featureful:
--- b 2024-12-10 21:37:27.182448452 +0100
+++ a 2024-12-10 21:41:14.118310513 +0100
@@ -12,24 +12,24 @@
-mabm [disabled]
-maccumulate-outgoing-args [disabled]
-maddress-mode= long
- -madx [disabled]
- -maes [disabled]
+ -madx [enabled]
+ -maes [enabled]
-malign-data= compat
-malign-double [disabled]
-malign-functions= 0
-malign-jumps= 0
-malign-loops= 0
-malign-stringops [enabled]
- -mamx-bf16 [disabled]
+ -mamx-bf16 [enabled]
-mamx-complex [disabled]
-mamx-fp16 [disabled]
- -mamx-int8 [disabled]
- -mamx-tile [disabled]
+ -mamx-int8 [enabled]
+ -mamx-tile [enabled]
-mandroid [disabled]
-mapx-features= none
-mapx-inline-asm-use-gpr32 [disabled]
-mapxf [disabled]
- -march= x86-64
+ -march= emeraldrapids
-masm= att
-mavx [disabled]
-mavx10.1 -mavx10.1-256
@@ -62,27 +62,27 @@
-mavxvnniint16 [disabled]
-mavxvnniint8 [disabled]
-mbionic [disabled]
- -mbmi [disabled]
- -mbmi2 [disabled]
+ -mbmi [enabled]
+ -mbmi2 [enabled]
-mbranch-cost=<0,5> 3
-mcall-ms2sysv-xlogues [disabled]
-mcet-switch [disabled]
-mcld [disabled]
- -mcldemote [disabled]
- -mclflushopt [disabled]
- -mclwb [disabled]
+ -mcldemote [enabled]
+ -mclflushopt [enabled]
+ -mclwb [enabled]
-mclzero [disabled]
-mcmodel= kernel
-mcmpccxadd [disabled]
-mcpu=
-mcrc32 [disabled]
- -mcx16 [disabled]
+ -mcx16 [enabled]
-mdaz-ftz [disabled]
-mdirect-extern-access [enabled]
-mdispatch-scheduler [disabled]
-mdump-tune-features [disabled]
- -menqcmd [disabled]
- -mevex512 [disabled]
+ -menqcmd [enabled]
+ -mevex512 [enabled]
-mf16c [disabled]
-mfancy-math-387 [disabled]
-mfentry [disabled]
@@ -94,17 +94,17 @@
-mforce-indirect-call [disabled]
-mfp-ret-in-387 [disabled]
-mfpmath= 387
- -mfsgsbase [disabled]
+ -mfsgsbase [enabled]
-mfunction-return= keep
-mfused-madd -ffp-contract=fast
-mfxsr [enabled]
-mgather -mtune-ctrl=use_gather
-mgeneral-regs-only [disabled]
- -mgfni [disabled]
+ -mgfni [enabled]
-mglibc [enabled]
-mhard-float [disabled]
-mharden-sls= none
- -mhle [disabled]
+ -mhle [enabled]
-mhreset [disabled]
-miamcu [disabled]
-mieee-fp [enabled]
@@ -123,15 +123,15 @@
-mlong-double-64 [disabled]
-mlong-double-80 [enabled]
-mlwp [disabled]
- -mlzcnt [disabled]
+ -mlzcnt [enabled]
-mmanual-endbr [disabled]
-mmemcpy-strategy=
-mmemset-strategy=
-mmitigate-rop [disabled]
-mmmx [disabled]
- -mmovbe [disabled]
- -mmovdir64b [disabled]
- -mmovdiri [disabled]
+ -mmovbe [enabled]
+ -mmovdir64b [enabled]
+ -mmovdiri [enabled]
-mmove-max= 128
-mmpx [disabled]
-mms-bitfields [disabled]
@@ -152,23 +152,23 @@
-mpc32 [disabled]
-mpc64 [disabled]
-mpc80 [disabled]
- -mpclmul [disabled]
+ -mpclmul [enabled]
-mpcommit [disabled]
- -mpconfig [disabled]
- -mpku [disabled]
- -mpopcnt [disabled]
+ -mpconfig [enabled]
+ -mpku [enabled]
+ -mpopcnt [enabled]
-mprefer-avx128 -mprefer-vector-width=128
-mprefer-vector-width= none
-mpreferred-stack-boundary= 3
-mprefetchi [disabled]
-mprefetchwt1 [disabled]
- -mprfchw [disabled]
- -mptwrite [disabled]
+ -mprfchw [enabled]
+ -mptwrite [enabled]
-mpush-args [enabled]
-mraoint [disabled]
- -mrdpid [disabled]
- -mrdrnd [disabled]
- -mrdseed [disabled]
+ -mrdpid [enabled]
+ -mrdrnd [enabled]
+ -mrdseed [enabled]
-mrecip [disabled]
-mrecip=
-mrecord-mcount [disabled]
@@ -178,11 +178,11 @@
-mrelax-cmpxchg-loop [disabled]
-mrtd [disabled]
-mrtm [disabled]
- -msahf [disabled]
+ -msahf [enabled]
-mscatter -mtune-ctrl=use_scatter
- -mserialize [disabled]
- -msgx [disabled]
- -msha [disabled]
+ -mserialize [enabled]
+ -msgx [enabled]
+ -msha [enabled]
-msha512 [disabled]
-mshstk [disabled]
-mskip-rax-setup [enabled]
@@ -212,11 +212,11 @@
-mtbm [disabled]
-mtls-dialect= gnu
-mtls-direct-seg-refs [enabled]
- -mtsxldtrk [disabled]
+ -mtsxldtrk [enabled]
-mtune-ctrl=
-mtune= generic
-muclibc [disabled]
- -muintr [disabled]
+ -muintr [enabled]
-munroll-only-small-loops [enabled]
-musermsr [disabled]
-mvaes [disabled]
@@ -224,15 +224,15 @@
-mvect8-ret-in-mem [disabled]
-mvpclmulqdq [disabled]
-mvzeroupper [enabled]
- -mwaitpkg [disabled]
- -mwbnoinvd [disabled]
+ -mwaitpkg [enabled]
+ -mwbnoinvd [enabled]
-mwidekl [disabled]
-mx32 [disabled]
-mxop [disabled]
- -mxsave [disabled]
- -mxsavec [disabled]
- -mxsaveopt [disabled]
- -mxsaves [disabled]
+ -mxsave [enabled]
+ -mxsavec [enabled]
+ -mxsaveopt [enabled]
+ -mxsaves [enabled]
I don't know what most of them do, but the ones I looked
up seem to be mainly integer operations.
Arnd
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option
2024-12-10 20:56 ` Arnd Bergmann
@ 2024-12-10 21:08 ` irecca.kun
0 siblings, 0 replies; 21+ messages in thread
From: irecca.kun @ 2024-12-10 21:08 UTC (permalink / raw)
To: Arnd Bergmann, Arnd Bergmann, linux-kernel, x86
Cc: Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin, Linus Torvalds, Andy Shevchenko, Matthew Wilcox
On 12/11/24 01:56, Arnd Bergmann wrote:
> -ftree-vectorize is only enabled by default at -O3 level
You maybe missed it, but vectorization is enabled at -O2 level since GCC 12. https://www.phoronix.com/news/GCC-12-Auto-Vec-O2
Same goes for clang, it pretty much always had vectorized on -O2, iirc.
> avx2 is already turned off because of -mno-avx,
Hmm, I'm not sure. But if we look at existing KBUILD_RUSTFLAGS below, it has both -avx and -avx2.
^ permalink raw reply [flat|nested] 21+ messages in thread
* Re: [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option
2024-12-10 14:49 ` [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option Arnd Bergmann
2024-12-10 19:05 ` irecca.kun
@ 2024-12-10 21:02 ` Josh Triplett
1 sibling, 0 replies; 21+ messages in thread
From: Josh Triplett @ 2024-12-10 21:02 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-kernel, x86, Arnd Bergmann, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin, Linus Torvalds,
Andy Shevchenko, Matthew Wilcox
On Tue, Dec 10, 2024 at 03:49:39PM +0100, Arnd Bergmann wrote:
> From: Arnd Bergmann <arnd@arndb.de>
>
> As a replacement for the obsole MK8/MPSC/MCORE2 configuration options,
> allow building a specialized kernel for the local CPU, which is useful
> for users building their own kernels, and does not require maintaining
> a list of possible CPU options.
>
> Between -march=native and -mtune=native, I pick the former in order
> to give the best performance through the use of extra instructions,
> but at the cost of not being able to run on older CPUs at all. This
> creates a small risk of running into illegal instruction faults when
> the resulting binary ends up being run on a machine other than the
> one it was built on.
Setting this option makes the kernel build non-reproducible (as it'll
build differently on different systems).
I personally think this is a little questionable, as opposed to having
well-defined optimization levels that are tested and supported and
selecting one of those with a `make nativeconfig`. But if this does get
added:
- Could you please document in
Documentation/kbuild/reproducible-builds.rst that this option should
not be set if you want reproducible builds?
- Could you add something similar to the config options LTO uses, to
make `allyesconfig` and `allmodconfig` turn this back *off*?
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 06/11] x86: remove HIGHMEM64G support
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
` (4 preceding siblings ...)
2024-12-10 14:49 ` [PATCH v2 05/11] x86: add CONFIG_X86_64_NATIVE option Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 14:49 ` [PATCH v2 07/11] x86: drop SWIOTLB and PHYS_ADDR_T_64BIT for PAE Arnd Bergmann
` (5 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
From: Arnd Bergmann <arnd@arndb.de>
The HIGHMEM64G support was added in linux-2.3.25 to support (then)
high-end Pentium Pro and Pentium III Xeon servers with more than 4GB of
addressing, NUMA and PCI-X slots started appearing.
I have found no evidence of this ever being used in regular dual-socket
servers or consumer devices, all the users seem obsolete these days,
even by i386 standards:
- Support for NUMA servers (NUMA-Q, IBM x440, unisys) was already
removed ten years ago.
- 4+ socket non-NUMA servers based on Intel 450GX/450NX, HP F8 and
ServerWorks ServerSet/GrandChampion could theoretically still work
with 8GB, but these were exceptionally rare even 20 years ago and
would have usually been equipped with than the maximum amount of
RAM.
- Some SKUs of the Celeron D from 2004 had 64-bit mode fused off but
could still work in a Socket 775 mainboard designed for the later
Core 2 Duo and 8GB. Apparently most BIOSes at the time only allowed
64-bit CPUs.
- In the early days of x86-64 hardware, there was sometimes the need
to run a 32-bit kernel to work around bugs in the hardware drivers,
or in the syscall emulation for 32-bit userspace. This likely still
works but there should never be a need for this any more.
PAE mode is still required to get access to the 'NX' bit on Atom
'Pentium M' and 'Core Duo' CPUs.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
Documentation/admin-guide/kdump/kdump.rst | 4 --
Documentation/arch/x86/usb-legacy-support.rst | 11 +----
arch/x86/Kconfig | 46 +++----------------
arch/x86/configs/xen.config | 2 -
arch/x86/include/asm/page_32_types.h | 4 +-
arch/x86/mm/init_32.c | 9 +---
6 files changed, 11 insertions(+), 65 deletions(-)
diff --git a/Documentation/admin-guide/kdump/kdump.rst b/Documentation/admin-guide/kdump/kdump.rst
index 5376890adbeb..1f7f14c6e184 100644
--- a/Documentation/admin-guide/kdump/kdump.rst
+++ b/Documentation/admin-guide/kdump/kdump.rst
@@ -180,10 +180,6 @@ Dump-capture kernel config options (Arch Dependent, i386 and x86_64)
1) On i386, enable high memory support under "Processor type and
features"::
- CONFIG_HIGHMEM64G=y
-
- or::
-
CONFIG_HIGHMEM4G
2) With CONFIG_SMP=y, usually nr_cpus=1 need specified on the kernel
diff --git a/Documentation/arch/x86/usb-legacy-support.rst b/Documentation/arch/x86/usb-legacy-support.rst
index e01c08b7c981..b17bf122270a 100644
--- a/Documentation/arch/x86/usb-legacy-support.rst
+++ b/Documentation/arch/x86/usb-legacy-support.rst
@@ -20,11 +20,7 @@ It has several drawbacks, though:
features (wheel, extra buttons, touchpad mode) of the real PS/2 mouse may
not be available.
-2) If CONFIG_HIGHMEM64G is enabled, the PS/2 mouse emulation can cause
- system crashes, because the SMM BIOS is not expecting to be in PAE mode.
- The Intel E7505 is a typical machine where this happens.
-
-3) If AMD64 64-bit mode is enabled, again system crashes often happen,
+2) If AMD64 64-bit mode is enabled, again system crashes often happen,
because the SMM BIOS isn't expecting the CPU to be in 64-bit mode. The
BIOS manufacturers only test with Windows, and Windows doesn't do 64-bit
yet.
@@ -38,11 +34,6 @@ Problem 1)
compiled-in, too.
Problem 2)
- can currently only be solved by either disabling HIGHMEM64G
- in the kernel config or USB Legacy support in the BIOS. A BIOS update
- could help, but so far no such update exists.
-
-Problem 3)
is usually fixed by a BIOS update. Check the board
manufacturers web site. If an update is not available, disable USB
Legacy support in the BIOS. If this alone doesn't help, try also adding
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 42494739344d..b373db8a8176 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1383,15 +1383,11 @@ config X86_CPUID
with major 203 and minors 0 to 31 for /dev/cpu/0/cpuid to
/dev/cpu/31/cpuid.
-choice
- prompt "High Memory Support"
- default HIGHMEM4G
+config HIGHMEM4G
+ bool "High Memory Support"
depends on X86_32
-
-config NOHIGHMEM
- bool "off"
help
- Linux can use up to 64 Gigabytes of physical memory on x86 systems.
+ Linux can use up to 4 Gigabytes of physical memory on x86 systems.
However, the address space of 32-bit x86 processors is only 4
Gigabytes large. That means that, if you have a large amount of
physical memory, not all of it can be "permanently mapped" by the
@@ -1407,38 +1403,9 @@ config NOHIGHMEM
possible.
If the machine has between 1 and 4 Gigabytes physical RAM, then
- answer "4GB" here.
+ answer "Y" here.
- If more than 4 Gigabytes is used then answer "64GB" here. This
- selection turns Intel PAE (Physical Address Extension) mode on.
- PAE implements 3-level paging on IA32 processors. PAE is fully
- supported by Linux, PAE mode is implemented on all recent Intel
- processors (Pentium Pro and better). NOTE: If you say "64GB" here,
- then the kernel will not boot on CPUs that don't support PAE!
-
- The actual amount of total physical memory will either be
- auto detected or can be forced by using a kernel command line option
- such as "mem=256M". (Try "man bootparam" or see the documentation of
- your boot loader (lilo or loadlin) about how to pass options to the
- kernel at boot time.)
-
- If unsure, say "off".
-
-config HIGHMEM4G
- bool "4GB"
- help
- Select this if you have a 32-bit processor and between 1 and 4
- gigabytes of physical RAM.
-
-config HIGHMEM64G
- bool "64GB"
- depends on X86_HAVE_PAE
- select X86_PAE
- help
- Select this if you have a 32-bit processor and more than 4
- gigabytes of physical RAM.
-
-endchoice
+ If unsure, say N.
choice
prompt "Memory split" if EXPERT
@@ -1484,8 +1451,7 @@ config PAGE_OFFSET
depends on X86_32
config HIGHMEM
- def_bool y
- depends on X86_32 && (HIGHMEM64G || HIGHMEM4G)
+ def_bool HIGHMEM4G
config X86_PAE
bool "PAE (Physical Address Extension) Support"
diff --git a/arch/x86/configs/xen.config b/arch/x86/configs/xen.config
index 581296255b39..d5d091e03bd3 100644
--- a/arch/x86/configs/xen.config
+++ b/arch/x86/configs/xen.config
@@ -1,6 +1,4 @@
# global x86 required specific stuff
-# On 32-bit HIGHMEM4G is not allowed
-CONFIG_HIGHMEM64G=y
CONFIG_64BIT=y
# These enable us to allow some of the
diff --git a/arch/x86/include/asm/page_32_types.h b/arch/x86/include/asm/page_32_types.h
index faf9cc1c14bb..25c32652f404 100644
--- a/arch/x86/include/asm/page_32_types.h
+++ b/arch/x86/include/asm/page_32_types.h
@@ -11,8 +11,8 @@
* a virtual address space of one gigabyte, which limits the
* amount of physical memory you can use to about 950MB.
*
- * If you want more physical memory than this then see the CONFIG_HIGHMEM4G
- * and CONFIG_HIGHMEM64G options in the kernel configuration.
+ * If you want more physical memory than this then see the CONFIG_VMSPLIT_2G
+ * and CONFIG_HIGHMEM4G options in the kernel configuration.
*/
#define __PAGE_OFFSET_BASE _AC(CONFIG_PAGE_OFFSET, UL)
#define __PAGE_OFFSET __PAGE_OFFSET_BASE
diff --git a/arch/x86/mm/init_32.c b/arch/x86/mm/init_32.c
index ac41b1e0940d..f288aad8dc74 100644
--- a/arch/x86/mm/init_32.c
+++ b/arch/x86/mm/init_32.c
@@ -582,7 +582,7 @@ static void __init lowmem_pfn_init(void)
"only %luMB highmem pages available, ignoring highmem size of %luMB!\n"
#define MSG_HIGHMEM_TRIMMED \
- "Warning: only 4GB will be used. Use a HIGHMEM64G enabled kernel!\n"
+ "Warning: only 4GB will be used. Support for for CONFIG_HIGHMEM64G was removed!\n"
/*
* We have more RAM than fits into lowmem - we try to put it into
* highmem, also taking the highmem=x boot parameter into account:
@@ -606,18 +606,13 @@ static void __init highmem_pfn_init(void)
#ifndef CONFIG_HIGHMEM
/* Maximum memory usable is what is directly addressable */
printk(KERN_WARNING "Warning only %ldMB will be used.\n", MAXMEM>>20);
- if (max_pfn > MAX_NONPAE_PFN)
- printk(KERN_WARNING "Use a HIGHMEM64G enabled kernel.\n");
- else
- printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
+ printk(KERN_WARNING "Use a HIGHMEM enabled kernel.\n");
max_pfn = MAXMEM_PFN;
#else /* !CONFIG_HIGHMEM */
-#ifndef CONFIG_HIGHMEM64G
if (max_pfn > MAX_NONPAE_PFN) {
max_pfn = MAX_NONPAE_PFN;
printk(KERN_WARNING MSG_HIGHMEM_TRIMMED);
}
-#endif /* !CONFIG_HIGHMEM64G */
#endif /* !CONFIG_HIGHMEM */
}
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v2 07/11] x86: drop SWIOTLB and PHYS_ADDR_T_64BIT for PAE
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
` (5 preceding siblings ...)
2024-12-10 14:49 ` [PATCH v2 06/11] x86: remove HIGHMEM64G support Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-20 2:52 ` kernel test robot
2024-12-10 14:49 ` [PATCH v2 08/11] x86: drop support for CONFIG_HIGHPTE Arnd Bergmann
` (4 subsequent siblings)
11 siblings, 1 reply; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
From: Arnd Bergmann <arnd@arndb.de>
Since kernels with and without CONFIG_X86_PAE are now limited
to the low 4GB of physical address space, there is no need to
use either swiotlb or 64-bit phys_addr_t any more, so stop
selecting these and fix up the build warnings from that.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/x86/Kconfig | 2 --
arch/x86/mm/pgtable.c | 5 +++--
include/linux/mm.h | 2 +-
3 files changed, 4 insertions(+), 5 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index b373db8a8176..d0d055f6f56e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1456,8 +1456,6 @@ config HIGHMEM
config X86_PAE
bool "PAE (Physical Address Extension) Support"
depends on X86_32 && X86_HAVE_PAE
- select PHYS_ADDR_T_64BIT
- select SWIOTLB
help
PAE is required for NX support, and furthermore enables
larger swapspace support for non-overcommit purposes. It
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index 5745a354a241..b8f9e69b25c1 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -765,11 +765,12 @@ int pud_set_huge(pud_t *pud, phys_addr_t addr, pgprot_t prot)
int pmd_set_huge(pmd_t *pmd, phys_addr_t addr, pgprot_t prot)
{
u8 uniform;
+ struct resource res = DEFINE_RES_MEM(addr, PMD_SIZE);
mtrr_type_lookup(addr, addr + PMD_SIZE, &uniform);
if (!uniform) {
- pr_warn_once("%s: Cannot satisfy [mem %#010llx-%#010llx] with a huge-page mapping due to MTRR override.\n",
- __func__, addr, addr + PMD_SIZE);
+ pr_warn_once("%s: Cannot satisfy %pR with a huge-page mapping due to MTRR override.\n",
+ __func__, &res);
return 0;
}
diff --git a/include/linux/mm.h b/include/linux/mm.h
index c39c4945946c..7725e9e46e90 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -99,7 +99,7 @@ extern int mmap_rnd_compat_bits __read_mostly;
#ifndef DIRECT_MAP_PHYSMEM_END
# ifdef MAX_PHYSMEM_BITS
-# define DIRECT_MAP_PHYSMEM_END ((1ULL << MAX_PHYSMEM_BITS) - 1)
+# define DIRECT_MAP_PHYSMEM_END (phys_addr_t)((1ULL << MAX_PHYSMEM_BITS) - 1)
# else
# define DIRECT_MAP_PHYSMEM_END (((phys_addr_t)-1)&~(1ULL<<63))
# endif
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v2 07/11] x86: drop SWIOTLB and PHYS_ADDR_T_64BIT for PAE
2024-12-10 14:49 ` [PATCH v2 07/11] x86: drop SWIOTLB and PHYS_ADDR_T_64BIT for PAE Arnd Bergmann
@ 2024-12-20 2:52 ` kernel test robot
2024-12-22 21:19 ` Arnd Bergmann
0 siblings, 1 reply; 21+ messages in thread
From: kernel test robot @ 2024-12-20 2:52 UTC (permalink / raw)
To: Arnd Bergmann
Cc: oe-lkp, lkp, linux-kernel, linux-mm, x86, Arnd Bergmann,
Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin, Linus Torvalds, Andy Shevchenko, Matthew Wilcox,
oliver.sang
Hello,
kernel test robot noticed "WARNING:at_mm/sparse.c:#sparse_init" on:
commit: a20f815a6f361e18a0a2a9480b5a5340c5860c7f ("[PATCH v2 07/11] x86: drop SWIOTLB and PHYS_ADDR_T_64BIT for PAE")
url: https://github.com/intel-lab-lkp/linux/commits/Arnd-Bergmann/x86-Kconfig-Geode-CPU-has-cmpxchg8b/20241210-225443
base: https://git.kernel.org/cgit/linux/kernel/git/tip/tip.git f576cfc3d433316990802cd521ddea645eb3971b
patch link: https://lore.kernel.org/all/20241210144945.2325330-8-arnd@kernel.org/
patch subject: [PATCH v2 07/11] x86: drop SWIOTLB and PHYS_ADDR_T_64BIT for PAE
in testcase: boot
config: i386-randconfig-001-20241213
compiler: gcc-12
test machine: qemu-system-i386 -enable-kvm -cpu SandyBridge -smp 2 -m 4G
(please refer to attached dmesg/kmsg for entire log/backtrace)
+------------------------------------------------+------------+------------+
| | 620a8e2d2b | a20f815a6f |
+------------------------------------------------+------------+------------+
| WARNING:at_mm/sparse.c:#sparse_init | 0 | 12 |
| EIP:sparse_init | 0 | 12 |
| BUG:kernel_NULL_pointer_dereference,address | 0 | 12 |
| Oops | 0 | 12 |
| Kernel_panic-not_syncing:Fatal_exception | 0 | 12 |
+------------------------------------------------+------------+------------+
If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <oliver.sang@intel.com>
| Closes: https://lore.kernel.org/oe-lkp/202412201005.77fb063-lkp@intel.com
[ 0.068283][ T0] ------------[ cut here ]------------
[ 0.068644][ T0] WARNING: CPU: 0 PID: 0 at mm/sparse.c:149 sparse_init (mm/sparse.c:149 mm/sparse.c:227 mm/sparse.c:268 mm/sparse.c:565)
[ 0.069169][ T0] Modules linked in:
[ 0.069424][ T0] CPU: 0 UID: 0 PID: 0 Comm: swapper Not tainted 6.13.0-rc2-00153-ga20f815a6f36 #1 55e1ad47972e976fedebf027f6853ef569639c5a
[ 0.070285][ T0] Hardware name: QEMU Standard PC (i440FX + PIIX, 1996), BIOS 1.16.2-debian-1.16.2-1 04/01/2014
[ 0.070972][ T0] EIP: sparse_init (mm/sparse.c:149 mm/sparse.c:227 mm/sparse.c:268 mm/sparse.c:565)
[ 0.071277][ T0] Code: 85 d2 74 d1 8b 0d 44 5f 72 b2 85 c9 7e 1c 89 54 24 08 31 c0 31 d2 89 44 24 0c 89 54 24 04 c7 04 24 d8 e5 04 b2 e8 55 ea a2 fe <0f> 0b eb a7 90 8b 0d 80 16 e7 b2 31 d2 8d b4 26 00 00 00 00 90 83
All code
========
0: 85 d2 test %edx,%edx
2: 74 d1 je 0xffffffffffffffd5
4: 8b 0d 44 5f 72 b2 mov -0x4d8da0bc(%rip),%ecx # 0xffffffffb2725f4e
a: 85 c9 test %ecx,%ecx
c: 7e 1c jle 0x2a
e: 89 54 24 08 mov %edx,0x8(%rsp)
12: 31 c0 xor %eax,%eax
14: 31 d2 xor %edx,%edx
16: 89 44 24 0c mov %eax,0xc(%rsp)
1a: 89 54 24 04 mov %edx,0x4(%rsp)
1e: c7 04 24 d8 e5 04 b2 movl $0xb204e5d8,(%rsp)
25: e8 55 ea a2 fe call 0xfffffffffea2ea7f
2a:* 0f 0b ud2 <-- trapping instruction
2c: eb a7 jmp 0xffffffffffffffd5
2e: 90 nop
2f: 8b 0d 80 16 e7 b2 mov -0x4d18e980(%rip),%ecx # 0xffffffffb2e716b5
35: 31 d2 xor %edx,%edx
37: 8d b4 26 00 00 00 00 lea 0x0(%rsi,%riz,1),%esi
3e: 90 nop
3f: 83 .byte 0x83
Code starting with the faulting instruction
===========================================
0: 0f 0b ud2
2: eb a7 jmp 0xffffffffffffffab
4: 90 nop
5: 8b 0d 80 16 e7 b2 mov -0x4d18e980(%rip),%ecx # 0xffffffffb2e7168b
b: 31 d2 xor %edx,%edx
d: 8d b4 26 00 00 00 00 lea 0x0(%rsi,%riz,1),%esi
14: 90 nop
15: 83 .byte 0x83
[ 0.072580][ T0] EAX: 00000000 EBX: b218feb4 ECX: 00000000 EDX: 0000009f
[ 0.073047][ T0] ESI: b218febc EDI: 00000000 EBP: b218fecc ESP: b218feb4
[ 0.073513][ T0] DS: 007b ES: 007b FS: 0000 GS: 0000 SS: febc EFLAGS: 00210046
[ 0.074016][ T0] CR0: 80050033 CR2: 00000000 CR3: 02773000 CR4: 00000090
[ 0.074492][ T0] Call Trace:
[ 0.074709][ T0] ? show_regs (arch/x86/kernel/dumpstack.c:479)
[ 0.074989][ T0] ? sparse_init (mm/sparse.c:149 mm/sparse.c:227 mm/sparse.c:268 mm/sparse.c:565)
[ 0.075283][ T0] ? __warn (kernel/panic.c:748)
[ 0.075550][ T0] ? sparse_init (mm/sparse.c:149 mm/sparse.c:227 mm/sparse.c:268 mm/sparse.c:565)
[ 0.075845][ T0] ? sparse_init (mm/sparse.c:149 mm/sparse.c:227 mm/sparse.c:268 mm/sparse.c:565)
[ 0.076140][ T0] ? report_bug (lib/bug.c:180 lib/bug.c:219)
[ 0.076437][ T0] ? sparse_init (mm/sparse.c:149 mm/sparse.c:227 mm/sparse.c:268 mm/sparse.c:565)
[ 0.076731][ T0] ? early_fixup_exception (arch/x86/mm/extable.c:415)
[ 0.077081][ T0] ? early_idt_handler_common (arch/x86/kernel/head_32.S:352)
[ 0.077450][ T0] ? register_lock_class (kernel/locking/lockdep.c:195 kernel/locking/lockdep.c:1322)
[ 0.077799][ T0] ? sparse_init (mm/sparse.c:149 mm/sparse.c:227 mm/sparse.c:268 mm/sparse.c:565)
[ 0.078113][ T0] ? native_flush_tlb_global (arch/x86/include/asm/irqflags.h:154 arch/x86/mm/tlb.c:1225)
[ 0.078480][ T0] paging_init (arch/x86/mm/init_32.c:685)
[ 0.078759][ T0] native_pagetable_init (arch/x86/mm/init_32.c:481)
[ 0.079101][ T0] ? _printk (kernel/printk/printk.c:2461)
[ 0.079367][ T0] ? dma_contiguous_reserve (kernel/dma/contiguous.c:250)
[ 0.079722][ T0] setup_arch (arch/x86/kernel/setup.c:1130)
[ 0.080011][ T0] start_kernel (init/main.c:924 (discriminator 3))
[ 0.080301][ T0] ? load_ucode_bsp (arch/x86/kernel/cpu/microcode/core.c:135)
[ 0.080622][ T0] i386_start_kernel (??:?)
[ 0.080936][ T0] startup_32_smp (arch/x86/kernel/head_32.S:292)
[ 0.081247][ T0] irq event stamp: 0
[ 0.081500][ T0] hardirqs last enabled at (0): 0x0
[ 0.081922][ T0] hardirqs last disabled at (0): 0x0
[ 0.082349][ T0] softirqs last enabled at (0): 0x0
[ 0.082771][ T0] softirqs last disabled at (0): 0x0
[ 0.083193][ T0] ---[ end trace 0000000000000000 ]---
The kernel config and materials to reproduce are available at:
https://download.01.org/0day-ci/archive/20241220/202412201005.77fb063-lkp@intel.com
--
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki
^ permalink raw reply [flat|nested] 21+ messages in thread* Re: [PATCH v2 07/11] x86: drop SWIOTLB and PHYS_ADDR_T_64BIT for PAE
2024-12-20 2:52 ` kernel test robot
@ 2024-12-22 21:19 ` Arnd Bergmann
0 siblings, 0 replies; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-22 21:19 UTC (permalink / raw)
To: kernel test robot, Arnd Bergmann
Cc: oe-lkp, kernel test robot, linux-kernel, linux-mm, x86,
Thomas Gleixner, Ingo Molnar, Borislav Petkov, Dave Hansen,
H. Peter Anvin, Linus Torvalds, Andy Shevchenko, Matthew Wilcox
On Fri, Dec 20, 2024, at 03:52, kernel test robot wrote:
>
> config: i386-randconfig-001-20241213
> compiler: gcc-12
> test machine: qemu-system-i386 -enable-kvm -cpu SandyBridge -smp 2 -m 4G
>
> (please refer to attached dmesg/kmsg for entire log/backtrace)
>
I haven't been able to figure this out, apparently something goes
wrong on a KVM guest that has more than 32-bit of addressing (RAM+MMIO)
when it uses a 32-bit phys_addr_t.
I changed the patch now to only drop SWIOTLB, not PHYS_ADDR_T_64BIT.
Arnd
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 08/11] x86: drop support for CONFIG_HIGHPTE
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
` (6 preceding siblings ...)
2024-12-10 14:49 ` [PATCH v2 07/11] x86: drop SWIOTLB and PHYS_ADDR_T_64BIT for PAE Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 14:49 ` [PATCH v2 09/11] x86: document X86_INTEL_MID as 64-bit-only Arnd Bergmann
` (3 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
From: Arnd Bergmann <arnd@arndb.de>
With the maximum amount of RAM now 4GB, there is very little point
to still have PTE pages in highmem. Drop this for simplification.
The only other architecture supporting HIGHPTE is 32-bit arm, and
once that feature is removed as well, the highpte logic can be
dropped from common code as well.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
.../admin-guide/kernel-parameters.txt | 7 -----
arch/x86/Kconfig | 9 -------
arch/x86/include/asm/pgalloc.h | 5 ----
arch/x86/mm/pgtable.c | 27 +------------------
4 files changed, 1 insertion(+), 47 deletions(-)
diff --git a/Documentation/admin-guide/kernel-parameters.txt b/Documentation/admin-guide/kernel-parameters.txt
index eca370e99844..cf25853a5c4a 100644
--- a/Documentation/admin-guide/kernel-parameters.txt
+++ b/Documentation/admin-guide/kernel-parameters.txt
@@ -7341,13 +7341,6 @@
16 - SIGBUS faults
Example: user_debug=31
- userpte=
- [X86,EARLY] Flags controlling user PTE allocations.
-
- nohigh = do not allocate PTE pages in
- HIGHMEM regardless of setting
- of CONFIG_HIGHPTE.
-
vdso= [X86,SH,SPARC]
On X86_32, this is an alias for vdso32=. Otherwise:
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index d0d055f6f56e..d8a8bf9ea9b9 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -1621,15 +1621,6 @@ config X86_PMEM_LEGACY
Say Y if unsure.
-config HIGHPTE
- bool "Allocate 3rd-level pagetables from highmem"
- depends on HIGHMEM
- help
- The VM uses one page table entry for each page of physical memory.
- For systems with a lot of RAM, this can be wasteful of precious
- low memory. Setting this option will put user-space page table
- entries in high memory.
-
config X86_CHECK_BIOS_CORRUPTION
bool "Check for low memory corruption"
help
diff --git a/arch/x86/include/asm/pgalloc.h b/arch/x86/include/asm/pgalloc.h
index dcd836b59beb..582cf5b7ec8c 100644
--- a/arch/x86/include/asm/pgalloc.h
+++ b/arch/x86/include/asm/pgalloc.h
@@ -29,11 +29,6 @@ static inline void paravirt_release_pud(unsigned long pfn) {}
static inline void paravirt_release_p4d(unsigned long pfn) {}
#endif
-/*
- * Flags to use when allocating a user page table page.
- */
-extern gfp_t __userpte_alloc_gfp;
-
#ifdef CONFIG_MITIGATION_PAGE_TABLE_ISOLATION
/*
* Instead of one PGD, we acquire two PGDs. Being order-1, it is
diff --git a/arch/x86/mm/pgtable.c b/arch/x86/mm/pgtable.c
index b8f9e69b25c1..3d7072aec486 100644
--- a/arch/x86/mm/pgtable.c
+++ b/arch/x86/mm/pgtable.c
@@ -12,12 +12,6 @@ phys_addr_t physical_mask __ro_after_init = (1ULL << __PHYSICAL_MASK_SHIFT) - 1;
EXPORT_SYMBOL(physical_mask);
#endif
-#ifdef CONFIG_HIGHPTE
-#define PGTABLE_HIGHMEM __GFP_HIGHMEM
-#else
-#define PGTABLE_HIGHMEM 0
-#endif
-
#ifndef CONFIG_PARAVIRT
static inline
void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table)
@@ -26,29 +20,10 @@ void paravirt_tlb_remove_table(struct mmu_gather *tlb, void *table)
}
#endif
-gfp_t __userpte_alloc_gfp = GFP_PGTABLE_USER | PGTABLE_HIGHMEM;
-
pgtable_t pte_alloc_one(struct mm_struct *mm)
{
- return __pte_alloc_one(mm, __userpte_alloc_gfp);
-}
-
-static int __init setup_userpte(char *arg)
-{
- if (!arg)
- return -EINVAL;
-
- /*
- * "userpte=nohigh" disables allocation of user pagetables in
- * high memory.
- */
- if (strcmp(arg, "nohigh") == 0)
- __userpte_alloc_gfp &= ~__GFP_HIGHMEM;
- else
- return -EINVAL;
- return 0;
+ return __pte_alloc_one(mm, GFP_PGTABLE_USER);
}
-early_param("userpte", setup_userpte);
void ___pte_free_tlb(struct mmu_gather *tlb, struct page *pte)
{
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v2 09/11] x86: document X86_INTEL_MID as 64-bit-only
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
` (7 preceding siblings ...)
2024-12-10 14:49 ` [PATCH v2 08/11] x86: drop support for CONFIG_HIGHPTE Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 14:49 ` [PATCH v2 10/11] x86: remove old STA2x11 support Arnd Bergmann
` (2 subsequent siblings)
11 siblings, 0 replies; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox, Ferry Toth
From: Arnd Bergmann <arnd@arndb.de>
The X86_INTEL_MID code was originally introduced for the 32-bit
Moorestown/Medfield/Clovertrail platform, later the 64-bit
Merrifield/Moorefield variants were added, but the final Morganfield
14nm platform was canceled before it hit the market.
To help users understand what the option actually refers to, update the
help text, and add a dependency on 64-bit kernels.
Ferry confirmed that all the hardware can run 64-bit kernels these days,
but is still testing 32-bit kernels on the Intel Edison board, so this
remains possible, but is guarded by a CONFIG_EXPERT dependency now,
to gently push remaining users towards using CONFIG_64BIT.
Cc: Ferry Toth <fntoth@gmail.com>
Link: https://lore.kernel.org/lkml/d890eecc-97de-4abf-8e0e-b881d5db5c1d@gmail.com/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/x86/Kconfig | 50 ++++++++++++++++++++++++++++--------------------
1 file changed, 29 insertions(+), 21 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index d8a8bf9ea9b9..5ca8049004cb 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -544,12 +544,12 @@ config X86_EXTENDED_PLATFORM
RDC R-321x SoC
SGI 320/540 (Visual Workstation)
STA2X11-based (e.g. Northville)
- Moorestown MID devices
64-bit platforms (CONFIG_64BIT=y):
Numascale NumaChip
ScaleMP vSMP
SGI Ultraviolet
+ Merrifield/Moorefield MID devices
If you have one of these systems, or if you want to build a
generic distribution kernel, say Y here - otherwise say N.
@@ -594,8 +594,31 @@ config X86_UV
This option is needed in order to support SGI Ultraviolet systems.
If you don't have one of these, you should say N here.
-# Following is an alphabetically sorted list of 32 bit extended platforms
-# Please maintain the alphabetic order if and when there are additions
+config X86_INTEL_MID
+ bool "Intel Z34xx/Z35xx MID platform support"
+ depends on X86_EXTENDED_PLATFORM
+ depends on X86_PLATFORM_DEVICES
+ depends on PCI
+ depends on X86_64 || (EXPERT && PCI_GOANY)
+ depends on X86_IO_APIC
+ select I2C
+ select DW_APB_TIMER
+ select INTEL_SCU_PCI
+ help
+ Select to build a kernel capable of supporting 64-bit Intel MID
+ (Mobile Internet Device) platform systems which do not have
+ the PCI legacy interfaces.
+
+ The only supported devices are the 22nm Merrified (Z34xx)
+ and Moorefield (Z35xx) SoC used in the Intel Edison board and
+ a small number of Android devices such as the Asus Zenfone 2,
+ Asus FonePad 8 and Dell Venue 7.
+
+ If you are building for a PC class system or non-MID tablet
+ SoCs like Bay Trail (Z36xx/Z37xx), say N here.
+
+ Intel MID platforms are based on an Intel processor and chipset which
+ consume less power than most of the x86 derivatives.
config X86_GOLDFISH
bool "Goldfish (Virtual Platform)"
@@ -605,6 +628,9 @@ config X86_GOLDFISH
for Android development. Unless you are building for the Android
Goldfish emulator say N here.
+# Following is an alphabetically sorted list of 32 bit extended platforms
+# Please maintain the alphabetic order if and when there are additions
+
config X86_INTEL_CE
bool "CE4100 TV platform"
depends on PCI
@@ -620,24 +646,6 @@ config X86_INTEL_CE
This option compiles in support for the CE4100 SOC for settop
boxes and media devices.
-config X86_INTEL_MID
- bool "Intel MID platform support"
- depends on X86_EXTENDED_PLATFORM
- depends on X86_PLATFORM_DEVICES
- depends on PCI
- depends on X86_64 || (PCI_GOANY && X86_32)
- depends on X86_IO_APIC
- select I2C
- select DW_APB_TIMER
- select INTEL_SCU_PCI
- help
- Select to build a kernel capable of supporting Intel MID (Mobile
- Internet Device) platform systems which do not have the PCI legacy
- interfaces. If you are building for a PC class system say N here.
-
- Intel MID platforms are based on an Intel processor and chipset which
- consume less power than most of the x86 derivatives.
-
config X86_INTEL_QUARK
bool "Intel Quark platform support"
depends on X86_32
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* [PATCH v2 10/11] x86: remove old STA2x11 support
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
` (8 preceding siblings ...)
2024-12-10 14:49 ` [PATCH v2 09/11] x86: document X86_INTEL_MID as 64-bit-only Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 15:39 ` Andy Shevchenko
2024-12-10 14:49 ` [PATCH v2 11/11] x86: Move platforms to Kconfig.platforms Arnd Bergmann
2024-12-10 15:43 ` [PATCH v2 00/11] x86: 32-bit cleanups Andy Shevchenko
11 siblings, 1 reply; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
From: Arnd Bergmann <arnd@arndb.de>
ST ConneXt STA2x11 was an interface chip for Atom E6xx processors,
using a number of components usually found on Arm SoCs. Most of this
was merged upstream, but it was never complete enough to actually work
and has been abandoned for many years.
We already had an agreement on removing it in 2022, but nobody ever
submitted the patch to do it.
Without STA2x11, the CONFIG_X86_32_NON_STANDARD no longer has any
use.
Link: https://lore.kernel.org/lkml/Yw3DKCuDoPkCaqxE@arcana.i.gnudd.com/
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/x86/Kconfig | 32 +----
arch/x86/include/asm/sta2x11.h | 13 --
arch/x86/pci/Makefile | 2 -
arch/x86/pci/sta2x11-fixup.c | 233 ---------------------------------
4 files changed, 3 insertions(+), 277 deletions(-)
delete mode 100644 arch/x86/include/asm/sta2x11.h
delete mode 100644 arch/x86/pci/sta2x11-fixup.c
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 5ca8049004cb..fb071548bc1e 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -543,7 +543,6 @@ config X86_EXTENDED_PLATFORM
AMD Elan
RDC R-321x SoC
SGI 320/540 (Visual Workstation)
- STA2X11-based (e.g. Northville)
64-bit platforms (CONFIG_64BIT=y):
Numascale NumaChip
@@ -727,18 +726,6 @@ config X86_RDC321X
as R-8610-(G).
If you don't have one of these chips, you should say N here.
-config X86_32_NON_STANDARD
- bool "Support non-standard 32-bit SMP architectures"
- depends on X86_32 && SMP
- depends on X86_EXTENDED_PLATFORM
- help
- This option compiles in the STA2X11 default
- subarchitecture. It is intended for a generic binary
- kernel. If you select them all, kernel will probe it one by
- one and will fallback to default.
-
-# Alphabetically sorted list of Non standard 32 bit platforms
-
config X86_SUPPORTS_MEMORY_FAILURE
def_bool y
# MCE code calls memory_failure():
@@ -748,19 +735,6 @@ config X86_SUPPORTS_MEMORY_FAILURE
depends on X86_64 || !SPARSEMEM
select ARCH_SUPPORTS_MEMORY_FAILURE
-config STA2X11
- bool "STA2X11 Companion Chip Support"
- depends on X86_32_NON_STANDARD && PCI
- select SWIOTLB
- select MFD_STA2X11
- select GPIOLIB
- help
- This adds support for boards based on the STA2X11 IO-Hub,
- a.k.a. "ConneXt". The chip is used in place of the standard
- PC chipset, so all "standard" peripherals are missing. If this
- option is selected the kernel will still be able to boot on
- standard PC machines.
-
config X86_32_IRIS
tristate "Eurobraille/Iris poweroff module"
depends on X86_32
@@ -1098,7 +1072,7 @@ config UP_LATE_INIT
config X86_UP_APIC
bool "Local APIC support on uniprocessors" if !PCI_MSI
default PCI_MSI
- depends on X86_32 && !SMP && !X86_32_NON_STANDARD
+ depends on X86_32 && !SMP
help
A local APIC (Advanced Programmable Interrupt Controller) is an
integrated interrupt controller in the CPU. If you have a single-CPU
@@ -1123,7 +1097,7 @@ config X86_UP_IOAPIC
config X86_LOCAL_APIC
def_bool y
- depends on X86_64 || SMP || X86_32_NON_STANDARD || X86_UP_APIC || PCI_MSI
+ depends on X86_64 || SMP || X86_UP_APIC || PCI_MSI
select IRQ_DOMAIN_HIERARCHY
config ACPI_MADT_WAKEUP
@@ -1583,7 +1557,7 @@ config ARCH_FLATMEM_ENABLE
config ARCH_SPARSEMEM_ENABLE
def_bool y
- depends on X86_64 || NUMA || X86_32 || X86_32_NON_STANDARD
+ depends on X86_64 || NUMA || X86_32
select SPARSEMEM_STATIC if X86_32
select SPARSEMEM_VMEMMAP_ENABLE if X86_64
diff --git a/arch/x86/include/asm/sta2x11.h b/arch/x86/include/asm/sta2x11.h
deleted file mode 100644
index e0975e9c4f47..000000000000
--- a/arch/x86/include/asm/sta2x11.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-/*
- * Header file for STMicroelectronics ConneXt (STA2X11) IOHub
- */
-#ifndef __ASM_STA2X11_H
-#define __ASM_STA2X11_H
-
-#include <linux/pci.h>
-
-/* This needs to be called from the MFD to configure its sub-devices */
-struct sta2x11_instance *sta2x11_get_instance(struct pci_dev *pdev);
-
-#endif /* __ASM_STA2X11_H */
diff --git a/arch/x86/pci/Makefile b/arch/x86/pci/Makefile
index 48bcada5cabe..4933fb337983 100644
--- a/arch/x86/pci/Makefile
+++ b/arch/x86/pci/Makefile
@@ -12,8 +12,6 @@ obj-$(CONFIG_X86_INTEL_CE) += ce4100.o
obj-$(CONFIG_ACPI) += acpi.o
obj-y += legacy.o irq.o
-obj-$(CONFIG_STA2X11) += sta2x11-fixup.o
-
obj-$(CONFIG_X86_NUMACHIP) += numachip.o
obj-$(CONFIG_X86_INTEL_MID) += intel_mid_pci.o
diff --git a/arch/x86/pci/sta2x11-fixup.c b/arch/x86/pci/sta2x11-fixup.c
deleted file mode 100644
index 8c8ddc4dcc08..000000000000
--- a/arch/x86/pci/sta2x11-fixup.c
+++ /dev/null
@@ -1,233 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0-only
-/*
- * DMA translation between STA2x11 AMBA memory mapping and the x86 memory mapping
- *
- * ST Microelectronics ConneXt (STA2X11/STA2X10)
- *
- * Copyright (c) 2010-2011 Wind River Systems, Inc.
- */
-
-#include <linux/pci.h>
-#include <linux/pci_ids.h>
-#include <linux/export.h>
-#include <linux/list.h>
-#include <linux/dma-map-ops.h>
-#include <linux/swiotlb.h>
-#include <asm/iommu.h>
-#include <asm/sta2x11.h>
-
-#define STA2X11_SWIOTLB_SIZE (4*1024*1024)
-
-/*
- * We build a list of bus numbers that are under the ConneXt. The
- * main bridge hosts 4 busses, which are the 4 endpoints, in order.
- */
-#define STA2X11_NR_EP 4 /* 0..3 included */
-#define STA2X11_NR_FUNCS 8 /* 0..7 included */
-#define STA2X11_AMBA_SIZE (512 << 20)
-
-struct sta2x11_ahb_regs { /* saved during suspend */
- u32 base, pexlbase, pexhbase, crw;
-};
-
-struct sta2x11_mapping {
- int is_suspended;
- struct sta2x11_ahb_regs regs[STA2X11_NR_FUNCS];
-};
-
-struct sta2x11_instance {
- struct list_head list;
- int bus0;
- struct sta2x11_mapping map[STA2X11_NR_EP];
-};
-
-static LIST_HEAD(sta2x11_instance_list);
-
-/* At probe time, record new instances of this bridge (likely one only) */
-static void sta2x11_new_instance(struct pci_dev *pdev)
-{
- struct sta2x11_instance *instance;
-
- instance = kzalloc(sizeof(*instance), GFP_ATOMIC);
- if (!instance)
- return;
- /* This has a subordinate bridge, with 4 more-subordinate ones */
- instance->bus0 = pdev->subordinate->number + 1;
-
- if (list_empty(&sta2x11_instance_list)) {
- int size = STA2X11_SWIOTLB_SIZE;
- /* First instance: register your own swiotlb area */
- dev_info(&pdev->dev, "Using SWIOTLB (size %i)\n", size);
- if (swiotlb_init_late(size, GFP_DMA, NULL))
- dev_emerg(&pdev->dev, "init swiotlb failed\n");
- }
- list_add(&instance->list, &sta2x11_instance_list);
-}
-DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, 0xcc17, sta2x11_new_instance);
-
-/*
- * Utility functions used in this file from below
- */
-static struct sta2x11_instance *sta2x11_pdev_to_instance(struct pci_dev *pdev)
-{
- struct sta2x11_instance *instance;
- int ep;
-
- list_for_each_entry(instance, &sta2x11_instance_list, list) {
- ep = pdev->bus->number - instance->bus0;
- if (ep >= 0 && ep < STA2X11_NR_EP)
- return instance;
- }
- return NULL;
-}
-
-static int sta2x11_pdev_to_ep(struct pci_dev *pdev)
-{
- struct sta2x11_instance *instance;
-
- instance = sta2x11_pdev_to_instance(pdev);
- if (!instance)
- return -1;
-
- return pdev->bus->number - instance->bus0;
-}
-
-/* This is exported, as some devices need to access the MFD registers */
-struct sta2x11_instance *sta2x11_get_instance(struct pci_dev *pdev)
-{
- return sta2x11_pdev_to_instance(pdev);
-}
-EXPORT_SYMBOL(sta2x11_get_instance);
-
-/* At setup time, we use our own ops if the device is a ConneXt one */
-static void sta2x11_setup_pdev(struct pci_dev *pdev)
-{
- struct sta2x11_instance *instance = sta2x11_pdev_to_instance(pdev);
-
- if (!instance) /* either a sta2x11 bridge or another ST device */
- return;
-
- /* We must enable all devices as master, for audio DMA to work */
- pci_set_master(pdev);
-}
-DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_setup_pdev);
-
-/*
- * At boot we must set up the mappings for the pcie-to-amba bridge.
- * It involves device access, and the same happens at suspend/resume time
- */
-
-#define AHB_MAPB 0xCA4
-#define AHB_CRW(i) (AHB_MAPB + 0 + (i) * 0x10)
-#define AHB_CRW_SZMASK 0xfffffc00UL
-#define AHB_CRW_ENABLE (1 << 0)
-#define AHB_CRW_WTYPE_MEM (2 << 1)
-#define AHB_CRW_ROE (1UL << 3) /* Relax Order Ena */
-#define AHB_CRW_NSE (1UL << 4) /* No Snoop Enable */
-#define AHB_BASE(i) (AHB_MAPB + 4 + (i) * 0x10)
-#define AHB_PEXLBASE(i) (AHB_MAPB + 8 + (i) * 0x10)
-#define AHB_PEXHBASE(i) (AHB_MAPB + 12 + (i) * 0x10)
-
-/* At probe time, enable mapping for each endpoint, using the pdev */
-static void sta2x11_map_ep(struct pci_dev *pdev)
-{
- struct sta2x11_instance *instance = sta2x11_pdev_to_instance(pdev);
- struct device *dev = &pdev->dev;
- u32 amba_base, max_amba_addr;
- int i, ret;
-
- if (!instance)
- return;
-
- pci_read_config_dword(pdev, AHB_BASE(0), &amba_base);
- max_amba_addr = amba_base + STA2X11_AMBA_SIZE - 1;
-
- ret = dma_direct_set_offset(dev, 0, amba_base, STA2X11_AMBA_SIZE);
- if (ret)
- dev_err(dev, "sta2x11: could not set DMA offset\n");
-
- dev->bus_dma_limit = max_amba_addr;
- dma_set_mask_and_coherent(&pdev->dev, max_amba_addr);
-
- /* Configure AHB mapping */
- pci_write_config_dword(pdev, AHB_PEXLBASE(0), 0);
- pci_write_config_dword(pdev, AHB_PEXHBASE(0), 0);
- pci_write_config_dword(pdev, AHB_CRW(0), STA2X11_AMBA_SIZE |
- AHB_CRW_WTYPE_MEM | AHB_CRW_ENABLE);
-
- /* Disable all the other windows */
- for (i = 1; i < STA2X11_NR_FUNCS; i++)
- pci_write_config_dword(pdev, AHB_CRW(i), 0);
-
- dev_info(&pdev->dev,
- "sta2x11: Map EP %i: AMBA address %#8x-%#8x\n",
- sta2x11_pdev_to_ep(pdev), amba_base, max_amba_addr);
-}
-DECLARE_PCI_FIXUP_ENABLE(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, sta2x11_map_ep);
-
-#ifdef CONFIG_PM /* Some register values must be saved and restored */
-
-static struct sta2x11_mapping *sta2x11_pdev_to_mapping(struct pci_dev *pdev)
-{
- struct sta2x11_instance *instance;
- int ep;
-
- instance = sta2x11_pdev_to_instance(pdev);
- if (!instance)
- return NULL;
- ep = sta2x11_pdev_to_ep(pdev);
- return instance->map + ep;
-}
-
-static void suspend_mapping(struct pci_dev *pdev)
-{
- struct sta2x11_mapping *map = sta2x11_pdev_to_mapping(pdev);
- int i;
-
- if (!map)
- return;
-
- if (map->is_suspended)
- return;
- map->is_suspended = 1;
-
- /* Save all window configs */
- for (i = 0; i < STA2X11_NR_FUNCS; i++) {
- struct sta2x11_ahb_regs *regs = map->regs + i;
-
- pci_read_config_dword(pdev, AHB_BASE(i), ®s->base);
- pci_read_config_dword(pdev, AHB_PEXLBASE(i), ®s->pexlbase);
- pci_read_config_dword(pdev, AHB_PEXHBASE(i), ®s->pexhbase);
- pci_read_config_dword(pdev, AHB_CRW(i), ®s->crw);
- }
-}
-DECLARE_PCI_FIXUP_SUSPEND(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, suspend_mapping);
-
-static void resume_mapping(struct pci_dev *pdev)
-{
- struct sta2x11_mapping *map = sta2x11_pdev_to_mapping(pdev);
- int i;
-
- if (!map)
- return;
-
-
- if (!map->is_suspended)
- goto out;
- map->is_suspended = 0;
-
- /* Restore all window configs */
- for (i = 0; i < STA2X11_NR_FUNCS; i++) {
- struct sta2x11_ahb_regs *regs = map->regs + i;
-
- pci_write_config_dword(pdev, AHB_BASE(i), regs->base);
- pci_write_config_dword(pdev, AHB_PEXLBASE(i), regs->pexlbase);
- pci_write_config_dword(pdev, AHB_PEXHBASE(i), regs->pexhbase);
- pci_write_config_dword(pdev, AHB_CRW(i), regs->crw);
- }
-out:
- pci_set_master(pdev); /* Like at boot, enable master on all devices */
-}
-DECLARE_PCI_FIXUP_RESUME(PCI_VENDOR_ID_STMICRO, PCI_ANY_ID, resume_mapping);
-
-#endif /* CONFIG_PM */
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v2 10/11] x86: remove old STA2x11 support
2024-12-10 14:49 ` [PATCH v2 10/11] x86: remove old STA2x11 support Arnd Bergmann
@ 2024-12-10 15:39 ` Andy Shevchenko
0 siblings, 0 replies; 21+ messages in thread
From: Andy Shevchenko @ 2024-12-10 15:39 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-kernel, x86, Arnd Bergmann, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin, Linus Torvalds,
Andy Shevchenko, Matthew Wilcox
On Tue, Dec 10, 2024 at 4:50 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> ST ConneXt STA2x11 was an interface chip for Atom E6xx processors,
> using a number of components usually found on Arm SoCs. Most of this
> was merged upstream, but it was never complete enough to actually work
> and has been abandoned for many years.
>
> We already had an agreement on removing it in 2022, but nobody ever
> submitted the patch to do it.
>
> Without STA2x11, the CONFIG_X86_32_NON_STANDARD no longer has any
> use.
>
> Link: https://lore.kernel.org/lkml/Yw3DKCuDoPkCaqxE@arcana.i.gnudd.com/
> Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Hmm... Haven't you got a tag for (at least) this one?
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 21+ messages in thread
* [PATCH v2 11/11] x86: Move platforms to Kconfig.platforms
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
` (9 preceding siblings ...)
2024-12-10 14:49 ` [PATCH v2 10/11] x86: remove old STA2x11 support Arnd Bergmann
@ 2024-12-10 14:49 ` Arnd Bergmann
2024-12-10 15:43 ` [PATCH v2 00/11] x86: 32-bit cleanups Andy Shevchenko
11 siblings, 0 replies; 21+ messages in thread
From: Arnd Bergmann @ 2024-12-10 14:49 UTC (permalink / raw)
To: linux-kernel, x86
Cc: Arnd Bergmann, Thomas Gleixner, Ingo Molnar, Borislav Petkov,
Dave Hansen, H. Peter Anvin, Linus Torvalds, Andy Shevchenko,
Matthew Wilcox
From: Arnd Bergmann <arnd@arndb.de>
The x86 platform options in Kconfig are rather confusing, as they are a
mix of options that just control visibility of drivers and those that are
fundamental to the operation, with some of the code in arch/x86/platforms
and other code in drivers/platform/x86, and the options listed in various
places in arch/x86/Kconfig.
Make this a little more consistent by moving all options that control a
platform from arch/x86/Kconfig to arch/x86/Kconfig.platforms and put them
into a submenu.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
---
arch/x86/Kconfig | 363 +------------------------------------
arch/x86/Kconfig.platforms | 361 ++++++++++++++++++++++++++++++++++++
2 files changed, 363 insertions(+), 361 deletions(-)
create mode 100644 arch/x86/Kconfig.platforms
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index fb071548bc1e..98530ce14eab 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -526,205 +526,7 @@ config X86_FRED
ring transitions and exception/interrupt handling if the
system supports it.
-config X86_EXTENDED_PLATFORM
- bool "Support for extended (non-PC) x86 platforms"
- default y
- help
- If you disable this option then the kernel will only support
- standard PC platforms. (which covers the vast majority of
- systems out there.)
-
- If you enable this option then you'll be able to select support
- for the following non-PC x86 platforms, depending on the value of
- CONFIG_64BIT.
-
- 32-bit platforms (CONFIG_64BIT=n):
- Goldfish (Android emulator)
- AMD Elan
- RDC R-321x SoC
- SGI 320/540 (Visual Workstation)
-
- 64-bit platforms (CONFIG_64BIT=y):
- Numascale NumaChip
- ScaleMP vSMP
- SGI Ultraviolet
- Merrifield/Moorefield MID devices
-
- If you have one of these systems, or if you want to build a
- generic distribution kernel, say Y here - otherwise say N.
-
-# This is an alphabetically sorted list of 64 bit extended platforms
-# Please maintain the alphabetic order if and when there are additions
-config X86_NUMACHIP
- bool "Numascale NumaChip"
- depends on X86_64
- depends on X86_EXTENDED_PLATFORM
- depends on NUMA
- depends on SMP
- depends on X86_X2APIC
- depends on PCI_MMCONFIG
- help
- Adds support for Numascale NumaChip large-SMP systems. Needed to
- enable more than ~168 cores.
- If you don't have one of these, you should say N here.
-
-config X86_VSMP
- bool "ScaleMP vSMP"
- select HYPERVISOR_GUEST
- select PARAVIRT
- depends on X86_64 && PCI
- depends on X86_EXTENDED_PLATFORM
- depends on SMP
- help
- Support for ScaleMP vSMP systems. Say 'Y' here if this kernel is
- supposed to run on these EM64T-based machines. Only choose this option
- if you have one of these machines.
-
-config X86_UV
- bool "SGI Ultraviolet"
- depends on X86_64
- depends on X86_EXTENDED_PLATFORM
- depends on NUMA
- depends on EFI
- depends on KEXEC_CORE
- depends on X86_X2APIC
- depends on PCI
- help
- This option is needed in order to support SGI Ultraviolet systems.
- If you don't have one of these, you should say N here.
-
-config X86_INTEL_MID
- bool "Intel Z34xx/Z35xx MID platform support"
- depends on X86_EXTENDED_PLATFORM
- depends on X86_PLATFORM_DEVICES
- depends on PCI
- depends on X86_64 || (EXPERT && PCI_GOANY)
- depends on X86_IO_APIC
- select I2C
- select DW_APB_TIMER
- select INTEL_SCU_PCI
- help
- Select to build a kernel capable of supporting 64-bit Intel MID
- (Mobile Internet Device) platform systems which do not have
- the PCI legacy interfaces.
-
- The only supported devices are the 22nm Merrified (Z34xx)
- and Moorefield (Z35xx) SoC used in the Intel Edison board and
- a small number of Android devices such as the Asus Zenfone 2,
- Asus FonePad 8 and Dell Venue 7.
-
- If you are building for a PC class system or non-MID tablet
- SoCs like Bay Trail (Z36xx/Z37xx), say N here.
-
- Intel MID platforms are based on an Intel processor and chipset which
- consume less power than most of the x86 derivatives.
-
-config X86_GOLDFISH
- bool "Goldfish (Virtual Platform)"
- depends on X86_EXTENDED_PLATFORM
- help
- Enable support for the Goldfish virtual platform used primarily
- for Android development. Unless you are building for the Android
- Goldfish emulator say N here.
-
-# Following is an alphabetically sorted list of 32 bit extended platforms
-# Please maintain the alphabetic order if and when there are additions
-
-config X86_INTEL_CE
- bool "CE4100 TV platform"
- depends on PCI
- depends on PCI_GODIRECT
- depends on X86_IO_APIC
- depends on X86_32
- depends on X86_EXTENDED_PLATFORM
- select X86_REBOOTFIXUPS
- select OF
- select OF_EARLY_FLATTREE
- help
- Select for the Intel CE media processor (CE4100) SOC.
- This option compiles in support for the CE4100 SOC for settop
- boxes and media devices.
-
-config X86_INTEL_QUARK
- bool "Intel Quark platform support"
- depends on X86_32
- depends on X86_EXTENDED_PLATFORM
- depends on X86_PLATFORM_DEVICES
- depends on X86_TSC
- depends on PCI
- depends on PCI_GOANY
- depends on X86_IO_APIC
- select IOSF_MBI
- select INTEL_IMR
- select COMMON_CLK
- help
- Select to include support for Quark X1000 SoC.
- Say Y here if you have a Quark based system such as the Arduino
- compatible Intel Galileo.
-
-config X86_INTEL_LPSS
- bool "Intel Low Power Subsystem Support"
- depends on X86 && ACPI && PCI
- select COMMON_CLK
- select PINCTRL
- select IOSF_MBI
- help
- Select to build support for Intel Low Power Subsystem such as
- found on Intel Lynxpoint PCH. Selecting this option enables
- things like clock tree (common clock framework) and pincontrol
- which are needed by the LPSS peripheral drivers.
-
-config X86_AMD_PLATFORM_DEVICE
- bool "AMD ACPI2Platform devices support"
- depends on ACPI
- select COMMON_CLK
- select PINCTRL
- help
- Select to interpret AMD specific ACPI device to platform device
- such as I2C, UART, GPIO found on AMD Carrizo and later chipsets.
- I2C and UART depend on COMMON_CLK to set clock. GPIO driver is
- implemented under PINCTRL subsystem.
-
-config IOSF_MBI
- tristate "Intel SoC IOSF Sideband support for SoC platforms"
- depends on PCI
- help
- This option enables sideband register access support for Intel SoC
- platforms. On these platforms the IOSF sideband is used in lieu of
- MSR's for some register accesses, mostly but not limited to thermal
- and power. Drivers may query the availability of this device to
- determine if they need the sideband in order to work on these
- platforms. The sideband is available on the following SoC products.
- This list is not meant to be exclusive.
- - BayTrail
- - Braswell
- - Quark
-
- You should say Y if you are running a kernel on one of these SoC's.
-
-config IOSF_MBI_DEBUG
- bool "Enable IOSF sideband access through debugfs"
- depends on IOSF_MBI && DEBUG_FS
- help
- Select this option to expose the IOSF sideband access registers (MCR,
- MDR, MCRX) through debugfs to write and read register information from
- different units on the SoC. This is most useful for obtaining device
- state information for debug and analysis. As this is a general access
- mechanism, users of this option would have specific knowledge of the
- device they want to access.
-
- If you don't require the option or are in doubt, say N.
-
-config X86_RDC321X
- bool "RDC R-321x SoC"
- depends on X86_32
- depends on X86_EXTENDED_PLATFORM
- select M486
- select X86_REBOOTFIXUPS
- help
- This option is needed for RDC R-321x system-on-chip, also known
- as R-8610-(G).
- If you don't have one of these chips, you should say N here.
+source "arch/x86/Kconfig.platforms"
config X86_SUPPORTS_MEMORY_FAILURE
def_bool y
@@ -735,19 +537,6 @@ config X86_SUPPORTS_MEMORY_FAILURE
depends on X86_64 || !SPARSEMEM
select ARCH_SUPPORTS_MEMORY_FAILURE
-config X86_32_IRIS
- tristate "Eurobraille/Iris poweroff module"
- depends on X86_32
- help
- The Iris machines from EuroBraille do not have APM or ACPI support
- to shut themselves down properly. A special I/O sequence is
- needed to do so, which is what this module does at
- kernel shutdown.
-
- This is only for Iris machines from EuroBraille.
-
- If unused, say N.
-
config SCHED_OMIT_FRAME_POINTER
def_bool y
prompt "Single-depth WCHAN output"
@@ -1275,39 +1064,6 @@ config X86_IOPL_IOPERM
ability to disable interrupts from user space which would be
granted if the hardware IOPL mechanism would be used.
-config TOSHIBA
- tristate "Toshiba Laptop support"
- depends on X86_32
- help
- This adds a driver to safely access the System Management Mode of
- the CPU on Toshiba portables with a genuine Toshiba BIOS. It does
- not work on models with a Phoenix BIOS. The System Management Mode
- is used to set the BIOS and power saving options on Toshiba portables.
-
- For information on utilities to make use of this driver see the
- Toshiba Linux utilities web site at:
- <http://www.buzzard.org.uk/toshiba/>.
-
- Say Y if you intend to run this kernel on a Toshiba portable.
- Say N otherwise.
-
-config X86_REBOOTFIXUPS
- bool "Enable X86 board specific fixups for reboot"
- depends on X86_32
- help
- This enables chipset and/or board specific fixups to be done
- in order to get reboot to work correctly. This is only needed on
- some combinations of hardware and BIOS. The symptom, for which
- this config is intended, is when reboot ends with a stalled/hung
- system.
-
- Currently, the only fixup is for the Geode machines using
- CS5530A and CS5536 chipsets and the RDC R-321x SoC.
-
- Say Y if you want to enable the fixup. Currently, it's safe to
- enable this option even if you don't need it.
- Say N otherwise.
-
config MICROCODE
def_bool y
depends on CPU_SUP_AMD || CPU_SUP_INTEL
@@ -2927,10 +2683,9 @@ config ISA_DMA_API
Enables ISA-style DMA support for devices requiring such controllers.
If unsure, say Y.
-if X86_32
-
config ISA
bool "ISA support"
+ depends on X86_32
help
Find out whether you have ISA slots on your motherboard. ISA is the
name of a bus system, i.e. the way the CPU talks to the other stuff
@@ -2938,120 +2693,6 @@ config ISA
(MCA) or VESA. ISA is an older system, now being displaced by PCI;
newer boards don't support it. If you have ISA, say Y, otherwise N.
-config SCx200
- tristate "NatSemi SCx200 support"
- help
- This provides basic support for National Semiconductor's
- (now AMD's) Geode processors. The driver probes for the
- PCI-IDs of several on-chip devices, so its a good dependency
- for other scx200_* drivers.
-
- If compiled as a module, the driver is named scx200.
-
-config SCx200HR_TIMER
- tristate "NatSemi SCx200 27MHz High-Resolution Timer Support"
- depends on SCx200
- default y
- help
- This driver provides a clocksource built upon the on-chip
- 27MHz high-resolution timer. Its also a workaround for
- NSC Geode SC-1100's buggy TSC, which loses time when the
- processor goes idle (as is done by the scheduler). The
- other workaround is idle=poll boot option.
-
-config OLPC
- bool "One Laptop Per Child support"
- depends on !X86_PAE
- select GPIOLIB
- select OF
- select OF_PROMTREE
- select IRQ_DOMAIN
- select OLPC_EC
- help
- Add support for detecting the unique features of the OLPC
- XO hardware.
-
-config OLPC_XO1_PM
- bool "OLPC XO-1 Power Management"
- depends on OLPC && MFD_CS5535=y && PM_SLEEP
- help
- Add support for poweroff and suspend of the OLPC XO-1 laptop.
-
-config OLPC_XO1_RTC
- bool "OLPC XO-1 Real Time Clock"
- depends on OLPC_XO1_PM && RTC_DRV_CMOS
- help
- Add support for the XO-1 real time clock, which can be used as a
- programmable wakeup source.
-
-config OLPC_XO1_SCI
- bool "OLPC XO-1 SCI extras"
- depends on OLPC && OLPC_XO1_PM && GPIO_CS5535=y
- depends on INPUT=y
- select POWER_SUPPLY
- help
- Add support for SCI-based features of the OLPC XO-1 laptop:
- - EC-driven system wakeups
- - Power button
- - Ebook switch
- - Lid switch
- - AC adapter status updates
- - Battery status updates
-
-config OLPC_XO15_SCI
- bool "OLPC XO-1.5 SCI extras"
- depends on OLPC && ACPI
- select POWER_SUPPLY
- help
- Add support for SCI-based features of the OLPC XO-1.5 laptop:
- - EC-driven system wakeups
- - AC adapter status updates
- - Battery status updates
-
-config GEODE_COMMON
- bool
-
-config ALIX
- bool "PCEngines ALIX System Support (LED setup)"
- select GPIOLIB
- select GEODE_COMMON
- help
- This option enables system support for the PCEngines ALIX.
- At present this just sets up LEDs for GPIO control on
- ALIX2/3/6 boards. However, other system specific setup should
- get added here.
-
- Note: You must still enable the drivers for GPIO and LED support
- (GPIO_CS5535 & LEDS_GPIO) to actually use the LEDs
-
- Note: You have to set alix.force=1 for boards with Award BIOS.
-
-config NET5501
- bool "Soekris Engineering net5501 System Support (LEDS, GPIO, etc)"
- select GPIOLIB
- select GEODE_COMMON
- help
- This option enables system support for the Soekris Engineering net5501.
-
-config GEOS
- bool "Traverse Technologies GEOS System Support (LEDS, GPIO, etc)"
- select GPIOLIB
- select GEODE_COMMON
- depends on DMI
- help
- This option enables system support for the Traverse Technologies GEOS.
-
-config TS5500
- bool "Technologic Systems TS-5500 platform support"
- depends on MELAN
- select CHECK_SIGNATURE
- select NEW_LEDS
- select LEDS_CLASS
- help
- This option enables system support for the Technologic Systems TS-5500.
-
-endif # X86_32
-
config AMD_NB
def_bool y
depends on CPU_SUP_AMD && PCI
diff --git a/arch/x86/Kconfig.platforms b/arch/x86/Kconfig.platforms
new file mode 100644
index 000000000000..cac6753bacea
--- /dev/null
+++ b/arch/x86/Kconfig.platforms
@@ -0,0 +1,361 @@
+menu "Platform selection"
+
+config X86_EXTENDED_PLATFORM
+ bool "Support for extended (non-PC) x86 platforms"
+ default y
+ help
+ If you disable this option then the kernel will only support
+ standard PC platforms. (which covers the vast majority of
+ systems out there.)
+
+ If you enable this option then you'll be able to select support
+ for the following non-PC x86 platforms, depending on the value of
+ CONFIG_64BIT.
+
+ 32-bit platforms (CONFIG_64BIT=n):
+ Intel CE4100
+ Intel Quark
+ AMD Geode
+ AMD Elan
+ RDC R-321x
+
+ 64-bit platforms (CONFIG_64BIT=y):
+ Numascale NumaChip
+ ScaleMP vSMP
+ SGI Ultraviolet
+ Merrifield/Moorefield MID devices
+ Goldfish (Android emulator)
+
+ If you have one of these systems, or if you want to build a
+ generic distribution kernel, say Y here - otherwise say N.
+
+# This is an alphabetically sorted list of 64 bit extended platforms
+# Please maintain the alphabetic order if and when there are additions
+config X86_NUMACHIP
+ bool "Numascale NumaChip"
+ depends on X86_64
+ depends on X86_EXTENDED_PLATFORM
+ depends on NUMA
+ depends on SMP
+ depends on X86_X2APIC
+ depends on PCI_MMCONFIG
+ help
+ Adds support for Numascale NumaChip large-SMP systems. Needed to
+ enable more than ~168 cores.
+ If you don't have one of these, you should say N here.
+
+config X86_VSMP
+ bool "ScaleMP vSMP"
+ select HYPERVISOR_GUEST
+ select PARAVIRT
+ depends on X86_64 && PCI
+ depends on X86_EXTENDED_PLATFORM
+ depends on SMP
+ help
+ Support for ScaleMP vSMP systems. Say 'Y' here if this kernel is
+ supposed to run on these EM64T-based machines. Only choose this option
+ if you have one of these machines.
+
+config X86_UV
+ bool "SGI Ultraviolet"
+ depends on X86_64
+ depends on X86_EXTENDED_PLATFORM
+ depends on NUMA
+ depends on EFI
+ depends on KEXEC_CORE
+ depends on X86_X2APIC
+ depends on PCI
+ help
+ This option is needed in order to support SGI Ultraviolet systems.
+ If you don't have one of these, you should say N here.
+
+config X86_INTEL_MID
+ bool "Intel Z34xx/Z35xx MID platform support"
+ depends on X86_EXTENDED_PLATFORM
+ depends on X86_PLATFORM_DEVICES
+ depends on PCI
+ depends on X86_64 || (EXPERT && PCI_GOANY)
+ depends on X86_IO_APIC
+ select I2C
+ select DW_APB_TIMER
+ select INTEL_SCU_PCI
+ help
+ Select to build a kernel capable of supporting 64-bit Intel MID
+ (Mobile Internet Device) platform systems which do not have
+ the PCI legacy interfaces.
+
+ The only supported devices are the 22nm Merrified (Z34xx)
+ and Moorefield (Z35xx) SoC used in the Intel Edison board and
+ a small number of Android devices such as the Asus Zenfone 2,
+ Asus FonePad 8 and Dell Venue 7.
+
+ If you are building for a PC class system or non-MID tablet
+ SoCs like Bay Trail (Z36xx/Z37xx), say N here.
+
+ Intel MID platforms are based on an Intel processor and chipset which
+ consume less power than most of the x86 derivatives.
+
+config X86_GOLDFISH
+ bool "Goldfish (Virtual Platform)"
+ depends on X86_EXTENDED_PLATFORM
+ help
+ Enable support for the Goldfish virtual platform used primarily
+ for Android development. Unless you are building for the Android
+ Goldfish emulator say N here.
+
+# Following is an alphabetically sorted list of 32 bit extended platforms
+# Please maintain the alphabetic order if and when there are additions
+
+if X86_32 && X86_EXTENDED_PLATFORM
+
+config X86_INTEL_CE
+ bool "CE4100 TV platform"
+ depends on PCI
+ depends on PCI_GODIRECT
+ depends on X86_IO_APIC
+ select X86_REBOOTFIXUPS
+ select OF
+ select OF_EARLY_FLATTREE
+ help
+ Select for the Intel CE media processor (CE4100) SOC.
+ This option compiles in support for the CE4100 SOC for settop
+ boxes and media devices.
+
+config X86_INTEL_QUARK
+ bool "Intel Quark platform support"
+ depends on X86_PLATFORM_DEVICES
+ depends on X86_TSC
+ depends on PCI
+ depends on PCI_GOANY
+ depends on X86_IO_APIC
+ select IOSF_MBI
+ select INTEL_IMR
+ select COMMON_CLK
+ help
+ Select to include support for Quark X1000 SoC.
+ Say Y here if you have a Quark based system such as the Arduino
+ compatible Intel Galileo.
+
+config SCx200
+ tristate "NatSemi SCx200 support"
+ help
+ This provides basic support for National Semiconductor's
+ (now AMD's) Geode processors. The driver probes for the
+ PCI-IDs of several on-chip devices, so its a good dependency
+ for other scx200_* drivers.
+
+ If compiled as a module, the driver is named scx200.
+
+config SCx200HR_TIMER
+ tristate "NatSemi SCx200 27MHz High-Resolution Timer Support"
+ depends on SCx200
+ default y
+ help
+ This driver provides a clocksource built upon the on-chip
+ 27MHz high-resolution timer. Its also a workaround for
+ NSC Geode SC-1100's buggy TSC, which loses time when the
+ processor goes idle (as is done by the scheduler). The
+ other workaround is idle=poll boot option.
+
+config OLPC
+ bool "One Laptop Per Child support"
+ depends on !X86_PAE
+ select GPIOLIB
+ select OF
+ select OF_PROMTREE
+ select IRQ_DOMAIN
+ select OLPC_EC
+ help
+ Add support for detecting the unique features of the OLPC
+ XO hardware.
+
+config OLPC_XO1_PM
+ bool "OLPC XO-1 Power Management"
+ depends on OLPC && MFD_CS5535=y && PM_SLEEP
+ help
+ Add support for poweroff and suspend of the OLPC XO-1 laptop.
+
+config OLPC_XO1_RTC
+ bool "OLPC XO-1 Real Time Clock"
+ depends on OLPC_XO1_PM && RTC_DRV_CMOS
+ help
+ Add support for the XO-1 real time clock, which can be used as a
+ programmable wakeup source.
+
+config OLPC_XO1_SCI
+ bool "OLPC XO-1 SCI extras"
+ depends on OLPC && OLPC_XO1_PM && GPIO_CS5535=y
+ depends on INPUT=y
+ select POWER_SUPPLY
+ help
+ Add support for SCI-based features of the OLPC XO-1 laptop:
+ - EC-driven system wakeups
+ - Power button
+ - Ebook switch
+ - Lid switch
+ - AC adapter status updates
+ - Battery status updates
+
+config OLPC_XO15_SCI
+ bool "OLPC XO-1.5 SCI extras"
+ depends on OLPC && ACPI
+ select POWER_SUPPLY
+ help
+ Add support for SCI-based features of the OLPC XO-1.5 laptop:
+ - EC-driven system wakeups
+ - AC adapter status updates
+ - Battery status updates
+
+config GEODE_COMMON
+ bool
+
+config ALIX
+ bool "PCEngines ALIX System Support (LED setup)"
+ select GPIOLIB
+ select GEODE_COMMON
+ help
+ This option enables system support for the PCEngines ALIX.
+ At present this just sets up LEDs for GPIO control on
+ ALIX2/3/6 boards. However, other system specific setup should
+ get added here.
+
+ Note: You must still enable the drivers for GPIO and LED support
+ (GPIO_CS5535 & LEDS_GPIO) to actually use the LEDs
+
+ Note: You have to set alix.force=1 for boards with Award BIOS.
+
+config NET5501
+ bool "Soekris Engineering net5501 System Support (LEDS, GPIO, etc)"
+ select GPIOLIB
+ select GEODE_COMMON
+ help
+ This option enables system support for the Soekris Engineering net5501.
+
+config GEOS
+ bool "Traverse Technologies GEOS System Support (LEDS, GPIO, etc)"
+ select GPIOLIB
+ select GEODE_COMMON
+ depends on DMI
+ help
+ This option enables system support for the Traverse Technologies GEOS.
+
+config TS5500
+ bool "Technologic Systems TS-5500 platform support"
+ depends on MELAN
+ select CHECK_SIGNATURE
+ select NEW_LEDS
+ select LEDS_CLASS
+ help
+ This option enables system support for the Technologic Systems TS-5500.
+
+config X86_RDC321X
+ bool "RDC R-321x SoC"
+ select M486
+ select X86_REBOOTFIXUPS
+ help
+ This option is needed for RDC R-321x system-on-chip, also known
+ as R-8610-(G).
+ If you don't have one of these chips, you should say N here.
+
+config X86_REBOOTFIXUPS
+ bool "Enable X86 board specific fixups for reboot"
+ depends on X86_32
+ help
+ This enables chipset and/or board specific fixups to be done
+ in order to get reboot to work correctly. This is only needed on
+ some combinations of hardware and BIOS. The symptom, for which
+ this config is intended, is when reboot ends with a stalled/hung
+ system.
+
+ Currently, the only fixup is for the Geode machines using
+ CS5530A and CS5536 chipsets and the RDC R-321x SoC.
+
+ Say Y if you want to enable the fixup. Currently, it's safe to
+ enable this option even if you don't need it.
+ Say N otherwise.
+
+endif # X86_32 extended platform
+
+config TOSHIBA
+ tristate "Toshiba Laptop support"
+ depends on X86_32
+ help
+ This adds a driver to safely access the System Management Mode of
+ the CPU on Toshiba portables with a genuine Toshiba BIOS. It does
+ not work on models with a Phoenix BIOS. The System Management Mode
+ is used to set the BIOS and power saving options on Toshiba portables.
+
+ For information on utilities to make use of this driver see the
+ Toshiba Linux utilities web site at:
+ <http://www.buzzard.org.uk/toshiba/>.
+
+ Say Y if you intend to run this kernel on a Toshiba portable.
+ Say N otherwise.
+
+config X86_32_IRIS
+ tristate "Eurobraille/Iris poweroff module"
+ depends on X86_32
+ help
+ The Iris machines from EuroBraille do not have APM or ACPI support
+ to shut themselves down properly. A special I/O sequence is
+ needed to do so, which is what this module does at
+ kernel shutdown.
+
+ This is only for Iris machines from EuroBraille.
+
+ If unused, say N.
+
+config X86_INTEL_LPSS
+ bool "Intel Low Power Subsystem Support"
+ depends on X86 && ACPI && PCI
+ select COMMON_CLK
+ select PINCTRL
+ select IOSF_MBI
+ help
+ Select to build support for Intel Low Power Subsystem such as
+ found on Intel Lynxpoint PCH. Selecting this option enables
+ things like clock tree (common clock framework) and pincontrol
+ which are needed by the LPSS peripheral drivers.
+
+config X86_AMD_PLATFORM_DEVICE
+ bool "AMD ACPI2Platform devices support"
+ depends on ACPI
+ select COMMON_CLK
+ select PINCTRL
+ help
+ Select to interpret AMD specific ACPI device to platform device
+ such as I2C, UART, GPIO found on AMD Carrizo and later chipsets.
+ I2C and UART depend on COMMON_CLK to set clock. GPIO driver is
+ implemented under PINCTRL subsystem.
+
+config IOSF_MBI
+ tristate "Intel SoC IOSF Sideband support for SoC platforms"
+ depends on PCI
+ help
+ This option enables sideband register access support for Intel SoC
+ platforms. On these platforms the IOSF sideband is used in lieu of
+ MSR's for some register accesses, mostly but not limited to thermal
+ and power. Drivers may query the availability of this device to
+ determine if they need the sideband in order to work on these
+ platforms. The sideband is available on the following SoC products.
+ This list is not meant to be exclusive.
+ - BayTrail
+ - Braswell
+ - Quark
+
+ You should say Y if you are running a kernel on one of these SoC's.
+
+config IOSF_MBI_DEBUG
+ bool "Enable IOSF sideband access through debugfs"
+ depends on IOSF_MBI && DEBUG_FS
+ help
+ Select this option to expose the IOSF sideband access registers (MCR,
+ MDR, MCRX) through debugfs to write and read register information from
+ different units on the SoC. This is most useful for obtaining device
+ state information for debug and analysis. As this is a general access
+ mechanism, users of this option would have specific knowledge of the
+ device they want to access.
+
+ If you don't require the option or are in doubt, say N.
+
+endmenu
--
2.39.5
^ permalink raw reply related [flat|nested] 21+ messages in thread* Re: [PATCH v2 00/11] x86: 32-bit cleanups
2024-12-10 14:49 [PATCH v2 00/11] x86: 32-bit cleanups Arnd Bergmann
` (10 preceding siblings ...)
2024-12-10 14:49 ` [PATCH v2 11/11] x86: Move platforms to Kconfig.platforms Arnd Bergmann
@ 2024-12-10 15:43 ` Andy Shevchenko
11 siblings, 0 replies; 21+ messages in thread
From: Andy Shevchenko @ 2024-12-10 15:43 UTC (permalink / raw)
To: Arnd Bergmann
Cc: linux-kernel, x86, Arnd Bergmann, Thomas Gleixner, Ingo Molnar,
Borislav Petkov, Dave Hansen, H. Peter Anvin, Linus Torvalds,
Andy Shevchenko, Matthew Wilcox
On Tue, Dec 10, 2024 at 4:49 PM Arnd Bergmann <arnd@kernel.org> wrote:
>
> From: Arnd Bergmann <arnd@arndb.de>
>
> [sorry for sending a duplicate series, I just noticed I had
> dropped lkml from cc when I sent this a few minutes ago]
>
> While looking at 32-bit arm cleanups, I came across some related topics
> on x86 and ended up making a series for those as well.
>
> Primarily this is about running 32-bit kernels on 64-bit hardware,
> which usually works but should probably be discouraged more clearly by
> only providing support for features that are used on real 32-bit hardware:
>
> I found only a few 2003-era high-end servers (HP DL740 and DL760 G2)
> that were the only possible remaining uses of HIGHMEM64G and BIGSMP after
> the removal of 32-bit NUMA machines in 2014. Similary, there is only
Similarly
> one generation of hardware with support for VT-x. All these features
> can be removed without hurting users.
>
> In the CPU selection, building a 32-bit kernel optimized for AMD K8
> or Intel Core2 is anachronistic, so instead only 32-bit CPU types need
> to be offered as optimization targets. The "generic" target on 64-bit
> turned out to be slightly broken, so I included a fix for that as well.
...
> x86: document X86_INTEL_MID as 64-bit-only
Acked-by: Andy Shevchenko <andy@kernel.org>
--
With Best Regards,
Andy Shevchenko
^ permalink raw reply [flat|nested] 21+ messages in thread