From: Niklas Cassel <cassel@kernel.org>
To: Anand Moon <linux.amoon@gmail.com>
Cc: "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] PCI: dw-rockchip: Enable async probe by default
Date: Fri, 3 Jan 2025 16:10:29 +0100 [thread overview]
Message-ID: <Z3f95RXj7GhZZHEP@ryzen> (raw)
In-Reply-To: <CANAwSgRTcHuDNLvPJAs7ZaV-NnepeOkHj_kVc5OAJtP03hd6pQ@mail.gmail.com>
On Fri, Jan 03, 2025 at 08:36:18PM +0530, Anand Moon wrote:
> > >
> > > We need to enable the GMAC PHY and reset it using the proper GPIO pin
> > > (PCIE_PERST_L).
> > > Please refer to the schematic for more details.
> >
> > The PERST# GPIO is already asserted + deasserted from the PCIe Root Complex
> > (host) driver:
> > https://github.com/torvalds/linux/blob/v6.13-rc5/drivers/pci/controller/dwc/pcie-dw-rockchip.c#L191-L206
> >
> > which will cause the endpoint device (a RTL8125 NIC in this case)
> > to be reset during bootup.
> >
> Thanks for letting me know. It seems like a workaround.
> I'll try to disable this and test it again.
>
> My point is that we haven't enabled the GMAC PHY (device nodes)
> and must properly reset the GMAC.
>
> We're relying on the code above hack to do that job.
I do not think it is a hack.
If you look in most PCIe controller drivers, they toggle PERST before
enumerating the bus:
$ git grep gpiod_set_value drivers/pci/controller/
Kind regards,
Niklas
WARNING: multiple messages have this Message-ID (diff)
From: Niklas Cassel <cassel@kernel.org>
To: Anand Moon <linux.amoon@gmail.com>
Cc: "Manivannan Sadhasivam" <manivannan.sadhasivam@linaro.org>,
"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kw@linux.com>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Heiko Stuebner" <heiko@sntech.de>,
linux-pci@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2] PCI: dw-rockchip: Enable async probe by default
Date: Fri, 3 Jan 2025 16:10:29 +0100 [thread overview]
Message-ID: <Z3f95RXj7GhZZHEP@ryzen> (raw)
In-Reply-To: <CANAwSgRTcHuDNLvPJAs7ZaV-NnepeOkHj_kVc5OAJtP03hd6pQ@mail.gmail.com>
On Fri, Jan 03, 2025 at 08:36:18PM +0530, Anand Moon wrote:
> > >
> > > We need to enable the GMAC PHY and reset it using the proper GPIO pin
> > > (PCIE_PERST_L).
> > > Please refer to the schematic for more details.
> >
> > The PERST# GPIO is already asserted + deasserted from the PCIe Root Complex
> > (host) driver:
> > https://github.com/torvalds/linux/blob/v6.13-rc5/drivers/pci/controller/dwc/pcie-dw-rockchip.c#L191-L206
> >
> > which will cause the endpoint device (a RTL8125 NIC in this case)
> > to be reset during bootup.
> >
> Thanks for letting me know. It seems like a workaround.
> I'll try to disable this and test it again.
>
> My point is that we haven't enabled the GMAC PHY (device nodes)
> and must properly reset the GMAC.
>
> We're relying on the code above hack to do that job.
I do not think it is a hack.
If you look in most PCIe controller drivers, they toggle PERST before
enumerating the bus:
$ git grep gpiod_set_value drivers/pci/controller/
Kind regards,
Niklas
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
next prev parent reply other threads:[~2025-01-03 15:12 UTC|newest]
Thread overview: 60+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-09 7:36 [PATCH v2] PCI: dw-rockchip: Enable async probe by default Anand Moon
2024-08-09 7:36 ` Anand Moon
2025-01-03 11:31 ` Niklas Cassel
2025-01-03 11:31 ` Niklas Cassel
2025-01-03 13:54 ` Anand Moon
2025-01-03 13:54 ` Anand Moon
2025-01-03 14:25 ` Niklas Cassel
2025-01-03 14:25 ` Niklas Cassel
2025-01-03 14:40 ` Anand Moon
2025-01-03 14:40 ` Anand Moon
2025-01-03 14:45 ` Niklas Cassel
2025-01-03 14:45 ` Niklas Cassel
2025-01-03 15:06 ` Anand Moon
2025-01-03 15:06 ` Anand Moon
2025-01-03 15:10 ` Niklas Cassel [this message]
2025-01-03 15:10 ` Niklas Cassel
2025-01-03 15:29 ` Anand Moon
2025-01-03 15:29 ` Anand Moon
2025-01-03 15:45 ` Niklas Cassel
2025-01-03 15:45 ` Niklas Cassel
2025-01-05 16:35 ` Manivannan Sadhasivam
2025-01-05 16:35 ` Manivannan Sadhasivam
2025-01-05 17:46 ` Anand Moon
2025-01-05 17:46 ` Anand Moon
2025-01-03 16:04 ` Andrew Lunn
2025-01-03 16:04 ` Andrew Lunn
2025-01-05 17:46 ` Anand Moon
2025-01-05 17:46 ` Anand Moon
2025-01-05 17:57 ` Andrew Lunn
2025-01-05 17:57 ` Andrew Lunn
2025-01-06 7:58 ` Anand Moon
2025-01-06 7:58 ` Anand Moon
2025-01-06 12:02 ` Niklas Cassel
2025-01-06 12:02 ` Niklas Cassel
2025-01-06 13:44 ` Andrew Lunn
2025-01-06 13:44 ` Andrew Lunn
2025-01-07 11:13 ` Anand Moon
2025-01-07 11:13 ` Anand Moon
2025-01-07 13:13 ` Andrew Lunn
2025-01-07 13:13 ` Andrew Lunn
2025-01-07 14:57 ` Anand Moon
2025-01-07 14:57 ` Anand Moon
2025-01-15 17:49 ` Manivannan Sadhasivam
2025-01-15 17:49 ` Manivannan Sadhasivam
2026-01-29 14:06 ` Grimmauld
2026-01-29 14:06 ` Grimmauld
2026-01-30 10:25 ` Niklas Cassel
2026-01-30 10:25 ` Niklas Cassel
2026-01-31 9:38 ` Anand Moon
2026-01-31 9:38 ` Anand Moon
2026-02-02 9:54 ` Niklas Cassel
2026-02-02 9:54 ` Niklas Cassel
2026-02-02 18:05 ` Anand Moon
2026-02-02 18:05 ` Anand Moon
2026-02-03 11:01 ` Niklas Cassel
2026-02-03 11:01 ` Niklas Cassel
2026-02-02 10:02 ` Niklas Cassel
2026-02-02 10:02 ` Niklas Cassel
2026-02-02 18:07 ` Anand Moon
2026-02-02 18:07 ` Anand Moon
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