Re: [PATCH 1/2] drm/i915/mtl: Disable render power-gating during selftest only

[Rodrigo Vivi <rodrigo.vivi@intel.com>]

On Fri, Jan 10, 2025 at 07:39:46PM +0530, Badal Nilawar wrote:
> The temporary wa ‘drm/i915/mtl: do not enable render power-gating on MTL’ disables RPG
> globally. Since the issue seen during live self-tests disabling it during these tests.
> 
> Fixes: 25e7976db86b ("drm/i915/mtl: do not enable render power-gating on MTL")
> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com>
> Cc: Andi Shyti <andi.shyti@intel.com>
> Cc: Andrzej Hajda <andrzej.hajda@intel.com>
> Signed-off-by: Badal Nilawar <badal.nilawar@intel.com>
> ---
>  drivers/gpu/drm/i915/gt/intel_rc6.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/i915/gt/intel_rc6.c b/drivers/gpu/drm/i915/gt/intel_rc6.c
> index 9378d5901c49..2dd68ca7ec0e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_rc6.c
> +++ b/drivers/gpu/drm/i915/gt/intel_rc6.c
> @@ -123,7 +123,7 @@ static void gen11_rc6_enable(struct intel_rc6 *rc6)
>  	 * temporary wa and should be removed after fixing real cause
>  	 * of forcewake timeouts.
>  	 */
> -	if (IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))
> +	if (i915_selftest.live && IS_GFX_GT_IP_RANGE(gt, IP_VER(12, 70), IP_VER(12, 74)))


hmmm... is there something we could do inside the selftest to mitigate that?
here it is crossing (abusing?!) a lot of layers to workaround a case...

also this starts to depend on some config flags, what the compilation bot test hit...

>  		pg_enable =
>  			GEN9_MEDIA_PG_ENABLE |
>  			GEN11_MEDIA_SAMPLER_PG_ENABLE;
> -- 
> 2.34.1
>