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From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Jouni Högander" <jouni.hogander@intel.com>
Cc: intel-gfx@lists.freedesktop.org, intel-xe@lists.freedesktop.org,
	animesh.manna@intel.com, ville.syrjala@intel.com
Subject: Re: [PATCH v6 11/12] drm/i915/display: Ensure we have "Frame Change" event in DSB commit
Date: Mon, 10 Feb 2025 18:34:55 +0200	[thread overview]
Message-ID: <Z6oqrxiu_7Ye1wef@intel.com> (raw)
In-Reply-To: <20250127102846.1237560-12-jouni.hogander@intel.com>

On Mon, Jan 27, 2025 at 12:28:45PM +0200, Jouni Högander wrote:
> We may have commit which doesn't have any non-arming plane register
> writes. In that case there aren't "Frame Change" event before DSB vblank
> evasion which hangs as PIPEDSL register is reading as 0 when PSR state is
> SRDENT(PSR1) or DEEP_SLEEP(PSR2). Handle this by ensuring "Frame Change"
> event at the begin of DSB commit if using PSR/PR.
> 
> v2: use intel_psr_trigger_frame_change_event
> 
> Signed-off-by: Jouni Högander <jouni.hogander@intel.com>

Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>

> ---
>  drivers/gpu/drm/i915/display/intel_display.c | 8 ++++++++
>  1 file changed, 8 insertions(+)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index 5db2af86d0c8a..67041d76763fe 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -7725,6 +7725,14 @@ static void intel_atomic_dsb_finish(struct intel_atomic_state *state,
>  		intel_crtc_planes_update_noarm(new_crtc_state->dsb_commit,
>  					       state, crtc);
>  
> +		/*
> +		 * Ensure we have "Frame Change" event when PSR state is
> +		 * SRDENT(PSR1) or DEEP_SLEEP(PSR2). Otherwise DSB vblank
> +		 * evasion hangs as PIPEDSL is reading as 0.
> +		 */
> +		intel_psr_trigger_frame_change_event(state, new_crtc_state->dsb_commit,
> +						     crtc);
> +
>  		intel_dsb_vblank_evade(state, new_crtc_state->dsb_commit);
>  
>  		if (intel_crtc_needs_color_update(new_crtc_state))
> -- 
> 2.43.0

-- 
Ville Syrjälä
Intel

  reply	other threads:[~2025-02-10 16:35 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-01-27 10:28 [PATCH v6 00/12] PSR DSB support Jouni Högander
2025-01-27 10:28 ` [PATCH v6 01/12] drm/i915/psr: Use PSR2_MAN_TRK_CTL CFF bit only to send full update Jouni Högander
2025-01-27 10:28 ` [PATCH v6 02/12] drm/i915/psr: Rename psr_force_hw_tracking_exit as intel_psr_force_update Jouni Högander
2025-01-27 10:28 ` [PATCH v6 03/12] drm/i915/psr: Split setting sff and cff bits away from intel_psr_force_update Jouni Högander
2025-01-27 10:28 ` [PATCH v6 04/12] drm/i915/psr: Add register definitions for SFF_CTL and CFF_CTL registers Jouni Högander
2025-01-27 10:28 ` [PATCH v6 05/12] drm/i915/psr: Use SFF_CTL on invalidate/flush for LunarLake onwards Jouni Högander
2025-01-27 10:28 ` [PATCH v6 06/12] drm/i915/psr: Allow writing PSR2_MAN_TRK_CTL using DSB Jouni Högander
2025-01-27 10:28 ` [PATCH v6 07/12] drm/i915/psr: Changes for PSR2_MAN_TRK_CTL handling when DSB is in use Jouni Högander
2025-02-10 16:26   ` Ville Syrjälä
2025-02-11  6:24     ` Hogander, Jouni
2025-02-11 20:10       ` Ville Syrjälä
2025-01-27 10:28 ` [PATCH v6 08/12] drm/i915/psr: Remove DSB_SKIP_WAITS_EN chicken bit Jouni Högander
2025-02-10 16:28   ` Ville Syrjälä
2025-01-27 10:28 ` [PATCH v6 09/12] drm/i915/display: Evade scanline 0 as well if PSR1 or PSR2 is enabled Jouni Högander
2025-02-10 16:29   ` Ville Syrjälä
2025-01-27 10:28 ` [PATCH v6 10/12] drm/i915/psr: Add function for triggering "Frame Change" event Jouni Högander
2025-02-10 16:34   ` Ville Syrjälä
2025-01-27 10:28 ` [PATCH v6 11/12] drm/i915/display: Ensure we have "Frame Change" event in DSB commit Jouni Högander
2025-02-10 16:34   ` Ville Syrjälä [this message]
2025-01-27 10:28 ` [PATCH v6 12/12] drm/i915/psr: Allow DSB usage when PSR is enabled Jouni Högander
2025-01-27 11:24 ` ✓ CI.Patch_applied: success for PSR DSB support (rev6) Patchwork
2025-01-27 11:25 ` ✓ CI.checkpatch: " Patchwork
2025-01-27 11:26 ` ✓ CI.KUnit: " Patchwork
2025-01-27 11:41 ` ✗ Fi.CI.SPARSE: warning for PSR DSB support (rev7) Patchwork
2025-01-27 11:42 ` ✓ CI.Build: success for PSR DSB support (rev6) Patchwork
2025-01-27 11:44 ` ✓ CI.Hooks: " Patchwork
2025-01-27 11:46 ` ✗ CI.checksparse: warning " Patchwork
2025-01-27 11:58 ` ✗ i915.CI.BAT: failure for PSR DSB support (rev7) Patchwork
2025-01-27 12:05 ` ✓ Xe.CI.BAT: success for PSR DSB support (rev6) Patchwork
2025-01-27 13:29 ` ✗ Xe.CI.Full: failure " Patchwork
2025-01-28 15:28 ` ✗ Fi.CI.SPARSE: warning for PSR DSB support (rev8) Patchwork
2025-01-28 15:49 ` ✓ i915.CI.BAT: success " Patchwork
2025-01-29  7:24 ` ✗ i915.CI.Full: failure " Patchwork

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