Re: [PATCH v2 07/10] clk: socfpga: add agilex5 clock support

[Sascha Hauer <s.hauer@pengutronix.de>]

On Tue, Feb 18, 2025 at 10:21:32AM +0100, Steffen Trumtrar wrote:
> Add support for the Stratix10 and Agilex5 pll,gate and periph clocks.
> 
> Only tested on Agilex5.
> 
> Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
> ---
>  drivers/clk/socfpga/Makefile         |   4 +-
>  drivers/clk/socfpga/clk-agilex5.c    | 833 +++++++++++++++++++++++++++++++++++
>  drivers/clk/socfpga/clk-gate-s10.c   | 184 ++++++++
>  drivers/clk/socfpga/clk-periph-s10.c | 163 +++++++
>  drivers/clk/socfpga/clk-pll-s10.c    | 140 ++++++
>  drivers/clk/socfpga/clk.h            |   9 +
>  drivers/clk/socfpga/stratix10-clk.h  |  73 +++
>  7 files changed, 1405 insertions(+), 1 deletion(-)
> 
> +
> +static int socfpga_gate_get_parent(struct clk_hw *hwclk)
> +{
> +	struct socfpga_gate_clk *socfpgaclk = to_socfpga_gate_clk(hwclk);
> +	u32 mask, second_bypass;
> +	u8 parent = 0;
> +	const char *name = clk_hw_get_name(hwclk);
> +
> +printk("%s: %s\n", __func__, name);
> +
> +	if (socfpgaclk->bypass_reg) {
> +		mask = (0x1 << socfpgaclk->bypass_shift);
> +		parent = ((readl(socfpgaclk->bypass_reg) & mask) >>
> +			  socfpgaclk->bypass_shift);
> +printk("%s: parent %d\n", __func__, parent);

Debugging leftovers.

Sascha


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