[PATCH 0/3] Add missing CPUIDs to the CPUID database

[PATCH 0/3] Add missing CPUIDs to the CPUID database

[Avadhut Naik]

This set adds some publicly known CPUIDs to the database. These CPUIDs
were introduced in AMD's Zen5 SOCs and have not yet been added
to the database.

The first patch adds ABMC and SDCIAE bits to the database.

The second patch adds WL_CLASS_SUPPORT, ERAPS, SBPB, IBPB_BRTYPE, SRSO_NO,
SRSO_USER_KERNEL_NO and SRSO_MSR_FIX bits to the database.

The third patch adds Rapsize bit to the database and modifies the number
of bits allocated to MicrocodePatchSize field from 12 to 16 per Zen5 PPR

Avadhut Naik (3):
  db/leaf_80000020: Add ABMC and SDCIAE CPUID bits
  db/leaf_80000021: Add missing CPUID bits
  db/leaf_80000021: Add Rapsize CPUID bit

 db/xml/leaf_80000020.xml |  6 ++++++
 db/xml/leaf_80000021.xml | 39 ++++++++++++++++++++++++++++++++++++++-
 2 files changed, 44 insertions(+), 1 deletion(-)


base-commit: e1dbdd1664078cb8961ae0ef0253c4e86ee755e9
-- 
2.43.0

[PATCH 1/3] db/leaf_80000020: Add ABMC and SDCIAE CPUID bits

[Avadhut Naik]

AMD's Zen5 generation SOCs introduce two new bits viz. Assignable
Bandwidth Monitoring Counters (ABMC) and Smart Data Cache Injection
(SDCI) Allocation Enforcement (SDCIAE) to the CPUID leaf 0x80000020.

Add these new bits to the database.

Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
---
 db/xml/leaf_80000020.xml | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/db/xml/leaf_80000020.xml b/db/xml/leaf_80000020.xml
index 2ae6e6e93a70..1eda95b37dd1 100644
--- a/db/xml/leaf_80000020.xml
+++ b/db/xml/leaf_80000020.xml
@@ -27,6 +27,12 @@
         <linux        feature="true"               proc="false" />
       </bit3>
       <bit4  len="1"  id="l3rr"                    desc="L3 Range Reservation support" />
+      <bit5  len="1"  id="abmc"                    desc="Assignable Bandwidth Monitoring Counters">
+        <linux        feature="true"               proc="false" />
+      </bit5>
+      <bit6  len="1"  id="sdciae"                  desc="Smart Data Cache Injection (SDCI) Allocation Enforcement">
+        <linux        feature="true"               proc="false" />
+      </bit6>
     </ebx>
   </subleaf>
   <subleaf id="1">
-- 
2.43.0

[PATCH 2/3] db/leaf_80000021: Add missing CPUID bits

[Avadhut Naik]

AMD's ZEN5 generation SOCs introduce the following new CPUID bits to
0x80000021 leaf:

WL_CLASS_SUPPORT: Indicates support for workload based heuristic feedback
to OS for scheduling decisions.

ERAPS: Indicates support for enhanced return address predictor security.

SBPB: Indicates support for the Selective Branch Predictor Barrier.

IBPB_BRTYPE: Indicates that PRED_CMD[IBPB] MSR flushes all branch type
predictions from the CPU branch predictor.

SRSO_NO: Indicates that the CPU is not subject to the SRSO vulnerability.

SRSO_USER_KERNEL_NO: Indicates that the CPU is not subject to the SRSO
vulnerability across user/kernel boundaries

SRSO_MSR_FIX: Indicates that software may use MSR BP_CFG[BpSpecReduce] to
mitigate SRSO

Add these new bits to the database.

Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
---
 db/xml/leaf_80000021.xml | 32 ++++++++++++++++++++++++++++++++
 1 file changed, 32 insertions(+)

diff --git a/db/xml/leaf_80000021.xml b/db/xml/leaf_80000021.xml
index 1daef091e686..ce1a8dcca805 100644
--- a/db/xml/leaf_80000021.xml
+++ b/db/xml/leaf_80000021.xml
@@ -37,8 +37,40 @@
       <bit10 len="1"  id="fsrs_supported"          desc="Fast Short Rep Stosb (FSRS) is supported" />
       <bit11 len="1"  id="fsrc_supported"          desc="Fast Short Repe Cmpsb (FSRC) is supported" />
       <bit13 len="1"  id="prefetch_ctl_msr"        desc="Prefetch control MSR is supported" />
+      <bit16 len="1"  id="opcode_reclaim"          desc="Reserves opcode space">
+        <text>
+          Reserves opcode space 0F 01/7 for AMD use, returns illegal instruction for opcodes
+          in this space.
+        </text>
+        <linux        feature="true"               proc="false" />
+      </bit16>
       <bit17 len="1"  id="user_cpuid_disable"      desc="#GP when executing CPUID at CPL > 0 is supported" />
       <bit18 len="1"  id="epsf_supported"          desc="Enhanced Predictive Store Forwarding (EPSF) is supported" />
+      <bit22 len="1"  id="wl_feedback"             desc="Workload-based heuristic feedback to OS">
+        <linux        feature="true"               proc="false" />
+      </bit22>
+      <bit24 len="1"  id="eraps_support"           desc="Enhanced Return Address Predictor Security">
+        <linux        feature="true"               proc="false" />
+      </bit24>
+      <bit27 len="1"  id="sbpb"                    desc="Support for the Selective Branch Predictor Barrier">
+        <linux        feature="true"               proc="false" />
+      </bit27>
+      <bit28 len="1"  id="ibpb_brtype"             desc="Branch predictions flushed from CPU branch predictor">
+        <text>
+          Indicates that MSR 49h (PRED_CMD) bit 0 (IBPB) flushes all branch type predictions
+          from the CPU branch predictor.
+        </text>
+        <linux        feature="true"               proc="false" />
+      </bit28>
+      <bit29 len="1"  id="srso_no"                 desc="CPU is not subject to the SRSO vulnerability">
+        <linux        feature="true"               proc="false" />
+      </bit29>
+      <bit30 len="1"  id="srso_uk_no"              desc="CPU is not vulnerable to SRSO at user-kernel boundary">
+        <linux        feature="true"               proc="false" />
+      </bit30>
+      <bit31 len="1"  id="srso_msr_fix"            desc="Software may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO">
+        <linux        feature="true"               proc="false" />
+      </bit31>
     </eax>
     <ebx>
       <bit0  len="12" id="microcode_patch_size"    desc="Size of microcode patch, in 16-byte units">
-- 
2.43.0

[PATCH 3/3] db/leaf_80000021: Add Rapsize CPUID bit

[Avadhut Naik]

AMD's Zen5 generation SOCs introduce a new CPUID bit for Return Address
Predictor size to the CPUID leaf 0x80000021.

Add this new bit to the database.

Additionally, the number of bits assigned for MicrocodePatchSize field
has been increased from 12 to 16 on Zen5 SOCs. Modify the database
accordingly.

Signed-off-by: Avadhut Naik <avadhut.naik@amd.com>
---
 db/xml/leaf_80000021.xml | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

diff --git a/db/xml/leaf_80000021.xml b/db/xml/leaf_80000021.xml
index ce1a8dcca805..64d8e57b7582 100644
--- a/db/xml/leaf_80000021.xml
+++ b/db/xml/leaf_80000021.xml
@@ -73,11 +73,16 @@
       </bit31>
     </eax>
     <ebx>
-      <bit0  len="12" id="microcode_patch_size"    desc="Size of microcode patch, in 16-byte units">
+      <bit0  len="16" id="microcode_patch_size"    desc="Size of microcode patch, in 16-byte units">
         <text>
           If 0 is returned, then the size of the microcode patch is ≤ 5568 (0x15c0) bytes.
         </text>
       </bit0>
+      <bit16  len="8" id="rapsize"                 desc="Return Address Predictor size">
+        <text>
+          RapSize x 8 is the minimum number of CALL instructions software needs to execute to flush the RAP.
+        </text>
+      </bit16>
     </ebx>
   </subleaf>
 </leaf>
-- 
2.43.0

Re: [PATCH 0/3] Add missing CPUIDs to the CPUID database

[Naik, Avadhut]

Hi,

Any feedback on this set?

On 11/15/2024 12:11, Avadhut Naik wrote:
> This set adds some publicly known CPUIDs to the database. These CPUIDs
> were introduced in AMD's Zen5 SOCs and have not yet been added
> to the database.
> 
> The first patch adds ABMC and SDCIAE bits to the database.
> 
> The second patch adds WL_CLASS_SUPPORT, ERAPS, SBPB, IBPB_BRTYPE, SRSO_NO,
> SRSO_USER_KERNEL_NO and SRSO_MSR_FIX bits to the database.
> 
> The third patch adds Rapsize bit to the database and modifies the number
> of bits allocated to MicrocodePatchSize field from 12 to 16 per Zen5 PPR
> 
> Avadhut Naik (3):
>   db/leaf_80000020: Add ABMC and SDCIAE CPUID bits
>   db/leaf_80000021: Add missing CPUID bits
>   db/leaf_80000021: Add Rapsize CPUID bit
> 
>  db/xml/leaf_80000020.xml |  6 ++++++
>  db/xml/leaf_80000021.xml | 39 ++++++++++++++++++++++++++++++++++++++-
>  2 files changed, 44 insertions(+), 1 deletion(-)
> 
> 
> base-commit: e1dbdd1664078cb8961ae0ef0253c4e86ee755e9

-- 
Thanks,
Avadhut Naik

Re: [PATCH 0/3] Add missing CPUIDs to the CPUID database

[Ahmed S. Darwish]

Hi Avadhut,

On Tue, 10 Dec 2024, Naik, Avadhut wrote:
>
> Any feedback on this set?
>

I apologize.  For some reason, the x86-cpuid mailing list didn't forward
/any/ emails to me, and I've just discovered all the pending ML emails
through a random check of the lore archive :(

I'm checking this now.

All the best,

--
Ahmed S. Darwish
Linutronix GmbH

Re: [PATCH 0/3] Add missing CPUIDs to the CPUID database

[Ahmed S. Darwish]

Hi Avadhut,

On Fri, 15 Nov 2024, Avadhut Naik wrote:
>
> This set adds some publicly known CPUIDs to the database. These CPUIDs
> were introduced in AMD's Zen5 SOCs and have not yet been added
> to the database.
>
> The first patch adds ABMC and SDCIAE bits to the database.
>
> The second patch adds WL_CLASS_SUPPORT, ERAPS, SBPB, IBPB_BRTYPE, SRSO_NO,
> SRSO_USER_KERNEL_NO and SRSO_MSR_FIX bits to the database.
>
> The third patch adds Rapsize bit to the database and modifies the number
> of bits allocated to MicrocodePatchSize field from 12 to 16 per Zen5 PPR
>
> Avadhut Naik (3):
>   db/leaf_80000020: Add ABMC and SDCIAE CPUID bits
>   db/leaf_80000021: Add missing CPUID bits
>   db/leaf_80000021: Add Rapsize CPUID bit
>

Thanks!  The three patches are now merged to tip:

    https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/commits/tip

They should also be part of the project's v2.1 release, to be pushed
this week.

All the best,

--
Ahmed S. Darwish
Linutronix GmbH

Re: [PATCH 0/3] Add missing CPUIDs to the CPUID database

[Naik, Avadhut]

Thank you so much!

On 3/4/2025 10:34, Ahmed S. Darwish wrote:
> Hi Avadhut,
> 
> On Fri, 15 Nov 2024, Avadhut Naik wrote:
>>
>> This set adds some publicly known CPUIDs to the database. These CPUIDs
>> were introduced in AMD's Zen5 SOCs and have not yet been added
>> to the database.
>>
>> The first patch adds ABMC and SDCIAE bits to the database.
>>
>> The second patch adds WL_CLASS_SUPPORT, ERAPS, SBPB, IBPB_BRTYPE, SRSO_NO,
>> SRSO_USER_KERNEL_NO and SRSO_MSR_FIX bits to the database.
>>
>> The third patch adds Rapsize bit to the database and modifies the number
>> of bits allocated to MicrocodePatchSize field from 12 to 16 per Zen5 PPR
>>
>> Avadhut Naik (3):
>>   db/leaf_80000020: Add ABMC and SDCIAE CPUID bits
>>   db/leaf_80000021: Add missing CPUID bits
>>   db/leaf_80000021: Add Rapsize CPUID bit
>>
> 
> Thanks!  The three patches are now merged to tip:
> 
>     https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/commits/tip
> 
> They should also be part of the project's v2.1 release, to be pushed
> this week.
> 
> All the best,
> 
> --
> Ahmed S. Darwish
> Linutronix GmbH

-- 
Thanks,
Avadhut Naik

Re: [PATCH 0/3] Add missing CPUIDs to the CPUID database

[Ahmed S. Darwish]

On Tue, 04 Mar 2025, Naik, Avadhut wrote:
>
> Thank you so much!
>

Welcome :)