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* [Intel-gfx] [PATCH v2 0/2] Correction to QGV related register addresses
@ 2023-03-22 14:20 Vinod Govindapillai
  2023-03-22 14:20 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/reg: fix QGV points register access offsets Vinod Govindapillai
                   ` (4 more replies)
  0 siblings, 5 replies; 8+ messages in thread
From: Vinod Govindapillai @ 2023-03-22 14:20 UTC (permalink / raw)
  To: intel-gfx; +Cc: ville.syrjala

Wrong offsets are calculated to read QGV points from mem ss. Also
a wrong register address is used to get the dagv block time. Fix
these two issues.

Vinod Govindapillai (2):
  drm/i915/reg: fix QGV points register access offsets
  drm/i915/reg: use the correct register to access SAGV block time

 drivers/gpu/drm/i915/i915_reg.h | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

-- 
2.34.1


^ permalink raw reply	[flat|nested] 8+ messages in thread

end of thread, other threads:[~2023-03-23 11:48 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-03-22 14:20 [Intel-gfx] [PATCH v2 0/2] Correction to QGV related register addresses Vinod Govindapillai
2023-03-22 14:20 ` [Intel-gfx] [PATCH v2 1/2] drm/i915/reg: fix QGV points register access offsets Vinod Govindapillai
2023-03-22 14:36   ` Ville Syrjälä
2023-03-23 11:48     ` Govindapillai, Vinod
2023-03-22 14:20 ` [Intel-gfx] [PATCH v2 2/2] drm/i915/reg: use the correct register to access SAGV block time Vinod Govindapillai
2023-03-22 15:23 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Correction to QGV related register addresses (rev2) Patchwork
2023-03-22 15:37 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-03-22 20:18 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork

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