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From: Andrea Parri <parri.andrea@gmail.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar <prabhakar.csengg@gmail.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Albert Ou <aou@eecs.berkeley.edu>, Arnd Bergmann <arnd@arndb.de>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Samuel Holland <samuel@sholland.org>,
	Heiko Stuebner <heiko@sntech.de>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"linux-renesas-soc@vger.kernel.org"
	<linux-renesas-soc@vger.kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Rob Herring <robh+dt@kernel.org>, Guo Ren <guoren@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH v7 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management
Date: Fri, 7 Apr 2023 02:03:36 +0200	[thread overview]
Message-ID: <ZC9d2DIOMy27AAT9@andrea> (raw)
In-Reply-To: <ZCxFUb8+eQPzqBmo@infradead.org>

> But other other point is adding more cache flushing variants should not
> be easy.  Everyone should be using the standardize version.  If it's not
> implemented in hardware despite having ratified extensions you can fake
> it up in SBI.  Yes, that's way more expensive than indirect calls, but
> that's what you get for taping out new hardware that ignores the actual
> architecture specification and just does their own made up shit.

FWIW, ALTERNATIVE_X() for "three instructions with (what should be a)
crystal-clear semantics" already smells like "we're doing it wrong" to
me, function pointers would be closer to "we're looking for trouble".

Thanks,
  Andrea

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linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Andrea Parri <parri.andrea@gmail.com>
To: Christoph Hellwig <hch@infradead.org>
Cc: Biju Das <biju.das.jz@bp.renesas.com>,
	Prabhakar <prabhakar.csengg@gmail.com>,
	"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
	Albert Ou <aou@eecs.berkeley.edu>, Arnd Bergmann <arnd@arndb.de>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Samuel Holland <samuel@sholland.org>,
	Heiko Stuebner <heiko@sntech.de>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
	Prabhakar Mahadev Lad <prabhakar.mahadev-lad.rj@bp.renesas.com>,
	"linux-renesas-soc@vger.kernel.org" 
	<linux-renesas-soc@vger.kernel.org>,
	Conor Dooley <conor.dooley@microchip.com>,
	Rob Herring <robh+dt@kernel.org>, Guo Ren <guoren@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	"linux-riscv@lists.infradead.org"
	<linux-riscv@lists.infradead.org>,
	Andrew Jones <ajones@ventanamicro.com>
Subject: Re: [PATCH v7 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management
Date: Fri, 7 Apr 2023 02:03:36 +0200	[thread overview]
Message-ID: <ZC9d2DIOMy27AAT9@andrea> (raw)
In-Reply-To: <ZCxFUb8+eQPzqBmo@infradead.org>

> But other other point is adding more cache flushing variants should not
> be easy.  Everyone should be using the standardize version.  If it's not
> implemented in hardware despite having ratified extensions you can fake
> it up in SBI.  Yes, that's way more expensive than indirect calls, but
> that's what you get for taping out new hardware that ignores the actual
> architecture specification and just does their own made up shit.

FWIW, ALTERNATIVE_X() for "three instructions with (what should be a)
crystal-clear semantics" already smells like "we're doing it wrong" to
me, function pointers would be closer to "we're looking for trouble".

Thanks,
  Andrea

  parent reply	other threads:[~2023-04-07  0:04 UTC|newest]

Thread overview: 80+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-30 20:42 [PATCH v7 0/6] RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP Prabhakar
2023-03-30 20:42 ` Prabhakar
2023-03-30 20:42 ` [PATCH v7 1/6] riscv: mm: dma-noncoherent: Switch using function pointers for cache management Prabhakar
2023-03-30 20:42   ` Prabhakar
2023-03-30 21:34   ` Arnd Bergmann
2023-03-30 21:34     ` Arnd Bergmann
2023-03-31  7:54     ` Conor Dooley
2023-03-31  7:54       ` Conor Dooley
2023-03-31  7:58       ` Arnd Bergmann
2023-03-31  7:58         ` Arnd Bergmann
2023-03-31 10:37     ` Lad, Prabhakar
2023-03-31 10:37       ` Lad, Prabhakar
2023-03-31 10:44       ` Arnd Bergmann
2023-03-31 10:44         ` Arnd Bergmann
2023-03-31 12:11         ` Lad, Prabhakar
2023-03-31 12:11           ` Lad, Prabhakar
2023-04-03 17:00         ` Lad, Prabhakar
2023-04-03 17:00           ` Lad, Prabhakar
2023-03-31 10:55       ` Conor Dooley
2023-03-31 10:55         ` Conor Dooley
2023-03-31 11:36         ` Arnd Bergmann
2023-03-31 11:36           ` Arnd Bergmann
2023-03-31  7:31   ` Geert Uytterhoeven
2023-03-31  7:31     ` Geert Uytterhoeven
2023-03-31 10:45     ` Lad, Prabhakar
2023-03-31 10:45       ` Lad, Prabhakar
2023-03-31 12:24   ` Conor Dooley
2023-03-31 12:24     ` Conor Dooley
2023-04-03 18:23     ` Lad, Prabhakar
2023-04-03 18:23       ` Lad, Prabhakar
2023-04-03 18:31       ` Conor Dooley
2023-04-03 18:31         ` Conor Dooley
2023-04-04  5:29   ` Christoph Hellwig
2023-04-04  5:29     ` Christoph Hellwig
2023-04-04  6:24     ` Biju Das
2023-04-04  6:24       ` Biju Das
2023-04-04 15:42       ` Christoph Hellwig
2023-04-04 15:42         ` Christoph Hellwig
2023-04-05  6:08         ` Biju Das
2023-04-05  6:08           ` Biju Das
2023-04-07  0:03         ` Andrea Parri [this message]
2023-04-07  0:03           ` Andrea Parri
2023-04-07  5:33           ` Christoph Hellwig
2023-04-07  5:33             ` Christoph Hellwig
2023-04-04  6:50     ` Arnd Bergmann
2023-04-04  6:50       ` Arnd Bergmann
2023-04-04  6:59       ` Conor Dooley
2023-04-04  6:59         ` Conor Dooley
2023-04-06 18:59     ` Lad, Prabhakar
2023-04-06 18:59       ` Lad, Prabhakar
2023-03-30 20:42 ` [PATCH v7 2/6] riscv: asm: vendorid_list: Add Andes Technology to the vendors list Prabhakar
2023-03-30 20:42   ` Prabhakar
2023-03-30 20:42 ` [PATCH v7 3/6] riscv: errata: Add Andes alternative ports Prabhakar
2023-03-30 20:42   ` Prabhakar
2023-03-30 20:42 ` [PATCH v7 4/6] dt-bindings: cache: r9a07g043f-l2-cache: Add DT binding documentation for L2 cache controller Prabhakar
2023-03-30 20:42   ` Prabhakar
2023-03-31 10:21   ` Conor Dooley
2023-03-31 10:21     ` Conor Dooley
2023-03-31 10:47     ` Lad, Prabhakar
2023-03-31 10:47       ` Lad, Prabhakar
2023-03-30 20:42 ` [PATCH v7 5/6] cache: Add L2 cache management for Andes AX45MP RISC-V core Prabhakar
2023-03-30 20:42   ` Prabhakar
2023-03-31 12:45   ` Conor Dooley
2023-03-31 12:45     ` Conor Dooley
2023-03-31 20:17     ` Lad, Prabhakar
2023-03-31 20:17       ` Lad, Prabhakar
2023-03-30 20:42 ` [PATCH v7 6/6] soc: renesas: Kconfig: Select the required configs for RZ/Five SoC Prabhakar
2023-03-30 20:42   ` Prabhakar
2023-03-31  7:37   ` Geert Uytterhoeven
2023-03-31  7:37     ` Geert Uytterhoeven
2023-03-31  7:37     ` Geert Uytterhoeven
2023-03-31  7:37       ` Geert Uytterhoeven
2023-03-31 18:05 ` [PATCH v7 0/6] RISC-V non-coherent function pointer based CMO + non-coherent DMA support for AX45MP Conor Dooley
2023-03-31 18:05   ` Conor Dooley
2023-03-31 20:09   ` Lad, Prabhakar
2023-03-31 20:09     ` Lad, Prabhakar
2023-03-31 20:15     ` Conor Dooley
2023-03-31 20:15       ` Conor Dooley
2023-04-01  1:47       ` Icenowy Zheng
2023-04-01  1:47         ` Icenowy Zheng

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