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From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Siddharth Vadapalli <s-vadapalli@ti.com>
Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
	pabeni@redhat.com, rogerq@kernel.org, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, srk@ti.com
Subject: Re: [PATCH net-next 2/2] net: ethernet: ti: am65-cpsw: Enable USXGMII mode for J784S4 CPSW9G
Date: Fri, 31 Mar 2023 09:24:29 +0100	[thread overview]
Message-ID: <ZCaYve8wYl15YRxh@shell.armlinux.org.uk> (raw)
In-Reply-To: <54c3964b-5dd8-c55e-08db-61df4a07797c@ti.com>

On Fri, Mar 31, 2023 at 01:35:10PM +0530, Siddharth Vadapalli wrote:
> Hello Russell,
> 
> Thank you for reviewing the patch.
> 
> On 31/03/23 13:27, Russell King (Oracle) wrote:
> > On Fri, Mar 31, 2023 at 12:21:10PM +0530, Siddharth Vadapalli wrote:
> >> TI's J784S4 SoC supports USXGMII mode. Add USXGMII mode to the
> >> extra_modes member of the J784S4 SoC data. Additionally, configure the
> >> MAC Control register for supporting USXGMII mode. Also, for USXGMII
> >> mode, include MAC_5000FD in the "mac_capabilities" member of struct
> >> "phylink_config".
> > 
> > I don't think TI "get" phylink at all...
> > 
> >> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> >> index 4b4d06199b45..ab33e6fe5b1a 100644
> >> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> >> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> >> @@ -1555,6 +1555,8 @@ static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy
> >>  		mac_control |= CPSW_SL_CTL_GIG;
> >>  	if (interface == PHY_INTERFACE_MODE_SGMII)
> >>  		mac_control |= CPSW_SL_CTL_EXT_EN;
> >> +	if (interface == PHY_INTERFACE_MODE_USXGMII)
> >> +		mac_control |= CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN;
> > 
> > The configuration of the interface mode should *not* happen in
> > mac_link_up(), but should happen in e.g. mac_config().
> 
> I will move all the interface mode associated configurations to mac_config() in
> the v2 series.

Looking at the whole of mac_link_up(), could you please describe what
effect these bits are having:

	CPSW_SL_CTL_GIG
	CPSW_SL_CTL_EXT_EN
	CPSW_SL_CTL_IFCTL_A

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

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WARNING: multiple messages have this Message-ID (diff)
From: "Russell King (Oracle)" <linux@armlinux.org.uk>
To: Siddharth Vadapalli <s-vadapalli@ti.com>
Cc: davem@davemloft.net, edumazet@google.com, kuba@kernel.org,
	pabeni@redhat.com, rogerq@kernel.org, netdev@vger.kernel.org,
	linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, srk@ti.com
Subject: Re: [PATCH net-next 2/2] net: ethernet: ti: am65-cpsw: Enable USXGMII mode for J784S4 CPSW9G
Date: Fri, 31 Mar 2023 09:24:29 +0100	[thread overview]
Message-ID: <ZCaYve8wYl15YRxh@shell.armlinux.org.uk> (raw)
In-Reply-To: <54c3964b-5dd8-c55e-08db-61df4a07797c@ti.com>

On Fri, Mar 31, 2023 at 01:35:10PM +0530, Siddharth Vadapalli wrote:
> Hello Russell,
> 
> Thank you for reviewing the patch.
> 
> On 31/03/23 13:27, Russell King (Oracle) wrote:
> > On Fri, Mar 31, 2023 at 12:21:10PM +0530, Siddharth Vadapalli wrote:
> >> TI's J784S4 SoC supports USXGMII mode. Add USXGMII mode to the
> >> extra_modes member of the J784S4 SoC data. Additionally, configure the
> >> MAC Control register for supporting USXGMII mode. Also, for USXGMII
> >> mode, include MAC_5000FD in the "mac_capabilities" member of struct
> >> "phylink_config".
> > 
> > I don't think TI "get" phylink at all...
> > 
> >> diff --git a/drivers/net/ethernet/ti/am65-cpsw-nuss.c b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> >> index 4b4d06199b45..ab33e6fe5b1a 100644
> >> --- a/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> >> +++ b/drivers/net/ethernet/ti/am65-cpsw-nuss.c
> >> @@ -1555,6 +1555,8 @@ static void am65_cpsw_nuss_mac_link_up(struct phylink_config *config, struct phy
> >>  		mac_control |= CPSW_SL_CTL_GIG;
> >>  	if (interface == PHY_INTERFACE_MODE_SGMII)
> >>  		mac_control |= CPSW_SL_CTL_EXT_EN;
> >> +	if (interface == PHY_INTERFACE_MODE_USXGMII)
> >> +		mac_control |= CPSW_SL_CTL_XGIG | CPSW_SL_CTL_XGMII_EN;
> > 
> > The configuration of the interface mode should *not* happen in
> > mac_link_up(), but should happen in e.g. mac_config().
> 
> I will move all the interface mode associated configurations to mac_config() in
> the v2 series.

Looking at the whole of mac_link_up(), could you please describe what
effect these bits are having:

	CPSW_SL_CTL_GIG
	CPSW_SL_CTL_EXT_EN
	CPSW_SL_CTL_IFCTL_A

Thanks.

-- 
RMK's Patch system: https://www.armlinux.org.uk/developer/patches/
FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last!

  reply	other threads:[~2023-03-31  8:26 UTC|newest]

Thread overview: 38+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-03-31  6:51 [PATCH net-next 0/2] Add support for J784S4 CPSW9G Siddharth Vadapalli
2023-03-31  6:51 ` Siddharth Vadapalli
2023-03-31  6:51 ` [PATCH net-next 1/2] net: ethernet: ti: am65-cpsw: Enable QSGMII " Siddharth Vadapalli
2023-03-31  6:51   ` Siddharth Vadapalli
2023-03-31  6:51 ` [PATCH net-next 2/2] net: ethernet: ti: am65-cpsw: Enable USXGMII mode " Siddharth Vadapalli
2023-03-31  6:51   ` Siddharth Vadapalli
2023-03-31  7:57   ` Russell King (Oracle)
2023-03-31  7:57     ` Russell King (Oracle)
2023-03-31  8:05     ` Siddharth Vadapalli
2023-03-31  8:05       ` Siddharth Vadapalli
2023-03-31  8:24       ` Russell King (Oracle) [this message]
2023-03-31  8:24         ` Russell King (Oracle)
2023-03-31  9:25         ` Siddharth Vadapalli
2023-03-31  9:25           ` Siddharth Vadapalli
2023-03-31  9:46           ` Russell King (Oracle)
2023-03-31  9:46             ` Russell King (Oracle)
2023-03-31 10:53             ` Siddharth Vadapalli
2023-03-31 10:53               ` Siddharth Vadapalli
2023-03-31 11:12               ` Russell King (Oracle)
2023-03-31 11:12                 ` Russell King (Oracle)
2023-03-31 13:46                 ` Siddharth Vadapalli
2023-03-31 13:46                   ` Siddharth Vadapalli
2023-04-03  6:27                   ` Siddharth Vadapalli
2023-04-03  6:27                     ` Siddharth Vadapalli
2023-04-03  8:32                     ` Russell King (Oracle)
2023-04-03  8:32                       ` Russell King (Oracle)
2023-04-03  8:41                       ` Siddharth Vadapalli
2023-04-03  8:41                         ` Siddharth Vadapalli
2023-04-03  8:59                         ` Russell King (Oracle)
2023-04-03  8:59                           ` Russell King (Oracle)
2023-04-03  9:49                           ` Siddharth Vadapalli
2023-04-03  9:49                             ` Siddharth Vadapalli
2023-04-03  9:57                             ` Russell King (Oracle)
2023-04-03  9:57                               ` Russell King (Oracle)
2023-04-03 10:00                               ` Siddharth Vadapalli
2023-04-03 10:00                                 ` Siddharth Vadapalli
2023-03-31  7:46 ` [PATCH net-next 0/2] Add support " Roger Quadros
2023-03-31  7:46   ` Roger Quadros

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