From: Yixun Lan <dlan@gentoo.org>
To: Yangtao Li <frank.li@vivo.com>
Cc: devicetree@vger.kernel.org, Conor Dooley <conor+dt@kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Jisheng Zhang <jszhang@kernel.org>,
linux-kernel@vger.kernel.org, Rob Herring <robh+dt@kernel.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
linux-riscv@lists.infradead.org, Wei Fu <wefu@redhat.com>
Subject: Re: [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
Date: Thu, 11 May 2023 08:42:31 +0800 [thread overview]
Message-ID: <ZFw59xlxoCSyb--J@ofant> (raw)
In-Reply-To: <20230510204456.57202-3-frank.li@vivo.com>
Hi Yangtao:
On 04:44 Thu 11 May , Yangtao Li wrote:
> From: Jisheng Zhang <jszhang@kernel.org>
>
> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> module which is powered by T-HEAD's light(a.k.a TH1520) SoC. Add
> minimal device tree files for the core module and the development
> board.
>
> Support basic uart/gpio/dmac drivers, so supports booting to a basic
> shell.
>
> Cc: Icenowy Zheng <uwu@icenowy.me>
> Cc: Wei Fu <wefu@redhat.com>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Signed-off-by: Yangtao Li <frank.li@vivo.com>
> ---
> v2:
> -cleanup `light`
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/thead/Makefile | 2 +
> .../dts/thead/th1520-lichee-module-4a.dtsi | 39 +++++++++++++++++++
> .../boot/dts/thead/th1520-lichee-pi-4a.dts | 33 ++++++++++++++++
> 4 files changed, 75 insertions(+)
> create mode 100644 arch/riscv/boot/dts/thead/Makefile
> create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index f0d9f89054f8..1e884868ccba 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -2,6 +2,7 @@
> subdir-y += allwinner
> subdir-y += sifive
> subdir-y += starfive
> +subdir-y += thead
> subdir-y += canaan
> subdir-y += microchip
> subdir-y += renesas
> diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile
> new file mode 100644
> index 000000000000..e311fc9a5939
> --- /dev/null
> +++ b/arch/riscv/boot/dts/thead/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> new file mode 100644
> index 000000000000..bc5f8677d546
> --- /dev/null
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "th1520.dtsi"
> +
> +/ {
> + model = "Sipeed Lichee Module 4A";
> + compatible = "sipeed,lichee-module-4a", "thead,th1520";
we should have these compatibles documented, so a DT-Binding should go first
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x00000000 0x2 0x00000000>;
> + };
> +};
> +
> +&osc {
> + clock-frequency = <24000000>;
> +};
> +
> +&osc_32k {
> + clock-frequency = <32768>;
> +};
> +
> +&apb_clk {
> + clock-frequency = <62500000>;
> +};
> +
> +&uart_sclk {
> + clock-frequency = <100000000>;
> +};
for all the above clock-frequency, if it's a real fixed one - so should all hardware
be the same? then probably moving them to th1520.dtsi would be better?
> +
> +&dmac0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> new file mode 100644
> index 000000000000..86d677175feb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com>
> + */
> +
> +#include "th1520-lichee-module-4a.dtsi"
> +
> +/ {
> + model = "Sipeed Lichee Pi 4A";
> + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
ditto
> +
> + aliases {
> + gpio0 = &gpio0;
> + gpio1 = &gpio1;
> + gpio2 = &gpio2;
> + gpio3 = &gpio3;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> --
> 2.34.1
>
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
WARNING: multiple messages have this Message-ID (diff)
From: Yixun Lan <dlan@gentoo.org>
To: Yangtao Li <frank.li@vivo.com>
Cc: Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Jisheng Zhang <jszhang@kernel.org>, Wei Fu <wefu@redhat.com>,
Icenowy Zheng <uwu@icenowy.me>,
devicetree@vger.kernel.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board device tree
Date: Thu, 11 May 2023 08:42:31 +0800 [thread overview]
Message-ID: <ZFw59xlxoCSyb--J@ofant> (raw)
In-Reply-To: <20230510204456.57202-3-frank.li@vivo.com>
Hi Yangtao:
On 04:44 Thu 11 May , Yangtao Li wrote:
> From: Jisheng Zhang <jszhang@kernel.org>
>
> Sipeed's Lichee Pi 4A development board uses Lichee Module 4A core
> module which is powered by T-HEAD's light(a.k.a TH1520) SoC. Add
> minimal device tree files for the core module and the development
> board.
>
> Support basic uart/gpio/dmac drivers, so supports booting to a basic
> shell.
>
> Cc: Icenowy Zheng <uwu@icenowy.me>
> Cc: Wei Fu <wefu@redhat.com>
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> Signed-off-by: Yangtao Li <frank.li@vivo.com>
> ---
> v2:
> -cleanup `light`
> arch/riscv/boot/dts/Makefile | 1 +
> arch/riscv/boot/dts/thead/Makefile | 2 +
> .../dts/thead/th1520-lichee-module-4a.dtsi | 39 +++++++++++++++++++
> .../boot/dts/thead/th1520-lichee-pi-4a.dts | 33 ++++++++++++++++
> 4 files changed, 75 insertions(+)
> create mode 100644 arch/riscv/boot/dts/thead/Makefile
> create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> create mode 100644 arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
>
> diff --git a/arch/riscv/boot/dts/Makefile b/arch/riscv/boot/dts/Makefile
> index f0d9f89054f8..1e884868ccba 100644
> --- a/arch/riscv/boot/dts/Makefile
> +++ b/arch/riscv/boot/dts/Makefile
> @@ -2,6 +2,7 @@
> subdir-y += allwinner
> subdir-y += sifive
> subdir-y += starfive
> +subdir-y += thead
> subdir-y += canaan
> subdir-y += microchip
> subdir-y += renesas
> diff --git a/arch/riscv/boot/dts/thead/Makefile b/arch/riscv/boot/dts/thead/Makefile
> new file mode 100644
> index 000000000000..e311fc9a5939
> --- /dev/null
> +++ b/arch/riscv/boot/dts/thead/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_THEAD) += th1520-lichee-pi-4a.dtb
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> new file mode 100644
> index 000000000000..bc5f8677d546
> --- /dev/null
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-module-4a.dtsi
> @@ -0,0 +1,39 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com>
> + */
> +
> +/dts-v1/;
> +
> +#include "th1520.dtsi"
> +
> +/ {
> + model = "Sipeed Lichee Module 4A";
> + compatible = "sipeed,lichee-module-4a", "thead,th1520";
we should have these compatibles documented, so a DT-Binding should go first
> +
> + memory@0 {
> + device_type = "memory";
> + reg = <0x0 0x00000000 0x2 0x00000000>;
> + };
> +};
> +
> +&osc {
> + clock-frequency = <24000000>;
> +};
> +
> +&osc_32k {
> + clock-frequency = <32768>;
> +};
> +
> +&apb_clk {
> + clock-frequency = <62500000>;
> +};
> +
> +&uart_sclk {
> + clock-frequency = <100000000>;
> +};
for all the above clock-frequency, if it's a real fixed one - so should all hardware
be the same? then probably moving them to th1520.dtsi would be better?
> +
> +&dmac0 {
> + status = "okay";
> +};
> diff --git a/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> new file mode 100644
> index 000000000000..86d677175feb
> --- /dev/null
> +++ b/arch/riscv/boot/dts/thead/th1520-lichee-pi-4a.dts
> @@ -0,0 +1,33 @@
> +// SPDX-License-Identifier: GPL-2.0
> +/*
> + * Copyright (C) 2023 Jisheng Zhang <jszhang@kernel.org>
> + * Copyright (C) 2023 Yangtao Li <frank.li@vivo.com>
> + */
> +
> +#include "th1520-lichee-module-4a.dtsi"
> +
> +/ {
> + model = "Sipeed Lichee Pi 4A";
> + compatible = "sipeed,lichee-pi-4a", "sipeed,lichee-module-4a", "thead,th1520";
ditto
> +
> + aliases {
> + gpio0 = &gpio0;
> + gpio1 = &gpio1;
> + gpio2 = &gpio2;
> + gpio3 = &gpio3;
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + serial3 = &uart3;
> + serial4 = &uart4;
> + serial5 = &uart5;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> +
> +&uart0 {
> + status = "okay";
> +};
> --
> 2.34.1
>
--
Yixun Lan (dlan)
Gentoo Linux Developer
GPG Key ID AABEFD55
next prev parent reply other threads:[~2023-05-11 0:42 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-10 20:44 [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yangtao Li
2023-05-10 20:44 ` Yangtao Li
2023-05-10 20:44 ` [PATCH v2 2/5] riscv: dts: add initial T-HEAD light SoC device tree Yangtao Li
2023-05-10 20:44 ` Yangtao Li
2023-05-11 0:35 ` Yixun Lan
2023-05-11 0:35 ` Yixun Lan
2023-05-11 0:39 ` Jisheng Zhang
2023-05-11 0:39 ` Jisheng Zhang
2023-05-11 9:05 ` Krzysztof Kozlowski
2023-05-11 9:05 ` Krzysztof Kozlowski
2023-05-10 20:44 ` [PATCH v2 3/5] riscv: dts: thead: add sipeed Lichee Pi 4A board " Yangtao Li
2023-05-10 20:44 ` Yangtao Li
2023-05-11 0:42 ` Yixun Lan [this message]
2023-05-11 0:42 ` Yixun Lan
2023-05-11 9:12 ` Krzysztof Kozlowski
2023-05-11 9:12 ` Krzysztof Kozlowski
2023-05-10 20:44 ` [PATCH v2 4/5] riscv: defconfig: Enable the T-HEAD SoC Yangtao Li
2023-05-10 20:44 ` Yangtao Li
2023-05-10 20:44 ` [PATCH v2 5/5] MAINTAINERS: add entry for T-HEAD RISC-V SoC Yangtao Li
2023-05-10 20:44 ` Yangtao Li
2023-05-10 20:52 ` Conor Dooley
2023-05-10 20:52 ` Conor Dooley
2023-05-11 0:54 ` Yixun Lan
2023-05-11 0:54 ` Yixun Lan
2023-05-11 5:20 ` Conor Dooley
2023-05-11 5:20 ` Conor Dooley
2023-05-10 23:49 ` [PATCH v2 1/5] riscv: Add the T-HEAD SoC family Kconfig option Yixun Lan
2023-05-10 23:49 ` Yixun Lan
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=ZFw59xlxoCSyb--J@ofant \
--to=dlan@gentoo.org \
--cc=aou@eecs.berkeley.edu \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=frank.li@vivo.com \
--cc=jszhang@kernel.org \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=wefu@redhat.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.