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From: Vinod Koul <vkoul@kernel.org>
To: Frank Li <Frank.Li@nxp.com>
Cc: devicetree@vger.kernel.org, fushi.peng@nxp.com,
	imx@lists.linux.dev, kernel@pengutronix.de, kishon@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
	robh+dt@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org
Subject: Re: [PATCH v4 3/6] phy: cadence: salvo: add bist fix
Date: Tue, 16 May 2023 22:04:04 +0530	[thread overview]
Message-ID: <ZGOwfFlqWIrAXpHy@matsya> (raw)
In-Reply-To: <20230516154329.3155031-4-Frank.Li@nxp.com>

On 16-05-23, 11:43, Frank Li wrote:
> From: Peter Chen <peter.chen@nxp.com>
> 
> Very limited parts may fail to work on full speed mode (both host and
> device modes) for USB3 port due to higher threshold in full speed receiver
> of USB2.0 PHY.
> 
> One example failure symptom is, the enumeration is failed when connecting
> full speed USB mouse to USB3 port, especially under high temperature.
> 
> The workaround is to configure threshold voltage value of single ended
> receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101.
> 
> Signed-off-by: Peter Chen <peter.chen@nxp.com>

This needs senders S-o-b as well!

> ---
>  drivers/phy/cadence/phy-cadence-salvo.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
> index 2e3d4d8fb8eb..b9866dc146ce 100644
> --- a/drivers/phy/cadence/phy-cadence-salvo.c
> +++ b/drivers/phy/cadence/phy-cadence-salvo.c
> @@ -91,6 +91,7 @@
>  
>  /* USB2 PHY register definition */
>  #define UTMI_REG15				0xaf
> +#define UTMI_AFE_RX_REG5			0x12
>  
>  /* TB_ADDR_TX_RCVDETSC_CTRL */
>  #define RXDET_IN_P3_32KHZ			BIT(0)
> @@ -247,6 +248,8 @@ static int cdns_salvo_phy_init(struct phy *phy)
>  	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15,
>  			 value | TXVALID_GATE_THRESHOLD_HS_0US);
>  
> +	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG5,
> +			 0x5);

single line reads better

>  	udelay(10);
>  
>  	clk_disable_unprepare(salvo_phy->clk);
> -- 
> 2.34.1

-- 
~Vinod

WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vkoul@kernel.org>
To: Frank Li <Frank.Li@nxp.com>
Cc: devicetree@vger.kernel.org, fushi.peng@nxp.com,
	imx@lists.linux.dev, kernel@pengutronix.de, kishon@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
	robh+dt@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org
Subject: Re: [PATCH v4 3/6] phy: cadence: salvo: add bist fix
Date: Tue, 16 May 2023 22:04:04 +0530	[thread overview]
Message-ID: <ZGOwfFlqWIrAXpHy@matsya> (raw)
In-Reply-To: <20230516154329.3155031-4-Frank.Li@nxp.com>

On 16-05-23, 11:43, Frank Li wrote:
> From: Peter Chen <peter.chen@nxp.com>
> 
> Very limited parts may fail to work on full speed mode (both host and
> device modes) for USB3 port due to higher threshold in full speed receiver
> of USB2.0 PHY.
> 
> One example failure symptom is, the enumeration is failed when connecting
> full speed USB mouse to USB3 port, especially under high temperature.
> 
> The workaround is to configure threshold voltage value of single ended
> receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101.
> 
> Signed-off-by: Peter Chen <peter.chen@nxp.com>

This needs senders S-o-b as well!

> ---
>  drivers/phy/cadence/phy-cadence-salvo.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
> index 2e3d4d8fb8eb..b9866dc146ce 100644
> --- a/drivers/phy/cadence/phy-cadence-salvo.c
> +++ b/drivers/phy/cadence/phy-cadence-salvo.c
> @@ -91,6 +91,7 @@
>  
>  /* USB2 PHY register definition */
>  #define UTMI_REG15				0xaf
> +#define UTMI_AFE_RX_REG5			0x12
>  
>  /* TB_ADDR_TX_RCVDETSC_CTRL */
>  #define RXDET_IN_P3_32KHZ			BIT(0)
> @@ -247,6 +248,8 @@ static int cdns_salvo_phy_init(struct phy *phy)
>  	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15,
>  			 value | TXVALID_GATE_THRESHOLD_HS_0US);
>  
> +	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG5,
> +			 0x5);

single line reads better

>  	udelay(10);
>  
>  	clk_disable_unprepare(salvo_phy->clk);
> -- 
> 2.34.1

-- 
~Vinod

-- 
linux-phy mailing list
linux-phy@lists.infradead.org
https://lists.infradead.org/mailman/listinfo/linux-phy

WARNING: multiple messages have this Message-ID (diff)
From: Vinod Koul <vkoul@kernel.org>
To: Frank Li <Frank.Li@nxp.com>
Cc: devicetree@vger.kernel.org, fushi.peng@nxp.com,
	imx@lists.linux.dev, kernel@pengutronix.de, kishon@kernel.org,
	krzysztof.kozlowski+dt@linaro.org,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org,
	robh+dt@kernel.org, s.hauer@pengutronix.de, shawnguo@kernel.org
Subject: Re: [PATCH v4 3/6] phy: cadence: salvo: add bist fix
Date: Tue, 16 May 2023 22:04:04 +0530	[thread overview]
Message-ID: <ZGOwfFlqWIrAXpHy@matsya> (raw)
In-Reply-To: <20230516154329.3155031-4-Frank.Li@nxp.com>

On 16-05-23, 11:43, Frank Li wrote:
> From: Peter Chen <peter.chen@nxp.com>
> 
> Very limited parts may fail to work on full speed mode (both host and
> device modes) for USB3 port due to higher threshold in full speed receiver
> of USB2.0 PHY.
> 
> One example failure symptom is, the enumeration is failed when connecting
> full speed USB mouse to USB3 port, especially under high temperature.
> 
> The workaround is to configure threshold voltage value of single ended
> receiver by setting USB2.0 PHY register AFE_RX_REG5[2:0] to 3'b101.
> 
> Signed-off-by: Peter Chen <peter.chen@nxp.com>

This needs senders S-o-b as well!

> ---
>  drivers/phy/cadence/phy-cadence-salvo.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/drivers/phy/cadence/phy-cadence-salvo.c b/drivers/phy/cadence/phy-cadence-salvo.c
> index 2e3d4d8fb8eb..b9866dc146ce 100644
> --- a/drivers/phy/cadence/phy-cadence-salvo.c
> +++ b/drivers/phy/cadence/phy-cadence-salvo.c
> @@ -91,6 +91,7 @@
>  
>  /* USB2 PHY register definition */
>  #define UTMI_REG15				0xaf
> +#define UTMI_AFE_RX_REG5			0x12
>  
>  /* TB_ADDR_TX_RCVDETSC_CTRL */
>  #define RXDET_IN_P3_32KHZ			BIT(0)
> @@ -247,6 +248,8 @@ static int cdns_salvo_phy_init(struct phy *phy)
>  	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_REG15,
>  			 value | TXVALID_GATE_THRESHOLD_HS_0US);
>  
> +	cdns_salvo_write(salvo_phy, USB2_PHY_OFFSET, UTMI_AFE_RX_REG5,
> +			 0x5);

single line reads better

>  	udelay(10);
>  
>  	clk_disable_unprepare(salvo_phy->clk);
> -- 
> 2.34.1

-- 
~Vinod

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2023-05-16 16:34 UTC|newest]

Thread overview: 27+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-16 15:43 [PATCH v4 0/6] phy: cadence: salvo: some fixes and workarounds Frank Li
2023-05-16 15:43 ` Frank Li
2023-05-16 15:43 ` Frank Li
2023-05-16 15:43 ` [PATCH v4 1/6] phy: cadence: salvo: add access for USB2PHY Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 15:43 ` [PATCH v4 2/6] phy: cadence: salvo: decrease delay value to zero for txvalid Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 15:43 ` [PATCH v4 3/6] phy: cadence: salvo: add bist fix Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 16:34   ` Vinod Koul [this message]
2023-05-16 16:34     ` Vinod Koul
2023-05-16 16:34     ` Vinod Koul
2023-05-16 15:43 ` [PATCH v4 4/6] phy: cadence: salvo: add .set_mode API Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 16:35   ` Vinod Koul
2023-05-16 16:35     ` Vinod Koul
2023-05-16 16:35     ` Vinod Koul
2023-05-16 15:43 ` [PATCH v4 5/6] phy: cadence: salvo: Add cdns,usb2-disconnect-threshold-microvolt property Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 15:43 ` [PATCH v4 6/6] dt-bindings: phy: cdns,salvo: add property cdns,usb2-disconnect-threshold-microvolt Frank Li
2023-05-16 15:43   ` Frank Li
2023-05-16 15:43   ` Frank Li

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