From: Nicolin Chen <nicolinc@nvidia.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: <will@kernel.org>, <joro@8bytes.org>, <iommu@lists.linux.dev>,
<linux-arm-kernel@lists.infradead.org>,
<jean-philippe@linaro.org>
Subject: Re: [PATCH 1/4] iommu/arm-smmu-v3: Work around MMU-600 erratum 1076982
Date: Wed, 17 May 2023 17:53:19 -0700 [thread overview]
Message-ID: <ZGV2/6487F9S3Blq@Asurada-Nvidia> (raw)
In-Reply-To: <ZFvXF3gKL4WHiBeZ@Asurada-Nvidia>
On Wed, May 10, 2023 at 10:40:42AM -0700, Nicolin Chen wrote:
> On Wed, May 10, 2023 at 04:38:43PM +0100, Robin Murphy wrote:
>
> > MMU-600 versions prior to r1p0 fail to correctly generate a WFE wakeup
> > event when the command queue transitions fom full to non-full. We can
> > easily work around this by simply hiding the SEV capability such that we
> > fall back to polling for space in the queue - since MMU-600 implements
> > MSIs we wouldn't expect to need SEV for sync completion either, so this
> > should have little to no impact.
> >
> > Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>
> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
It happens that I have a simulation environment where the
IIDR value hits the errata, i.e. the NESTING feature bit
gets canceled by this patch. So,
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Hopefully we can get this series merged soon.
Thanks!
Nic
WARNING: multiple messages have this Message-ID (diff)
From: Nicolin Chen <nicolinc@nvidia.com>
To: Robin Murphy <robin.murphy@arm.com>
Cc: <will@kernel.org>, <joro@8bytes.org>, <iommu@lists.linux.dev>,
<linux-arm-kernel@lists.infradead.org>,
<jean-philippe@linaro.org>
Subject: Re: [PATCH 1/4] iommu/arm-smmu-v3: Work around MMU-600 erratum 1076982
Date: Wed, 17 May 2023 17:53:19 -0700 [thread overview]
Message-ID: <ZGV2/6487F9S3Blq@Asurada-Nvidia> (raw)
In-Reply-To: <ZFvXF3gKL4WHiBeZ@Asurada-Nvidia>
On Wed, May 10, 2023 at 10:40:42AM -0700, Nicolin Chen wrote:
> On Wed, May 10, 2023 at 04:38:43PM +0100, Robin Murphy wrote:
>
> > MMU-600 versions prior to r1p0 fail to correctly generate a WFE wakeup
> > event when the command queue transitions fom full to non-full. We can
> > easily work around this by simply hiding the SEV capability such that we
> > fall back to polling for space in the queue - since MMU-600 implements
> > MSIs we wouldn't expect to need SEV for sync completion either, so this
> > should have little to no impact.
> >
> > Signed-off-by: Robin Murphy <robin.murphy@arm.com>
>
> Reviewed-by: Nicolin Chen <nicolinc@nvidia.com>
It happens that I have a simulation environment where the
IIDR value hits the errata, i.e. the NESTING feature bit
gets canceled by this patch. So,
Tested-by: Nicolin Chen <nicolinc@nvidia.com>
Hopefully we can get this series merged soon.
Thanks!
Nic
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next prev parent reply other threads:[~2023-05-18 0:53 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-05-10 15:38 [PATCH 0/4] iommu/arm-smmu-v3: Arm SMMU errata bits Robin Murphy
2023-05-10 15:38 ` [PATCH 1/4] iommu/arm-smmu-v3: Work around MMU-600 erratum 1076982 Robin Murphy
2023-05-10 17:40 ` Nicolin Chen
2023-05-12 19:02 ` Robin Murphy
2023-05-18 0:53 ` Nicolin Chen [this message]
2023-05-18 0:53 ` Nicolin Chen
2023-05-10 15:38 ` [PATCH 2/4] iommu/arm-smmu-v3: Document MMU-700 erratum 2812531 Robin Murphy
2023-05-10 18:12 ` Nicolin Chen
2023-05-10 18:31 ` Nicolin Chen
2023-05-12 19:23 ` Robin Murphy
2023-05-15 15:44 ` Nicolin Chen
2023-05-15 15:44 ` Nicolin Chen
2023-05-10 15:38 ` [PATCH 3/4] iommu/arm-smmu-v3: Add explicit feature for nesting Robin Murphy
2023-05-10 18:13 ` Nicolin Chen
2023-05-10 15:38 ` [PATCH 4/4] iommu/arm-smmu-v3: Document nesting-related errata Robin Murphy
2023-05-10 18:37 ` Nicolin Chen
2023-06-08 21:36 ` [PATCH 0/4] iommu/arm-smmu-v3: Arm SMMU errata bits Will Deacon
2023-06-08 21:36 ` Will Deacon
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