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* [Intel-gfx] [PATCH] drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate
@ 2023-06-28 10:08 Stanislav Lisovskiy
  2023-06-28 14:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
                   ` (4 more replies)
  0 siblings, 5 replies; 8+ messages in thread
From: Stanislav Lisovskiy @ 2023-06-28 10:08 UTC (permalink / raw)
  To: intel-gfx; +Cc: jani.nikula

We are currently having FIFO underruns happening for kms_dsc test case,
problem is that, we check if curreny cdclk is >= pixel rate only if
there is a single VDSC engine enabled(i.e dsc_split=false) however if
we happen to have 2 VDSC engines enabled, we just kinda rely that this
would be automatically enough.
However pixel rate can be even >= than VDSC clock(cdclk) * 2, so in that
case even with 2 VDSC engines enabled, we still need to tweak it up.
So lets compare pixel rate with cdclk * slice count(VDSC engine count) and
check if it still requires bumping up.
Previously we had to bump up CDCLK many times for similar reasons.

Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
---
 drivers/gpu/drm/i915/display/intel_cdclk.c | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_cdclk.c b/drivers/gpu/drm/i915/display/intel_cdclk.c
index 4207863b7b2a..5880dcb11588 100644
--- a/drivers/gpu/drm/i915/display/intel_cdclk.c
+++ b/drivers/gpu/drm/i915/display/intel_cdclk.c
@@ -2607,9 +2607,14 @@ int intel_crtc_compute_min_cdclk(const struct intel_crtc_state *crtc_state)
 	 * When we decide to use only one VDSC engine, since
 	 * each VDSC operates with 1 ppc throughput, pixel clock
 	 * cannot be higher than the VDSC clock (cdclk)
+	 * If there 2 VDSC engines, then pixel clock can't be higher than
+	 * VDSC clock(cdclk) * 2. However even that can still be not enough.
+	 * Slice count reflects amount of VDSC engines,
+	 * so lets use that to determine, if need still need to tweak CDCLK higher.
 	 */
-	if (crtc_state->dsc.compression_enable && !crtc_state->dsc.dsc_split)
-		min_cdclk = max(min_cdclk, (int)crtc_state->pixel_rate);
+	if (crtc_state->dsc.compression_enable)
+		min_cdclk = max_t(int, min_cdclk * crtc_state->dsc.slice_count,
+			          crtc_state->pixel_rate);
 
 	/*
 	 * HACK. Currently for TGL/DG2 platforms we calculate
-- 
2.37.3


^ permalink raw reply related	[flat|nested] 8+ messages in thread
end of thread, other threads:[~2023-07-03  9:35 UTC | newest]

Thread overview: 8+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-06-28 10:08 [Intel-gfx] [PATCH] drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate Stanislav Lisovskiy
2023-06-28 14:56 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-06-28 15:14 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-06-29 17:30 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate (rev2) Patchwork
2023-06-29 17:45 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-07-03  4:53 ` [Intel-gfx] [PATCH] drm/i915: Don't rely that 2 VDSC engines are always enough for pixel rate Nautiyal, Ankit K
2023-07-03  8:50   ` Lisovskiy, Stanislav
2023-07-03  9:35     ` Nautiyal, Ankit K

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