Re: [PATCH v2 1/2] riscv: allow kmalloc() caches aligned to the smallest value

[Jisheng Zhang <jszhang@kernel.org>]

On Tue, Jul 18, 2023 at 11:23:50AM +0100, Conor Dooley wrote:
> Hey Jisheng,
> 
> On Mon, Jul 17, 2023 at 12:51:46AM +0800, Jisheng Zhang wrote:
> > Currently, riscv defines ARCH_DMA_MINALIGN as L1_CACHE_BYTES, I.E
> > 64Bytes, if CONFIG_RISCV_DMA_NONCOHERENT=y. To support unified kernel
> > Image, usually we have to enable CONFIG_RISCV_DMA_NONCOHERENT, thus
> > it brings some bad effects to coherent platforms:
> > 
> > Firstly, it wastes memory, kmalloc-96, kmalloc-32, kmalloc-16 and
> > kmalloc-8 slab caches don't exist any more, they are replaced with
> > either kmalloc-128 or kmalloc-64.
> > 
> > Secondly, larger than necessary kmalloc aligned allocations results
> > in unnecessary cache/TLB pressure.
> > 
> > This issue also exists on arm64 platforms. From last year, Catalin
> > tried to solve this issue by decoupling ARCH_KMALLOC_MINALIGN from
> > ARCH_DMA_MINALIGN, limiting kmalloc() minimum alignment to
> > dma_get_cache_alignment() and replacing ARCH_KMALLOC_MINALIGN usage
> > in various drivers with ARCH_DMA_MINALIGN etc.[1]
> > 
> > One fact we can make use of for riscv: if the CPU doesn't support
> > ZICBOM or T-HEAD CMO, we know the platform is coherent. Based on
> > Catalin's work and above fact, we can easily solve the kmalloc align
> > issue for riscv: we can override dma_get_cache_alignment(), then let
> > it return ARCH_DMA_MINALIGN at the beginning and return 1 once we know
> > the underlying HW neither supports ZICBOM nor supports T-HEAD CMO.
> > 
> > So what about if the CPU supports ZICBOM and T-HEAD CMO, but all the
> > devices are dma coherent? Well, we use ARCH_DMA_MINALIGN as the
> > kmalloc minimum alignment, nothing changed in this case. This case
> > can be improved in the future.
> > 
> > After this patch, a simple test of booting to a small buildroot rootfs
> > on qemu shows:
> > 
> > kmalloc-96           5041    5041     96  ...
> > kmalloc-64           9606    9606     64  ...
> > kmalloc-32           5128    5128     32  ...
> > kmalloc-16           7682    7682     16  ...
> > kmalloc-8           10246   10246      8  ...
> > 
> > So we save about 1268KB memory. The saving will be much larger in normal
> > OS env on real HW platforms.
> > 
> > [1] Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/
> 
> In the future,
> 
> Link: https://lore.kernel.org/linux-arm-kernel/20230524171904.3967031-1-catalin.marinas@arm.com/ [1]
> 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > Change-Id: Ica249d0f8058a02bd4bc6543b4ffc2946a4734a2
> 
> How come this has ended up with a Change-ID? Checkpatch says this is
> something to do with Gerrit & needs to be removed.

Oops, when amending, I forgot to add "-n". And I thought only amending
doesn't need to try checkpatch. Will fix it soon.

Thank you.

> 
> > ---
> >  arch/riscv/include/asm/cache.h      | 14 ++++++++++++++
> >  arch/riscv/include/asm/cacheflush.h |  2 ++
> >  arch/riscv/kernel/setup.c           |  1 +
> >  arch/riscv/mm/dma-noncoherent.c     |  8 ++++++++
> >  4 files changed, 25 insertions(+)
> > 
> > diff --git a/arch/riscv/include/asm/cache.h b/arch/riscv/include/asm/cache.h
> > index d3036df23ccb..2174fe7bac9a 100644
> > --- a/arch/riscv/include/asm/cache.h
> > +++ b/arch/riscv/include/asm/cache.h
> > @@ -13,6 +13,7 @@
> >  
> >  #ifdef CONFIG_RISCV_DMA_NONCOHERENT
> >  #define ARCH_DMA_MINALIGN L1_CACHE_BYTES
> > +#define ARCH_KMALLOC_MINALIGN	(8)
> >  #endif
> >  
> >  /*
> > @@ -23,4 +24,17 @@
> >  #define ARCH_SLAB_MINALIGN	16
> >  #endif
> >  
> > +#ifndef __ASSEMBLY__
> > +
> > +#ifdef CONFIG_RISCV_DMA_NONCOHERENT
> > +extern int dma_cache_alignment;
> > +#define dma_get_cache_alignment dma_get_cache_alignment
> > +static inline int dma_get_cache_alignment(void)
> > +{
> > +	return dma_cache_alignment;
> > +}
> > +#endif
> > +
> > +#endif	/* __ASSEMBLY__ */
> > +
> >  #endif /* _ASM_RISCV_CACHE_H */
> > diff --git a/arch/riscv/include/asm/cacheflush.h b/arch/riscv/include/asm/cacheflush.h
> > index 8091b8bf4883..c640ab6f843b 100644
> > --- a/arch/riscv/include/asm/cacheflush.h
> > +++ b/arch/riscv/include/asm/cacheflush.h
> > @@ -55,8 +55,10 @@ void riscv_init_cbo_blocksizes(void);
> >  
> >  #ifdef CONFIG_RISCV_DMA_NONCOHERENT
> >  void riscv_noncoherent_supported(void);
> > +void __init riscv_set_dma_cache_alignment(void);
> >  #else
> >  static inline void riscv_noncoherent_supported(void) {}
> > +static inline void riscv_set_dma_cache_alignment(void) {}
> >  #endif
> >  
> >  /*
> > diff --git a/arch/riscv/kernel/setup.c b/arch/riscv/kernel/setup.c
> > index 971fe776e2f8..027879b1557a 100644
> > --- a/arch/riscv/kernel/setup.c
> > +++ b/arch/riscv/kernel/setup.c
> > @@ -311,6 +311,7 @@ void __init setup_arch(char **cmdline_p)
> >  	if (IS_ENABLED(CONFIG_RISCV_ISA_ZICBOM) &&
> >  	    riscv_isa_extension_available(NULL, ZICBOM))
> >  		riscv_noncoherent_supported();
> > +	riscv_set_dma_cache_alignment();
> >  }
> >  
> >  static int __init topology_init(void)
> > diff --git a/arch/riscv/mm/dma-noncoherent.c b/arch/riscv/mm/dma-noncoherent.c
> > index d51a75864e53..811227e54bbd 100644
> > --- a/arch/riscv/mm/dma-noncoherent.c
> > +++ b/arch/riscv/mm/dma-noncoherent.c
> > @@ -11,6 +11,8 @@
> >  #include <asm/cacheflush.h>
> >  
> >  static bool noncoherent_supported __ro_after_init;
> > +int dma_cache_alignment __ro_after_init = ARCH_DMA_MINALIGN;
> > +EXPORT_SYMBOL(dma_cache_alignment);
> 
> Why is this not EXPORT_SYMBOL_GPL()?
> 
> Otherwise, this is generally good to me, thanks.
> 
> Conor.
> 
> >  
> >  void arch_sync_dma_for_device(phys_addr_t paddr, size_t size,
> >  			      enum dma_data_direction dir)
> > @@ -78,3 +80,9 @@ void riscv_noncoherent_supported(void)
> >  	     "Non-coherent DMA support enabled without a block size\n");
> >  	noncoherent_supported = true;
> >  }
> > +
> > +void __init riscv_set_dma_cache_alignment(void)
> > +{
> > +	if (!noncoherent_supported)
> > +		dma_cache_alignment = 1;
> > +}
> > -- 
> > 2.40.1
> > 



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