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From: Catalin Marinas <catalin.marinas@arm.com>
To: Kefeng Wang <wangkefeng.wang@huawei.com>
Cc: Andrew Morton <akpm@linux-foundation.org>,
	Will Deacon <will@kernel.org>,
	Mike Kravetz <mike.kravetz@oracle.com>,
	Muchun Song <muchun.song@linux.dev>,
	Mina Almasry <almasrymina@google.com>,
	kirill@shutemov.name, joel@joelfernandes.org,
	william.kucharski@oracle.com, kaleshsingh@google.com,
	linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/4] arm64: tlb: set huge page size to stride for hugepage
Date: Mon, 31 Jul 2023 14:18:12 +0100	[thread overview]
Message-ID: <ZMe0lIQZI2oHDe2o@arm.com> (raw)
In-Reply-To: <70e81ce8-a27a-325f-68d1-836532ed2ba0@huawei.com>

On Mon, Jul 31, 2023 at 07:27:14PM +0800, Kefeng Wang wrote:
> On 2023/7/31 19:11, Catalin Marinas wrote:
> > On Mon, Jul 31, 2023 at 03:48:29PM +0800, Kefeng Wang wrote:
> > > +/*
> > > + * We cannot use leaf-only invalidation here, since we may be invalidating
> > > + * table entries as part of collapsing hugepages or moving page tables.
> > > + * Set the tlb_level to 0 because we can not get enough information here.
> > > + */
> > > +#define flush_tlb_range(vma, start, end)				\
> > > +	__flush_tlb_range(vma, start, end,				\
> > > +				((vma)->vm_flags & VM_HUGETLB)		\
> > > +				? huge_page_size(hstate_vma(vma))	\
> > > +				: PAGE_SIZE, false, 0)
> > 
> > This won't work if we use the contiguous PTE to get 64K hugetlb pages on
> > a 4K base page configuration. The 16 base pages in the range would have
> > to be invalidated individually (the contig PTE bit is just a hint, the
> > hardware may or may not take it into account).
> 
> Got it, the contig huge page is depended on hardware implementation,
> but for normal hugepage(2M/1G), we could use this, right?

Right. Only the pmd/pud cases.

-- 
Catalin

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WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Kefeng Wang <wangkefeng.wang@huawei.com>
Cc: Andrew Morton <akpm@linux-foundation.org>,
	Will Deacon <will@kernel.org>,
	Mike Kravetz <mike.kravetz@oracle.com>,
	Muchun Song <muchun.song@linux.dev>,
	Mina Almasry <almasrymina@google.com>,
	kirill@shutemov.name, joel@joelfernandes.org,
	william.kucharski@oracle.com, kaleshsingh@google.com,
	linux-mm@kvack.org, linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org
Subject: Re: [PATCH 4/4] arm64: tlb: set huge page size to stride for hugepage
Date: Mon, 31 Jul 2023 14:18:12 +0100	[thread overview]
Message-ID: <ZMe0lIQZI2oHDe2o@arm.com> (raw)
In-Reply-To: <70e81ce8-a27a-325f-68d1-836532ed2ba0@huawei.com>

On Mon, Jul 31, 2023 at 07:27:14PM +0800, Kefeng Wang wrote:
> On 2023/7/31 19:11, Catalin Marinas wrote:
> > On Mon, Jul 31, 2023 at 03:48:29PM +0800, Kefeng Wang wrote:
> > > +/*
> > > + * We cannot use leaf-only invalidation here, since we may be invalidating
> > > + * table entries as part of collapsing hugepages or moving page tables.
> > > + * Set the tlb_level to 0 because we can not get enough information here.
> > > + */
> > > +#define flush_tlb_range(vma, start, end)				\
> > > +	__flush_tlb_range(vma, start, end,				\
> > > +				((vma)->vm_flags & VM_HUGETLB)		\
> > > +				? huge_page_size(hstate_vma(vma))	\
> > > +				: PAGE_SIZE, false, 0)
> > 
> > This won't work if we use the contiguous PTE to get 64K hugetlb pages on
> > a 4K base page configuration. The 16 base pages in the range would have
> > to be invalidated individually (the contig PTE bit is just a hint, the
> > hardware may or may not take it into account).
> 
> Got it, the contig huge page is depended on hardware implementation,
> but for normal hugepage(2M/1G), we could use this, right?

Right. Only the pmd/pud cases.

-- 
Catalin


  reply	other threads:[~2023-07-31 13:18 UTC|newest]

Thread overview: 40+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-31  7:48 [PATCH 0/4] mm: mremap: fix move page tables Kefeng Wang
2023-07-31  7:48 ` Kefeng Wang
2023-07-31  7:48 ` [PATCH 1/4] mm: hugetlb: use flush_hugetlb_tlb_range() in move_hugetlb_page_tables() Kefeng Wang
2023-07-31  7:48   ` Kefeng Wang
2023-07-31 23:40   ` Mike Kravetz
2023-07-31 23:40     ` Mike Kravetz
2023-08-03  0:26     ` Mina Almasry
2023-08-03  0:26       ` Mina Almasry
2023-08-01  2:06   ` Muchun Song
2023-08-01  2:06     ` Muchun Song
2023-07-31  7:48 ` [PATCH 2/4] mm: mremap: use flush_pmd_tlb_range() in move_normal_pmd() Kefeng Wang
2023-07-31  7:48   ` Kefeng Wang
2023-07-31 11:05   ` Catalin Marinas
2023-07-31 11:05     ` Catalin Marinas
2023-07-31 11:20     ` Kefeng Wang
2023-07-31 11:20       ` Kefeng Wang
2023-07-31 13:58   ` kernel test robot
2023-07-31 13:58     ` kernel test robot
2023-07-31 21:43   ` kernel test robot
2023-07-31 21:43     ` kernel test robot
2023-07-31  7:48 ` [PATCH 3/4] mm: mremap: use flush_pud_tlb_range in move_normal_pud() Kefeng Wang
2023-07-31  7:48   ` Kefeng Wang
2023-07-31 16:42   ` kernel test robot
2023-07-31 16:42     ` kernel test robot
2023-07-31  7:48 ` [PATCH 4/4] arm64: tlb: set huge page size to stride for hugepage Kefeng Wang
2023-07-31  7:48   ` Kefeng Wang
2023-07-31  8:33   ` Barry Song
2023-07-31  8:33     ` Barry Song
2023-07-31  8:43     ` Barry Song
2023-07-31  8:43       ` Barry Song
2023-07-31  9:28       ` Kefeng Wang
2023-07-31  9:28         ` Kefeng Wang
2023-07-31 10:21         ` Barry Song
2023-07-31 10:21           ` Barry Song
2023-07-31 11:11   ` Catalin Marinas
2023-07-31 11:11     ` Catalin Marinas
2023-07-31 11:27     ` Kefeng Wang
2023-07-31 11:27       ` Kefeng Wang
2023-07-31 13:18       ` Catalin Marinas [this message]
2023-07-31 13:18         ` Catalin Marinas

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