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From: Catalin Marinas <catalin.marinas@arm.com>
To: Yicong Yang <yangyicong@huawei.com>
Cc: akpm@linux-foundation.org, linux-mm@kvack.org,
	linux-arm-kernel@lists.infradead.org, 21cnbao@gmail.com,
	yangyicong@hisilicon.com
Subject: Re: [PATCH -mm] arm64: tlbflush: Add some comments for TLB batched flushing
Date: Mon, 31 Jul 2023 11:34:50 +0100	[thread overview]
Message-ID: <ZMeOStwxmmUsfwAZ@arm.com> (raw)
In-Reply-To: <20230729131448.15531-1-yangyicong@huawei.com>

On Sat, Jul 29, 2023 at 09:14:48PM +0800, Yicong Yang wrote:
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 3456866c6a1d..2bad230b95b4 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -300,11 +300,26 @@ static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *b
>  	__flush_tlb_page_nosync(mm, uaddr);
>  }
>  
> +/*
> + * If mprotect/munmap/etc occurs during TLB batched flushing, we need to
> + * synchronise all the TLBI issued by a DSB to avoid the race mentioned in

Nitpick: s/by a DSB/with a DSB/ as it somehow reads that the DSB issued
the TLBI.

Since the rest of the series went in via the mm tree, I assume Andrew
will pick this up as well.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

Thanks.

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WARNING: multiple messages have this Message-ID (diff)
From: Catalin Marinas <catalin.marinas@arm.com>
To: Yicong Yang <yangyicong@huawei.com>
Cc: akpm@linux-foundation.org, linux-mm@kvack.org,
	linux-arm-kernel@lists.infradead.org, 21cnbao@gmail.com,
	yangyicong@hisilicon.com
Subject: Re: [PATCH -mm] arm64: tlbflush: Add some comments for TLB batched flushing
Date: Mon, 31 Jul 2023 11:34:50 +0100	[thread overview]
Message-ID: <ZMeOStwxmmUsfwAZ@arm.com> (raw)
In-Reply-To: <20230729131448.15531-1-yangyicong@huawei.com>

On Sat, Jul 29, 2023 at 09:14:48PM +0800, Yicong Yang wrote:
> diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h
> index 3456866c6a1d..2bad230b95b4 100644
> --- a/arch/arm64/include/asm/tlbflush.h
> +++ b/arch/arm64/include/asm/tlbflush.h
> @@ -300,11 +300,26 @@ static inline void arch_tlbbatch_add_pending(struct arch_tlbflush_unmap_batch *b
>  	__flush_tlb_page_nosync(mm, uaddr);
>  }
>  
> +/*
> + * If mprotect/munmap/etc occurs during TLB batched flushing, we need to
> + * synchronise all the TLBI issued by a DSB to avoid the race mentioned in

Nitpick: s/by a DSB/with a DSB/ as it somehow reads that the DSB issued
the TLBI.

Since the rest of the series went in via the mm tree, I assume Andrew
will pick this up as well.

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

Thanks.


  reply	other threads:[~2023-07-31 10:35 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-29 13:14 [PATCH -mm] arm64: tlbflush: Add some comments for TLB batched flushing Yicong Yang
2023-07-29 13:14 ` Yicong Yang
2023-07-31 10:34 ` Catalin Marinas [this message]
2023-07-31 10:34   ` Catalin Marinas
2023-08-01  1:10 ` Alistair Popple
2023-08-01  1:10   ` Alistair Popple

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