* [Intel-xe] [RFC PATCH 0/1] Rename engine to exec_queue
@ 2023-07-31 16:08 Francois Dugast
2023-07-31 16:08 ` [Intel-xe] [RFC PATCH 1/1] drm/xe: " Francois Dugast
` (5 more replies)
0 siblings, 6 replies; 9+ messages in thread
From: Francois Dugast @ 2023-07-31 16:08 UTC (permalink / raw)
To: intel-xe; +Cc: Francois Dugast
This is an attempt to rename engine to exec queue in order to prevent confusion
between engine and hw engine, as discussed here:
https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/162
Sending as RFC to get feedback on potential mixups between engine and hw engine,
either because an occurrence of hw engine has incorrectly been renamed to exec
queue or because an occurrence of engine has not been renamed to exec queue.
Francois Dugast (1):
drm/xe: Rename engine to exec_queue
drivers/gpu/drm/xe/Makefile | 2 +-
drivers/gpu/drm/xe/tests/xe_migrate.c | 18 +-
drivers/gpu/drm/xe/xe_bb.c | 26 +-
drivers/gpu/drm/xe/xe_bb.h | 8 +-
drivers/gpu/drm/xe/xe_devcoredump.c | 40 +-
drivers/gpu/drm/xe/xe_devcoredump.h | 6 +-
drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 +-
drivers/gpu/drm/xe/xe_device.c | 62 +-
drivers/gpu/drm/xe/xe_device.h | 8 +-
drivers/gpu/drm/xe/xe_device_types.h | 2 +-
drivers/gpu/drm/xe/xe_engine.c | 850 -------------
drivers/gpu/drm/xe/xe_engine.h | 63 -
drivers/gpu/drm/xe/xe_exec.c | 62 +-
drivers/gpu/drm/xe/xe_exec_queue.c | 850 +++++++++++++
drivers/gpu/drm/xe/xe_exec_queue.h | 63 +
...e_engine_types.h => xe_exec_queue_types.h} | 110 +-
drivers/gpu/drm/xe/xe_execlist.c | 126 +-
drivers/gpu/drm/xe/xe_execlist_types.h | 8 +-
drivers/gpu/drm/xe/xe_gt.c | 72 +-
drivers/gpu/drm/xe/xe_gt_types.h | 6 +-
drivers/gpu/drm/xe/xe_guc_ads.c | 2 +-
drivers/gpu/drm/xe/xe_guc_ct.c | 10 +-
...gine_types.h => xe_guc_exec_queue_types.h} | 10 +-
drivers/gpu/drm/xe/xe_guc_fwif.h | 6 +-
drivers/gpu/drm/xe/xe_guc_submit.c | 1074 ++++++++---------
drivers/gpu/drm/xe/xe_guc_submit.h | 20 +-
drivers/gpu/drm/xe/xe_guc_submit_types.h | 20 +-
drivers/gpu/drm/xe/xe_guc_types.h | 4 +-
drivers/gpu/drm/xe/xe_lrc.c | 10 +-
drivers/gpu/drm/xe/xe_lrc.h | 4 +-
drivers/gpu/drm/xe/xe_migrate.c | 62 +-
drivers/gpu/drm/xe/xe_migrate.h | 6 +-
drivers/gpu/drm/xe/xe_mocs.c | 2 +-
drivers/gpu/drm/xe/xe_mocs.h | 2 +-
drivers/gpu/drm/xe/xe_preempt_fence.c | 32 +-
drivers/gpu/drm/xe/xe_preempt_fence.h | 4 +-
drivers/gpu/drm/xe/xe_preempt_fence_types.h | 5 +-
drivers/gpu/drm/xe/xe_pt.c | 18 +-
drivers/gpu/drm/xe/xe_pt.h | 6 +-
drivers/gpu/drm/xe/xe_query.c | 4 +-
drivers/gpu/drm/xe/xe_ring_ops.c | 38 +-
drivers/gpu/drm/xe/xe_sched_job.c | 76 +-
drivers/gpu/drm/xe/xe_sched_job.h | 4 +-
drivers/gpu/drm/xe/xe_sched_job_types.h | 6 +-
drivers/gpu/drm/xe/xe_trace.h | 140 +--
drivers/gpu/drm/xe/xe_vm.c | 178 +--
drivers/gpu/drm/xe/xe_vm.h | 4 +-
drivers/gpu/drm/xe/xe_vm_types.h | 6 +-
include/uapi/drm/xe_drm.h | 86 +-
49 files changed, 2111 insertions(+), 2112 deletions(-)
delete mode 100644 drivers/gpu/drm/xe/xe_engine.c
delete mode 100644 drivers/gpu/drm/xe/xe_engine.h
create mode 100644 drivers/gpu/drm/xe/xe_exec_queue.c
create mode 100644 drivers/gpu/drm/xe/xe_exec_queue.h
rename drivers/gpu/drm/xe/{xe_engine_types.h => xe_exec_queue_types.h} (52%)
rename drivers/gpu/drm/xe/{xe_guc_engine_types.h => xe_guc_exec_queue_types.h} (88%)
--
2.34.1
^ permalink raw reply [flat|nested] 9+ messages in thread* [Intel-xe] [RFC PATCH 1/1] drm/xe: Rename engine to exec_queue 2023-07-31 16:08 [Intel-xe] [RFC PATCH 0/1] Rename engine to exec_queue Francois Dugast @ 2023-07-31 16:08 ` Francois Dugast 2023-07-31 18:03 ` Rodrigo Vivi 2023-07-31 16:12 ` [Intel-xe] ✓ CI.Patch_applied: success for " Patchwork ` (4 subsequent siblings) 5 siblings, 1 reply; 9+ messages in thread From: Francois Dugast @ 2023-07-31 16:08 UTC (permalink / raw) To: intel-xe; +Cc: Francois Dugast Engine was inappropriately used to refer to execution queues and it also created some confusion with hardware engines. Where it applies the exec_queue variable name is changed to q and comments are also updated. Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/162 Signed-off-by: Francois Dugast <francois.dugast@intel.com> --- drivers/gpu/drm/xe/Makefile | 2 +- drivers/gpu/drm/xe/tests/xe_migrate.c | 18 +- drivers/gpu/drm/xe/xe_bb.c | 26 +- drivers/gpu/drm/xe/xe_bb.h | 8 +- drivers/gpu/drm/xe/xe_devcoredump.c | 40 +- drivers/gpu/drm/xe/xe_devcoredump.h | 6 +- drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 +- drivers/gpu/drm/xe/xe_device.c | 62 +- drivers/gpu/drm/xe/xe_device.h | 8 +- drivers/gpu/drm/xe/xe_device_types.h | 2 +- drivers/gpu/drm/xe/xe_engine.c | 850 ------------- drivers/gpu/drm/xe/xe_engine.h | 63 - drivers/gpu/drm/xe/xe_exec.c | 62 +- drivers/gpu/drm/xe/xe_exec_queue.c | 850 +++++++++++++ drivers/gpu/drm/xe/xe_exec_queue.h | 63 + ...e_engine_types.h => xe_exec_queue_types.h} | 110 +- drivers/gpu/drm/xe/xe_execlist.c | 126 +- drivers/gpu/drm/xe/xe_execlist_types.h | 8 +- drivers/gpu/drm/xe/xe_gt.c | 72 +- drivers/gpu/drm/xe/xe_gt_types.h | 6 +- drivers/gpu/drm/xe/xe_guc_ads.c | 2 +- drivers/gpu/drm/xe/xe_guc_ct.c | 10 +- ...gine_types.h => xe_guc_exec_queue_types.h} | 10 +- drivers/gpu/drm/xe/xe_guc_fwif.h | 6 +- drivers/gpu/drm/xe/xe_guc_submit.c | 1074 ++++++++--------- drivers/gpu/drm/xe/xe_guc_submit.h | 20 +- drivers/gpu/drm/xe/xe_guc_submit_types.h | 20 +- drivers/gpu/drm/xe/xe_guc_types.h | 4 +- drivers/gpu/drm/xe/xe_lrc.c | 10 +- drivers/gpu/drm/xe/xe_lrc.h | 4 +- drivers/gpu/drm/xe/xe_migrate.c | 62 +- drivers/gpu/drm/xe/xe_migrate.h | 6 +- drivers/gpu/drm/xe/xe_mocs.c | 2 +- drivers/gpu/drm/xe/xe_mocs.h | 2 +- drivers/gpu/drm/xe/xe_preempt_fence.c | 32 +- drivers/gpu/drm/xe/xe_preempt_fence.h | 4 +- drivers/gpu/drm/xe/xe_preempt_fence_types.h | 5 +- drivers/gpu/drm/xe/xe_pt.c | 18 +- drivers/gpu/drm/xe/xe_pt.h | 6 +- drivers/gpu/drm/xe/xe_query.c | 4 +- drivers/gpu/drm/xe/xe_ring_ops.c | 38 +- drivers/gpu/drm/xe/xe_sched_job.c | 76 +- drivers/gpu/drm/xe/xe_sched_job.h | 4 +- drivers/gpu/drm/xe/xe_sched_job_types.h | 6 +- drivers/gpu/drm/xe/xe_trace.h | 140 +-- drivers/gpu/drm/xe/xe_vm.c | 178 +-- drivers/gpu/drm/xe/xe_vm.h | 4 +- drivers/gpu/drm/xe/xe_vm_types.h | 6 +- include/uapi/drm/xe_drm.h | 86 +- 49 files changed, 2111 insertions(+), 2112 deletions(-) delete mode 100644 drivers/gpu/drm/xe/xe_engine.c delete mode 100644 drivers/gpu/drm/xe/xe_engine.h create mode 100644 drivers/gpu/drm/xe/xe_exec_queue.c create mode 100644 drivers/gpu/drm/xe/xe_exec_queue.h rename drivers/gpu/drm/xe/{xe_engine_types.h => xe_exec_queue_types.h} (52%) rename drivers/gpu/drm/xe/{xe_guc_engine_types.h => xe_guc_exec_queue_types.h} (88%) diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile index 4ea9e3150c20..e79624ab2cb3 100644 --- a/drivers/gpu/drm/xe/Makefile +++ b/drivers/gpu/drm/xe/Makefile @@ -51,9 +51,9 @@ xe-y += xe_bb.o \ xe_device.o \ xe_device_sysfs.o \ xe_dma_buf.o \ - xe_engine.o \ xe_exec.o \ xe_execlist.o \ + xe_exec_queue.o \ xe_force_wake.o \ xe_ggtt.o \ xe_gt.o \ diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c index 9e9b228fe315..5c8d5e78d9bc 100644 --- a/drivers/gpu/drm/xe/tests/xe_migrate.c +++ b/drivers/gpu/drm/xe/tests/xe_migrate.c @@ -38,7 +38,7 @@ static int run_sanity_job(struct xe_migrate *m, struct xe_device *xe, struct kunit *test) { u64 batch_base = xe_migrate_batch_base(m, xe->info.supports_usm); - struct xe_sched_job *job = xe_bb_create_migration_job(m->eng, bb, + struct xe_sched_job *job = xe_bb_create_migration_job(m->q, bb, batch_base, second_idx); struct dma_fence *fence; @@ -215,7 +215,7 @@ static void test_pt_update(struct xe_migrate *m, struct xe_bo *pt, xe_map_memset(xe, &pt->vmap, 0, (u8)expected, pt->size); then = ktime_get(); - fence = xe_migrate_update_pgtables(m, NULL, NULL, m->eng, &update, 1, + fence = xe_migrate_update_pgtables(m, NULL, NULL, m->q, &update, 1, NULL, 0, &pt_update); now = ktime_get(); if (sanity_fence_failed(xe, fence, "Migration pagetable update", test)) @@ -257,7 +257,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) return; } - big = xe_bo_create_pin_map(xe, tile, m->eng->vm, SZ_4M, + big = xe_bo_create_pin_map(xe, tile, m->q->vm, SZ_4M, ttm_bo_type_kernel, XE_BO_CREATE_VRAM_IF_DGFX(tile) | XE_BO_CREATE_PINNED_BIT); @@ -266,7 +266,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) goto vunmap; } - pt = xe_bo_create_pin_map(xe, tile, m->eng->vm, XE_PAGE_SIZE, + pt = xe_bo_create_pin_map(xe, tile, m->q->vm, XE_PAGE_SIZE, ttm_bo_type_kernel, XE_BO_CREATE_VRAM_IF_DGFX(tile) | XE_BO_CREATE_PINNED_BIT); @@ -276,7 +276,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) goto free_big; } - tiny = xe_bo_create_pin_map(xe, tile, m->eng->vm, + tiny = xe_bo_create_pin_map(xe, tile, m->q->vm, 2 * SZ_4K, ttm_bo_type_kernel, XE_BO_CREATE_VRAM_IF_DGFX(tile) | @@ -295,14 +295,14 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) } kunit_info(test, "Starting tests, top level PT addr: %lx, special pagetable base addr: %lx\n", - (unsigned long)xe_bo_main_addr(m->eng->vm->pt_root[id]->bo, XE_PAGE_SIZE), + (unsigned long)xe_bo_main_addr(m->q->vm->pt_root[id]->bo, XE_PAGE_SIZE), (unsigned long)xe_bo_main_addr(m->pt_bo, XE_PAGE_SIZE)); /* First part of the test, are we updating our pagetable bo with a new entry? */ xe_map_wr(xe, &bo->vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1), u64, 0xdeaddeadbeefbeef); expected = xe_pte_encode(pt, 0, XE_CACHE_WB, 0); - if (m->eng->vm->flags & XE_VM_FLAG_64K) + if (m->q->vm->flags & XE_VM_FLAG_64K) expected |= XE_PTE_PS64; if (xe_bo_is_vram(pt)) xe_res_first(pt->ttm.resource, 0, pt->size, &src_it); @@ -399,11 +399,11 @@ static int migrate_test_run_device(struct xe_device *xe) struct ww_acquire_ctx ww; kunit_info(test, "Testing tile id %d.\n", id); - xe_vm_lock(m->eng->vm, &ww, 0, true); + xe_vm_lock(m->q->vm, &ww, 0, true); xe_device_mem_access_get(xe); xe_migrate_sanity_test(m, test); xe_device_mem_access_put(xe); - xe_vm_unlock(m->eng->vm, &ww); + xe_vm_unlock(m->q->vm, &ww); } return 0; diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c index b15a7cb7db4c..38f4ce83a207 100644 --- a/drivers/gpu/drm/xe/xe_bb.c +++ b/drivers/gpu/drm/xe/xe_bb.c @@ -7,7 +7,7 @@ #include "regs/xe_gpu_commands.h" #include "xe_device.h" -#include "xe_engine_types.h" +#include "xe_exec_queue_types.h" #include "xe_gt.h" #include "xe_hw_fence.h" #include "xe_sa.h" @@ -60,30 +60,30 @@ struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm) } static struct xe_sched_job * -__xe_bb_create_job(struct xe_engine *kernel_eng, struct xe_bb *bb, u64 *addr) +__xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 *addr) { u32 size = drm_suballoc_size(bb->bo); bb->cs[bb->len++] = MI_BATCH_BUFFER_END; - WARN_ON(bb->len * 4 + bb_prefetch(kernel_eng->gt) > size); + WARN_ON(bb->len * 4 + bb_prefetch(q->gt) > size); xe_sa_bo_flush_write(bb->bo); - return xe_sched_job_create(kernel_eng, addr); + return xe_sched_job_create(q, addr); } -struct xe_sched_job *xe_bb_create_wa_job(struct xe_engine *wa_eng, +struct xe_sched_job *xe_bb_create_wa_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 batch_base_ofs) { u64 addr = batch_base_ofs + drm_suballoc_soffset(bb->bo); - XE_WARN_ON(!(wa_eng->vm->flags & XE_VM_FLAG_MIGRATION)); + XE_WARN_ON(!(q->vm->flags & XE_VM_FLAG_MIGRATION)); - return __xe_bb_create_job(wa_eng, bb, &addr); + return __xe_bb_create_job(q, bb, &addr); } -struct xe_sched_job *xe_bb_create_migration_job(struct xe_engine *kernel_eng, +struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 batch_base_ofs, u32 second_idx) @@ -95,18 +95,18 @@ struct xe_sched_job *xe_bb_create_migration_job(struct xe_engine *kernel_eng, }; XE_WARN_ON(second_idx > bb->len); - XE_WARN_ON(!(kernel_eng->vm->flags & XE_VM_FLAG_MIGRATION)); + XE_WARN_ON(!(q->vm->flags & XE_VM_FLAG_MIGRATION)); - return __xe_bb_create_job(kernel_eng, bb, addr); + return __xe_bb_create_job(q, bb, addr); } -struct xe_sched_job *xe_bb_create_job(struct xe_engine *kernel_eng, +struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb) { u64 addr = xe_sa_bo_gpu_addr(bb->bo); - XE_WARN_ON(kernel_eng->vm && kernel_eng->vm->flags & XE_VM_FLAG_MIGRATION); - return __xe_bb_create_job(kernel_eng, bb, &addr); + XE_WARN_ON(q->vm && q->vm->flags & XE_VM_FLAG_MIGRATION); + return __xe_bb_create_job(q, bb, &addr); } void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence) diff --git a/drivers/gpu/drm/xe/xe_bb.h b/drivers/gpu/drm/xe/xe_bb.h index 0cc9260c9634..c5ae0770bab5 100644 --- a/drivers/gpu/drm/xe/xe_bb.h +++ b/drivers/gpu/drm/xe/xe_bb.h @@ -11,16 +11,16 @@ struct dma_fence; struct xe_gt; -struct xe_engine; +struct xe_exec_queue; struct xe_sched_job; struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 size, bool usm); -struct xe_sched_job *xe_bb_create_job(struct xe_engine *kernel_eng, +struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb); -struct xe_sched_job *xe_bb_create_migration_job(struct xe_engine *kernel_eng, +struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 batch_ofs, u32 second_idx); -struct xe_sched_job *xe_bb_create_wa_job(struct xe_engine *wa_eng, +struct xe_sched_job *xe_bb_create_wa_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 batch_ofs); void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence); diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c index f53f4b51233a..68abc0b195be 100644 --- a/drivers/gpu/drm/xe/xe_devcoredump.c +++ b/drivers/gpu/drm/xe/xe_devcoredump.c @@ -10,7 +10,7 @@ #include <generated/utsrelease.h> #include "xe_device.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_guc_ct.h" @@ -53,9 +53,9 @@ static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump) return container_of(coredump, struct xe_device, devcoredump); } -static struct xe_guc *engine_to_guc(struct xe_engine *e) +static struct xe_guc *exec_queue_to_guc(struct xe_exec_queue *q) { - return &e->gt->uc.guc; + return &q->gt->uc.guc; } static ssize_t xe_devcoredump_read(char *buffer, loff_t offset, @@ -91,7 +91,7 @@ static ssize_t xe_devcoredump_read(char *buffer, loff_t offset, drm_printf(&p, "\n**** GuC CT ****\n"); xe_guc_ct_snapshot_print(coredump->snapshot.ct, &p); - xe_guc_engine_snapshot_print(coredump->snapshot.ge, &p); + xe_guc_exec_queue_snapshot_print(coredump->snapshot.ge, &p); drm_printf(&p, "\n**** HW Engines ****\n"); for (i = 0; i < XE_NUM_HW_ENGINES; i++) @@ -112,7 +112,7 @@ static void xe_devcoredump_free(void *data) return; xe_guc_ct_snapshot_free(coredump->snapshot.ct); - xe_guc_engine_snapshot_free(coredump->snapshot.ge); + xe_guc_exec_queue_snapshot_free(coredump->snapshot.ge); for (i = 0; i < XE_NUM_HW_ENGINES; i++) if (coredump->snapshot.hwe[i]) xe_hw_engine_snapshot_free(coredump->snapshot.hwe[i]); @@ -123,14 +123,14 @@ static void xe_devcoredump_free(void *data) } static void devcoredump_snapshot(struct xe_devcoredump *coredump, - struct xe_engine *e) + struct xe_exec_queue *q) { struct xe_devcoredump_snapshot *ss = &coredump->snapshot; - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); struct xe_hw_engine *hwe; enum xe_hw_engine_id id; - u32 adj_logical_mask = e->logical_mask; - u32 width_mask = (0x1 << e->width) - 1; + u32 adj_logical_mask = q->logical_mask; + u32 width_mask = (0x1 << q->width) - 1; int i; bool cookie; @@ -138,22 +138,22 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump, ss->boot_time = ktime_get_boottime(); cookie = dma_fence_begin_signalling(); - for (i = 0; e->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { + for (i = 0; q->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { if (adj_logical_mask & BIT(i)) { adj_logical_mask |= width_mask << i; - i += e->width; + i += q->width; } else { ++i; } } - xe_force_wake_get(gt_to_fw(e->gt), XE_FORCEWAKE_ALL); + xe_force_wake_get(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); coredump->snapshot.ct = xe_guc_ct_snapshot_capture(&guc->ct, true); - coredump->snapshot.ge = xe_guc_engine_snapshot_capture(e); + coredump->snapshot.ge = xe_guc_exec_queue_snapshot_capture(q); - for_each_hw_engine(hwe, e->gt, id) { - if (hwe->class != e->hwe->class || + for_each_hw_engine(hwe, q->gt, id) { + if (hwe->class != q->hwe->class || !(BIT(hwe->logical_instance) & adj_logical_mask)) { coredump->snapshot.hwe[id] = NULL; continue; @@ -161,21 +161,21 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump, coredump->snapshot.hwe[id] = xe_hw_engine_snapshot_capture(hwe); } - xe_force_wake_put(gt_to_fw(e->gt), XE_FORCEWAKE_ALL); + xe_force_wake_put(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); dma_fence_end_signalling(cookie); } /** * xe_devcoredump - Take the required snapshots and initialize coredump device. - * @e: The faulty xe_engine, where the issue was detected. + * @q: The faulty xe_exec_queue, where the issue was detected. * * This function should be called at the crash time within the serialized * gt_reset. It is skipped if we still have the core dump device available * with the information of the 'first' snapshot. */ -void xe_devcoredump(struct xe_engine *e) +void xe_devcoredump(struct xe_exec_queue *q) { - struct xe_device *xe = gt_to_xe(e->gt); + struct xe_device *xe = gt_to_xe(q->gt); struct xe_devcoredump *coredump = &xe->devcoredump; if (coredump->captured) { @@ -184,7 +184,7 @@ void xe_devcoredump(struct xe_engine *e) } coredump->captured = true; - devcoredump_snapshot(coredump, e); + devcoredump_snapshot(coredump, q); drm_info(&xe->drm, "Xe device coredump has been created\n"); drm_info(&xe->drm, "Check your /sys/class/drm/card%d/device/devcoredump/data\n", diff --git a/drivers/gpu/drm/xe/xe_devcoredump.h b/drivers/gpu/drm/xe/xe_devcoredump.h index 854882129227..6ac218a5c194 100644 --- a/drivers/gpu/drm/xe/xe_devcoredump.h +++ b/drivers/gpu/drm/xe/xe_devcoredump.h @@ -7,12 +7,12 @@ #define _XE_DEVCOREDUMP_H_ struct xe_device; -struct xe_engine; +struct xe_exec_queue; #ifdef CONFIG_DEV_COREDUMP -void xe_devcoredump(struct xe_engine *e); +void xe_devcoredump(struct xe_exec_queue *q); #else -static inline void xe_devcoredump(struct xe_engine *e) +static inline void xe_devcoredump(struct xe_exec_queue *q) { } #endif diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h index c0d711eb6ab3..7fdad9c3d3dd 100644 --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h @@ -30,7 +30,7 @@ struct xe_devcoredump_snapshot { /** @ct: GuC CT snapshot */ struct xe_guc_ct_snapshot *ct; /** @ge: Guc Engine snapshot */ - struct xe_guc_submit_engine_snapshot *ge; + struct xe_guc_submit_exec_queue_snapshot *ge; /** @hwe: HW Engine snapshot array */ struct xe_hw_engine_snapshot *hwe[XE_NUM_HW_ENGINES]; }; diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c index 5409cf7895d3..766df07de979 100644 --- a/drivers/gpu/drm/xe/xe_device.c +++ b/drivers/gpu/drm/xe/xe_device.c @@ -19,7 +19,7 @@ #include "xe_display.h" #include "xe_dma_buf.h" #include "xe_drv.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_exec.h" #include "xe_gt.h" #include "xe_irq.h" @@ -54,33 +54,33 @@ static int xe_file_open(struct drm_device *dev, struct drm_file *file) mutex_init(&xef->vm.lock); xa_init_flags(&xef->vm.xa, XA_FLAGS_ALLOC1); - mutex_init(&xef->engine.lock); - xa_init_flags(&xef->engine.xa, XA_FLAGS_ALLOC1); + mutex_init(&xef->exec_queue.lock); + xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1); file->driver_priv = xef; return 0; } -static void device_kill_persistent_engines(struct xe_device *xe, - struct xe_file *xef); +static void device_kill_persistent_exec_queues(struct xe_device *xe, + struct xe_file *xef); static void xe_file_close(struct drm_device *dev, struct drm_file *file) { struct xe_device *xe = to_xe_device(dev); struct xe_file *xef = file->driver_priv; struct xe_vm *vm; - struct xe_engine *e; + struct xe_exec_queue *q; unsigned long idx; - mutex_lock(&xef->engine.lock); - xa_for_each(&xef->engine.xa, idx, e) { - xe_engine_kill(e); - xe_engine_put(e); + mutex_lock(&xef->exec_queue.lock); + xa_for_each(&xef->exec_queue.xa, idx, q) { + xe_exec_queue_kill(q); + xe_exec_queue_put(q); } - mutex_unlock(&xef->engine.lock); - xa_destroy(&xef->engine.xa); - mutex_destroy(&xef->engine.lock); - device_kill_persistent_engines(xe, xef); + mutex_unlock(&xef->exec_queue.lock); + xa_destroy(&xef->exec_queue.xa); + mutex_destroy(&xef->exec_queue.lock); + device_kill_persistent_exec_queues(xe, xef); mutex_lock(&xef->vm.lock); xa_for_each(&xef->vm.xa, idx, vm) @@ -100,15 +100,15 @@ static const struct drm_ioctl_desc xe_ioctls[] = { DRM_IOCTL_DEF_DRV(XE_VM_CREATE, xe_vm_create_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(XE_VM_DESTROY, xe_vm_destroy_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(XE_VM_BIND, xe_vm_bind_ioctl, DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(XE_ENGINE_CREATE, xe_engine_create_ioctl, + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_CREATE, xe_exec_queue_create_ioctl, DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(XE_ENGINE_GET_PROPERTY, xe_engine_get_property_ioctl, + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_GET_PROPERTY, xe_exec_queue_get_property_ioctl, DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(XE_ENGINE_DESTROY, xe_engine_destroy_ioctl, + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_DESTROY, xe_exec_queue_destroy_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(XE_EXEC, xe_exec_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(XE_MMIO, xe_mmio_ioctl, DRM_RENDER_ALLOW), - DRM_IOCTL_DEF_DRV(XE_ENGINE_SET_PROPERTY, xe_engine_set_property_ioctl, + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_SET_PROPERTY, xe_exec_queue_set_property_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(XE_WAIT_USER_FENCE, xe_wait_user_fence_ioctl, DRM_RENDER_ALLOW), @@ -372,33 +372,33 @@ void xe_device_shutdown(struct xe_device *xe) { } -void xe_device_add_persistent_engines(struct xe_device *xe, struct xe_engine *e) +void xe_device_add_persistent_exec_queues(struct xe_device *xe, struct xe_exec_queue *q) { mutex_lock(&xe->persistent_engines.lock); - list_add_tail(&e->persistent.link, &xe->persistent_engines.list); + list_add_tail(&q->persistent.link, &xe->persistent_engines.list); mutex_unlock(&xe->persistent_engines.lock); } -void xe_device_remove_persistent_engines(struct xe_device *xe, - struct xe_engine *e) +void xe_device_remove_persistent_exec_queues(struct xe_device *xe, + struct xe_exec_queue *q) { mutex_lock(&xe->persistent_engines.lock); - if (!list_empty(&e->persistent.link)) - list_del(&e->persistent.link); + if (!list_empty(&q->persistent.link)) + list_del(&q->persistent.link); mutex_unlock(&xe->persistent_engines.lock); } -static void device_kill_persistent_engines(struct xe_device *xe, - struct xe_file *xef) +static void device_kill_persistent_exec_queues(struct xe_device *xe, + struct xe_file *xef) { - struct xe_engine *e, *next; + struct xe_exec_queue *q, *next; mutex_lock(&xe->persistent_engines.lock); - list_for_each_entry_safe(e, next, &xe->persistent_engines.list, + list_for_each_entry_safe(q, next, &xe->persistent_engines.list, persistent.link) - if (e->persistent.xef == xef) { - xe_engine_kill(e); - list_del_init(&e->persistent.link); + if (q->persistent.xef == xef) { + xe_exec_queue_kill(q); + list_del_init(&q->persistent.link); } mutex_unlock(&xe->persistent_engines.lock); } diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h index 61a5cf1f7300..71582094834c 100644 --- a/drivers/gpu/drm/xe/xe_device.h +++ b/drivers/gpu/drm/xe/xe_device.h @@ -6,7 +6,7 @@ #ifndef _XE_DEVICE_H_ #define _XE_DEVICE_H_ -struct xe_engine; +struct xe_exec_queue; struct xe_file; #include <drm/drm_util.h> @@ -41,9 +41,9 @@ int xe_device_probe(struct xe_device *xe); void xe_device_remove(struct xe_device *xe); void xe_device_shutdown(struct xe_device *xe); -void xe_device_add_persistent_engines(struct xe_device *xe, struct xe_engine *e); -void xe_device_remove_persistent_engines(struct xe_device *xe, - struct xe_engine *e); +void xe_device_add_persistent_exec_queues(struct xe_device *xe, struct xe_exec_queue *q); +void xe_device_remove_persistent_exec_queues(struct xe_device *xe, + struct xe_exec_queue *q); void xe_device_wmb(struct xe_device *xe); diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h index b156f69d7320..f6665cd16a66 100644 --- a/drivers/gpu/drm/xe/xe_device_types.h +++ b/drivers/gpu/drm/xe/xe_device_types.h @@ -494,7 +494,7 @@ struct xe_file { struct xarray xa; /** @lock: protects file engine state */ struct mutex lock; - } engine; + } exec_queue; }; #endif diff --git a/drivers/gpu/drm/xe/xe_engine.c b/drivers/gpu/drm/xe/xe_engine.c deleted file mode 100644 index c30810a687b1..000000000000 --- a/drivers/gpu/drm/xe/xe_engine.c +++ /dev/null @@ -1,850 +0,0 @@ -// SPDX-License-Identifier: MIT -/* - * Copyright © 2021 Intel Corporation - */ - -#include "xe_engine.h" - -#include <linux/nospec.h> - -#include <drm/drm_device.h> -#include <drm/drm_file.h> -#include <drm/xe_drm.h> - -#include "xe_device.h" -#include "xe_gt.h" -#include "xe_hw_fence.h" -#include "xe_lrc.h" -#include "xe_macros.h" -#include "xe_migrate.h" -#include "xe_pm.h" -#include "xe_ring_ops_types.h" -#include "xe_trace.h" -#include "xe_vm.h" - -static struct xe_engine *__xe_engine_create(struct xe_device *xe, - struct xe_vm *vm, - u32 logical_mask, - u16 width, struct xe_hw_engine *hwe, - u32 flags) -{ - struct xe_engine *e; - struct xe_gt *gt = hwe->gt; - int err; - int i; - - e = kzalloc(sizeof(*e) + sizeof(struct xe_lrc) * width, GFP_KERNEL); - if (!e) - return ERR_PTR(-ENOMEM); - - kref_init(&e->refcount); - e->flags = flags; - e->hwe = hwe; - e->gt = gt; - if (vm) - e->vm = xe_vm_get(vm); - e->class = hwe->class; - e->width = width; - e->logical_mask = logical_mask; - e->fence_irq = >->fence_irq[hwe->class]; - e->ring_ops = gt->ring_ops[hwe->class]; - e->ops = gt->engine_ops; - INIT_LIST_HEAD(&e->persistent.link); - INIT_LIST_HEAD(&e->compute.link); - INIT_LIST_HEAD(&e->multi_gt_link); - - /* FIXME: Wire up to configurable default value */ - e->sched_props.timeslice_us = 1 * 1000; - e->sched_props.preempt_timeout_us = 640 * 1000; - - if (xe_engine_is_parallel(e)) { - e->parallel.composite_fence_ctx = dma_fence_context_alloc(1); - e->parallel.composite_fence_seqno = XE_FENCE_INITIAL_SEQNO; - } - if (e->flags & ENGINE_FLAG_VM) { - e->bind.fence_ctx = dma_fence_context_alloc(1); - e->bind.fence_seqno = XE_FENCE_INITIAL_SEQNO; - } - - for (i = 0; i < width; ++i) { - err = xe_lrc_init(e->lrc + i, hwe, e, vm, SZ_16K); - if (err) - goto err_lrc; - } - - err = e->ops->init(e); - if (err) - goto err_lrc; - - /* - * Normally the user vm holds an rpm ref to keep the device - * awake, and the context holds a ref for the vm, however for - * some engines we use the kernels migrate vm underneath which - * offers no such rpm ref. Make sure we keep a ref here, so we - * can perform GuC CT actions when needed. Caller is expected to - * have already grabbed the rpm ref outside any sensitive locks. - */ - if (e->flags & ENGINE_FLAG_VM) - drm_WARN_ON(&xe->drm, !xe_device_mem_access_get_if_ongoing(xe)); - - return e; - -err_lrc: - for (i = i - 1; i >= 0; --i) - xe_lrc_finish(e->lrc + i); - kfree(e); - return ERR_PTR(err); -} - -struct xe_engine *xe_engine_create(struct xe_device *xe, struct xe_vm *vm, - u32 logical_mask, u16 width, - struct xe_hw_engine *hwe, u32 flags) -{ - struct ww_acquire_ctx ww; - struct xe_engine *e; - int err; - - if (vm) { - err = xe_vm_lock(vm, &ww, 0, true); - if (err) - return ERR_PTR(err); - } - e = __xe_engine_create(xe, vm, logical_mask, width, hwe, flags); - if (vm) - xe_vm_unlock(vm, &ww); - - return e; -} - -struct xe_engine *xe_engine_create_class(struct xe_device *xe, struct xe_gt *gt, - struct xe_vm *vm, - enum xe_engine_class class, u32 flags) -{ - struct xe_hw_engine *hwe, *hwe0 = NULL; - enum xe_hw_engine_id id; - u32 logical_mask = 0; - - for_each_hw_engine(hwe, gt, id) { - if (xe_hw_engine_is_reserved(hwe)) - continue; - - if (hwe->class == class) { - logical_mask |= BIT(hwe->logical_instance); - if (!hwe0) - hwe0 = hwe; - } - } - - if (!logical_mask) - return ERR_PTR(-ENODEV); - - return xe_engine_create(xe, vm, logical_mask, 1, hwe0, flags); -} - -void xe_engine_destroy(struct kref *ref) -{ - struct xe_engine *e = container_of(ref, struct xe_engine, refcount); - struct xe_engine *engine, *next; - - if (!(e->flags & ENGINE_FLAG_BIND_ENGINE_CHILD)) { - list_for_each_entry_safe(engine, next, &e->multi_gt_list, - multi_gt_link) - xe_engine_put(engine); - } - - e->ops->fini(e); -} - -void xe_engine_fini(struct xe_engine *e) -{ - int i; - - for (i = 0; i < e->width; ++i) - xe_lrc_finish(e->lrc + i); - if (e->vm) - xe_vm_put(e->vm); - if (e->flags & ENGINE_FLAG_VM) - xe_device_mem_access_put(gt_to_xe(e->gt)); - - kfree(e); -} - -struct xe_engine *xe_engine_lookup(struct xe_file *xef, u32 id) -{ - struct xe_engine *e; - - mutex_lock(&xef->engine.lock); - e = xa_load(&xef->engine.xa, id); - if (e) - xe_engine_get(e); - mutex_unlock(&xef->engine.lock); - - return e; -} - -enum drm_sched_priority -xe_engine_device_get_max_priority(struct xe_device *xe) -{ - return capable(CAP_SYS_NICE) ? DRM_SCHED_PRIORITY_HIGH : - DRM_SCHED_PRIORITY_NORMAL; -} - -static int engine_set_priority(struct xe_device *xe, struct xe_engine *e, - u64 value, bool create) -{ - if (XE_IOCTL_DBG(xe, value > DRM_SCHED_PRIORITY_HIGH)) - return -EINVAL; - - if (XE_IOCTL_DBG(xe, value > xe_engine_device_get_max_priority(xe))) - return -EPERM; - - return e->ops->set_priority(e, value); -} - -static int engine_set_timeslice(struct xe_device *xe, struct xe_engine *e, - u64 value, bool create) -{ - if (!capable(CAP_SYS_NICE)) - return -EPERM; - - return e->ops->set_timeslice(e, value); -} - -static int engine_set_preemption_timeout(struct xe_device *xe, - struct xe_engine *e, u64 value, - bool create) -{ - if (!capable(CAP_SYS_NICE)) - return -EPERM; - - return e->ops->set_preempt_timeout(e, value); -} - -static int engine_set_compute_mode(struct xe_device *xe, struct xe_engine *e, - u64 value, bool create) -{ - if (XE_IOCTL_DBG(xe, !create)) - return -EINVAL; - - if (XE_IOCTL_DBG(xe, e->flags & ENGINE_FLAG_COMPUTE_MODE)) - return -EINVAL; - - if (XE_IOCTL_DBG(xe, e->flags & ENGINE_FLAG_VM)) - return -EINVAL; - - if (value) { - struct xe_vm *vm = e->vm; - int err; - - if (XE_IOCTL_DBG(xe, xe_vm_in_fault_mode(vm))) - return -EOPNOTSUPP; - - if (XE_IOCTL_DBG(xe, !xe_vm_in_compute_mode(vm))) - return -EOPNOTSUPP; - - if (XE_IOCTL_DBG(xe, e->width != 1)) - return -EINVAL; - - e->compute.context = dma_fence_context_alloc(1); - spin_lock_init(&e->compute.lock); - - err = xe_vm_add_compute_engine(vm, e); - if (XE_IOCTL_DBG(xe, err)) - return err; - - e->flags |= ENGINE_FLAG_COMPUTE_MODE; - e->flags &= ~ENGINE_FLAG_PERSISTENT; - } - - return 0; -} - -static int engine_set_persistence(struct xe_device *xe, struct xe_engine *e, - u64 value, bool create) -{ - if (XE_IOCTL_DBG(xe, !create)) - return -EINVAL; - - if (XE_IOCTL_DBG(xe, e->flags & ENGINE_FLAG_COMPUTE_MODE)) - return -EINVAL; - - if (value) - e->flags |= ENGINE_FLAG_PERSISTENT; - else - e->flags &= ~ENGINE_FLAG_PERSISTENT; - - return 0; -} - -static int engine_set_job_timeout(struct xe_device *xe, struct xe_engine *e, - u64 value, bool create) -{ - if (XE_IOCTL_DBG(xe, !create)) - return -EINVAL; - - if (!capable(CAP_SYS_NICE)) - return -EPERM; - - return e->ops->set_job_timeout(e, value); -} - -static int engine_set_acc_trigger(struct xe_device *xe, struct xe_engine *e, - u64 value, bool create) -{ - if (XE_IOCTL_DBG(xe, !create)) - return -EINVAL; - - if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) - return -EINVAL; - - e->usm.acc_trigger = value; - - return 0; -} - -static int engine_set_acc_notify(struct xe_device *xe, struct xe_engine *e, - u64 value, bool create) -{ - if (XE_IOCTL_DBG(xe, !create)) - return -EINVAL; - - if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) - return -EINVAL; - - e->usm.acc_notify = value; - - return 0; -} - -static int engine_set_acc_granularity(struct xe_device *xe, struct xe_engine *e, - u64 value, bool create) -{ - if (XE_IOCTL_DBG(xe, !create)) - return -EINVAL; - - if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) - return -EINVAL; - - e->usm.acc_granularity = value; - - return 0; -} - -typedef int (*xe_engine_set_property_fn)(struct xe_device *xe, - struct xe_engine *e, - u64 value, bool create); - -static const xe_engine_set_property_fn engine_set_property_funcs[] = { - [XE_ENGINE_SET_PROPERTY_PRIORITY] = engine_set_priority, - [XE_ENGINE_SET_PROPERTY_TIMESLICE] = engine_set_timeslice, - [XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT] = engine_set_preemption_timeout, - [XE_ENGINE_SET_PROPERTY_COMPUTE_MODE] = engine_set_compute_mode, - [XE_ENGINE_SET_PROPERTY_PERSISTENCE] = engine_set_persistence, - [XE_ENGINE_SET_PROPERTY_JOB_TIMEOUT] = engine_set_job_timeout, - [XE_ENGINE_SET_PROPERTY_ACC_TRIGGER] = engine_set_acc_trigger, - [XE_ENGINE_SET_PROPERTY_ACC_NOTIFY] = engine_set_acc_notify, - [XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY] = engine_set_acc_granularity, -}; - -static int engine_user_ext_set_property(struct xe_device *xe, - struct xe_engine *e, - u64 extension, - bool create) -{ - u64 __user *address = u64_to_user_ptr(extension); - struct drm_xe_ext_engine_set_property ext; - int err; - u32 idx; - - err = __copy_from_user(&ext, address, sizeof(ext)); - if (XE_IOCTL_DBG(xe, err)) - return -EFAULT; - - if (XE_IOCTL_DBG(xe, ext.property >= - ARRAY_SIZE(engine_set_property_funcs)) || - XE_IOCTL_DBG(xe, ext.pad)) - return -EINVAL; - - idx = array_index_nospec(ext.property, ARRAY_SIZE(engine_set_property_funcs)); - return engine_set_property_funcs[idx](xe, e, ext.value, create); -} - -typedef int (*xe_engine_user_extension_fn)(struct xe_device *xe, - struct xe_engine *e, - u64 extension, - bool create); - -static const xe_engine_set_property_fn engine_user_extension_funcs[] = { - [XE_ENGINE_EXTENSION_SET_PROPERTY] = engine_user_ext_set_property, -}; - -#define MAX_USER_EXTENSIONS 16 -static int engine_user_extensions(struct xe_device *xe, struct xe_engine *e, - u64 extensions, int ext_number, bool create) -{ - u64 __user *address = u64_to_user_ptr(extensions); - struct xe_user_extension ext; - int err; - u32 idx; - - if (XE_IOCTL_DBG(xe, ext_number >= MAX_USER_EXTENSIONS)) - return -E2BIG; - - err = __copy_from_user(&ext, address, sizeof(ext)); - if (XE_IOCTL_DBG(xe, err)) - return -EFAULT; - - if (XE_IOCTL_DBG(xe, ext.pad) || - XE_IOCTL_DBG(xe, ext.name >= - ARRAY_SIZE(engine_user_extension_funcs))) - return -EINVAL; - - idx = array_index_nospec(ext.name, - ARRAY_SIZE(engine_user_extension_funcs)); - err = engine_user_extension_funcs[idx](xe, e, extensions, create); - if (XE_IOCTL_DBG(xe, err)) - return err; - - if (ext.next_extension) - return engine_user_extensions(xe, e, ext.next_extension, - ++ext_number, create); - - return 0; -} - -static const enum xe_engine_class user_to_xe_engine_class[] = { - [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, - [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, - [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, - [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, - [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, -}; - -static struct xe_hw_engine * -find_hw_engine(struct xe_device *xe, - struct drm_xe_engine_class_instance eci) -{ - u32 idx; - - if (eci.engine_class > ARRAY_SIZE(user_to_xe_engine_class)) - return NULL; - - if (eci.gt_id >= xe->info.gt_count) - return NULL; - - idx = array_index_nospec(eci.engine_class, - ARRAY_SIZE(user_to_xe_engine_class)); - - return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id), - user_to_xe_engine_class[idx], - eci.engine_instance, true); -} - -static u32 bind_engine_logical_mask(struct xe_device *xe, struct xe_gt *gt, - struct drm_xe_engine_class_instance *eci, - u16 width, u16 num_placements) -{ - struct xe_hw_engine *hwe; - enum xe_hw_engine_id id; - u32 logical_mask = 0; - - if (XE_IOCTL_DBG(xe, width != 1)) - return 0; - if (XE_IOCTL_DBG(xe, num_placements != 1)) - return 0; - if (XE_IOCTL_DBG(xe, eci[0].engine_instance != 0)) - return 0; - - eci[0].engine_class = DRM_XE_ENGINE_CLASS_COPY; - - for_each_hw_engine(hwe, gt, id) { - if (xe_hw_engine_is_reserved(hwe)) - continue; - - if (hwe->class == - user_to_xe_engine_class[DRM_XE_ENGINE_CLASS_COPY]) - logical_mask |= BIT(hwe->logical_instance); - } - - return logical_mask; -} - -static u32 calc_validate_logical_mask(struct xe_device *xe, struct xe_gt *gt, - struct drm_xe_engine_class_instance *eci, - u16 width, u16 num_placements) -{ - int len = width * num_placements; - int i, j, n; - u16 class; - u16 gt_id; - u32 return_mask = 0, prev_mask; - - if (XE_IOCTL_DBG(xe, !xe_device_guc_submission_enabled(xe) && - len > 1)) - return 0; - - for (i = 0; i < width; ++i) { - u32 current_mask = 0; - - for (j = 0; j < num_placements; ++j) { - struct xe_hw_engine *hwe; - - n = j * width + i; - - hwe = find_hw_engine(xe, eci[n]); - if (XE_IOCTL_DBG(xe, !hwe)) - return 0; - - if (XE_IOCTL_DBG(xe, xe_hw_engine_is_reserved(hwe))) - return 0; - - if (XE_IOCTL_DBG(xe, n && eci[n].gt_id != gt_id) || - XE_IOCTL_DBG(xe, n && eci[n].engine_class != class)) - return 0; - - class = eci[n].engine_class; - gt_id = eci[n].gt_id; - - if (width == 1 || !i) - return_mask |= BIT(eci[n].engine_instance); - current_mask |= BIT(eci[n].engine_instance); - } - - /* Parallel submissions must be logically contiguous */ - if (i && XE_IOCTL_DBG(xe, current_mask != prev_mask << 1)) - return 0; - - prev_mask = current_mask; - } - - return return_mask; -} - -int xe_engine_create_ioctl(struct drm_device *dev, void *data, - struct drm_file *file) -{ - struct xe_device *xe = to_xe_device(dev); - struct xe_file *xef = to_xe_file(file); - struct drm_xe_engine_create *args = data; - struct drm_xe_engine_class_instance eci[XE_HW_ENGINE_MAX_INSTANCE]; - struct drm_xe_engine_class_instance __user *user_eci = - u64_to_user_ptr(args->instances); - struct xe_hw_engine *hwe; - struct xe_vm *vm, *migrate_vm; - struct xe_gt *gt; - struct xe_engine *e = NULL; - u32 logical_mask; - u32 id; - u32 len; - int err; - - if (XE_IOCTL_DBG(xe, args->flags) || - XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) - return -EINVAL; - - len = args->width * args->num_placements; - if (XE_IOCTL_DBG(xe, !len || len > XE_HW_ENGINE_MAX_INSTANCE)) - return -EINVAL; - - err = __copy_from_user(eci, user_eci, - sizeof(struct drm_xe_engine_class_instance) * - len); - if (XE_IOCTL_DBG(xe, err)) - return -EFAULT; - - if (XE_IOCTL_DBG(xe, eci[0].gt_id >= xe->info.gt_count)) - return -EINVAL; - - if (eci[0].engine_class == DRM_XE_ENGINE_CLASS_VM_BIND) { - for_each_gt(gt, xe, id) { - struct xe_engine *new; - - if (xe_gt_is_media_type(gt)) - continue; - - eci[0].gt_id = gt->info.id; - logical_mask = bind_engine_logical_mask(xe, gt, eci, - args->width, - args->num_placements); - if (XE_IOCTL_DBG(xe, !logical_mask)) - return -EINVAL; - - hwe = find_hw_engine(xe, eci[0]); - if (XE_IOCTL_DBG(xe, !hwe)) - return -EINVAL; - - /* The migration vm doesn't hold rpm ref */ - xe_device_mem_access_get(xe); - - migrate_vm = xe_migrate_get_vm(gt_to_tile(gt)->migrate); - new = xe_engine_create(xe, migrate_vm, logical_mask, - args->width, hwe, - ENGINE_FLAG_PERSISTENT | - ENGINE_FLAG_VM | - (id ? - ENGINE_FLAG_BIND_ENGINE_CHILD : - 0)); - - xe_device_mem_access_put(xe); /* now held by engine */ - - xe_vm_put(migrate_vm); - if (IS_ERR(new)) { - err = PTR_ERR(new); - if (e) - goto put_engine; - return err; - } - if (id == 0) - e = new; - else - list_add_tail(&new->multi_gt_list, - &e->multi_gt_link); - } - } else { - gt = xe_device_get_gt(xe, eci[0].gt_id); - logical_mask = calc_validate_logical_mask(xe, gt, eci, - args->width, - args->num_placements); - if (XE_IOCTL_DBG(xe, !logical_mask)) - return -EINVAL; - - hwe = find_hw_engine(xe, eci[0]); - if (XE_IOCTL_DBG(xe, !hwe)) - return -EINVAL; - - vm = xe_vm_lookup(xef, args->vm_id); - if (XE_IOCTL_DBG(xe, !vm)) - return -ENOENT; - - err = down_read_interruptible(&vm->lock); - if (err) { - xe_vm_put(vm); - return err; - } - - if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) { - up_read(&vm->lock); - xe_vm_put(vm); - return -ENOENT; - } - - e = xe_engine_create(xe, vm, logical_mask, - args->width, hwe, - xe_vm_no_dma_fences(vm) ? 0 : - ENGINE_FLAG_PERSISTENT); - up_read(&vm->lock); - xe_vm_put(vm); - if (IS_ERR(e)) - return PTR_ERR(e); - } - - if (args->extensions) { - err = engine_user_extensions(xe, e, args->extensions, 0, true); - if (XE_IOCTL_DBG(xe, err)) - goto put_engine; - } - - if (XE_IOCTL_DBG(xe, e->vm && xe_vm_in_compute_mode(e->vm) != - !!(e->flags & ENGINE_FLAG_COMPUTE_MODE))) { - err = -EOPNOTSUPP; - goto put_engine; - } - - e->persistent.xef = xef; - - mutex_lock(&xef->engine.lock); - err = xa_alloc(&xef->engine.xa, &id, e, xa_limit_32b, GFP_KERNEL); - mutex_unlock(&xef->engine.lock); - if (err) - goto put_engine; - - args->engine_id = id; - - return 0; - -put_engine: - xe_engine_kill(e); - xe_engine_put(e); - return err; -} - -int xe_engine_get_property_ioctl(struct drm_device *dev, void *data, - struct drm_file *file) -{ - struct xe_device *xe = to_xe_device(dev); - struct xe_file *xef = to_xe_file(file); - struct drm_xe_engine_get_property *args = data; - struct xe_engine *e; - int ret; - - if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) - return -EINVAL; - - e = xe_engine_lookup(xef, args->engine_id); - if (XE_IOCTL_DBG(xe, !e)) - return -ENOENT; - - switch (args->property) { - case XE_ENGINE_GET_PROPERTY_BAN: - args->value = !!(e->flags & ENGINE_FLAG_BANNED); - ret = 0; - break; - default: - ret = -EINVAL; - } - - xe_engine_put(e); - - return ret; -} - -static void engine_kill_compute(struct xe_engine *e) -{ - if (!xe_vm_in_compute_mode(e->vm)) - return; - - down_write(&e->vm->lock); - list_del(&e->compute.link); - --e->vm->preempt.num_engines; - if (e->compute.pfence) { - dma_fence_enable_sw_signaling(e->compute.pfence); - dma_fence_put(e->compute.pfence); - e->compute.pfence = NULL; - } - up_write(&e->vm->lock); -} - -/** - * xe_engine_is_lr() - Whether an engine is long-running - * @e: The engine - * - * Return: True if the engine is long-running, false otherwise. - */ -bool xe_engine_is_lr(struct xe_engine *e) -{ - return e->vm && xe_vm_no_dma_fences(e->vm) && - !(e->flags & ENGINE_FLAG_VM); -} - -static s32 xe_engine_num_job_inflight(struct xe_engine *e) -{ - return e->lrc->fence_ctx.next_seqno - xe_lrc_seqno(e->lrc) - 1; -} - -/** - * xe_engine_ring_full() - Whether an engine's ring is full - * @e: The engine - * - * Return: True if the engine's ring is full, false otherwise. - */ -bool xe_engine_ring_full(struct xe_engine *e) -{ - struct xe_lrc *lrc = e->lrc; - s32 max_job = lrc->ring.size / MAX_JOB_SIZE_BYTES; - - return xe_engine_num_job_inflight(e) >= max_job; -} - -/** - * xe_engine_is_idle() - Whether an engine is idle. - * @engine: The engine - * - * FIXME: Need to determine what to use as the short-lived - * timeline lock for the engines, so that the return value - * of this function becomes more than just an advisory - * snapshot in time. The timeline lock must protect the - * seqno from racing submissions on the same engine. - * Typically vm->resv, but user-created timeline locks use the migrate vm - * and never grabs the migrate vm->resv so we have a race there. - * - * Return: True if the engine is idle, false otherwise. - */ -bool xe_engine_is_idle(struct xe_engine *engine) -{ - if (XE_WARN_ON(xe_engine_is_parallel(engine))) - return false; - - return xe_lrc_seqno(&engine->lrc[0]) == - engine->lrc[0].fence_ctx.next_seqno - 1; -} - -void xe_engine_kill(struct xe_engine *e) -{ - struct xe_engine *engine = e, *next; - - list_for_each_entry_safe(engine, next, &engine->multi_gt_list, - multi_gt_link) { - e->ops->kill(engine); - engine_kill_compute(engine); - } - - e->ops->kill(e); - engine_kill_compute(e); -} - -int xe_engine_destroy_ioctl(struct drm_device *dev, void *data, - struct drm_file *file) -{ - struct xe_device *xe = to_xe_device(dev); - struct xe_file *xef = to_xe_file(file); - struct drm_xe_engine_destroy *args = data; - struct xe_engine *e; - - if (XE_IOCTL_DBG(xe, args->pad) || - XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) - return -EINVAL; - - mutex_lock(&xef->engine.lock); - e = xa_erase(&xef->engine.xa, args->engine_id); - mutex_unlock(&xef->engine.lock); - if (XE_IOCTL_DBG(xe, !e)) - return -ENOENT; - - if (!(e->flags & ENGINE_FLAG_PERSISTENT)) - xe_engine_kill(e); - else - xe_device_add_persistent_engines(xe, e); - - trace_xe_engine_close(e); - xe_engine_put(e); - - return 0; -} - -int xe_engine_set_property_ioctl(struct drm_device *dev, void *data, - struct drm_file *file) -{ - struct xe_device *xe = to_xe_device(dev); - struct xe_file *xef = to_xe_file(file); - struct drm_xe_engine_set_property *args = data; - struct xe_engine *e; - int ret; - u32 idx; - - if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) - return -EINVAL; - - e = xe_engine_lookup(xef, args->engine_id); - if (XE_IOCTL_DBG(xe, !e)) - return -ENOENT; - - if (XE_IOCTL_DBG(xe, args->property >= - ARRAY_SIZE(engine_set_property_funcs))) { - ret = -EINVAL; - goto out; - } - - idx = array_index_nospec(args->property, - ARRAY_SIZE(engine_set_property_funcs)); - ret = engine_set_property_funcs[idx](xe, e, args->value, false); - if (XE_IOCTL_DBG(xe, ret)) - goto out; - - if (args->extensions) - ret = engine_user_extensions(xe, e, args->extensions, 0, - false); -out: - xe_engine_put(e); - - return ret; -} diff --git a/drivers/gpu/drm/xe/xe_engine.h b/drivers/gpu/drm/xe/xe_engine.h deleted file mode 100644 index 2e60f6d90226..000000000000 --- a/drivers/gpu/drm/xe/xe_engine.h +++ /dev/null @@ -1,63 +0,0 @@ -/* SPDX-License-Identifier: MIT */ -/* - * Copyright © 2021 Intel Corporation - */ - -#ifndef _XE_ENGINE_H_ -#define _XE_ENGINE_H_ - -#include "xe_engine_types.h" -#include "xe_vm_types.h" - -struct drm_device; -struct drm_file; -struct xe_device; -struct xe_file; - -struct xe_engine *xe_engine_create(struct xe_device *xe, struct xe_vm *vm, - u32 logical_mask, u16 width, - struct xe_hw_engine *hw_engine, u32 flags); -struct xe_engine *xe_engine_create_class(struct xe_device *xe, struct xe_gt *gt, - struct xe_vm *vm, - enum xe_engine_class class, u32 flags); - -void xe_engine_fini(struct xe_engine *e); -void xe_engine_destroy(struct kref *ref); - -struct xe_engine *xe_engine_lookup(struct xe_file *xef, u32 id); - -static inline struct xe_engine *xe_engine_get(struct xe_engine *engine) -{ - kref_get(&engine->refcount); - return engine; -} - -static inline void xe_engine_put(struct xe_engine *engine) -{ - kref_put(&engine->refcount, xe_engine_destroy); -} - -static inline bool xe_engine_is_parallel(struct xe_engine *engine) -{ - return engine->width > 1; -} - -bool xe_engine_is_lr(struct xe_engine *e); - -bool xe_engine_ring_full(struct xe_engine *e); - -bool xe_engine_is_idle(struct xe_engine *engine); - -void xe_engine_kill(struct xe_engine *e); - -int xe_engine_create_ioctl(struct drm_device *dev, void *data, - struct drm_file *file); -int xe_engine_destroy_ioctl(struct drm_device *dev, void *data, - struct drm_file *file); -int xe_engine_set_property_ioctl(struct drm_device *dev, void *data, - struct drm_file *file); -int xe_engine_get_property_ioctl(struct drm_device *dev, void *data, - struct drm_file *file); -enum drm_sched_priority xe_engine_device_get_max_priority(struct xe_device *xe); - -#endif diff --git a/drivers/gpu/drm/xe/xe_exec.c b/drivers/gpu/drm/xe/xe_exec.c index fff4a9d9d12a..8a5b614df090 100644 --- a/drivers/gpu/drm/xe/xe_exec.c +++ b/drivers/gpu/drm/xe/xe_exec.c @@ -12,7 +12,7 @@ #include "xe_bo.h" #include "xe_device.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_macros.h" #include "xe_ring_ops_types.h" #include "xe_sched_job.h" @@ -95,19 +95,19 @@ #define XE_EXEC_BIND_RETRY_TIMEOUT_MS 1000 -static int xe_exec_begin(struct xe_engine *e, struct ww_acquire_ctx *ww, +static int xe_exec_begin(struct xe_exec_queue *q, struct ww_acquire_ctx *ww, struct ttm_validate_buffer tv_onstack[], struct ttm_validate_buffer **tv, struct list_head *objs) { - struct xe_vm *vm = e->vm; + struct xe_vm *vm = q->vm; struct xe_vma *vma; LIST_HEAD(dups); ktime_t end = 0; int err = 0; *tv = NULL; - if (xe_vm_no_dma_fences(e->vm)) + if (xe_vm_no_dma_fences(q->vm)) return 0; retry: @@ -153,14 +153,14 @@ static int xe_exec_begin(struct xe_engine *e, struct ww_acquire_ctx *ww, return err; } -static void xe_exec_end(struct xe_engine *e, +static void xe_exec_end(struct xe_exec_queue *q, struct ttm_validate_buffer *tv_onstack, struct ttm_validate_buffer *tv, struct ww_acquire_ctx *ww, struct list_head *objs) { - if (!xe_vm_no_dma_fences(e->vm)) - xe_vm_unlock_dma_resv(e->vm, tv_onstack, tv, ww, objs); + if (!xe_vm_no_dma_fences(q->vm)) + xe_vm_unlock_dma_resv(q->vm, tv_onstack, tv, ww, objs); } int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) @@ -170,7 +170,7 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) struct drm_xe_exec *args = data; struct drm_xe_sync __user *syncs_user = u64_to_user_ptr(args->syncs); u64 __user *addresses_user = u64_to_user_ptr(args->address); - struct xe_engine *engine; + struct xe_exec_queue *q; struct xe_sync_entry *syncs = NULL; u64 addresses[XE_HW_ENGINE_MAX_INSTANCE]; struct ttm_validate_buffer tv_onstack[XE_ONSTACK_TV]; @@ -189,30 +189,30 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) return -EINVAL; - engine = xe_engine_lookup(xef, args->engine_id); - if (XE_IOCTL_DBG(xe, !engine)) + q = xe_exec_queue_lookup(xef, args->exec_queue_id); + if (XE_IOCTL_DBG(xe, !q)) return -ENOENT; - if (XE_IOCTL_DBG(xe, engine->flags & ENGINE_FLAG_VM)) + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_VM)) return -EINVAL; - if (XE_IOCTL_DBG(xe, engine->width != args->num_batch_buffer)) + if (XE_IOCTL_DBG(xe, q->width != args->num_batch_buffer)) return -EINVAL; - if (XE_IOCTL_DBG(xe, engine->flags & ENGINE_FLAG_BANNED)) { + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_BANNED)) { err = -ECANCELED; - goto err_engine; + goto err_exec_queue; } if (args->num_syncs) { syncs = kcalloc(args->num_syncs, sizeof(*syncs), GFP_KERNEL); if (!syncs) { err = -ENOMEM; - goto err_engine; + goto err_exec_queue; } } - vm = engine->vm; + vm = q->vm; for (i = 0; i < args->num_syncs; i++) { err = xe_sync_entry_parse(xe, xef, &syncs[num_syncs++], @@ -222,9 +222,9 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) goto err_syncs; } - if (xe_engine_is_parallel(engine)) { + if (xe_exec_queue_is_parallel(q)) { err = __copy_from_user(addresses, addresses_user, sizeof(u64) * - engine->width); + q->width); if (err) { err = -EFAULT; goto err_syncs; @@ -294,26 +294,26 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) goto err_unlock_list; } - err = xe_exec_begin(engine, &ww, tv_onstack, &tv, &objs); + err = xe_exec_begin(q, &ww, tv_onstack, &tv, &objs); if (err) goto err_unlock_list; - if (xe_vm_is_closed_or_banned(engine->vm)) { + if (xe_vm_is_closed_or_banned(q->vm)) { drm_warn(&xe->drm, "Trying to schedule after vm is closed or banned\n"); err = -ECANCELED; - goto err_engine_end; + goto err_exec_queue_end; } - if (xe_engine_is_lr(engine) && xe_engine_ring_full(engine)) { + if (xe_exec_queue_is_lr(q) && xe_exec_queue_ring_full(q)) { err = -EWOULDBLOCK; - goto err_engine_end; + goto err_exec_queue_end; } - job = xe_sched_job_create(engine, xe_engine_is_parallel(engine) ? + job = xe_sched_job_create(q, xe_exec_queue_is_parallel(q) ? addresses : &args->address); if (IS_ERR(job)) { err = PTR_ERR(job); - goto err_engine_end; + goto err_exec_queue_end; } /* @@ -395,8 +395,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) xe_sync_entry_signal(&syncs[i], job, &job->drm.s_fence->finished); - if (xe_engine_is_lr(engine)) - engine->ring_ops->emit_job(job); + if (xe_exec_queue_is_lr(q)) + q->ring_ops->emit_job(job); xe_sched_job_push(job); xe_vm_reactivate_rebind(vm); @@ -412,8 +412,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) err_put_job: if (err) xe_sched_job_put(job); -err_engine_end: - xe_exec_end(engine, tv_onstack, tv, &ww, &objs); +err_exec_queue_end: + xe_exec_end(q, tv_onstack, tv, &ww, &objs); err_unlock_list: if (write_locked) up_write(&vm->lock); @@ -425,8 +425,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) for (i = 0; i < num_syncs; i++) xe_sync_entry_cleanup(&syncs[i]); kfree(syncs); -err_engine: - xe_engine_put(engine); +err_exec_queue: + xe_exec_queue_put(q); return err; } diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c new file mode 100644 index 000000000000..49cff0dd2bc7 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_exec_queue.c @@ -0,0 +1,850 @@ +// SPDX-License-Identifier: MIT +/* + * Copyright © 2021 Intel Corporation + */ + +#include "xe_exec_queue.h" + +#include <linux/nospec.h> + +#include <drm/drm_device.h> +#include <drm/drm_file.h> +#include <drm/xe_drm.h> + +#include "xe_device.h" +#include "xe_gt.h" +#include "xe_hw_fence.h" +#include "xe_lrc.h" +#include "xe_macros.h" +#include "xe_migrate.h" +#include "xe_pm.h" +#include "xe_ring_ops_types.h" +#include "xe_trace.h" +#include "xe_vm.h" + +static struct xe_exec_queue *__xe_exec_queue_create(struct xe_device *xe, + struct xe_vm *vm, + u32 logical_mask, + u16 width, struct xe_hw_engine *hwe, + u32 flags) +{ + struct xe_exec_queue *q; + struct xe_gt *gt = hwe->gt; + int err; + int i; + + q = kzalloc(sizeof(*q) + sizeof(struct xe_lrc) * width, GFP_KERNEL); + if (!q) + return ERR_PTR(-ENOMEM); + + kref_init(&q->refcount); + q->flags = flags; + q->hwe = hwe; + q->gt = gt; + if (vm) + q->vm = xe_vm_get(vm); + q->class = hwe->class; + q->width = width; + q->logical_mask = logical_mask; + q->fence_irq = >->fence_irq[hwe->class]; + q->ring_ops = gt->ring_ops[hwe->class]; + q->ops = gt->exec_queue_ops; + INIT_LIST_HEAD(&q->persistent.link); + INIT_LIST_HEAD(&q->compute.link); + INIT_LIST_HEAD(&q->multi_gt_link); + + /* FIXME: Wire up to configurable default value */ + q->sched_props.timeslice_us = 1 * 1000; + q->sched_props.preempt_timeout_us = 640 * 1000; + + if (xe_exec_queue_is_parallel(q)) { + q->parallel.composite_fence_ctx = dma_fence_context_alloc(1); + q->parallel.composite_fence_seqno = XE_FENCE_INITIAL_SEQNO; + } + if (q->flags & EXEC_QUEUE_FLAG_VM) { + q->bind.fence_ctx = dma_fence_context_alloc(1); + q->bind.fence_seqno = XE_FENCE_INITIAL_SEQNO; + } + + for (i = 0; i < width; ++i) { + err = xe_lrc_init(q->lrc + i, hwe, q, vm, SZ_16K); + if (err) + goto err_lrc; + } + + err = q->ops->init(q); + if (err) + goto err_lrc; + + /* + * Normally the user vm holds an rpm ref to keep the device + * awake, and the context holds a ref for the vm, however for + * some engines we use the kernels migrate vm underneath which + * offers no such rpm ref. Make sure we keep a ref here, so we + * can perform GuC CT actions when needed. Caller is expected to + * have already grabbed the rpm ref outside any sensitive locks. + */ + if (q->flags & EXEC_QUEUE_FLAG_VM) + drm_WARN_ON(&xe->drm, !xe_device_mem_access_get_if_ongoing(xe)); + + return q; + +err_lrc: + for (i = i - 1; i >= 0; --i) + xe_lrc_finish(q->lrc + i); + kfree(q); + return ERR_PTR(err); +} + +struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm, + u32 logical_mask, u16 width, + struct xe_hw_engine *hwe, u32 flags) +{ + struct ww_acquire_ctx ww; + struct xe_exec_queue *q; + int err; + + if (vm) { + err = xe_vm_lock(vm, &ww, 0, true); + if (err) + return ERR_PTR(err); + } + q = __xe_exec_queue_create(xe, vm, logical_mask, width, hwe, flags); + if (vm) + xe_vm_unlock(vm, &ww); + + return q; +} + +struct xe_exec_queue *xe_exec_queue_create_class(struct xe_device *xe, struct xe_gt *gt, + struct xe_vm *vm, + enum xe_engine_class class, u32 flags) +{ + struct xe_hw_engine *hwe, *hwe0 = NULL; + enum xe_hw_engine_id id; + u32 logical_mask = 0; + + for_each_hw_engine(hwe, gt, id) { + if (xe_hw_engine_is_reserved(hwe)) + continue; + + if (hwe->class == class) { + logical_mask |= BIT(hwe->logical_instance); + if (!hwe0) + hwe0 = hwe; + } + } + + if (!logical_mask) + return ERR_PTR(-ENODEV); + + return xe_exec_queue_create(xe, vm, logical_mask, 1, hwe0, flags); +} + +void xe_exec_queue_destroy(struct kref *ref) +{ + struct xe_exec_queue *q = container_of(ref, struct xe_exec_queue, refcount); + struct xe_exec_queue *eq, *next; + + if (!(q->flags & EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD)) { + list_for_each_entry_safe(eq, next, &q->multi_gt_list, + multi_gt_link) + xe_exec_queue_put(eq); + } + + q->ops->fini(q); +} + +void xe_exec_queue_fini(struct xe_exec_queue *q) +{ + int i; + + for (i = 0; i < q->width; ++i) + xe_lrc_finish(q->lrc + i); + if (q->vm) + xe_vm_put(q->vm); + if (q->flags & EXEC_QUEUE_FLAG_VM) + xe_device_mem_access_put(gt_to_xe(q->gt)); + + kfree(q); +} + +struct xe_exec_queue *xe_exec_queue_lookup(struct xe_file *xef, u32 id) +{ + struct xe_exec_queue *q; + + mutex_lock(&xef->exec_queue.lock); + q = xa_load(&xef->exec_queue.xa, id); + if (q) + xe_exec_queue_get(q); + mutex_unlock(&xef->exec_queue.lock); + + return q; +} + +enum drm_sched_priority +xe_exec_queue_device_get_max_priority(struct xe_device *xe) +{ + return capable(CAP_SYS_NICE) ? DRM_SCHED_PRIORITY_HIGH : + DRM_SCHED_PRIORITY_NORMAL; +} + +static int exec_queue_set_priority(struct xe_device *xe, struct xe_exec_queue *q, + u64 value, bool create) +{ + if (XE_IOCTL_DBG(xe, value > DRM_SCHED_PRIORITY_HIGH)) + return -EINVAL; + + if (XE_IOCTL_DBG(xe, value > xe_exec_queue_device_get_max_priority(xe))) + return -EPERM; + + return q->ops->set_priority(q, value); +} + +static int exec_queue_set_timeslice(struct xe_device *xe, struct xe_exec_queue *q, + u64 value, bool create) +{ + if (!capable(CAP_SYS_NICE)) + return -EPERM; + + return q->ops->set_timeslice(q, value); +} + +static int exec_queue_set_preemption_timeout(struct xe_device *xe, + struct xe_exec_queue *q, u64 value, + bool create) +{ + if (!capable(CAP_SYS_NICE)) + return -EPERM; + + return q->ops->set_preempt_timeout(q, value); +} + +static int exec_queue_set_compute_mode(struct xe_device *xe, struct xe_exec_queue *q, + u64 value, bool create) +{ + if (XE_IOCTL_DBG(xe, !create)) + return -EINVAL; + + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_COMPUTE_MODE)) + return -EINVAL; + + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_VM)) + return -EINVAL; + + if (value) { + struct xe_vm *vm = q->vm; + int err; + + if (XE_IOCTL_DBG(xe, xe_vm_in_fault_mode(vm))) + return -EOPNOTSUPP; + + if (XE_IOCTL_DBG(xe, !xe_vm_in_compute_mode(vm))) + return -EOPNOTSUPP; + + if (XE_IOCTL_DBG(xe, q->width != 1)) + return -EINVAL; + + q->compute.context = dma_fence_context_alloc(1); + spin_lock_init(&q->compute.lock); + + err = xe_vm_add_compute_exec_queue(vm, q); + if (XE_IOCTL_DBG(xe, err)) + return err; + + q->flags |= EXEC_QUEUE_FLAG_COMPUTE_MODE; + q->flags &= ~EXEC_QUEUE_FLAG_PERSISTENT; + } + + return 0; +} + +static int exec_queue_set_persistence(struct xe_device *xe, struct xe_exec_queue *q, + u64 value, bool create) +{ + if (XE_IOCTL_DBG(xe, !create)) + return -EINVAL; + + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_COMPUTE_MODE)) + return -EINVAL; + + if (value) + q->flags |= EXEC_QUEUE_FLAG_PERSISTENT; + else + q->flags &= ~EXEC_QUEUE_FLAG_PERSISTENT; + + return 0; +} + +static int exec_queue_set_job_timeout(struct xe_device *xe, struct xe_exec_queue *q, + u64 value, bool create) +{ + if (XE_IOCTL_DBG(xe, !create)) + return -EINVAL; + + if (!capable(CAP_SYS_NICE)) + return -EPERM; + + return q->ops->set_job_timeout(q, value); +} + +static int exec_queue_set_acc_trigger(struct xe_device *xe, struct xe_exec_queue *q, + u64 value, bool create) +{ + if (XE_IOCTL_DBG(xe, !create)) + return -EINVAL; + + if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) + return -EINVAL; + + q->usm.acc_trigger = value; + + return 0; +} + +static int exec_queue_set_acc_notify(struct xe_device *xe, struct xe_exec_queue *q, + u64 value, bool create) +{ + if (XE_IOCTL_DBG(xe, !create)) + return -EINVAL; + + if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) + return -EINVAL; + + q->usm.acc_notify = value; + + return 0; +} + +static int exec_queue_set_acc_granularity(struct xe_device *xe, struct xe_exec_queue *q, + u64 value, bool create) +{ + if (XE_IOCTL_DBG(xe, !create)) + return -EINVAL; + + if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) + return -EINVAL; + + q->usm.acc_granularity = value; + + return 0; +} + +typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe, + struct xe_exec_queue *q, + u64 value, bool create); + +static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = { + [XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY] = exec_queue_set_priority, + [XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice, + [XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT] = exec_queue_set_preemption_timeout, + [XE_EXEC_QUEUE_SET_PROPERTY_COMPUTE_MODE] = exec_queue_set_compute_mode, + [XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE] = exec_queue_set_persistence, + [XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT] = exec_queue_set_job_timeout, + [XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER] = exec_queue_set_acc_trigger, + [XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY] = exec_queue_set_acc_notify, + [XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY] = exec_queue_set_acc_granularity, +}; + +static int exec_queue_user_ext_set_property(struct xe_device *xe, + struct xe_exec_queue *q, + u64 extension, + bool create) +{ + u64 __user *address = u64_to_user_ptr(extension); + struct drm_xe_ext_exec_queue_set_property ext; + int err; + u32 idx; + + err = __copy_from_user(&ext, address, sizeof(ext)); + if (XE_IOCTL_DBG(xe, err)) + return -EFAULT; + + if (XE_IOCTL_DBG(xe, ext.property >= + ARRAY_SIZE(exec_queue_set_property_funcs)) || + XE_IOCTL_DBG(xe, ext.pad)) + return -EINVAL; + + idx = array_index_nospec(ext.property, ARRAY_SIZE(exec_queue_set_property_funcs)); + return exec_queue_set_property_funcs[idx](xe, q, ext.value, create); +} + +typedef int (*xe_exec_queue_user_extension_fn)(struct xe_device *xe, + struct xe_exec_queue *q, + u64 extension, + bool create); + +static const xe_exec_queue_set_property_fn exec_queue_user_extension_funcs[] = { + [XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY] = exec_queue_user_ext_set_property, +}; + +#define MAX_USER_EXTENSIONS 16 +static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q, + u64 extensions, int ext_number, bool create) +{ + u64 __user *address = u64_to_user_ptr(extensions); + struct xe_user_extension ext; + int err; + u32 idx; + + if (XE_IOCTL_DBG(xe, ext_number >= MAX_USER_EXTENSIONS)) + return -E2BIG; + + err = __copy_from_user(&ext, address, sizeof(ext)); + if (XE_IOCTL_DBG(xe, err)) + return -EFAULT; + + if (XE_IOCTL_DBG(xe, ext.pad) || + XE_IOCTL_DBG(xe, ext.name >= + ARRAY_SIZE(exec_queue_user_extension_funcs))) + return -EINVAL; + + idx = array_index_nospec(ext.name, + ARRAY_SIZE(exec_queue_user_extension_funcs)); + err = exec_queue_user_extension_funcs[idx](xe, q, extensions, create); + if (XE_IOCTL_DBG(xe, err)) + return err; + + if (ext.next_extension) + return exec_queue_user_extensions(xe, q, ext.next_extension, + ++ext_number, create); + + return 0; +} + +static const enum xe_engine_class user_to_xe_engine_class[] = { + [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, + [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, + [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, + [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, + [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, +}; + +static struct xe_hw_engine * +find_hw_engine(struct xe_device *xe, + struct drm_xe_engine_class_instance eci) +{ + u32 idx; + + if (eci.engine_class > ARRAY_SIZE(user_to_xe_engine_class)) + return NULL; + + if (eci.gt_id >= xe->info.gt_count) + return NULL; + + idx = array_index_nospec(eci.engine_class, + ARRAY_SIZE(user_to_xe_engine_class)); + + return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id), + user_to_xe_engine_class[idx], + eci.engine_instance, true); +} + +static u32 bind_exec_queue_logical_mask(struct xe_device *xe, struct xe_gt *gt, + struct drm_xe_engine_class_instance *eci, + u16 width, u16 num_placements) +{ + struct xe_hw_engine *hwe; + enum xe_hw_engine_id id; + u32 logical_mask = 0; + + if (XE_IOCTL_DBG(xe, width != 1)) + return 0; + if (XE_IOCTL_DBG(xe, num_placements != 1)) + return 0; + if (XE_IOCTL_DBG(xe, eci[0].engine_instance != 0)) + return 0; + + eci[0].engine_class = DRM_XE_ENGINE_CLASS_COPY; + + for_each_hw_engine(hwe, gt, id) { + if (xe_hw_engine_is_reserved(hwe)) + continue; + + if (hwe->class == + user_to_xe_engine_class[DRM_XE_ENGINE_CLASS_COPY]) + logical_mask |= BIT(hwe->logical_instance); + } + + return logical_mask; +} + +static u32 calc_validate_logical_mask(struct xe_device *xe, struct xe_gt *gt, + struct drm_xe_engine_class_instance *eci, + u16 width, u16 num_placements) +{ + int len = width * num_placements; + int i, j, n; + u16 class; + u16 gt_id; + u32 return_mask = 0, prev_mask; + + if (XE_IOCTL_DBG(xe, !xe_device_guc_submission_enabled(xe) && + len > 1)) + return 0; + + for (i = 0; i < width; ++i) { + u32 current_mask = 0; + + for (j = 0; j < num_placements; ++j) { + struct xe_hw_engine *hwe; + + n = j * width + i; + + hwe = find_hw_engine(xe, eci[n]); + if (XE_IOCTL_DBG(xe, !hwe)) + return 0; + + if (XE_IOCTL_DBG(xe, xe_hw_engine_is_reserved(hwe))) + return 0; + + if (XE_IOCTL_DBG(xe, n && eci[n].gt_id != gt_id) || + XE_IOCTL_DBG(xe, n && eci[n].engine_class != class)) + return 0; + + class = eci[n].engine_class; + gt_id = eci[n].gt_id; + + if (width == 1 || !i) + return_mask |= BIT(eci[n].engine_instance); + current_mask |= BIT(eci[n].engine_instance); + } + + /* Parallel submissions must be logically contiguous */ + if (i && XE_IOCTL_DBG(xe, current_mask != prev_mask << 1)) + return 0; + + prev_mask = current_mask; + } + + return return_mask; +} + +int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct xe_device *xe = to_xe_device(dev); + struct xe_file *xef = to_xe_file(file); + struct drm_xe_exec_queue_create *args = data; + struct drm_xe_engine_class_instance eci[XE_HW_ENGINE_MAX_INSTANCE]; + struct drm_xe_engine_class_instance __user *user_eci = + u64_to_user_ptr(args->instances); + struct xe_hw_engine *hwe; + struct xe_vm *vm, *migrate_vm; + struct xe_gt *gt; + struct xe_exec_queue *q = NULL; + u32 logical_mask; + u32 id; + u32 len; + int err; + + if (XE_IOCTL_DBG(xe, args->flags) || + XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) + return -EINVAL; + + len = args->width * args->num_placements; + if (XE_IOCTL_DBG(xe, !len || len > XE_HW_ENGINE_MAX_INSTANCE)) + return -EINVAL; + + err = __copy_from_user(eci, user_eci, + sizeof(struct drm_xe_engine_class_instance) * + len); + if (XE_IOCTL_DBG(xe, err)) + return -EFAULT; + + if (XE_IOCTL_DBG(xe, eci[0].gt_id >= xe->info.gt_count)) + return -EINVAL; + + if (eci[0].engine_class == DRM_XE_ENGINE_CLASS_VM_BIND) { + for_each_gt(gt, xe, id) { + struct xe_exec_queue *new; + + if (xe_gt_is_media_type(gt)) + continue; + + eci[0].gt_id = gt->info.id; + logical_mask = bind_exec_queue_logical_mask(xe, gt, eci, + args->width, + args->num_placements); + if (XE_IOCTL_DBG(xe, !logical_mask)) + return -EINVAL; + + hwe = find_hw_engine(xe, eci[0]); + if (XE_IOCTL_DBG(xe, !hwe)) + return -EINVAL; + + /* The migration vm doesn't hold rpm ref */ + xe_device_mem_access_get(xe); + + migrate_vm = xe_migrate_get_vm(gt_to_tile(gt)->migrate); + new = xe_exec_queue_create(xe, migrate_vm, logical_mask, + args->width, hwe, + EXEC_QUEUE_FLAG_PERSISTENT | + EXEC_QUEUE_FLAG_VM | + (id ? + EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD : + 0)); + + xe_device_mem_access_put(xe); /* now held by engine */ + + xe_vm_put(migrate_vm); + if (IS_ERR(new)) { + err = PTR_ERR(new); + if (q) + goto put_exec_queue; + return err; + } + if (id == 0) + q = new; + else + list_add_tail(&new->multi_gt_list, + &q->multi_gt_link); + } + } else { + gt = xe_device_get_gt(xe, eci[0].gt_id); + logical_mask = calc_validate_logical_mask(xe, gt, eci, + args->width, + args->num_placements); + if (XE_IOCTL_DBG(xe, !logical_mask)) + return -EINVAL; + + hwe = find_hw_engine(xe, eci[0]); + if (XE_IOCTL_DBG(xe, !hwe)) + return -EINVAL; + + vm = xe_vm_lookup(xef, args->vm_id); + if (XE_IOCTL_DBG(xe, !vm)) + return -ENOENT; + + err = down_read_interruptible(&vm->lock); + if (err) { + xe_vm_put(vm); + return err; + } + + if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) { + up_read(&vm->lock); + xe_vm_put(vm); + return -ENOENT; + } + + q = xe_exec_queue_create(xe, vm, logical_mask, + args->width, hwe, + xe_vm_no_dma_fences(vm) ? 0 : + EXEC_QUEUE_FLAG_PERSISTENT); + up_read(&vm->lock); + xe_vm_put(vm); + if (IS_ERR(q)) + return PTR_ERR(q); + } + + if (args->extensions) { + err = exec_queue_user_extensions(xe, q, args->extensions, 0, true); + if (XE_IOCTL_DBG(xe, err)) + goto put_exec_queue; + } + + if (XE_IOCTL_DBG(xe, q->vm && xe_vm_in_compute_mode(q->vm) != + !!(q->flags & EXEC_QUEUE_FLAG_COMPUTE_MODE))) { + err = -EOPNOTSUPP; + goto put_exec_queue; + } + + q->persistent.xef = xef; + + mutex_lock(&xef->exec_queue.lock); + err = xa_alloc(&xef->exec_queue.xa, &id, q, xa_limit_32b, GFP_KERNEL); + mutex_unlock(&xef->exec_queue.lock); + if (err) + goto put_exec_queue; + + args->exec_queue_id = id; + + return 0; + +put_exec_queue: + xe_exec_queue_kill(q); + xe_exec_queue_put(q); + return err; +} + +int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct xe_device *xe = to_xe_device(dev); + struct xe_file *xef = to_xe_file(file); + struct drm_xe_exec_queue_get_property *args = data; + struct xe_exec_queue *q; + int ret; + + if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) + return -EINVAL; + + q = xe_exec_queue_lookup(xef, args->exec_queue_id); + if (XE_IOCTL_DBG(xe, !q)) + return -ENOENT; + + switch (args->property) { + case XE_EXEC_QUEUE_GET_PROPERTY_BAN: + args->value = !!(q->flags & EXEC_QUEUE_FLAG_BANNED); + ret = 0; + break; + default: + ret = -EINVAL; + } + + xe_exec_queue_put(q); + + return ret; +} + +static void exec_queue_kill_compute(struct xe_exec_queue *q) +{ + if (!xe_vm_in_compute_mode(q->vm)) + return; + + down_write(&q->vm->lock); + list_del(&q->compute.link); + --q->vm->preempt.num_engines; + if (q->compute.pfence) { + dma_fence_enable_sw_signaling(q->compute.pfence); + dma_fence_put(q->compute.pfence); + q->compute.pfence = NULL; + } + up_write(&q->vm->lock); +} + +/** + * xe_exec_queue_is_lr() - Whether an exec_queue is long-running + * @q: The exec_queue + * + * Return: True if the exec_queue is long-running, false otherwise. + */ +bool xe_exec_queue_is_lr(struct xe_exec_queue *q) +{ + return q->vm && xe_vm_no_dma_fences(q->vm) && + !(q->flags & EXEC_QUEUE_FLAG_VM); +} + +static s32 xe_exec_queue_num_job_inflight(struct xe_exec_queue *q) +{ + return q->lrc->fence_ctx.next_seqno - xe_lrc_seqno(q->lrc) - 1; +} + +/** + * xe_exec_queue_ring_full() - Whether an exec_queue's ring is full + * @q: The exec_queue + * + * Return: True if the exec_queue's ring is full, false otherwise. + */ +bool xe_exec_queue_ring_full(struct xe_exec_queue *q) +{ + struct xe_lrc *lrc = q->lrc; + s32 max_job = lrc->ring.size / MAX_JOB_SIZE_BYTES; + + return xe_exec_queue_num_job_inflight(q) >= max_job; +} + +/** + * xe_exec_queue_is_idle() - Whether an exec_queue is idle. + * @q: The exec_queue + * + * FIXME: Need to determine what to use as the short-lived + * timeline lock for the exec_queues, so that the return value + * of this function becomes more than just an advisory + * snapshot in time. The timeline lock must protect the + * seqno from racing submissions on the same exec_queue. + * Typically vm->resv, but user-created timeline locks use the migrate vm + * and never grabs the migrate vm->resv so we have a race there. + * + * Return: True if the exec_queue is idle, false otherwise. + */ +bool xe_exec_queue_is_idle(struct xe_exec_queue *q) +{ + if (XE_WARN_ON(xe_exec_queue_is_parallel(q))) + return false; + + return xe_lrc_seqno(&q->lrc[0]) == + q->lrc[0].fence_ctx.next_seqno - 1; +} + +void xe_exec_queue_kill(struct xe_exec_queue *q) +{ + struct xe_exec_queue *eq = q, *next; + + list_for_each_entry_safe(eq, next, &eq->multi_gt_list, + multi_gt_link) { + q->ops->kill(eq); + exec_queue_kill_compute(eq); + } + + q->ops->kill(q); + exec_queue_kill_compute(q); +} + +int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct xe_device *xe = to_xe_device(dev); + struct xe_file *xef = to_xe_file(file); + struct drm_xe_exec_queue_destroy *args = data; + struct xe_exec_queue *q; + + if (XE_IOCTL_DBG(xe, args->pad) || + XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) + return -EINVAL; + + mutex_lock(&xef->exec_queue.lock); + q = xa_erase(&xef->exec_queue.xa, args->exec_queue_id); + mutex_unlock(&xef->exec_queue.lock); + if (XE_IOCTL_DBG(xe, !q)) + return -ENOENT; + + if (!(q->flags & EXEC_QUEUE_FLAG_PERSISTENT)) + xe_exec_queue_kill(q); + else + xe_device_add_persistent_exec_queues(xe, q); + + trace_xe_exec_queue_close(q); + xe_exec_queue_put(q); + + return 0; +} + +int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct xe_device *xe = to_xe_device(dev); + struct xe_file *xef = to_xe_file(file); + struct drm_xe_exec_queue_set_property *args = data; + struct xe_exec_queue *q; + int ret; + u32 idx; + + if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) + return -EINVAL; + + q = xe_exec_queue_lookup(xef, args->exec_queue_id); + if (XE_IOCTL_DBG(xe, !q)) + return -ENOENT; + + if (XE_IOCTL_DBG(xe, args->property >= + ARRAY_SIZE(exec_queue_set_property_funcs))) { + ret = -EINVAL; + goto out; + } + + idx = array_index_nospec(args->property, + ARRAY_SIZE(exec_queue_set_property_funcs)); + ret = exec_queue_set_property_funcs[idx](xe, q, args->value, false); + if (XE_IOCTL_DBG(xe, ret)) + goto out; + + if (args->extensions) + ret = exec_queue_user_extensions(xe, q, args->extensions, 0, + false); +out: + xe_exec_queue_put(q); + + return ret; +} diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h new file mode 100644 index 000000000000..024bc26a7006 --- /dev/null +++ b/drivers/gpu/drm/xe/xe_exec_queue.h @@ -0,0 +1,63 @@ +/* SPDX-License-Identifier: MIT */ +/* + * Copyright © 2021 Intel Corporation + */ + +#ifndef _XE_EXEC_QUEUE_H_ +#define _XE_EXEC_QUEUE_H_ + +#include "xe_exec_queue_types.h" +#include "xe_vm_types.h" + +struct drm_device; +struct drm_file; +struct xe_device; +struct xe_file; + +struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm, + u32 logical_mask, u16 width, + struct xe_hw_engine *hw_engine, u32 flags); +struct xe_exec_queue *xe_exec_queue_create_class(struct xe_device *xe, struct xe_gt *gt, + struct xe_vm *vm, + enum xe_engine_class class, u32 flags); + +void xe_exec_queue_fini(struct xe_exec_queue *q); +void xe_exec_queue_destroy(struct kref *ref); + +struct xe_exec_queue *xe_exec_queue_lookup(struct xe_file *xef, u32 id); + +static inline struct xe_exec_queue *xe_exec_queue_get(struct xe_exec_queue *q) +{ + kref_get(&q->refcount); + return q; +} + +static inline void xe_exec_queue_put(struct xe_exec_queue *q) +{ + kref_put(&q->refcount, xe_exec_queue_destroy); +} + +static inline bool xe_exec_queue_is_parallel(struct xe_exec_queue *q) +{ + return q->width > 1; +} + +bool xe_exec_queue_is_lr(struct xe_exec_queue *q); + +bool xe_exec_queue_ring_full(struct xe_exec_queue *q); + +bool xe_exec_queue_is_idle(struct xe_exec_queue *q); + +void xe_exec_queue_kill(struct xe_exec_queue *q); + +int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); +int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); +int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); +int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); +enum drm_sched_priority xe_exec_queue_device_get_max_priority(struct xe_device *xe); + +#endif diff --git a/drivers/gpu/drm/xe/xe_engine_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h similarity index 52% rename from drivers/gpu/drm/xe/xe_engine_types.h rename to drivers/gpu/drm/xe/xe_exec_queue_types.h index 7aa5d9ef7896..e3ae11b63e4a 100644 --- a/drivers/gpu/drm/xe/xe_engine_types.h +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h @@ -3,8 +3,8 @@ * Copyright © 2022 Intel Corporation */ -#ifndef _XE_ENGINE_TYPES_H_ -#define _XE_ENGINE_TYPES_H_ +#ifndef _XE_EXEC_QUEUE_TYPES_H_ +#define _XE_EXEC_QUEUE_TYPES_H_ #include <linux/kref.h> @@ -14,20 +14,20 @@ #include "xe_hw_fence_types.h" #include "xe_lrc_types.h" -struct xe_execlist_engine; +struct xe_execlist_exec_queue; struct xe_gt; -struct xe_guc_engine; +struct xe_guc_exec_queue; struct xe_hw_engine; struct xe_vm; /** - * struct xe_engine - Submission engine + * struct xe_exec_queue - Execution queue * * Contains all state necessary for submissions. Can either be a user object or * a kernel object. */ -struct xe_engine { - /** @gt: graphics tile this engine can submit to */ +struct xe_exec_queue { + /** @gt: graphics tile this exec queue can submit to */ struct xe_gt *gt; /** * @hwe: A hardware of the same class. May (physical engine) or may not @@ -35,34 +35,34 @@ struct xe_engine { * really be used for submissions. */ struct xe_hw_engine *hwe; - /** @refcount: ref count of this engine */ + /** @refcount: ref count of this exec queue */ struct kref refcount; - /** @vm: VM (address space) for this engine */ + /** @vm: VM (address space) for this exec queue */ struct xe_vm *vm; - /** @class: class of this engine */ + /** @class: class of this exec queue */ enum xe_engine_class class; /** - * @logical_mask: logical mask of where job submitted to engine can run + * @logical_mask: logical mask of where job submitted to exec queue can run */ u32 logical_mask; - /** @name: name of this engine */ + /** @name: name of this exec queue */ char name[MAX_FENCE_NAME_LEN]; - /** @width: width (number BB submitted per exec) of this engine */ + /** @width: width (number BB submitted per exec) of this exec queue */ u16 width; /** @fence_irq: fence IRQ used to signal job completion */ struct xe_hw_fence_irq *fence_irq; -#define ENGINE_FLAG_BANNED BIT(0) -#define ENGINE_FLAG_KERNEL BIT(1) -#define ENGINE_FLAG_PERSISTENT BIT(2) -#define ENGINE_FLAG_COMPUTE_MODE BIT(3) -/* Caller needs to hold rpm ref when creating engine with ENGINE_FLAG_VM */ -#define ENGINE_FLAG_VM BIT(4) -#define ENGINE_FLAG_BIND_ENGINE_CHILD BIT(5) -#define ENGINE_FLAG_WA BIT(6) +#define EXEC_QUEUE_FLAG_BANNED BIT(0) +#define EXEC_QUEUE_FLAG_KERNEL BIT(1) +#define EXEC_QUEUE_FLAG_PERSISTENT BIT(2) +#define EXEC_QUEUE_FLAG_COMPUTE_MODE BIT(3) +/* Caller needs to hold rpm ref when creating engine with EXEC_QUEUE_FLAG_VM */ +#define EXEC_QUEUE_FLAG_VM BIT(4) +#define EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD BIT(5) +#define EXEC_QUEUE_FLAG_WA BIT(6) /** - * @flags: flags for this engine, should statically setup aside from ban + * @flags: flags for this exec queue, should statically setup aside from ban * bit */ unsigned long flags; @@ -75,19 +75,19 @@ struct xe_engine { }; union { - /** @execlist: execlist backend specific state for engine */ - struct xe_execlist_engine *execlist; - /** @guc: GuC backend specific state for engine */ - struct xe_guc_engine *guc; + /** @execlist: execlist backend specific state for exec queue */ + struct xe_execlist_exec_queue *execlist; + /** @guc: GuC backend specific state for exec queue */ + struct xe_guc_exec_queue *guc; }; /** - * @persistent: persistent engine state + * @persistent: persistent exec queue state */ struct { - /** @xef: file which this engine belongs to */ + /** @xef: file which this exec queue belongs to */ struct xe_file *xef; - /** @link: link in list of persistent engines */ + /** @link: link in list of persistent exec queues */ struct list_head link; } persistent; @@ -144,53 +144,53 @@ struct xe_engine { u32 acc_granularity; } usm; - /** @ops: submission backend engine operations */ - const struct xe_engine_ops *ops; + /** @ops: submission backend exec queue operations */ + const struct xe_exec_queue_ops *ops; - /** @ring_ops: ring operations for this engine */ + /** @ring_ops: ring operations for this exec queue */ const struct xe_ring_ops *ring_ops; - /** @entity: DRM sched entity for this engine (1 to 1 relationship) */ + /** @entity: DRM sched entity for this exec queue (1 to 1 relationship) */ struct drm_sched_entity *entity; - /** @lrc: logical ring context for this engine */ + /** @lrc: logical ring context for this exec queue */ struct xe_lrc lrc[]; }; /** - * struct xe_engine_ops - Submission backend engine operations + * struct xe_exec_queue_ops - Submission backend exec queue operations */ -struct xe_engine_ops { - /** @init: Initialize engine for submission backend */ - int (*init)(struct xe_engine *e); +struct xe_exec_queue_ops { + /** @init: Initialize exec queue for submission backend */ + int (*init)(struct xe_exec_queue *q); /** @kill: Kill inflight submissions for backend */ - void (*kill)(struct xe_engine *e); - /** @fini: Fini engine for submission backend */ - void (*fini)(struct xe_engine *e); - /** @set_priority: Set priority for engine */ - int (*set_priority)(struct xe_engine *e, + void (*kill)(struct xe_exec_queue *q); + /** @fini: Fini exec queue for submission backend */ + void (*fini)(struct xe_exec_queue *q); + /** @set_priority: Set priority for exec queue */ + int (*set_priority)(struct xe_exec_queue *q, enum drm_sched_priority priority); - /** @set_timeslice: Set timeslice for engine */ - int (*set_timeslice)(struct xe_engine *e, u32 timeslice_us); - /** @set_preempt_timeout: Set preemption timeout for engine */ - int (*set_preempt_timeout)(struct xe_engine *e, u32 preempt_timeout_us); - /** @set_job_timeout: Set job timeout for engine */ - int (*set_job_timeout)(struct xe_engine *e, u32 job_timeout_ms); + /** @set_timeslice: Set timeslice for exec queue */ + int (*set_timeslice)(struct xe_exec_queue *q, u32 timeslice_us); + /** @set_preempt_timeout: Set preemption timeout for exec queue */ + int (*set_preempt_timeout)(struct xe_exec_queue *q, u32 preempt_timeout_us); + /** @set_job_timeout: Set job timeout for exec queue */ + int (*set_job_timeout)(struct xe_exec_queue *q, u32 job_timeout_ms); /** - * @suspend: Suspend engine from executing, allowed to be called + * @suspend: Suspend exec queue from executing, allowed to be called * multiple times in a row before resume with the caveat that * suspend_wait returns before calling suspend again. */ - int (*suspend)(struct xe_engine *e); + int (*suspend)(struct xe_exec_queue *q); /** - * @suspend_wait: Wait for an engine to suspend executing, should be + * @suspend_wait: Wait for an exec queue to suspend executing, should be * call after suspend. */ - void (*suspend_wait)(struct xe_engine *e); + void (*suspend_wait)(struct xe_exec_queue *q); /** - * @resume: Resume engine execution, engine must be in a suspended + * @resume: Resume exec queue execution, exec queue must be in a suspended * state and dma fence returned from most recent suspend call must be * signalled when this function is called. */ - void (*resume)(struct xe_engine *e); + void (*resume)(struct xe_exec_queue *q); }; #endif diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c index 0f9d919405b0..8ef98c7fd8e2 100644 --- a/drivers/gpu/drm/xe/xe_execlist.c +++ b/drivers/gpu/drm/xe/xe_execlist.c @@ -14,7 +14,7 @@ #include "regs/xe_regs.h" #include "xe_bo.h" #include "xe_device.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_gt.h" #include "xe_hw_fence.h" #include "xe_lrc.h" @@ -91,7 +91,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, } static void __xe_execlist_port_start(struct xe_execlist_port *port, - struct xe_execlist_engine *exl) + struct xe_execlist_exec_queue *exl) { struct xe_device *xe = gt_to_xe(port->hwe->gt); int max_ctx = FIELD_MAX(GEN11_SW_CTX_ID); @@ -109,7 +109,7 @@ static void __xe_execlist_port_start(struct xe_execlist_port *port, port->last_ctx_id = 1; } - __start_lrc(port->hwe, exl->engine->lrc, port->last_ctx_id); + __start_lrc(port->hwe, exl->q->lrc, port->last_ctx_id); port->running_exl = exl; exl->has_run = true; } @@ -128,16 +128,16 @@ static void __xe_execlist_port_idle(struct xe_execlist_port *port) port->running_exl = NULL; } -static bool xe_execlist_is_idle(struct xe_execlist_engine *exl) +static bool xe_execlist_is_idle(struct xe_execlist_exec_queue *exl) { - struct xe_lrc *lrc = exl->engine->lrc; + struct xe_lrc *lrc = exl->q->lrc; return lrc->ring.tail == lrc->ring.old_tail; } static void __xe_execlist_port_start_next_active(struct xe_execlist_port *port) { - struct xe_execlist_engine *exl = NULL; + struct xe_execlist_exec_queue *exl = NULL; int i; xe_execlist_port_assert_held(port); @@ -145,7 +145,7 @@ static void __xe_execlist_port_start_next_active(struct xe_execlist_port *port) for (i = ARRAY_SIZE(port->active) - 1; i >= 0; i--) { while (!list_empty(&port->active[i])) { exl = list_first_entry(&port->active[i], - struct xe_execlist_engine, + struct xe_execlist_exec_queue, active_link); list_del(&exl->active_link); @@ -208,7 +208,7 @@ static void xe_execlist_port_wake_locked(struct xe_execlist_port *port, __xe_execlist_port_start_next_active(port); } -static void xe_execlist_make_active(struct xe_execlist_engine *exl) +static void xe_execlist_make_active(struct xe_execlist_exec_queue *exl) { struct xe_execlist_port *port = exl->port; enum drm_sched_priority priority = exl->entity.priority; @@ -293,10 +293,10 @@ static struct dma_fence * execlist_run_job(struct drm_sched_job *drm_job) { struct xe_sched_job *job = to_xe_sched_job(drm_job); - struct xe_engine *e = job->engine; - struct xe_execlist_engine *exl = job->engine->execlist; + struct xe_exec_queue *q = job->q; + struct xe_execlist_exec_queue *exl = job->q->execlist; - e->ring_ops->emit_job(job); + q->ring_ops->emit_job(job); xe_execlist_make_active(exl); return dma_fence_get(job->fence); @@ -314,11 +314,11 @@ static const struct drm_sched_backend_ops drm_sched_ops = { .free_job = execlist_job_free, }; -static int execlist_engine_init(struct xe_engine *e) +static int execlist_exec_queue_init(struct xe_exec_queue *q) { struct drm_gpu_scheduler *sched; - struct xe_execlist_engine *exl; - struct xe_device *xe = gt_to_xe(e->gt); + struct xe_execlist_exec_queue *exl; + struct xe_device *xe = gt_to_xe(q->gt); int err; XE_WARN_ON(xe_device_guc_submission_enabled(xe)); @@ -329,14 +329,14 @@ static int execlist_engine_init(struct xe_engine *e) if (!exl) return -ENOMEM; - exl->engine = e; + exl->q = q; err = drm_sched_init(&exl->sched, &drm_sched_ops, NULL, - e->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, + q->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, XE_SCHED_HANG_LIMIT, XE_SCHED_JOB_TIMEOUT, - NULL, NULL, e->hwe->name, + NULL, NULL, q->hwe->name, DRM_SCHED_POLICY_SINGLE_ENTITY, - gt_to_xe(e->gt)->drm.dev); + gt_to_xe(q->gt)->drm.dev); if (err) goto err_free; @@ -346,30 +346,30 @@ static int execlist_engine_init(struct xe_engine *e) if (err) goto err_sched; - exl->port = e->hwe->exl_port; + exl->port = q->hwe->exl_port; exl->has_run = false; exl->active_priority = DRM_SCHED_PRIORITY_UNSET; - e->execlist = exl; - e->entity = &exl->entity; + q->execlist = exl; + q->entity = &exl->entity; - switch (e->class) { + switch (q->class) { case XE_ENGINE_CLASS_RENDER: - sprintf(e->name, "rcs%d", ffs(e->logical_mask) - 1); + sprintf(q->name, "rcs%d", ffs(q->logical_mask) - 1); break; case XE_ENGINE_CLASS_VIDEO_DECODE: - sprintf(e->name, "vcs%d", ffs(e->logical_mask) - 1); + sprintf(q->name, "vcs%d", ffs(q->logical_mask) - 1); break; case XE_ENGINE_CLASS_VIDEO_ENHANCE: - sprintf(e->name, "vecs%d", ffs(e->logical_mask) - 1); + sprintf(q->name, "vecs%d", ffs(q->logical_mask) - 1); break; case XE_ENGINE_CLASS_COPY: - sprintf(e->name, "bcs%d", ffs(e->logical_mask) - 1); + sprintf(q->name, "bcs%d", ffs(q->logical_mask) - 1); break; case XE_ENGINE_CLASS_COMPUTE: - sprintf(e->name, "ccs%d", ffs(e->logical_mask) - 1); + sprintf(q->name, "ccs%d", ffs(q->logical_mask) - 1); break; default: - XE_WARN_ON(e->class); + XE_WARN_ON(q->class); } return 0; @@ -381,96 +381,96 @@ static int execlist_engine_init(struct xe_engine *e) return err; } -static void execlist_engine_fini_async(struct work_struct *w) +static void execlist_exec_queue_fini_async(struct work_struct *w) { - struct xe_execlist_engine *ee = - container_of(w, struct xe_execlist_engine, fini_async); - struct xe_engine *e = ee->engine; - struct xe_execlist_engine *exl = e->execlist; + struct xe_execlist_exec_queue *ee = + container_of(w, struct xe_execlist_exec_queue, fini_async); + struct xe_exec_queue *q = ee->q; + struct xe_execlist_exec_queue *exl = q->execlist; unsigned long flags; - XE_WARN_ON(xe_device_guc_submission_enabled(gt_to_xe(e->gt))); + XE_WARN_ON(xe_device_guc_submission_enabled(gt_to_xe(q->gt))); spin_lock_irqsave(&exl->port->lock, flags); if (WARN_ON(exl->active_priority != DRM_SCHED_PRIORITY_UNSET)) list_del(&exl->active_link); spin_unlock_irqrestore(&exl->port->lock, flags); - if (e->flags & ENGINE_FLAG_PERSISTENT) - xe_device_remove_persistent_engines(gt_to_xe(e->gt), e); + if (q->flags & EXEC_QUEUE_FLAG_PERSISTENT) + xe_device_remove_persistent_exec_queues(gt_to_xe(q->gt), q); drm_sched_entity_fini(&exl->entity); drm_sched_fini(&exl->sched); kfree(exl); - xe_engine_fini(e); + xe_exec_queue_fini(q); } -static void execlist_engine_kill(struct xe_engine *e) +static void execlist_exec_queue_kill(struct xe_exec_queue *q) { /* NIY */ } -static void execlist_engine_fini(struct xe_engine *e) +static void execlist_exec_queue_fini(struct xe_exec_queue *q) { - INIT_WORK(&e->execlist->fini_async, execlist_engine_fini_async); - queue_work(system_unbound_wq, &e->execlist->fini_async); + INIT_WORK(&q->execlist->fini_async, execlist_exec_queue_fini_async); + queue_work(system_unbound_wq, &q->execlist->fini_async); } -static int execlist_engine_set_priority(struct xe_engine *e, - enum drm_sched_priority priority) +static int execlist_exec_queue_set_priority(struct xe_exec_queue *q, + enum drm_sched_priority priority) { /* NIY */ return 0; } -static int execlist_engine_set_timeslice(struct xe_engine *e, u32 timeslice_us) +static int execlist_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us) { /* NIY */ return 0; } -static int execlist_engine_set_preempt_timeout(struct xe_engine *e, - u32 preempt_timeout_us) +static int execlist_exec_queue_set_preempt_timeout(struct xe_exec_queue *q, + u32 preempt_timeout_us) { /* NIY */ return 0; } -static int execlist_engine_set_job_timeout(struct xe_engine *e, - u32 job_timeout_ms) +static int execlist_exec_queue_set_job_timeout(struct xe_exec_queue *q, + u32 job_timeout_ms) { /* NIY */ return 0; } -static int execlist_engine_suspend(struct xe_engine *e) +static int execlist_exec_queue_suspend(struct xe_exec_queue *q) { /* NIY */ return 0; } -static void execlist_engine_suspend_wait(struct xe_engine *e) +static void execlist_exec_queue_suspend_wait(struct xe_exec_queue *q) { /* NIY */ } -static void execlist_engine_resume(struct xe_engine *e) +static void execlist_exec_queue_resume(struct xe_exec_queue *q) { /* NIY */ } -static const struct xe_engine_ops execlist_engine_ops = { - .init = execlist_engine_init, - .kill = execlist_engine_kill, - .fini = execlist_engine_fini, - .set_priority = execlist_engine_set_priority, - .set_timeslice = execlist_engine_set_timeslice, - .set_preempt_timeout = execlist_engine_set_preempt_timeout, - .set_job_timeout = execlist_engine_set_job_timeout, - .suspend = execlist_engine_suspend, - .suspend_wait = execlist_engine_suspend_wait, - .resume = execlist_engine_resume, +static const struct xe_exec_queue_ops execlist_exec_queue_ops = { + .init = execlist_exec_queue_init, + .kill = execlist_exec_queue_kill, + .fini = execlist_exec_queue_fini, + .set_priority = execlist_exec_queue_set_priority, + .set_timeslice = execlist_exec_queue_set_timeslice, + .set_preempt_timeout = execlist_exec_queue_set_preempt_timeout, + .set_job_timeout = execlist_exec_queue_set_job_timeout, + .suspend = execlist_exec_queue_suspend, + .suspend_wait = execlist_exec_queue_suspend_wait, + .resume = execlist_exec_queue_resume, }; int xe_execlist_init(struct xe_gt *gt) @@ -479,7 +479,7 @@ int xe_execlist_init(struct xe_gt *gt) if (xe_device_guc_submission_enabled(gt_to_xe(gt))) return 0; - gt->engine_ops = &execlist_engine_ops; + gt->exec_queue_ops = &execlist_exec_queue_ops; return 0; } diff --git a/drivers/gpu/drm/xe/xe_execlist_types.h b/drivers/gpu/drm/xe/xe_execlist_types.h index 05a620940209..ee1fccd4ee8b 100644 --- a/drivers/gpu/drm/xe/xe_execlist_types.h +++ b/drivers/gpu/drm/xe/xe_execlist_types.h @@ -13,7 +13,7 @@ #include <drm/gpu_scheduler.h> struct xe_hw_engine; -struct xe_execlist_engine; +struct xe_execlist_exec_queue; struct xe_execlist_port { struct xe_hw_engine *hwe; @@ -24,13 +24,13 @@ struct xe_execlist_port { u32 last_ctx_id; - struct xe_execlist_engine *running_exl; + struct xe_execlist_exec_queue *running_exl; struct timer_list irq_fail; }; -struct xe_execlist_engine { - struct xe_engine *engine; +struct xe_execlist_exec_queue { + struct xe_exec_queue *q; struct drm_gpu_scheduler sched; diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c index 28bf577c7bf2..3077faa1e792 100644 --- a/drivers/gpu/drm/xe/xe_gt.c +++ b/drivers/gpu/drm/xe/xe_gt.c @@ -14,7 +14,7 @@ #include "xe_bb.h" #include "xe_bo.h" #include "xe_device.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_execlist.h" #include "xe_force_wake.h" #include "xe_ggtt.h" @@ -26,7 +26,7 @@ #include "xe_gt_sysfs.h" #include "xe_gt_tlb_invalidation.h" #include "xe_gt_topology.h" -#include "xe_guc_engine_types.h" +#include "xe_guc_exec_queue_types.h" #include "xe_hw_fence.h" #include "xe_irq.h" #include "xe_lrc.h" @@ -81,7 +81,7 @@ static void gt_fini(struct drm_device *drm, void *arg) static void gt_reset_worker(struct work_struct *w); -static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e) +static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) { struct xe_sched_job *job; struct xe_bb *bb; @@ -94,7 +94,7 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e) return PTR_ERR(bb); batch_ofs = xe_bo_ggtt_addr(gt_to_tile(gt)->mem.kernel_bb_pool->bo); - job = xe_bb_create_wa_job(e, bb, batch_ofs); + job = xe_bb_create_wa_job(q, bb, batch_ofs); if (IS_ERR(job)) { xe_bb_free(bb, NULL); return PTR_ERR(job); @@ -115,9 +115,9 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e) return 0; } -static int emit_wa_job(struct xe_gt *gt, struct xe_engine *e) +static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) { - struct xe_reg_sr *sr = &e->hwe->reg_lrc; + struct xe_reg_sr *sr = &q->hwe->reg_lrc; struct xe_reg_sr_entry *entry; unsigned long reg; struct xe_sched_job *job; @@ -143,7 +143,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_engine *e) } batch_ofs = xe_bo_ggtt_addr(gt_to_tile(gt)->mem.kernel_bb_pool->bo); - job = xe_bb_create_wa_job(e, bb, batch_ofs); + job = xe_bb_create_wa_job(q, bb, batch_ofs); if (IS_ERR(job)) { xe_bb_free(bb, NULL); return PTR_ERR(job); @@ -173,7 +173,7 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) int err = 0; for_each_hw_engine(hwe, gt, id) { - struct xe_engine *e, *nop_e; + struct xe_exec_queue *q, *nop_q; struct xe_vm *vm; void *default_lrc; @@ -192,58 +192,58 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) return -ENOMEM; vm = xe_migrate_get_vm(tile->migrate); - e = xe_engine_create(xe, vm, BIT(hwe->logical_instance), 1, - hwe, ENGINE_FLAG_WA); - if (IS_ERR(e)) { - err = PTR_ERR(e); - xe_gt_err(gt, "hwe %s: xe_engine_create failed (%pe)\n", - hwe->name, e); + q = xe_exec_queue_create(xe, vm, BIT(hwe->logical_instance), 1, + hwe, EXEC_QUEUE_FLAG_WA); + if (IS_ERR(q)) { + err = PTR_ERR(q); + xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", + hwe->name, q); goto put_vm; } /* Prime golden LRC with known good state */ - err = emit_wa_job(gt, e); + err = emit_wa_job(gt, q); if (err) { xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", - hwe->name, ERR_PTR(err), e->guc->id); - goto put_engine; + hwe->name, ERR_PTR(err), q->guc->id); + goto put_exec_queue; } - nop_e = xe_engine_create(xe, vm, BIT(hwe->logical_instance), - 1, hwe, ENGINE_FLAG_WA); - if (IS_ERR(nop_e)) { - err = PTR_ERR(nop_e); - xe_gt_err(gt, "hwe %s: nop xe_engine_create failed (%pe)\n", - hwe->name, nop_e); - goto put_engine; + nop_q = xe_exec_queue_create(xe, vm, BIT(hwe->logical_instance), + 1, hwe, EXEC_QUEUE_FLAG_WA); + if (IS_ERR(nop_q)) { + err = PTR_ERR(nop_q); + xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", + hwe->name, nop_q); + goto put_exec_queue; } /* Switch to different LRC */ - err = emit_nop_job(gt, nop_e); + err = emit_nop_job(gt, nop_q); if (err) { xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", - hwe->name, ERR_PTR(err), nop_e->guc->id); - goto put_nop_e; + hwe->name, ERR_PTR(err), nop_q->guc->id); + goto put_nop_q; } /* Reload golden LRC to record the effect of any indirect W/A */ - err = emit_nop_job(gt, e); + err = emit_nop_job(gt, q); if (err) { xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n", - hwe->name, ERR_PTR(err), e->guc->id); - goto put_nop_e; + hwe->name, ERR_PTR(err), q->guc->id); + goto put_nop_q; } xe_map_memcpy_from(xe, default_lrc, - &e->lrc[0].bo->vmap, - xe_lrc_pphwsp_offset(&e->lrc[0]), + &q->lrc[0].bo->vmap, + xe_lrc_pphwsp_offset(&q->lrc[0]), xe_lrc_size(xe, hwe->class)); gt->default_lrc[hwe->class] = default_lrc; -put_nop_e: - xe_engine_put(nop_e); -put_engine: - xe_engine_put(e); +put_nop_q: + xe_exec_queue_put(nop_q); +put_exec_queue: + xe_exec_queue_put(q); put_vm: xe_vm_put(vm); if (err) diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h index 78a9fe9f0bd3..c326932e53d7 100644 --- a/drivers/gpu/drm/xe/xe_gt_types.h +++ b/drivers/gpu/drm/xe/xe_gt_types.h @@ -14,7 +14,7 @@ #include "xe_sa_types.h" #include "xe_uc_types.h" -struct xe_engine_ops; +struct xe_exec_queue_ops; struct xe_migrate; struct xe_ring_ops; @@ -269,8 +269,8 @@ struct xe_gt { /** @gtidle: idle properties of GT */ struct xe_gt_idle gtidle; - /** @engine_ops: submission backend engine operations */ - const struct xe_engine_ops *engine_ops; + /** @exec_queue_ops: submission backend exec queue operations */ + const struct xe_exec_queue_ops *exec_queue_ops; /** * @ring_ops: ring operations for this hw engine (1 per engine class) diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c index a7da29be2e51..7d1244df959d 100644 --- a/drivers/gpu/drm/xe/xe_guc_ads.c +++ b/drivers/gpu/drm/xe/xe_guc_ads.c @@ -495,7 +495,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads) u8 gc; /* - * 1. Write all MMIO entries for this engine to the table. No + * 1. Write all MMIO entries for this exec queue to the table. No * need to worry about fused-off engines and when there are * entries in the regset: the reg_state_list has been zero'ed * by xe_guc_ads_populate() diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c index 7fb2690425f8..3d705c64b85d 100644 --- a/drivers/gpu/drm/xe/xe_guc_ct.c +++ b/drivers/gpu/drm/xe/xe_guc_ct.c @@ -889,11 +889,11 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len) ret = xe_guc_deregister_done_handler(guc, payload, adj_len); break; case XE_GUC_ACTION_CONTEXT_RESET_NOTIFICATION: - ret = xe_guc_engine_reset_handler(guc, payload, adj_len); + ret = xe_guc_exec_queue_reset_handler(guc, payload, adj_len); break; case XE_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION: - ret = xe_guc_engine_reset_failure_handler(guc, payload, - adj_len); + ret = xe_guc_exec_queue_reset_failure_handler(guc, payload, + adj_len); break; case XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE: /* Selftest only at the moment */ @@ -903,8 +903,8 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len) /* FIXME: Handle this */ break; case XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR: - ret = xe_guc_engine_memory_cat_error_handler(guc, payload, - adj_len); + ret = xe_guc_exec_queue_memory_cat_error_handler(guc, payload, + adj_len); break; case XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC: ret = xe_guc_pagefault_handler(guc, payload, adj_len); diff --git a/drivers/gpu/drm/xe/xe_guc_engine_types.h b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h similarity index 88% rename from drivers/gpu/drm/xe/xe_guc_engine_types.h rename to drivers/gpu/drm/xe/xe_guc_exec_queue_types.h index 5d83132034a6..395ed3fba218 100644 --- a/drivers/gpu/drm/xe/xe_guc_engine_types.h +++ b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h @@ -12,14 +12,14 @@ #include <drm/gpu_scheduler.h> struct dma_fence; -struct xe_engine; +struct xe_exec_queue; /** - * struct xe_guc_engine - GuC specific state for an xe_engine + * struct xe_guc_exec_queue - GuC specific state for an xe_engine */ -struct xe_guc_engine { +struct xe_guc_exec_queue { /** @engine: Backpointer to parent xe_engine */ - struct xe_engine *engine; + struct xe_exec_queue *q; /** @sched: GPU scheduler for this xe_engine */ struct drm_gpu_scheduler sched; /** @entity: Scheduler entity for this xe_engine */ @@ -43,7 +43,7 @@ struct xe_guc_engine { u32 wqi_head; /** @wqi_tail: work queue item tail */ u32 wqi_tail; - /** @id: GuC id for this xe_engine */ + /** @id: GuC id for this exec_queue */ u16 id; /** @suspend_wait: wait queue used to wait on pending suspends */ wait_queue_head_t suspend_wait; diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h index 7515d7fbb723..4216a6d9e478 100644 --- a/drivers/gpu/drm/xe/xe_guc_fwif.h +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h @@ -69,13 +69,13 @@ struct guc_klv_generic_dw_t { } __packed; /* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */ -struct guc_update_engine_policy_header { +struct guc_update_exec_queue_policy_header { u32 action; u32 guc_id; } __packed; -struct guc_update_engine_policy { - struct guc_update_engine_policy_header header; +struct guc_update_exec_queue_policy { + struct guc_update_exec_queue_policy_header header; struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS]; } __packed; diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c index 8d2b50e03ed2..448075411191 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit.c +++ b/drivers/gpu/drm/xe/xe_guc_submit.c @@ -16,12 +16,12 @@ #include "regs/xe_lrc_layout.h" #include "xe_devcoredump.h" #include "xe_device.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_force_wake.h" #include "xe_gt.h" #include "xe_guc.h" #include "xe_guc_ct.h" -#include "xe_guc_engine_types.h" +#include "xe_guc_exec_queue_types.h" #include "xe_guc_submit_types.h" #include "xe_hw_engine.h" #include "xe_hw_fence.h" @@ -47,9 +47,9 @@ guc_to_xe(struct xe_guc *guc) } static struct xe_guc * -engine_to_guc(struct xe_engine *e) +exec_queue_to_guc(struct xe_exec_queue *q) { - return &e->gt->uc.guc; + return &q->gt->uc.guc; } /* @@ -57,140 +57,140 @@ engine_to_guc(struct xe_engine *e) * as the same time (e.g. a suspend can be happning at the same time as schedule * engine done being processed). */ -#define ENGINE_STATE_REGISTERED (1 << 0) +#define EXEC_QUEUE_STATE_REGISTERED (1 << 0) #define ENGINE_STATE_ENABLED (1 << 1) -#define ENGINE_STATE_PENDING_ENABLE (1 << 2) -#define ENGINE_STATE_PENDING_DISABLE (1 << 3) -#define ENGINE_STATE_DESTROYED (1 << 4) +#define EXEC_QUEUE_STATE_PENDING_ENABLE (1 << 2) +#define EXEC_QUEUE_STATE_PENDING_DISABLE (1 << 3) +#define EXEC_QUEUE_STATE_DESTROYED (1 << 4) #define ENGINE_STATE_SUSPENDED (1 << 5) -#define ENGINE_STATE_RESET (1 << 6) +#define EXEC_QUEUE_STATE_RESET (1 << 6) #define ENGINE_STATE_KILLED (1 << 7) -static bool engine_registered(struct xe_engine *e) +static bool exec_queue_registered(struct xe_exec_queue *q) { - return atomic_read(&e->guc->state) & ENGINE_STATE_REGISTERED; + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_REGISTERED; } -static void set_engine_registered(struct xe_engine *e) +static void set_exec_queue_registered(struct xe_exec_queue *q) { - atomic_or(ENGINE_STATE_REGISTERED, &e->guc->state); + atomic_or(EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); } -static void clear_engine_registered(struct xe_engine *e) +static void clear_exec_queue_registered(struct xe_exec_queue *q) { - atomic_and(~ENGINE_STATE_REGISTERED, &e->guc->state); + atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); } -static bool engine_enabled(struct xe_engine *e) +static bool exec_queue_enabled(struct xe_exec_queue *q) { - return atomic_read(&e->guc->state) & ENGINE_STATE_ENABLED; + return atomic_read(&q->guc->state) & ENGINE_STATE_ENABLED; } -static void set_engine_enabled(struct xe_engine *e) +static void set_exec_queue_enabled(struct xe_exec_queue *q) { - atomic_or(ENGINE_STATE_ENABLED, &e->guc->state); + atomic_or(ENGINE_STATE_ENABLED, &q->guc->state); } -static void clear_engine_enabled(struct xe_engine *e) +static void clear_exec_queue_enabled(struct xe_exec_queue *q) { - atomic_and(~ENGINE_STATE_ENABLED, &e->guc->state); + atomic_and(~ENGINE_STATE_ENABLED, &q->guc->state); } -static bool engine_pending_enable(struct xe_engine *e) +static bool exec_queue_pending_enable(struct xe_exec_queue *q) { - return atomic_read(&e->guc->state) & ENGINE_STATE_PENDING_ENABLE; + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_ENABLE; } -static void set_engine_pending_enable(struct xe_engine *e) +static void set_exec_queue_pending_enable(struct xe_exec_queue *q) { - atomic_or(ENGINE_STATE_PENDING_ENABLE, &e->guc->state); + atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); } -static void clear_engine_pending_enable(struct xe_engine *e) +static void clear_exec_queue_pending_enable(struct xe_exec_queue *q) { - atomic_and(~ENGINE_STATE_PENDING_ENABLE, &e->guc->state); + atomic_and(~EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); } -static bool engine_pending_disable(struct xe_engine *e) +static bool exec_queue_pending_disable(struct xe_exec_queue *q) { - return atomic_read(&e->guc->state) & ENGINE_STATE_PENDING_DISABLE; + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_DISABLE; } -static void set_engine_pending_disable(struct xe_engine *e) +static void set_exec_queue_pending_disable(struct xe_exec_queue *q) { - atomic_or(ENGINE_STATE_PENDING_DISABLE, &e->guc->state); + atomic_or(EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); } -static void clear_engine_pending_disable(struct xe_engine *e) +static void clear_exec_queue_pending_disable(struct xe_exec_queue *q) { - atomic_and(~ENGINE_STATE_PENDING_DISABLE, &e->guc->state); + atomic_and(~EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); } -static bool engine_destroyed(struct xe_engine *e) +static bool exec_queue_destroyed(struct xe_exec_queue *q) { - return atomic_read(&e->guc->state) & ENGINE_STATE_DESTROYED; + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_DESTROYED; } -static void set_engine_destroyed(struct xe_engine *e) +static void set_exec_queue_destroyed(struct xe_exec_queue *q) { - atomic_or(ENGINE_STATE_DESTROYED, &e->guc->state); + atomic_or(EXEC_QUEUE_STATE_DESTROYED, &q->guc->state); } -static bool engine_banned(struct xe_engine *e) +static bool exec_queue_banned(struct xe_exec_queue *q) { - return (e->flags & ENGINE_FLAG_BANNED); + return (q->flags & EXEC_QUEUE_FLAG_BANNED); } -static void set_engine_banned(struct xe_engine *e) +static void set_exec_queue_banned(struct xe_exec_queue *q) { - e->flags |= ENGINE_FLAG_BANNED; + q->flags |= EXEC_QUEUE_FLAG_BANNED; } -static bool engine_suspended(struct xe_engine *e) +static bool exec_queue_suspended(struct xe_exec_queue *q) { - return atomic_read(&e->guc->state) & ENGINE_STATE_SUSPENDED; + return atomic_read(&q->guc->state) & ENGINE_STATE_SUSPENDED; } -static void set_engine_suspended(struct xe_engine *e) +static void set_exec_queue_suspended(struct xe_exec_queue *q) { - atomic_or(ENGINE_STATE_SUSPENDED, &e->guc->state); + atomic_or(ENGINE_STATE_SUSPENDED, &q->guc->state); } -static void clear_engine_suspended(struct xe_engine *e) +static void clear_exec_queue_suspended(struct xe_exec_queue *q) { - atomic_and(~ENGINE_STATE_SUSPENDED, &e->guc->state); + atomic_and(~ENGINE_STATE_SUSPENDED, &q->guc->state); } -static bool engine_reset(struct xe_engine *e) +static bool exec_queue_reset(struct xe_exec_queue *q) { - return atomic_read(&e->guc->state) & ENGINE_STATE_RESET; + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_RESET; } -static void set_engine_reset(struct xe_engine *e) +static void set_exec_queue_reset(struct xe_exec_queue *q) { - atomic_or(ENGINE_STATE_RESET, &e->guc->state); + atomic_or(EXEC_QUEUE_STATE_RESET, &q->guc->state); } -static bool engine_killed(struct xe_engine *e) +static bool exec_queue_killed(struct xe_exec_queue *q) { - return atomic_read(&e->guc->state) & ENGINE_STATE_KILLED; + return atomic_read(&q->guc->state) & ENGINE_STATE_KILLED; } -static void set_engine_killed(struct xe_engine *e) +static void set_exec_queue_killed(struct xe_exec_queue *q) { - atomic_or(ENGINE_STATE_KILLED, &e->guc->state); + atomic_or(ENGINE_STATE_KILLED, &q->guc->state); } -static bool engine_killed_or_banned(struct xe_engine *e) +static bool exec_queue_killed_or_banned(struct xe_exec_queue *q) { - return engine_killed(e) || engine_banned(e); + return exec_queue_killed(q) || exec_queue_banned(q); } static void guc_submit_fini(struct drm_device *drm, void *arg) { struct xe_guc *guc = arg; - xa_destroy(&guc->submission_state.engine_lookup); + xa_destroy(&guc->submission_state.exec_queue_lookup); ida_destroy(&guc->submission_state.guc_ids); bitmap_free(guc->submission_state.guc_ids_bitmap); } @@ -200,7 +200,7 @@ static void guc_submit_fini(struct drm_device *drm, void *arg) #define GUC_ID_NUMBER_SLRC (GUC_ID_MAX - GUC_ID_NUMBER_MLRC) #define GUC_ID_START_MLRC GUC_ID_NUMBER_SLRC -static const struct xe_engine_ops guc_engine_ops; +static const struct xe_exec_queue_ops guc_exec_queue_ops; static void primelockdep(struct xe_guc *guc) { @@ -227,10 +227,10 @@ int xe_guc_submit_init(struct xe_guc *guc) if (!guc->submission_state.guc_ids_bitmap) return -ENOMEM; - gt->engine_ops = &guc_engine_ops; + gt->exec_queue_ops = &guc_exec_queue_ops; mutex_init(&guc->submission_state.lock); - xa_init(&guc->submission_state.engine_lookup); + xa_init(&guc->submission_state.exec_queue_lookup); ida_init(&guc->submission_state.guc_ids); spin_lock_init(&guc->submission_state.suspend.lock); @@ -245,7 +245,7 @@ int xe_guc_submit_init(struct xe_guc *guc) return 0; } -static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) +static int alloc_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) { int ret; void *ptr; @@ -259,11 +259,11 @@ static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) */ lockdep_assert_held(&guc->submission_state.lock); - if (xe_engine_is_parallel(e)) { + if (xe_exec_queue_is_parallel(q)) { void *bitmap = guc->submission_state.guc_ids_bitmap; ret = bitmap_find_free_region(bitmap, GUC_ID_NUMBER_MLRC, - order_base_2(e->width)); + order_base_2(q->width)); } else { ret = ida_simple_get(&guc->submission_state.guc_ids, 0, GUC_ID_NUMBER_SLRC, GFP_NOWAIT); @@ -271,12 +271,12 @@ static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) if (ret < 0) return ret; - e->guc->id = ret; - if (xe_engine_is_parallel(e)) - e->guc->id += GUC_ID_START_MLRC; + q->guc->id = ret; + if (xe_exec_queue_is_parallel(q)) + q->guc->id += GUC_ID_START_MLRC; - ptr = xa_store(&guc->submission_state.engine_lookup, - e->guc->id, e, GFP_NOWAIT); + ptr = xa_store(&guc->submission_state.exec_queue_lookup, + q->guc->id, q, GFP_NOWAIT); if (IS_ERR(ptr)) { ret = PTR_ERR(ptr); goto err_release; @@ -285,29 +285,29 @@ static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) return 0; err_release: - ida_simple_remove(&guc->submission_state.guc_ids, e->guc->id); + ida_simple_remove(&guc->submission_state.guc_ids, q->guc->id); return ret; } -static void release_guc_id(struct xe_guc *guc, struct xe_engine *e) +static void release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) { mutex_lock(&guc->submission_state.lock); - xa_erase(&guc->submission_state.engine_lookup, e->guc->id); - if (xe_engine_is_parallel(e)) + xa_erase(&guc->submission_state.exec_queue_lookup, q->guc->id); + if (xe_exec_queue_is_parallel(q)) bitmap_release_region(guc->submission_state.guc_ids_bitmap, - e->guc->id - GUC_ID_START_MLRC, - order_base_2(e->width)); + q->guc->id - GUC_ID_START_MLRC, + order_base_2(q->width)); else - ida_simple_remove(&guc->submission_state.guc_ids, e->guc->id); + ida_simple_remove(&guc->submission_state.guc_ids, q->guc->id); mutex_unlock(&guc->submission_state.lock); } -struct engine_policy { +struct exec_queue_policy { u32 count; - struct guc_update_engine_policy h2g; + struct guc_update_exec_queue_policy h2g; }; -static u32 __guc_engine_policy_action_size(struct engine_policy *policy) +static u32 __guc_exec_queue_policy_action_size(struct exec_queue_policy *policy) { size_t bytes = sizeof(policy->h2g.header) + (sizeof(policy->h2g.klv[0]) * policy->count); @@ -315,8 +315,8 @@ static u32 __guc_engine_policy_action_size(struct engine_policy *policy) return bytes / sizeof(u32); } -static void __guc_engine_policy_start_klv(struct engine_policy *policy, - u16 guc_id) +static void __guc_exec_queue_policy_start_klv(struct exec_queue_policy *policy, + u16 guc_id) { policy->h2g.header.action = XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES; @@ -324,8 +324,8 @@ static void __guc_engine_policy_start_klv(struct engine_policy *policy, policy->count = 0; } -#define MAKE_ENGINE_POLICY_ADD(func, id) \ -static void __guc_engine_policy_add_##func(struct engine_policy *policy, \ +#define MAKE_EXEC_QUEUE_POLICY_ADD(func, id) \ +static void __guc_exec_queue_policy_add_##func(struct exec_queue_policy *policy, \ u32 data) \ { \ XE_WARN_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \ @@ -338,10 +338,10 @@ static void __guc_engine_policy_add_##func(struct engine_policy *policy, \ policy->count++; \ } -MAKE_ENGINE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM) -MAKE_ENGINE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT) -MAKE_ENGINE_POLICY_ADD(priority, SCHEDULING_PRIORITY) -#undef MAKE_ENGINE_POLICY_ADD +MAKE_EXEC_QUEUE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM) +MAKE_EXEC_QUEUE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT) +MAKE_EXEC_QUEUE_POLICY_ADD(priority, SCHEDULING_PRIORITY) +#undef MAKE_EXEC_QUEUE_POLICY_ADD static const int drm_sched_prio_to_guc[] = { [DRM_SCHED_PRIORITY_MIN] = GUC_CLIENT_PRIORITY_NORMAL, @@ -350,33 +350,33 @@ static const int drm_sched_prio_to_guc[] = { [DRM_SCHED_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH, }; -static void init_policies(struct xe_guc *guc, struct xe_engine *e) +static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q) { - struct engine_policy policy; - enum drm_sched_priority prio = e->entity->priority; - u32 timeslice_us = e->sched_props.timeslice_us; - u32 preempt_timeout_us = e->sched_props.preempt_timeout_us; + struct exec_queue_policy policy; + enum drm_sched_priority prio = q->entity->priority; + u32 timeslice_us = q->sched_props.timeslice_us; + u32 preempt_timeout_us = q->sched_props.preempt_timeout_us; - XE_WARN_ON(!engine_registered(e)); + XE_WARN_ON(!exec_queue_registered(q)); - __guc_engine_policy_start_klv(&policy, e->guc->id); - __guc_engine_policy_add_priority(&policy, drm_sched_prio_to_guc[prio]); - __guc_engine_policy_add_execution_quantum(&policy, timeslice_us); - __guc_engine_policy_add_preemption_timeout(&policy, preempt_timeout_us); + __guc_exec_queue_policy_start_klv(&policy, q->guc->id); + __guc_exec_queue_policy_add_priority(&policy, drm_sched_prio_to_guc[prio]); + __guc_exec_queue_policy_add_execution_quantum(&policy, timeslice_us); + __guc_exec_queue_policy_add_preemption_timeout(&policy, preempt_timeout_us); xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, - __guc_engine_policy_action_size(&policy), 0, 0); + __guc_exec_queue_policy_action_size(&policy), 0, 0); } -static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_engine *e) +static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue *q) { - struct engine_policy policy; + struct exec_queue_policy policy; - __guc_engine_policy_start_klv(&policy, e->guc->id); - __guc_engine_policy_add_preemption_timeout(&policy, 1); + __guc_exec_queue_policy_start_klv(&policy, q->guc->id); + __guc_exec_queue_policy_add_preemption_timeout(&policy, 1); xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, - __guc_engine_policy_action_size(&policy), 0, 0); + __guc_exec_queue_policy_action_size(&policy), 0, 0); } #define parallel_read(xe_, map_, field_) \ @@ -387,7 +387,7 @@ static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_engine *e) field_, val_) static void __register_mlrc_engine(struct xe_guc *guc, - struct xe_engine *e, + struct xe_exec_queue *q, struct guc_ctxt_registration_info *info) { #define MAX_MLRC_REG_SIZE (13 + XE_HW_ENGINE_MAX_INSTANCE * 2) @@ -395,7 +395,7 @@ static void __register_mlrc_engine(struct xe_guc *guc, int len = 0; int i; - XE_WARN_ON(!xe_engine_is_parallel(e)); + XE_WARN_ON(!xe_exec_queue_is_parallel(q)); action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC; action[len++] = info->flags; @@ -407,12 +407,12 @@ static void __register_mlrc_engine(struct xe_guc *guc, action[len++] = info->wq_base_lo; action[len++] = info->wq_base_hi; action[len++] = info->wq_size; - action[len++] = e->width; + action[len++] = q->width; action[len++] = info->hwlrca_lo; action[len++] = info->hwlrca_hi; - for (i = 1; i < e->width; ++i) { - struct xe_lrc *lrc = e->lrc + i; + for (i = 1; i < q->width; ++i) { + struct xe_lrc *lrc = q->lrc + i; action[len++] = lower_32_bits(xe_lrc_descriptor(lrc)); action[len++] = upper_32_bits(xe_lrc_descriptor(lrc)); @@ -445,24 +445,24 @@ static void __register_engine(struct xe_guc *guc, xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0); } -static void register_engine(struct xe_engine *e) +static void register_engine(struct xe_exec_queue *q) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); struct xe_device *xe = guc_to_xe(guc); - struct xe_lrc *lrc = e->lrc; + struct xe_lrc *lrc = q->lrc; struct guc_ctxt_registration_info info; - XE_WARN_ON(engine_registered(e)); + XE_WARN_ON(exec_queue_registered(q)); memset(&info, 0, sizeof(info)); - info.context_idx = e->guc->id; - info.engine_class = xe_engine_class_to_guc_class(e->class); - info.engine_submit_mask = e->logical_mask; + info.context_idx = q->guc->id; + info.engine_class = xe_engine_class_to_guc_class(q->class); + info.engine_submit_mask = q->logical_mask; info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc)); info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc)); info.flags = CONTEXT_REGISTRATION_FLAG_KMD; - if (xe_engine_is_parallel(e)) { + if (xe_exec_queue_is_parallel(q)) { u32 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc); struct iosys_map map = xe_lrc_parallel_map(lrc); @@ -476,8 +476,8 @@ static void register_engine(struct xe_engine *e) offsetof(struct guc_submit_parallel_scratch, wq[0])); info.wq_size = WQ_SIZE; - e->guc->wqi_head = 0; - e->guc->wqi_tail = 0; + q->guc->wqi_head = 0; + q->guc->wqi_tail = 0; xe_map_memset(xe, &map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE); parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE); } @@ -487,38 +487,38 @@ static void register_engine(struct xe_engine *e) * the GuC as jobs signal immediately and can't destroy an engine if the * GuC has a reference to it. */ - if (xe_engine_is_lr(e)) - xe_engine_get(e); + if (xe_exec_queue_is_lr(q)) + xe_exec_queue_get(q); - set_engine_registered(e); - trace_xe_engine_register(e); - if (xe_engine_is_parallel(e)) - __register_mlrc_engine(guc, e, &info); + set_exec_queue_registered(q); + trace_xe_exec_queue_register(q); + if (xe_exec_queue_is_parallel(q)) + __register_mlrc_engine(guc, q, &info); else __register_engine(guc, &info); - init_policies(guc, e); + init_policies(guc, q); } -static u32 wq_space_until_wrap(struct xe_engine *e) +static u32 wq_space_until_wrap(struct xe_exec_queue *q) { - return (WQ_SIZE - e->guc->wqi_tail); + return (WQ_SIZE - q->guc->wqi_tail); } -static int wq_wait_for_space(struct xe_engine *e, u32 wqi_size) +static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); struct xe_device *xe = guc_to_xe(guc); - struct iosys_map map = xe_lrc_parallel_map(e->lrc); + struct iosys_map map = xe_lrc_parallel_map(q->lrc); unsigned int sleep_period_ms = 1; #define AVAILABLE_SPACE \ - CIRC_SPACE(e->guc->wqi_tail, e->guc->wqi_head, WQ_SIZE) + CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE) if (wqi_size > AVAILABLE_SPACE) { try_again: - e->guc->wqi_head = parallel_read(xe, map, wq_desc.head); + q->guc->wqi_head = parallel_read(xe, map, wq_desc.head); if (wqi_size > AVAILABLE_SPACE) { if (sleep_period_ms == 1024) { - xe_gt_reset_async(e->gt); + xe_gt_reset_async(q->gt); return -ENODEV; } @@ -532,52 +532,52 @@ static int wq_wait_for_space(struct xe_engine *e, u32 wqi_size) return 0; } -static int wq_noop_append(struct xe_engine *e) +static int wq_noop_append(struct xe_exec_queue *q) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); struct xe_device *xe = guc_to_xe(guc); - struct iosys_map map = xe_lrc_parallel_map(e->lrc); - u32 len_dw = wq_space_until_wrap(e) / sizeof(u32) - 1; + struct iosys_map map = xe_lrc_parallel_map(q->lrc); + u32 len_dw = wq_space_until_wrap(q) / sizeof(u32) - 1; - if (wq_wait_for_space(e, wq_space_until_wrap(e))) + if (wq_wait_for_space(q, wq_space_until_wrap(q))) return -ENODEV; XE_WARN_ON(!FIELD_FIT(WQ_LEN_MASK, len_dw)); - parallel_write(xe, map, wq[e->guc->wqi_tail / sizeof(u32)], + parallel_write(xe, map, wq[q->guc->wqi_tail / sizeof(u32)], FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_NOOP) | FIELD_PREP(WQ_LEN_MASK, len_dw)); - e->guc->wqi_tail = 0; + q->guc->wqi_tail = 0; return 0; } -static void wq_item_append(struct xe_engine *e) +static void wq_item_append(struct xe_exec_queue *q) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); struct xe_device *xe = guc_to_xe(guc); - struct iosys_map map = xe_lrc_parallel_map(e->lrc); + struct iosys_map map = xe_lrc_parallel_map(q->lrc); #define WQ_HEADER_SIZE 4 /* Includes 1 LRC address too */ u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)]; - u32 wqi_size = (e->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32); + u32 wqi_size = (q->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32); u32 len_dw = (wqi_size / sizeof(u32)) - 1; int i = 0, j; - if (wqi_size > wq_space_until_wrap(e)) { - if (wq_noop_append(e)) + if (wqi_size > wq_space_until_wrap(q)) { + if (wq_noop_append(q)) return; } - if (wq_wait_for_space(e, wqi_size)) + if (wq_wait_for_space(q, wqi_size)) return; wqi[i++] = FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_MULTI_LRC) | FIELD_PREP(WQ_LEN_MASK, len_dw); - wqi[i++] = xe_lrc_descriptor(e->lrc); - wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, e->guc->id) | - FIELD_PREP(WQ_RING_TAIL_MASK, e->lrc->ring.tail / sizeof(u64)); + wqi[i++] = xe_lrc_descriptor(q->lrc); + wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, q->guc->id) | + FIELD_PREP(WQ_RING_TAIL_MASK, q->lrc->ring.tail / sizeof(u64)); wqi[i++] = 0; - for (j = 1; j < e->width; ++j) { - struct xe_lrc *lrc = e->lrc + j; + for (j = 1; j < q->width; ++j) { + struct xe_lrc *lrc = q->lrc + j; wqi[i++] = lrc->ring.tail / sizeof(u64); } @@ -585,55 +585,55 @@ static void wq_item_append(struct xe_engine *e) XE_WARN_ON(i != wqi_size / sizeof(u32)); iosys_map_incr(&map, offsetof(struct guc_submit_parallel_scratch, - wq[e->guc->wqi_tail / sizeof(u32)])); + wq[q->guc->wqi_tail / sizeof(u32)])); xe_map_memcpy_to(xe, &map, 0, wqi, wqi_size); - e->guc->wqi_tail += wqi_size; - XE_WARN_ON(e->guc->wqi_tail > WQ_SIZE); + q->guc->wqi_tail += wqi_size; + XE_WARN_ON(q->guc->wqi_tail > WQ_SIZE); xe_device_wmb(xe); - map = xe_lrc_parallel_map(e->lrc); - parallel_write(xe, map, wq_desc.tail, e->guc->wqi_tail); + map = xe_lrc_parallel_map(q->lrc); + parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail); } #define RESUME_PENDING ~0x0ull -static void submit_engine(struct xe_engine *e) +static void submit_exec_queue(struct xe_exec_queue *q) { - struct xe_guc *guc = engine_to_guc(e); - struct xe_lrc *lrc = e->lrc; + struct xe_guc *guc = exec_queue_to_guc(q); + struct xe_lrc *lrc = q->lrc; u32 action[3]; u32 g2h_len = 0; u32 num_g2h = 0; int len = 0; bool extra_submit = false; - XE_WARN_ON(!engine_registered(e)); + XE_WARN_ON(!exec_queue_registered(q)); - if (xe_engine_is_parallel(e)) - wq_item_append(e); + if (xe_exec_queue_is_parallel(q)) + wq_item_append(q); else xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); - if (engine_suspended(e) && !xe_engine_is_parallel(e)) + if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q)) return; - if (!engine_enabled(e) && !engine_suspended(e)) { + if (!exec_queue_enabled(q) && !exec_queue_suspended(q)) { action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET; - action[len++] = e->guc->id; + action[len++] = q->guc->id; action[len++] = GUC_CONTEXT_ENABLE; g2h_len = G2H_LEN_DW_SCHED_CONTEXT_MODE_SET; num_g2h = 1; - if (xe_engine_is_parallel(e)) + if (xe_exec_queue_is_parallel(q)) extra_submit = true; - e->guc->resume_time = RESUME_PENDING; - set_engine_pending_enable(e); - set_engine_enabled(e); - trace_xe_engine_scheduling_enable(e); + q->guc->resume_time = RESUME_PENDING; + set_exec_queue_pending_enable(q); + set_exec_queue_enabled(q); + trace_xe_exec_queue_scheduling_enable(q); } else { action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; - action[len++] = e->guc->id; - trace_xe_engine_submit(e); + action[len++] = q->guc->id; + trace_xe_exec_queue_submit(q); } xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h); @@ -641,31 +641,31 @@ static void submit_engine(struct xe_engine *e) if (extra_submit) { len = 0; action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; - action[len++] = e->guc->id; - trace_xe_engine_submit(e); + action[len++] = q->guc->id; + trace_xe_exec_queue_submit(q); xe_guc_ct_send(&guc->ct, action, len, 0, 0); } } static struct dma_fence * -guc_engine_run_job(struct drm_sched_job *drm_job) +guc_exec_queue_run_job(struct drm_sched_job *drm_job) { struct xe_sched_job *job = to_xe_sched_job(drm_job); - struct xe_engine *e = job->engine; - bool lr = xe_engine_is_lr(e); + struct xe_exec_queue *q = job->q; + bool lr = xe_exec_queue_is_lr(q); - XE_WARN_ON((engine_destroyed(e) || engine_pending_disable(e)) && - !engine_banned(e) && !engine_suspended(e)); + XE_WARN_ON((exec_queue_destroyed(q) || exec_queue_pending_disable(q)) && + !exec_queue_banned(q) && !exec_queue_suspended(q)); trace_xe_sched_job_run(job); - if (!engine_killed_or_banned(e) && !xe_sched_job_is_error(job)) { - if (!engine_registered(e)) - register_engine(e); + if (!exec_queue_killed_or_banned(q) && !xe_sched_job_is_error(job)) { + if (!exec_queue_registered(q)) + register_engine(q); if (!lr) /* LR jobs are emitted in the exec IOCTL */ - e->ring_ops->emit_job(job); - submit_engine(e); + q->ring_ops->emit_job(job); + submit_exec_queue(q); } if (lr) { @@ -678,7 +678,7 @@ guc_engine_run_job(struct drm_sched_job *drm_job) } } -static void guc_engine_free_job(struct drm_sched_job *drm_job) +static void guc_exec_queue_free_job(struct drm_sched_job *drm_job) { struct xe_sched_job *job = to_xe_sched_job(drm_job); @@ -691,38 +691,38 @@ static int guc_read_stopped(struct xe_guc *guc) return atomic_read(&guc->submission_state.stopped); } -#define MAKE_SCHED_CONTEXT_ACTION(e, enable_disable) \ +#define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable) \ u32 action[] = { \ XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET, \ - e->guc->id, \ + q->guc->id, \ GUC_CONTEXT_##enable_disable, \ } #define MIN_SCHED_TIMEOUT 1 static void disable_scheduling_deregister(struct xe_guc *guc, - struct xe_engine *e) + struct xe_exec_queue *q) { - MAKE_SCHED_CONTEXT_ACTION(e, DISABLE); + MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); int ret; - set_min_preemption_timeout(guc, e); + set_min_preemption_timeout(guc, q); smp_rmb(); - ret = wait_event_timeout(guc->ct.wq, !engine_pending_enable(e) || + ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_enable(q) || guc_read_stopped(guc), HZ * 5); if (!ret) { - struct drm_gpu_scheduler *sched = &e->guc->sched; + struct drm_gpu_scheduler *sched = &q->guc->sched; XE_WARN_ON("Pending enable failed to respond"); sched->timeout = MIN_SCHED_TIMEOUT; drm_sched_run_wq_start(sched); - xe_gt_reset_async(e->gt); + xe_gt_reset_async(q->gt); return; } - clear_engine_enabled(e); - set_engine_pending_disable(e); - set_engine_destroyed(e); - trace_xe_engine_scheduling_disable(e); + clear_exec_queue_enabled(q); + set_exec_queue_pending_disable(q); + set_exec_queue_destroyed(q); + trace_xe_exec_queue_scheduling_disable(q); /* * Reserve space for both G2H here as the 2nd G2H is sent from a G2H @@ -733,27 +733,27 @@ static void disable_scheduling_deregister(struct xe_guc *guc, G2H_LEN_DW_DEREGISTER_CONTEXT, 2); } -static void guc_engine_print(struct xe_engine *e, struct drm_printer *p); +static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p); #if IS_ENABLED(CONFIG_DRM_XE_SIMPLE_ERROR_CAPTURE) -static void simple_error_capture(struct xe_engine *e) +static void simple_error_capture(struct xe_exec_queue *q) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); struct drm_printer p = drm_err_printer(""); struct xe_hw_engine *hwe; enum xe_hw_engine_id id; - u32 adj_logical_mask = e->logical_mask; - u32 width_mask = (0x1 << e->width) - 1; + u32 adj_logical_mask = q->logical_mask; + u32 width_mask = (0x1 << q->width) - 1; int i; bool cookie; - if (e->vm && !e->vm->error_capture.capture_once) { - e->vm->error_capture.capture_once = true; + if (q->vm && !q->vm->error_capture.capture_once) { + q->vm->error_capture.capture_once = true; cookie = dma_fence_begin_signalling(); - for (i = 0; e->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { + for (i = 0; q->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { if (adj_logical_mask & BIT(i)) { adj_logical_mask |= width_mask << i; - i += e->width; + i += q->width; } else { ++i; } @@ -761,66 +761,66 @@ static void simple_error_capture(struct xe_engine *e) xe_force_wake_get(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL); xe_guc_ct_print(&guc->ct, &p, true); - guc_engine_print(e, &p); + guc_exec_queue_print(q, &p); for_each_hw_engine(hwe, guc_to_gt(guc), id) { - if (hwe->class != e->hwe->class || + if (hwe->class != q->hwe->class || !(BIT(hwe->logical_instance) & adj_logical_mask)) continue; xe_hw_engine_print(hwe, &p); } - xe_analyze_vm(&p, e->vm, e->gt->info.id); + xe_analyze_vm(&p, q->vm, q->gt->info.id); xe_force_wake_put(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL); dma_fence_end_signalling(cookie); } } #else -static void simple_error_capture(struct xe_engine *e) +static void simple_error_capture(struct xe_exec_queue *q) { } #endif -static void xe_guc_engine_trigger_cleanup(struct xe_engine *e) +static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); - if (xe_engine_is_lr(e)) - queue_work(guc_to_gt(guc)->ordered_wq, &e->guc->lr_tdr); + if (xe_exec_queue_is_lr(q)) + queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr); else - drm_sched_set_timeout(&e->guc->sched, MIN_SCHED_TIMEOUT); + drm_sched_set_timeout(&q->guc->sched, MIN_SCHED_TIMEOUT); } -static void xe_guc_engine_lr_cleanup(struct work_struct *w) +static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w) { - struct xe_guc_engine *ge = - container_of(w, struct xe_guc_engine, lr_tdr); - struct xe_engine *e = ge->engine; + struct xe_guc_exec_queue *ge = + container_of(w, struct xe_guc_exec_queue, lr_tdr); + struct xe_exec_queue *q = ge->q; struct drm_gpu_scheduler *sched = &ge->sched; - XE_WARN_ON(!xe_engine_is_lr(e)); - trace_xe_engine_lr_cleanup(e); + XE_WARN_ON(!xe_exec_queue_is_lr(q)); + trace_xe_exec_queue_lr_cleanup(q); /* Kill the run_job / process_msg entry points */ drm_sched_run_wq_stop(sched); /* Engine state now stable, disable scheduling / deregister if needed */ - if (engine_registered(e)) { - struct xe_guc *guc = engine_to_guc(e); + if (exec_queue_registered(q)) { + struct xe_guc *guc = exec_queue_to_guc(q); int ret; - set_engine_banned(e); - disable_scheduling_deregister(guc, e); + set_exec_queue_banned(q); + disable_scheduling_deregister(guc, q); /* * Must wait for scheduling to be disabled before signalling * any fences, if GT broken the GT reset code should signal us. */ ret = wait_event_timeout(guc->ct.wq, - !engine_pending_disable(e) || + !exec_queue_pending_disable(q) || guc_read_stopped(guc), HZ * 5); if (!ret) { XE_WARN_ON("Schedule disable failed to respond"); drm_sched_run_wq_start(sched); - xe_gt_reset_async(e->gt); + xe_gt_reset_async(q->gt); return; } } @@ -829,27 +829,27 @@ static void xe_guc_engine_lr_cleanup(struct work_struct *w) } static enum drm_gpu_sched_stat -guc_engine_timedout_job(struct drm_sched_job *drm_job) +guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) { struct xe_sched_job *job = to_xe_sched_job(drm_job); struct xe_sched_job *tmp_job; - struct xe_engine *e = job->engine; - struct drm_gpu_scheduler *sched = &e->guc->sched; - struct xe_device *xe = guc_to_xe(engine_to_guc(e)); + struct xe_exec_queue *q = job->q; + struct drm_gpu_scheduler *sched = &q->guc->sched; + struct xe_device *xe = guc_to_xe(exec_queue_to_guc(q)); int err = -ETIME; int i = 0; if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &job->fence->flags)) { - XE_WARN_ON(e->flags & ENGINE_FLAG_KERNEL); - XE_WARN_ON(e->flags & ENGINE_FLAG_VM && !engine_killed(e)); + XE_WARN_ON(q->flags & EXEC_QUEUE_FLAG_KERNEL); + XE_WARN_ON(q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q)); drm_warn(&xe->drm, "Timedout job: seqno=%u, guc_id=%d, flags=0x%lx", - xe_sched_job_seqno(job), e->guc->id, e->flags); - simple_error_capture(e); - xe_devcoredump(e); + xe_sched_job_seqno(job), q->guc->id, q->flags); + simple_error_capture(q); + xe_devcoredump(q); } else { drm_dbg(&xe->drm, "Timedout signaled job: seqno=%u, guc_id=%d, flags=0x%lx", - xe_sched_job_seqno(job), e->guc->id, e->flags); + xe_sched_job_seqno(job), q->guc->id, q->flags); } trace_xe_sched_job_timedout(job); @@ -860,26 +860,26 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) * Kernel jobs should never fail, nor should VM jobs if they do * somethings has gone wrong and the GT needs a reset */ - if (e->flags & ENGINE_FLAG_KERNEL || - (e->flags & ENGINE_FLAG_VM && !engine_killed(e))) { + if (q->flags & EXEC_QUEUE_FLAG_KERNEL || + (q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q))) { if (!drm_sched_invalidate_job(drm_job, 2)) { list_add(&drm_job->list, &sched->pending_list); drm_sched_run_wq_start(sched); - xe_gt_reset_async(e->gt); + xe_gt_reset_async(q->gt); goto out; } } /* Engine state now stable, disable scheduling if needed */ - if (engine_enabled(e)) { - struct xe_guc *guc = engine_to_guc(e); + if (exec_queue_enabled(q)) { + struct xe_guc *guc = exec_queue_to_guc(q); int ret; - if (engine_reset(e)) + if (exec_queue_reset(q)) err = -EIO; - set_engine_banned(e); - xe_engine_get(e); - disable_scheduling_deregister(guc, e); + set_exec_queue_banned(q); + xe_exec_queue_get(q); + disable_scheduling_deregister(guc, q); /* * Must wait for scheduling to be disabled before signalling @@ -891,20 +891,20 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) */ smp_rmb(); ret = wait_event_timeout(guc->ct.wq, - !engine_pending_disable(e) || + !exec_queue_pending_disable(q) || guc_read_stopped(guc), HZ * 5); if (!ret) { XE_WARN_ON("Schedule disable failed to respond"); sched->timeout = MIN_SCHED_TIMEOUT; list_add(&drm_job->list, &sched->pending_list); drm_sched_run_wq_start(sched); - xe_gt_reset_async(e->gt); + xe_gt_reset_async(q->gt); goto out; } } /* Stop fence signaling */ - xe_hw_fence_irq_stop(e->fence_irq); + xe_hw_fence_irq_stop(q->fence_irq); /* * Fence state now stable, stop / start scheduler which cleans up any @@ -912,7 +912,7 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) */ list_add(&drm_job->list, &sched->pending_list); drm_sched_run_wq_start(sched); - xe_guc_engine_trigger_cleanup(e); + xe_guc_exec_queue_trigger_cleanup(q); /* Mark all outstanding jobs as bad, thus completing them */ spin_lock(&sched->job_list_lock); @@ -921,53 +921,53 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) spin_unlock(&sched->job_list_lock); /* Start fence signaling */ - xe_hw_fence_irq_start(e->fence_irq); + xe_hw_fence_irq_start(q->fence_irq); out: return DRM_GPU_SCHED_STAT_NOMINAL; } -static void __guc_engine_fini_async(struct work_struct *w) +static void __guc_exec_queue_fini_async(struct work_struct *w) { - struct xe_guc_engine *ge = - container_of(w, struct xe_guc_engine, fini_async); - struct xe_engine *e = ge->engine; - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc_exec_queue *ge = + container_of(w, struct xe_guc_exec_queue, fini_async); + struct xe_exec_queue *q = ge->q; + struct xe_guc *guc = exec_queue_to_guc(q); - trace_xe_engine_destroy(e); + trace_xe_exec_queue_destroy(q); - if (xe_engine_is_lr(e)) + if (xe_exec_queue_is_lr(q)) cancel_work_sync(&ge->lr_tdr); - if (e->flags & ENGINE_FLAG_PERSISTENT) - xe_device_remove_persistent_engines(gt_to_xe(e->gt), e); - release_guc_id(guc, e); + if (q->flags & EXEC_QUEUE_FLAG_PERSISTENT) + xe_device_remove_persistent_exec_queues(gt_to_xe(q->gt), q); + release_guc_id(guc, q); drm_sched_entity_fini(&ge->entity); drm_sched_fini(&ge->sched); - if (!(e->flags & ENGINE_FLAG_KERNEL)) { + if (!(q->flags & EXEC_QUEUE_FLAG_KERNEL)) { kfree(ge); - xe_engine_fini(e); + xe_exec_queue_fini(q); } } -static void guc_engine_fini_async(struct xe_engine *e) +static void guc_exec_queue_fini_async(struct xe_exec_queue *q) { - bool kernel = e->flags & ENGINE_FLAG_KERNEL; + bool kernel = q->flags & EXEC_QUEUE_FLAG_KERNEL; - INIT_WORK(&e->guc->fini_async, __guc_engine_fini_async); - queue_work(system_wq, &e->guc->fini_async); + INIT_WORK(&q->guc->fini_async, __guc_exec_queue_fini_async); + queue_work(system_wq, &q->guc->fini_async); /* We must block on kernel engines so slabs are empty on driver unload */ if (kernel) { - struct xe_guc_engine *ge = e->guc; + struct xe_guc_exec_queue *ge = q->guc; flush_work(&ge->fini_async); kfree(ge); - xe_engine_fini(e); + xe_exec_queue_fini(q); } } -static void __guc_engine_fini(struct xe_guc *guc, struct xe_engine *e) +static void __guc_exec_queue_fini(struct xe_guc *guc, struct xe_exec_queue *q) { /* * Might be done from within the GPU scheduler, need to do async as we @@ -976,104 +976,104 @@ static void __guc_engine_fini(struct xe_guc *guc, struct xe_engine *e) * this we and don't really care when everything is fini'd, just that it * is. */ - guc_engine_fini_async(e); + guc_exec_queue_fini_async(q); } -static void __guc_engine_process_msg_cleanup(struct drm_sched_msg *msg) +static void __guc_exec_queue_process_msg_cleanup(struct drm_sched_msg *msg) { - struct xe_engine *e = msg->private_data; - struct xe_guc *guc = engine_to_guc(e); + struct xe_exec_queue *q = msg->private_data; + struct xe_guc *guc = exec_queue_to_guc(q); - XE_WARN_ON(e->flags & ENGINE_FLAG_KERNEL); - trace_xe_engine_cleanup_entity(e); + XE_WARN_ON(q->flags & EXEC_QUEUE_FLAG_KERNEL); + trace_xe_exec_queue_cleanup_entity(q); - if (engine_registered(e)) - disable_scheduling_deregister(guc, e); + if (exec_queue_registered(q)) + disable_scheduling_deregister(guc, q); else - __guc_engine_fini(guc, e); + __guc_exec_queue_fini(guc, q); } -static bool guc_engine_allowed_to_change_state(struct xe_engine *e) +static bool guc_exec_queue_allowed_to_change_state(struct xe_exec_queue *q) { - return !engine_killed_or_banned(e) && engine_registered(e); + return !exec_queue_killed_or_banned(q) && exec_queue_registered(q); } -static void __guc_engine_process_msg_set_sched_props(struct drm_sched_msg *msg) +static void __guc_exec_queue_process_msg_set_sched_props(struct drm_sched_msg *msg) { - struct xe_engine *e = msg->private_data; - struct xe_guc *guc = engine_to_guc(e); + struct xe_exec_queue *q = msg->private_data; + struct xe_guc *guc = exec_queue_to_guc(q); - if (guc_engine_allowed_to_change_state(e)) - init_policies(guc, e); + if (guc_exec_queue_allowed_to_change_state(q)) + init_policies(guc, q); kfree(msg); } -static void suspend_fence_signal(struct xe_engine *e) +static void suspend_fence_signal(struct xe_exec_queue *q) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); - XE_WARN_ON(!engine_suspended(e) && !engine_killed(e) && + XE_WARN_ON(!exec_queue_suspended(q) && !exec_queue_killed(q) && !guc_read_stopped(guc)); - XE_WARN_ON(!e->guc->suspend_pending); + XE_WARN_ON(!q->guc->suspend_pending); - e->guc->suspend_pending = false; + q->guc->suspend_pending = false; smp_wmb(); - wake_up(&e->guc->suspend_wait); + wake_up(&q->guc->suspend_wait); } -static void __guc_engine_process_msg_suspend(struct drm_sched_msg *msg) +static void __guc_exec_queue_process_msg_suspend(struct drm_sched_msg *msg) { - struct xe_engine *e = msg->private_data; - struct xe_guc *guc = engine_to_guc(e); + struct xe_exec_queue *q = msg->private_data; + struct xe_guc *guc = exec_queue_to_guc(q); - if (guc_engine_allowed_to_change_state(e) && !engine_suspended(e) && - engine_enabled(e)) { - wait_event(guc->ct.wq, e->guc->resume_time != RESUME_PENDING || + if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) && + exec_queue_enabled(q)) { + wait_event(guc->ct.wq, q->guc->resume_time != RESUME_PENDING || guc_read_stopped(guc)); if (!guc_read_stopped(guc)) { - MAKE_SCHED_CONTEXT_ACTION(e, DISABLE); + MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); s64 since_resume_ms = ktime_ms_delta(ktime_get(), - e->guc->resume_time); - s64 wait_ms = e->vm->preempt.min_run_period_ms - + q->guc->resume_time); + s64 wait_ms = q->vm->preempt.min_run_period_ms - since_resume_ms; - if (wait_ms > 0 && e->guc->resume_time) + if (wait_ms > 0 && q->guc->resume_time) msleep(wait_ms); - set_engine_suspended(e); - clear_engine_enabled(e); - set_engine_pending_disable(e); - trace_xe_engine_scheduling_disable(e); + set_exec_queue_suspended(q); + clear_exec_queue_enabled(q); + set_exec_queue_pending_disable(q); + trace_xe_exec_queue_scheduling_disable(q); xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); } - } else if (e->guc->suspend_pending) { - set_engine_suspended(e); - suspend_fence_signal(e); + } else if (q->guc->suspend_pending) { + set_exec_queue_suspended(q); + suspend_fence_signal(q); } } -static void __guc_engine_process_msg_resume(struct drm_sched_msg *msg) +static void __guc_exec_queue_process_msg_resume(struct drm_sched_msg *msg) { - struct xe_engine *e = msg->private_data; - struct xe_guc *guc = engine_to_guc(e); + struct xe_exec_queue *q = msg->private_data; + struct xe_guc *guc = exec_queue_to_guc(q); - if (guc_engine_allowed_to_change_state(e)) { - MAKE_SCHED_CONTEXT_ACTION(e, ENABLE); + if (guc_exec_queue_allowed_to_change_state(q)) { + MAKE_SCHED_CONTEXT_ACTION(q, ENABLE); - e->guc->resume_time = RESUME_PENDING; - clear_engine_suspended(e); - set_engine_pending_enable(e); - set_engine_enabled(e); - trace_xe_engine_scheduling_enable(e); + q->guc->resume_time = RESUME_PENDING; + clear_exec_queue_suspended(q); + set_exec_queue_pending_enable(q); + set_exec_queue_enabled(q); + trace_xe_exec_queue_scheduling_enable(q); xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); } else { - clear_engine_suspended(e); + clear_exec_queue_suspended(q); } } @@ -1082,22 +1082,22 @@ static void __guc_engine_process_msg_resume(struct drm_sched_msg *msg) #define SUSPEND 3 #define RESUME 4 -static void guc_engine_process_msg(struct drm_sched_msg *msg) +static void guc_exec_queue_process_msg(struct drm_sched_msg *msg) { trace_drm_sched_msg_recv(msg); switch (msg->opcode) { case CLEANUP: - __guc_engine_process_msg_cleanup(msg); + __guc_exec_queue_process_msg_cleanup(msg); break; case SET_SCHED_PROPS: - __guc_engine_process_msg_set_sched_props(msg); + __guc_exec_queue_process_msg_set_sched_props(msg); break; case SUSPEND: - __guc_engine_process_msg_suspend(msg); + __guc_exec_queue_process_msg_suspend(msg); break; case RESUME: - __guc_engine_process_msg_resume(msg); + __guc_exec_queue_process_msg_resume(msg); break; default: XE_WARN_ON("Unknown message type"); @@ -1105,17 +1105,17 @@ static void guc_engine_process_msg(struct drm_sched_msg *msg) } static const struct drm_sched_backend_ops drm_sched_ops = { - .run_job = guc_engine_run_job, - .free_job = guc_engine_free_job, - .timedout_job = guc_engine_timedout_job, - .process_msg = guc_engine_process_msg, + .run_job = guc_exec_queue_run_job, + .free_job = guc_exec_queue_free_job, + .timedout_job = guc_exec_queue_timedout_job, + .process_msg = guc_exec_queue_process_msg, }; -static int guc_engine_init(struct xe_engine *e) +static int guc_exec_queue_init(struct xe_exec_queue *q) { struct drm_gpu_scheduler *sched; - struct xe_guc *guc = engine_to_guc(e); - struct xe_guc_engine *ge; + struct xe_guc *guc = exec_queue_to_guc(q); + struct xe_guc_exec_queue *ge; long timeout; int err; @@ -1125,16 +1125,16 @@ static int guc_engine_init(struct xe_engine *e) if (!ge) return -ENOMEM; - e->guc = ge; - ge->engine = e; + q->guc = ge; + ge->q = q; init_waitqueue_head(&ge->suspend_wait); - timeout = xe_vm_no_dma_fences(e->vm) ? MAX_SCHEDULE_TIMEOUT : HZ * 5; + timeout = xe_vm_no_dma_fences(q->vm) ? MAX_SCHEDULE_TIMEOUT : HZ * 5; err = drm_sched_init(&ge->sched, &drm_sched_ops, NULL, - e->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, + q->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, 64, timeout, guc_to_gt(guc)->ordered_wq, NULL, - e->name, DRM_SCHED_POLICY_SINGLE_ENTITY, - gt_to_xe(e->gt)->drm.dev); + q->name, DRM_SCHED_POLICY_SINGLE_ENTITY, + gt_to_xe(q->gt)->drm.dev); if (err) goto err_free; @@ -1144,43 +1144,43 @@ static int guc_engine_init(struct xe_engine *e) if (err) goto err_sched; - if (xe_engine_is_lr(e)) - INIT_WORK(&e->guc->lr_tdr, xe_guc_engine_lr_cleanup); + if (xe_exec_queue_is_lr(q)) + INIT_WORK(&q->guc->lr_tdr, xe_guc_exec_queue_lr_cleanup); mutex_lock(&guc->submission_state.lock); - err = alloc_guc_id(guc, e); + err = alloc_guc_id(guc, q); if (err) goto err_entity; - e->entity = &ge->entity; + q->entity = &ge->entity; if (guc_read_stopped(guc)) drm_sched_stop(sched, NULL); mutex_unlock(&guc->submission_state.lock); - switch (e->class) { + switch (q->class) { case XE_ENGINE_CLASS_RENDER: - sprintf(e->name, "rcs%d", e->guc->id); + sprintf(q->name, "rcs%d", q->guc->id); break; case XE_ENGINE_CLASS_VIDEO_DECODE: - sprintf(e->name, "vcs%d", e->guc->id); + sprintf(q->name, "vcs%d", q->guc->id); break; case XE_ENGINE_CLASS_VIDEO_ENHANCE: - sprintf(e->name, "vecs%d", e->guc->id); + sprintf(q->name, "vecs%d", q->guc->id); break; case XE_ENGINE_CLASS_COPY: - sprintf(e->name, "bcs%d", e->guc->id); + sprintf(q->name, "bcs%d", q->guc->id); break; case XE_ENGINE_CLASS_COMPUTE: - sprintf(e->name, "ccs%d", e->guc->id); + sprintf(q->name, "ccs%d", q->guc->id); break; default: - XE_WARN_ON(e->class); + XE_WARN_ON(q->class); } - trace_xe_engine_create(e); + trace_xe_exec_queue_create(q); return 0; @@ -1194,132 +1194,132 @@ static int guc_engine_init(struct xe_engine *e) return err; } -static void guc_engine_kill(struct xe_engine *e) +static void guc_exec_queue_kill(struct xe_exec_queue *q) { - trace_xe_engine_kill(e); - set_engine_killed(e); - xe_guc_engine_trigger_cleanup(e); + trace_xe_exec_queue_kill(q); + set_exec_queue_killed(q); + xe_guc_exec_queue_trigger_cleanup(q); } -static void guc_engine_add_msg(struct xe_engine *e, struct drm_sched_msg *msg, - u32 opcode) +static void guc_exec_queue_add_msg(struct xe_exec_queue *q, struct drm_sched_msg *msg, + u32 opcode) { INIT_LIST_HEAD(&msg->link); msg->opcode = opcode; - msg->private_data = e; + msg->private_data = q; trace_drm_sched_msg_add(msg); - drm_sched_add_msg(&e->guc->sched, msg); + drm_sched_add_msg(&q->guc->sched, msg); } #define STATIC_MSG_CLEANUP 0 #define STATIC_MSG_SUSPEND 1 #define STATIC_MSG_RESUME 2 -static void guc_engine_fini(struct xe_engine *e) +static void guc_exec_queue_fini(struct xe_exec_queue *q) { - struct drm_sched_msg *msg = e->guc->static_msgs + STATIC_MSG_CLEANUP; + struct drm_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP; - if (!(e->flags & ENGINE_FLAG_KERNEL)) - guc_engine_add_msg(e, msg, CLEANUP); + if (!(q->flags & EXEC_QUEUE_FLAG_KERNEL)) + guc_exec_queue_add_msg(q, msg, CLEANUP); else - __guc_engine_fini(engine_to_guc(e), e); + __guc_exec_queue_fini(exec_queue_to_guc(q), q); } -static int guc_engine_set_priority(struct xe_engine *e, - enum drm_sched_priority priority) +static int guc_exec_queue_set_priority(struct xe_exec_queue *q, + enum drm_sched_priority priority) { struct drm_sched_msg *msg; - if (e->entity->priority == priority || engine_killed_or_banned(e)) + if (q->entity->priority == priority || exec_queue_killed_or_banned(q)) return 0; msg = kmalloc(sizeof(*msg), GFP_KERNEL); if (!msg) return -ENOMEM; - guc_engine_add_msg(e, msg, SET_SCHED_PROPS); + guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); return 0; } -static int guc_engine_set_timeslice(struct xe_engine *e, u32 timeslice_us) +static int guc_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us) { struct drm_sched_msg *msg; - if (e->sched_props.timeslice_us == timeslice_us || - engine_killed_or_banned(e)) + if (q->sched_props.timeslice_us == timeslice_us || + exec_queue_killed_or_banned(q)) return 0; msg = kmalloc(sizeof(*msg), GFP_KERNEL); if (!msg) return -ENOMEM; - e->sched_props.timeslice_us = timeslice_us; - guc_engine_add_msg(e, msg, SET_SCHED_PROPS); + q->sched_props.timeslice_us = timeslice_us; + guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); return 0; } -static int guc_engine_set_preempt_timeout(struct xe_engine *e, - u32 preempt_timeout_us) +static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q, + u32 preempt_timeout_us) { struct drm_sched_msg *msg; - if (e->sched_props.preempt_timeout_us == preempt_timeout_us || - engine_killed_or_banned(e)) + if (q->sched_props.preempt_timeout_us == preempt_timeout_us || + exec_queue_killed_or_banned(q)) return 0; msg = kmalloc(sizeof(*msg), GFP_KERNEL); if (!msg) return -ENOMEM; - e->sched_props.preempt_timeout_us = preempt_timeout_us; - guc_engine_add_msg(e, msg, SET_SCHED_PROPS); + q->sched_props.preempt_timeout_us = preempt_timeout_us; + guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); return 0; } -static int guc_engine_set_job_timeout(struct xe_engine *e, u32 job_timeout_ms) +static int guc_exec_queue_set_job_timeout(struct xe_exec_queue *q, u32 job_timeout_ms) { - struct drm_gpu_scheduler *sched = &e->guc->sched; + struct drm_gpu_scheduler *sched = &q->guc->sched; - XE_WARN_ON(engine_registered(e)); - XE_WARN_ON(engine_banned(e)); - XE_WARN_ON(engine_killed(e)); + XE_WARN_ON(exec_queue_registered(q)); + XE_WARN_ON(exec_queue_banned(q)); + XE_WARN_ON(exec_queue_killed(q)); sched->timeout = job_timeout_ms; return 0; } -static int guc_engine_suspend(struct xe_engine *e) +static int guc_exec_queue_suspend(struct xe_exec_queue *q) { - struct drm_sched_msg *msg = e->guc->static_msgs + STATIC_MSG_SUSPEND; + struct drm_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_SUSPEND; - if (engine_killed_or_banned(e) || e->guc->suspend_pending) + if (exec_queue_killed_or_banned(q) || q->guc->suspend_pending) return -EINVAL; - e->guc->suspend_pending = true; - guc_engine_add_msg(e, msg, SUSPEND); + q->guc->suspend_pending = true; + guc_exec_queue_add_msg(q, msg, SUSPEND); return 0; } -static void guc_engine_suspend_wait(struct xe_engine *e) +static void guc_exec_queue_suspend_wait(struct xe_exec_queue *q) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); - wait_event(e->guc->suspend_wait, !e->guc->suspend_pending || + wait_event(q->guc->suspend_wait, !q->guc->suspend_pending || guc_read_stopped(guc)); } -static void guc_engine_resume(struct xe_engine *e) +static void guc_exec_queue_resume(struct xe_exec_queue *q) { - struct drm_sched_msg *msg = e->guc->static_msgs + STATIC_MSG_RESUME; + struct drm_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_RESUME; - XE_WARN_ON(e->guc->suspend_pending); + XE_WARN_ON(q->guc->suspend_pending); - guc_engine_add_msg(e, msg, RESUME); + guc_exec_queue_add_msg(q, msg, RESUME); } /* @@ -1328,49 +1328,49 @@ static void guc_engine_resume(struct xe_engine *e) * really shouldn't do much other than trap into the DRM scheduler which * synchronizes these operations. */ -static const struct xe_engine_ops guc_engine_ops = { - .init = guc_engine_init, - .kill = guc_engine_kill, - .fini = guc_engine_fini, - .set_priority = guc_engine_set_priority, - .set_timeslice = guc_engine_set_timeslice, - .set_preempt_timeout = guc_engine_set_preempt_timeout, - .set_job_timeout = guc_engine_set_job_timeout, - .suspend = guc_engine_suspend, - .suspend_wait = guc_engine_suspend_wait, - .resume = guc_engine_resume, +static const struct xe_exec_queue_ops guc_exec_queue_ops = { + .init = guc_exec_queue_init, + .kill = guc_exec_queue_kill, + .fini = guc_exec_queue_fini, + .set_priority = guc_exec_queue_set_priority, + .set_timeslice = guc_exec_queue_set_timeslice, + .set_preempt_timeout = guc_exec_queue_set_preempt_timeout, + .set_job_timeout = guc_exec_queue_set_job_timeout, + .suspend = guc_exec_queue_suspend, + .suspend_wait = guc_exec_queue_suspend_wait, + .resume = guc_exec_queue_resume, }; -static void guc_engine_stop(struct xe_guc *guc, struct xe_engine *e) +static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q) { - struct drm_gpu_scheduler *sched = &e->guc->sched; + struct drm_gpu_scheduler *sched = &q->guc->sched; /* Stop scheduling + flush any DRM scheduler operations */ drm_sched_run_wq_stop(sched); /* Clean up lost G2H + reset engine state */ - if (engine_registered(e)) { - if ((engine_banned(e) && engine_destroyed(e)) || - xe_engine_is_lr(e)) - xe_engine_put(e); - else if (engine_destroyed(e)) - __guc_engine_fini(guc, e); + if (exec_queue_registered(q)) { + if ((exec_queue_banned(q) && exec_queue_destroyed(q)) || + xe_exec_queue_is_lr(q)) + xe_exec_queue_put(q); + else if (exec_queue_destroyed(q)) + __guc_exec_queue_fini(guc, q); } - if (e->guc->suspend_pending) { - set_engine_suspended(e); - suspend_fence_signal(e); + if (q->guc->suspend_pending) { + set_exec_queue_suspended(q); + suspend_fence_signal(q); } - atomic_and(ENGINE_STATE_DESTROYED | ENGINE_STATE_SUSPENDED, - &e->guc->state); - e->guc->resume_time = 0; - trace_xe_engine_stop(e); + atomic_and(EXEC_QUEUE_STATE_DESTROYED | ENGINE_STATE_SUSPENDED, + &q->guc->state); + q->guc->resume_time = 0; + trace_xe_exec_queue_stop(q); /* * Ban any engine (aside from kernel and engines used for VM ops) with a * started but not complete job or if a job has gone through a GT reset * more than twice. */ - if (!(e->flags & (ENGINE_FLAG_KERNEL | ENGINE_FLAG_VM))) { + if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) { struct drm_sched_job *drm_job = list_first_entry_or_null(&sched->pending_list, struct drm_sched_job, list); @@ -1383,7 +1383,7 @@ static void guc_engine_stop(struct xe_guc *guc, struct xe_engine *e) drm_sched_invalidate_job(drm_job, 2)) { trace_xe_sched_job_ban(job); sched->timeout = MIN_SCHED_TIMEOUT; - set_engine_banned(e); + set_exec_queue_banned(q); } } } @@ -1414,15 +1414,15 @@ void xe_guc_submit_reset_wait(struct xe_guc *guc) int xe_guc_submit_stop(struct xe_guc *guc) { - struct xe_engine *e; + struct xe_exec_queue *q; unsigned long index; XE_WARN_ON(guc_read_stopped(guc) != 1); mutex_lock(&guc->submission_state.lock); - xa_for_each(&guc->submission_state.engine_lookup, index, e) - guc_engine_stop(guc, e); + xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) + guc_exec_queue_stop(guc, q); mutex_unlock(&guc->submission_state.lock); @@ -1434,16 +1434,16 @@ int xe_guc_submit_stop(struct xe_guc *guc) return 0; } -static void guc_engine_start(struct xe_engine *e) +static void guc_exec_queue_start(struct xe_exec_queue *q) { - struct drm_gpu_scheduler *sched = &e->guc->sched; + struct drm_gpu_scheduler *sched = &q->guc->sched; - if (!engine_killed_or_banned(e)) { + if (!exec_queue_killed_or_banned(q)) { int i; - trace_xe_engine_resubmit(e); - for (i = 0; i < e->width; ++i) - xe_lrc_set_ring_head(e->lrc + i, e->lrc[i].ring.tail); + trace_xe_exec_queue_resubmit(q); + for (i = 0; i < q->width; ++i) + xe_lrc_set_ring_head(q->lrc + i, q->lrc[i].ring.tail); drm_sched_resubmit_jobs(sched); } @@ -1453,15 +1453,15 @@ static void guc_engine_start(struct xe_engine *e) int xe_guc_submit_start(struct xe_guc *guc) { - struct xe_engine *e; + struct xe_exec_queue *q; unsigned long index; XE_WARN_ON(guc_read_stopped(guc) != 1); mutex_lock(&guc->submission_state.lock); atomic_dec(&guc->submission_state.stopped); - xa_for_each(&guc->submission_state.engine_lookup, index, e) - guc_engine_start(e); + xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) + guc_exec_queue_start(q); mutex_unlock(&guc->submission_state.lock); wake_up_all(&guc->ct.wq); @@ -1469,36 +1469,36 @@ int xe_guc_submit_start(struct xe_guc *guc) return 0; } -static struct xe_engine * -g2h_engine_lookup(struct xe_guc *guc, u32 guc_id) +static struct xe_exec_queue * +g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id) { struct xe_device *xe = guc_to_xe(guc); - struct xe_engine *e; + struct xe_exec_queue *q; if (unlikely(guc_id >= GUC_ID_MAX)) { drm_err(&xe->drm, "Invalid guc_id %u", guc_id); return NULL; } - e = xa_load(&guc->submission_state.engine_lookup, guc_id); - if (unlikely(!e)) { + q = xa_load(&guc->submission_state.exec_queue_lookup, guc_id); + if (unlikely(!q)) { drm_err(&xe->drm, "Not engine present for guc_id %u", guc_id); return NULL; } - XE_WARN_ON(e->guc->id != guc_id); + XE_WARN_ON(q->guc->id != guc_id); - return e; + return q; } -static void deregister_engine(struct xe_guc *guc, struct xe_engine *e) +static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q) { u32 action[] = { XE_GUC_ACTION_DEREGISTER_CONTEXT, - e->guc->id, + q->guc->id, }; - trace_xe_engine_deregister(e); + trace_xe_exec_queue_deregister(q); xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action)); } @@ -1506,7 +1506,7 @@ static void deregister_engine(struct xe_guc *guc, struct xe_engine *e) int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) { struct xe_device *xe = guc_to_xe(guc); - struct xe_engine *e; + struct xe_exec_queue *q; u32 guc_id = msg[0]; if (unlikely(len < 2)) { @@ -1514,34 +1514,34 @@ int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) return -EPROTO; } - e = g2h_engine_lookup(guc, guc_id); - if (unlikely(!e)) + q = g2h_exec_queue_lookup(guc, guc_id); + if (unlikely(!q)) return -EPROTO; - if (unlikely(!engine_pending_enable(e) && - !engine_pending_disable(e))) { + if (unlikely(!exec_queue_pending_enable(q) && + !exec_queue_pending_disable(q))) { drm_err(&xe->drm, "Unexpected engine state 0x%04x", - atomic_read(&e->guc->state)); + atomic_read(&q->guc->state)); return -EPROTO; } - trace_xe_engine_scheduling_done(e); + trace_xe_exec_queue_scheduling_done(q); - if (engine_pending_enable(e)) { - e->guc->resume_time = ktime_get(); - clear_engine_pending_enable(e); + if (exec_queue_pending_enable(q)) { + q->guc->resume_time = ktime_get(); + clear_exec_queue_pending_enable(q); smp_wmb(); wake_up_all(&guc->ct.wq); } else { - clear_engine_pending_disable(e); - if (e->guc->suspend_pending) { - suspend_fence_signal(e); + clear_exec_queue_pending_disable(q); + if (q->guc->suspend_pending) { + suspend_fence_signal(q); } else { - if (engine_banned(e)) { + if (exec_queue_banned(q)) { smp_wmb(); wake_up_all(&guc->ct.wq); } - deregister_engine(guc, e); + deregister_exec_queue(guc, q); } } @@ -1551,7 +1551,7 @@ int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len) { struct xe_device *xe = guc_to_xe(guc); - struct xe_engine *e; + struct xe_exec_queue *q; u32 guc_id = msg[0]; if (unlikely(len < 1)) { @@ -1559,33 +1559,33 @@ int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len) return -EPROTO; } - e = g2h_engine_lookup(guc, guc_id); - if (unlikely(!e)) + q = g2h_exec_queue_lookup(guc, guc_id); + if (unlikely(!q)) return -EPROTO; - if (!engine_destroyed(e) || engine_pending_disable(e) || - engine_pending_enable(e) || engine_enabled(e)) { + if (!exec_queue_destroyed(q) || exec_queue_pending_disable(q) || + exec_queue_pending_enable(q) || exec_queue_enabled(q)) { drm_err(&xe->drm, "Unexpected engine state 0x%04x", - atomic_read(&e->guc->state)); + atomic_read(&q->guc->state)); return -EPROTO; } - trace_xe_engine_deregister_done(e); + trace_xe_exec_queue_deregister_done(q); - clear_engine_registered(e); + clear_exec_queue_registered(q); - if (engine_banned(e) || xe_engine_is_lr(e)) - xe_engine_put(e); + if (exec_queue_banned(q) || xe_exec_queue_is_lr(q)) + xe_exec_queue_put(q); else - __guc_engine_fini(guc, e); + __guc_exec_queue_fini(guc, q); return 0; } -int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) +int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) { struct xe_device *xe = guc_to_xe(guc); - struct xe_engine *e; + struct xe_exec_queue *q; u32 guc_id = msg[0]; if (unlikely(len < 1)) { @@ -1593,34 +1593,34 @@ int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) return -EPROTO; } - e = g2h_engine_lookup(guc, guc_id); - if (unlikely(!e)) + q = g2h_exec_queue_lookup(guc, guc_id); + if (unlikely(!q)) return -EPROTO; drm_warn(&xe->drm, "Engine reset: guc_id=%d", guc_id); /* FIXME: Do error capture, most likely async */ - trace_xe_engine_reset(e); + trace_xe_exec_queue_reset(q); /* * A banned engine is a NOP at this point (came from - * guc_engine_timedout_job). Otherwise, kick drm scheduler to cancel + * guc_exec_queue_timedout_job). Otherwise, kick drm scheduler to cancel * jobs by setting timeout of the job to the minimum value kicking - * guc_engine_timedout_job. + * guc_exec_queue_timedout_job. */ - set_engine_reset(e); - if (!engine_banned(e)) - xe_guc_engine_trigger_cleanup(e); + set_exec_queue_reset(q); + if (!exec_queue_banned(q)) + xe_guc_exec_queue_trigger_cleanup(q); return 0; } -int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, - u32 len) +int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, + u32 len) { struct xe_device *xe = guc_to_xe(guc); - struct xe_engine *e; + struct xe_exec_queue *q; u32 guc_id = msg[0]; if (unlikely(len < 1)) { @@ -1628,22 +1628,22 @@ int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, return -EPROTO; } - e = g2h_engine_lookup(guc, guc_id); - if (unlikely(!e)) + q = g2h_exec_queue_lookup(guc, guc_id); + if (unlikely(!q)) return -EPROTO; drm_warn(&xe->drm, "Engine memory cat error: guc_id=%d", guc_id); - trace_xe_engine_memory_cat_error(e); + trace_xe_exec_queue_memory_cat_error(q); /* Treat the same as engine reset */ - set_engine_reset(e); - if (!engine_banned(e)) - xe_guc_engine_trigger_cleanup(e); + set_exec_queue_reset(q); + if (!exec_queue_banned(q)) + xe_guc_exec_queue_trigger_cleanup(q); return 0; } -int xe_guc_engine_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) +int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) { struct xe_device *xe = guc_to_xe(guc); u8 guc_class, instance; @@ -1668,16 +1668,16 @@ int xe_guc_engine_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) } static void -guc_engine_wq_snapshot_capture(struct xe_engine *e, - struct xe_guc_submit_engine_snapshot *snapshot) +guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q, + struct xe_guc_submit_exec_queue_snapshot *snapshot) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); struct xe_device *xe = guc_to_xe(guc); - struct iosys_map map = xe_lrc_parallel_map(e->lrc); + struct iosys_map map = xe_lrc_parallel_map(q->lrc); int i; - snapshot->guc.wqi_head = e->guc->wqi_head; - snapshot->guc.wqi_tail = e->guc->wqi_tail; + snapshot->guc.wqi_head = q->guc->wqi_head; + snapshot->guc.wqi_tail = q->guc->wqi_tail; snapshot->parallel.wq_desc.head = parallel_read(xe, map, wq_desc.head); snapshot->parallel.wq_desc.tail = parallel_read(xe, map, wq_desc.tail); snapshot->parallel.wq_desc.status = parallel_read(xe, map, @@ -1694,8 +1694,8 @@ guc_engine_wq_snapshot_capture(struct xe_engine *e, } static void -guc_engine_wq_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, - struct drm_printer *p) +guc_exec_queue_wq_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, + struct drm_printer *p) { int i; @@ -1716,23 +1716,23 @@ guc_engine_wq_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, } /** - * xe_guc_engine_snapshot_capture - Take a quick snapshot of the GuC Engine. + * xe_guc_exec_queue_snapshot_capture - Take a quick snapshot of the GuC Engine. * @e: Xe Engine. * * This can be printed out in a later stage like during dev_coredump * analysis. * * Returns: a GuC Submit Engine snapshot object that must be freed by the - * caller, using `xe_guc_engine_snapshot_free`. + * caller, using `xe_guc_exec_queue_snapshot_free`. */ -struct xe_guc_submit_engine_snapshot * -xe_guc_engine_snapshot_capture(struct xe_engine *e) +struct xe_guc_submit_exec_queue_snapshot * +xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q) { - struct xe_guc *guc = engine_to_guc(e); + struct xe_guc *guc = exec_queue_to_guc(q); struct xe_device *xe = guc_to_xe(guc); - struct drm_gpu_scheduler *sched = &e->guc->sched; + struct drm_gpu_scheduler *sched = &q->guc->sched; struct xe_sched_job *job; - struct xe_guc_submit_engine_snapshot *snapshot; + struct xe_guc_submit_exec_queue_snapshot *snapshot; int i; snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); @@ -1742,25 +1742,25 @@ xe_guc_engine_snapshot_capture(struct xe_engine *e) return NULL; } - snapshot->guc.id = e->guc->id; - memcpy(&snapshot->name, &e->name, sizeof(snapshot->name)); - snapshot->class = e->class; - snapshot->logical_mask = e->logical_mask; - snapshot->width = e->width; - snapshot->refcount = kref_read(&e->refcount); + snapshot->guc.id = q->guc->id; + memcpy(&snapshot->name, &q->name, sizeof(snapshot->name)); + snapshot->class = q->class; + snapshot->logical_mask = q->logical_mask; + snapshot->width = q->width; + snapshot->refcount = kref_read(&q->refcount); snapshot->sched_timeout = sched->timeout; - snapshot->sched_props.timeslice_us = e->sched_props.timeslice_us; + snapshot->sched_props.timeslice_us = q->sched_props.timeslice_us; snapshot->sched_props.preempt_timeout_us = - e->sched_props.preempt_timeout_us; + q->sched_props.preempt_timeout_us; - snapshot->lrc = kmalloc_array(e->width, sizeof(struct lrc_snapshot), + snapshot->lrc = kmalloc_array(q->width, sizeof(struct lrc_snapshot), GFP_ATOMIC); if (!snapshot->lrc) { drm_err(&xe->drm, "Skipping GuC Engine LRC snapshot.\n"); } else { - for (i = 0; i < e->width; ++i) { - struct xe_lrc *lrc = e->lrc + i; + for (i = 0; i < q->width; ++i) { + struct xe_lrc *lrc = q->lrc + i; snapshot->lrc[i].context_desc = lower_32_bits(xe_lrc_ggtt_addr(lrc)); @@ -1773,12 +1773,12 @@ xe_guc_engine_snapshot_capture(struct xe_engine *e) } } - snapshot->schedule_state = atomic_read(&e->guc->state); - snapshot->engine_flags = e->flags; + snapshot->schedule_state = atomic_read(&q->guc->state); + snapshot->exec_queue_flags = q->flags; - snapshot->parallel_execution = xe_engine_is_parallel(e); + snapshot->parallel_execution = xe_exec_queue_is_parallel(q); if (snapshot->parallel_execution) - guc_engine_wq_snapshot_capture(e, snapshot); + guc_exec_queue_wq_snapshot_capture(q, snapshot); spin_lock(&sched->job_list_lock); snapshot->pending_list_size = list_count_nodes(&sched->pending_list); @@ -1808,15 +1808,15 @@ xe_guc_engine_snapshot_capture(struct xe_engine *e) } /** - * xe_guc_engine_snapshot_print - Print out a given GuC Engine snapshot. + * xe_guc_exec_queue_snapshot_print - Print out a given GuC Engine snapshot. * @snapshot: GuC Submit Engine snapshot object. * @p: drm_printer where it will be printed out. * * This function prints out a given GuC Submit Engine snapshot object. */ void -xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, - struct drm_printer *p) +xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, + struct drm_printer *p) { int i; @@ -1848,10 +1848,10 @@ xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, drm_printf(p, "\tSeqno: (memory) %d\n", snapshot->lrc[i].seqno); } drm_printf(p, "\tSchedule State: 0x%x\n", snapshot->schedule_state); - drm_printf(p, "\tFlags: 0x%lx\n", snapshot->engine_flags); + drm_printf(p, "\tFlags: 0x%lx\n", snapshot->exec_queue_flags); if (snapshot->parallel_execution) - guc_engine_wq_snapshot_print(snapshot, p); + guc_exec_queue_wq_snapshot_print(snapshot, p); for (i = 0; snapshot->pending_list && i < snapshot->pending_list_size; i++) @@ -1862,14 +1862,14 @@ xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, } /** - * xe_guc_engine_snapshot_free - Free all allocated objects for a given + * xe_guc_exec_queue_snapshot_free - Free all allocated objects for a given * snapshot. * @snapshot: GuC Submit Engine snapshot object. * * This function free all the memory that needed to be allocated at capture * time. */ -void xe_guc_engine_snapshot_free(struct xe_guc_submit_engine_snapshot *snapshot) +void xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot) { if (!snapshot) return; @@ -1879,13 +1879,13 @@ void xe_guc_engine_snapshot_free(struct xe_guc_submit_engine_snapshot *snapshot) kfree(snapshot); } -static void guc_engine_print(struct xe_engine *e, struct drm_printer *p) +static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p) { - struct xe_guc_submit_engine_snapshot *snapshot; + struct xe_guc_submit_exec_queue_snapshot *snapshot; - snapshot = xe_guc_engine_snapshot_capture(e); - xe_guc_engine_snapshot_print(snapshot, p); - xe_guc_engine_snapshot_free(snapshot); + snapshot = xe_guc_exec_queue_snapshot_capture(q); + xe_guc_exec_queue_snapshot_print(snapshot, p); + xe_guc_exec_queue_snapshot_free(snapshot); } /** @@ -1897,14 +1897,14 @@ static void guc_engine_print(struct xe_engine *e, struct drm_printer *p) */ void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p) { - struct xe_engine *e; + struct xe_exec_queue *q; unsigned long index; if (!xe_device_guc_submission_enabled(guc_to_xe(guc))) return; mutex_lock(&guc->submission_state.lock); - xa_for_each(&guc->submission_state.engine_lookup, index, e) - guc_engine_print(e, p); + xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) + guc_exec_queue_print(q, p); mutex_unlock(&guc->submission_state.lock); } diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h index 4153c2d22013..fc97869c5b86 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit.h +++ b/drivers/gpu/drm/xe/xe_guc_submit.h @@ -9,7 +9,7 @@ #include <linux/types.h> struct drm_printer; -struct xe_engine; +struct xe_exec_queue; struct xe_guc; int xe_guc_submit_init(struct xe_guc *guc); @@ -21,18 +21,18 @@ int xe_guc_submit_start(struct xe_guc *guc); int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len); int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len); -int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len); -int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, - u32 len); -int xe_guc_engine_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len); +int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len); +int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, + u32 len); +int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len); -struct xe_guc_submit_engine_snapshot * -xe_guc_engine_snapshot_capture(struct xe_engine *e); +struct xe_guc_submit_exec_queue_snapshot * +xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q); void -xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, - struct drm_printer *p); +xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, + struct drm_printer *p); void -xe_guc_engine_snapshot_free(struct xe_guc_submit_engine_snapshot *snapshot); +xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot); void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p); #endif diff --git a/drivers/gpu/drm/xe/xe_guc_submit_types.h b/drivers/gpu/drm/xe/xe_guc_submit_types.h index 6765b2c6eab1..649b0a852692 100644 --- a/drivers/gpu/drm/xe/xe_guc_submit_types.h +++ b/drivers/gpu/drm/xe/xe_guc_submit_types.h @@ -79,20 +79,20 @@ struct pending_list_snapshot { }; /** - * struct xe_guc_submit_engine_snapshot - Snapshot for devcoredump + * struct xe_guc_submit_exec_queue_snapshot - Snapshot for devcoredump */ -struct xe_guc_submit_engine_snapshot { - /** @name: name of this engine */ +struct xe_guc_submit_exec_queue_snapshot { + /** @name: name of this exec queue */ char name[MAX_FENCE_NAME_LEN]; - /** @class: class of this engine */ + /** @class: class of this exec queue */ enum xe_engine_class class; /** - * @logical_mask: logical mask of where job submitted to engine can run + * @logical_mask: logical mask of where job submitted to exec queue can run */ u32 logical_mask; - /** @width: width (number BB submitted per exec) of this engine */ + /** @width: width (number BB submitted per exec) of this exec queue */ u16 width; - /** @refcount: ref count of this engine */ + /** @refcount: ref count of this exec queue */ u32 refcount; /** * @sched_timeout: the time after which a job is removed from the @@ -113,8 +113,8 @@ struct xe_guc_submit_engine_snapshot { /** @schedule_state: Schedule State at the moment of Crash */ u32 schedule_state; - /** @engine_flags: Flags of the faulty engine */ - unsigned long engine_flags; + /** @exec_queue_flags: Flags of the faulty exec_queue */ + unsigned long exec_queue_flags; /** @guc: GuC Engine Snapshot */ struct { @@ -122,7 +122,7 @@ struct xe_guc_submit_engine_snapshot { u32 wqi_head; /** @wqi_tail: work queue item tail */ u32 wqi_tail; - /** @id: GuC id for this xe_engine */ + /** @id: GuC id for this exec_queue */ u16 id; } guc; diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h index a304dce4e9f4..a5e58917a499 100644 --- a/drivers/gpu/drm/xe/xe_guc_types.h +++ b/drivers/gpu/drm/xe/xe_guc_types.h @@ -33,8 +33,8 @@ struct xe_guc { struct xe_guc_pc pc; /** @submission_state: GuC submission state */ struct { - /** @engine_lookup: Lookup an xe_engine from guc_id */ - struct xarray engine_lookup; + /** @exec_queue_lookup: Lookup an xe_engine from guc_id */ + struct xarray exec_queue_lookup; /** @guc_ids: used to allocate new guc_ids, single-lrc */ struct ida guc_ids; /** @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc */ diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c index 05f3d8d68379..09db8da261a3 100644 --- a/drivers/gpu/drm/xe/xe_lrc.c +++ b/drivers/gpu/drm/xe/xe_lrc.c @@ -12,7 +12,7 @@ #include "regs/xe_regs.h" #include "xe_bo.h" #include "xe_device.h" -#include "xe_engine_types.h" +#include "xe_exec_queue_types.h" #include "xe_gt.h" #include "xe_hw_fence.h" #include "xe_map.h" @@ -604,7 +604,7 @@ static void xe_lrc_set_ppgtt(struct xe_lrc *lrc, struct xe_vm *vm) #define ACC_NOTIFY_S 16 int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, - struct xe_engine *e, struct xe_vm *vm, u32 ring_size) + struct xe_exec_queue *q, struct xe_vm *vm, u32 ring_size) { struct xe_gt *gt = hwe->gt; struct xe_tile *tile = gt_to_tile(gt); @@ -669,12 +669,12 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, RING_CTL_SIZE(lrc->ring.size) | RING_VALID); if (xe->info.has_asid && vm) xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID, - (e->usm.acc_granularity << + (q->usm.acc_granularity << ACC_GRANULARITY_S) | vm->usm.asid); if (xe->info.supports_usm && vm) xe_lrc_write_ctx_reg(lrc, PVC_CTX_ACC_CTR_THOLD, - (e->usm.acc_notify << ACC_NOTIFY_S) | - e->usm.acc_trigger); + (q->usm.acc_notify << ACC_NOTIFY_S) | + q->usm.acc_trigger); lrc->desc = GEN8_CTX_VALID; lrc->desc |= INTEL_LEGACY_64B_CONTEXT << GEN8_CTX_ADDRESSING_MODE_SHIFT; diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h index e37f89e75ef8..3a6e8fc5a837 100644 --- a/drivers/gpu/drm/xe/xe_lrc.h +++ b/drivers/gpu/drm/xe/xe_lrc.h @@ -8,7 +8,7 @@ #include "xe_lrc_types.h" struct xe_device; -struct xe_engine; +struct xe_exec_queue; enum xe_engine_class; struct xe_hw_engine; struct xe_vm; @@ -16,7 +16,7 @@ struct xe_vm; #define LRC_PPHWSP_SCRATCH_ADDR (0x34 * 4) int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, - struct xe_engine *e, struct xe_vm *vm, u32 ring_size); + struct xe_exec_queue *q, struct xe_vm *vm, u32 ring_size); void xe_lrc_finish(struct xe_lrc *lrc); size_t xe_lrc_size(struct xe_device *xe, enum xe_engine_class class); diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c index 414f93cddb28..7af2d74833c0 100644 --- a/drivers/gpu/drm/xe/xe_migrate.c +++ b/drivers/gpu/drm/xe/xe_migrate.c @@ -16,7 +16,7 @@ #include "tests/xe_test.h" #include "xe_bb.h" #include "xe_bo.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_ggtt.h" #include "xe_gt.h" #include "xe_hw_engine.h" @@ -35,7 +35,7 @@ */ struct xe_migrate { /** @eng: Default engine used for migration */ - struct xe_engine *eng; + struct xe_exec_queue *q; /** @tile: Backpointer to the tile this struct xe_migrate belongs to. */ struct xe_tile *tile; /** @job_mutex: Timeline mutex for @eng. */ @@ -78,9 +78,9 @@ struct xe_migrate { * * Return: The default migrate engine */ -struct xe_engine *xe_tile_migrate_engine(struct xe_tile *tile) +struct xe_exec_queue *xe_tile_migrate_engine(struct xe_tile *tile) { - return tile->migrate->eng; + return tile->migrate->q; } static void xe_migrate_fini(struct drm_device *dev, void *arg) @@ -88,11 +88,11 @@ static void xe_migrate_fini(struct drm_device *dev, void *arg) struct xe_migrate *m = arg; struct ww_acquire_ctx ww; - xe_vm_lock(m->eng->vm, &ww, 0, false); + xe_vm_lock(m->q->vm, &ww, 0, false); xe_bo_unpin(m->pt_bo); if (m->cleared_bo) xe_bo_unpin(m->cleared_bo); - xe_vm_unlock(m->eng->vm, &ww); + xe_vm_unlock(m->q->vm, &ww); dma_fence_put(m->fence); if (m->cleared_bo) @@ -100,8 +100,8 @@ static void xe_migrate_fini(struct drm_device *dev, void *arg) xe_bo_put(m->pt_bo); drm_suballoc_manager_fini(&m->vm_update_sa); mutex_destroy(&m->job_mutex); - xe_vm_close_and_put(m->eng->vm); - xe_engine_put(m->eng); + xe_vm_close_and_put(m->q->vm); + xe_exec_queue_put(m->q); } static u64 xe_migrate_vm_addr(u64 slot, u32 level) @@ -341,20 +341,20 @@ struct xe_migrate *xe_migrate_init(struct xe_tile *tile) if (!hwe) return ERR_PTR(-EINVAL); - m->eng = xe_engine_create(xe, vm, - BIT(hwe->logical_instance), 1, - hwe, ENGINE_FLAG_KERNEL); + m->q = xe_exec_queue_create(xe, vm, + BIT(hwe->logical_instance), 1, + hwe, EXEC_QUEUE_FLAG_KERNEL); } else { - m->eng = xe_engine_create_class(xe, primary_gt, vm, - XE_ENGINE_CLASS_COPY, - ENGINE_FLAG_KERNEL); + m->q = xe_exec_queue_create_class(xe, primary_gt, vm, + XE_ENGINE_CLASS_COPY, + EXEC_QUEUE_FLAG_KERNEL); } - if (IS_ERR(m->eng)) { + if (IS_ERR(m->q)) { xe_vm_close_and_put(vm); - return ERR_CAST(m->eng); + return ERR_CAST(m->q); } if (xe->info.supports_usm) - m->eng->entity->priority = DRM_SCHED_PRIORITY_KERNEL; + m->q->entity->priority = DRM_SCHED_PRIORITY_KERNEL; mutex_init(&m->job_mutex); @@ -456,7 +456,7 @@ static void emit_pte(struct xe_migrate *m, addr = xe_res_dma(cur) & PAGE_MASK; if (is_vram) { /* Is this a 64K PTE entry? */ - if ((m->eng->vm->flags & XE_VM_FLAG_64K) && + if ((m->q->vm->flags & XE_VM_FLAG_64K) && !(cur_ofs & (16 * 8 - 1))) { XE_WARN_ON(!IS_ALIGNED(addr, SZ_64K)); addr |= XE_PTE_PS64; @@ -714,7 +714,7 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m, src_L0, ccs_ofs, copy_ccs); mutex_lock(&m->job_mutex); - job = xe_bb_create_migration_job(m->eng, bb, + job = xe_bb_create_migration_job(m->q, bb, xe_migrate_batch_base(m, usm), update_idx); if (IS_ERR(job)) { @@ -938,7 +938,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m, } mutex_lock(&m->job_mutex); - job = xe_bb_create_migration_job(m->eng, bb, + job = xe_bb_create_migration_job(m->q, bb, xe_migrate_batch_base(m, usm), update_idx); if (IS_ERR(job)) { @@ -1024,7 +1024,7 @@ static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs, struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m) { - return xe_vm_get(m->eng->vm); + return xe_vm_get(m->q->vm); } #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) @@ -1132,7 +1132,7 @@ struct dma_fence * xe_migrate_update_pgtables(struct xe_migrate *m, struct xe_vm *vm, struct xe_bo *bo, - struct xe_engine *eng, + struct xe_exec_queue *q, const struct xe_vm_pgtable_update *updates, u32 num_updates, struct xe_sync_entry *syncs, u32 num_syncs, @@ -1150,13 +1150,13 @@ xe_migrate_update_pgtables(struct xe_migrate *m, u32 i, batch_size, ppgtt_ofs, update_idx, page_ofs = 0; u64 addr; int err = 0; - bool usm = !eng && xe->info.supports_usm; + bool usm = !q && xe->info.supports_usm; bool first_munmap_rebind = vma && vma->gpuva.flags & XE_VMA_FIRST_REBIND; - struct xe_engine *eng_override = !eng ? m->eng : eng; + struct xe_exec_queue *q_override = !q ? m->q : q; /* Use the CPU if no in syncs and engine is idle */ - if (no_in_syncs(syncs, num_syncs) && xe_engine_is_idle(eng_override)) { + if (no_in_syncs(syncs, num_syncs) && xe_exec_queue_is_idle(q_override)) { fence = xe_migrate_update_pgtables_cpu(m, vm, bo, updates, num_updates, first_munmap_rebind, @@ -1186,14 +1186,14 @@ xe_migrate_update_pgtables(struct xe_migrate *m, */ XE_WARN_ON(batch_size >= SZ_128K); - bb = xe_bb_new(gt, batch_size, !eng && xe->info.supports_usm); + bb = xe_bb_new(gt, batch_size, !q && xe->info.supports_usm); if (IS_ERR(bb)) return ERR_CAST(bb); /* For sysmem PTE's, need to map them in our hole.. */ if (!IS_DGFX(xe)) { ppgtt_ofs = NUM_KERNEL_PDE - 1; - if (eng) { + if (q) { XE_WARN_ON(num_updates > NUM_VMUSA_WRITES_PER_UNIT); sa_bo = drm_suballoc_new(&m->vm_update_sa, 1, @@ -1249,10 +1249,10 @@ xe_migrate_update_pgtables(struct xe_migrate *m, write_pgtable(tile, bb, 0, &updates[i], pt_update); } - if (!eng) + if (!q) mutex_lock(&m->job_mutex); - job = xe_bb_create_migration_job(eng ?: m->eng, bb, + job = xe_bb_create_migration_job(q ?: m->q, bb, xe_migrate_batch_base(m, usm), update_idx); if (IS_ERR(job)) { @@ -1295,7 +1295,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m, fence = dma_fence_get(&job->drm.s_fence->finished); xe_sched_job_push(job); - if (!eng) + if (!q) mutex_unlock(&m->job_mutex); xe_bb_free(bb, fence); @@ -1306,7 +1306,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m, err_job: xe_sched_job_put(job); err_bb: - if (!eng) + if (!q) mutex_unlock(&m->job_mutex); xe_bb_free(bb, NULL); err: diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h index 0d62aff6421c..c729241776ad 100644 --- a/drivers/gpu/drm/xe/xe_migrate.h +++ b/drivers/gpu/drm/xe/xe_migrate.h @@ -14,7 +14,7 @@ struct ttm_resource; struct xe_bo; struct xe_gt; -struct xe_engine; +struct xe_exec_queue; struct xe_migrate; struct xe_migrate_pt_update; struct xe_sync_entry; @@ -97,7 +97,7 @@ struct dma_fence * xe_migrate_update_pgtables(struct xe_migrate *m, struct xe_vm *vm, struct xe_bo *bo, - struct xe_engine *eng, + struct xe_exec_queue *q, const struct xe_vm_pgtable_update *updates, u32 num_updates, struct xe_sync_entry *syncs, u32 num_syncs, @@ -105,5 +105,5 @@ xe_migrate_update_pgtables(struct xe_migrate *m, void xe_migrate_wait(struct xe_migrate *m); -struct xe_engine *xe_tile_migrate_engine(struct xe_tile *tile); +struct xe_exec_queue *xe_tile_migrate_engine(struct xe_tile *tile); #endif diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c index ccc852500eda..c9653978fc9f 100644 --- a/drivers/gpu/drm/xe/xe_mocs.c +++ b/drivers/gpu/drm/xe/xe_mocs.c @@ -8,7 +8,7 @@ #include "regs/xe_gt_regs.h" #include "xe_bo.h" #include "xe_device.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_gt.h" #include "xe_mmio.h" #include "xe_platform_types.h" diff --git a/drivers/gpu/drm/xe/xe_mocs.h b/drivers/gpu/drm/xe/xe_mocs.h index 25f7b35a76da..d0f1ec4b0336 100644 --- a/drivers/gpu/drm/xe/xe_mocs.h +++ b/drivers/gpu/drm/xe/xe_mocs.h @@ -8,7 +8,7 @@ #include <linux/types.h> -struct xe_engine; +struct xe_exec_queue; struct xe_gt; void xe_mocs_init_early(struct xe_gt *gt); diff --git a/drivers/gpu/drm/xe/xe_preempt_fence.c b/drivers/gpu/drm/xe/xe_preempt_fence.c index 219eefeb90ff..e0ce1588a734 100644 --- a/drivers/gpu/drm/xe/xe_preempt_fence.c +++ b/drivers/gpu/drm/xe/xe_preempt_fence.c @@ -7,7 +7,7 @@ #include <linux/slab.h> -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_vm.h" static void preempt_fence_work_func(struct work_struct *w) @@ -15,19 +15,19 @@ static void preempt_fence_work_func(struct work_struct *w) bool cookie = dma_fence_begin_signalling(); struct xe_preempt_fence *pfence = container_of(w, typeof(*pfence), preempt_work); - struct xe_engine *e = pfence->engine; + struct xe_exec_queue *q = pfence->q; if (pfence->error) dma_fence_set_error(&pfence->base, pfence->error); else - e->ops->suspend_wait(e); + q->ops->suspend_wait(q); dma_fence_signal(&pfence->base); dma_fence_end_signalling(cookie); - xe_vm_queue_rebind_worker(e->vm); + xe_vm_queue_rebind_worker(q->vm); - xe_engine_put(e); + xe_exec_queue_put(q); } static const char * @@ -46,9 +46,9 @@ static bool preempt_fence_enable_signaling(struct dma_fence *fence) { struct xe_preempt_fence *pfence = container_of(fence, typeof(*pfence), base); - struct xe_engine *e = pfence->engine; + struct xe_exec_queue *q = pfence->q; - pfence->error = e->ops->suspend(e); + pfence->error = q->ops->suspend(q); queue_work(system_unbound_wq, &pfence->preempt_work); return true; } @@ -104,43 +104,43 @@ void xe_preempt_fence_free(struct xe_preempt_fence *pfence) * xe_preempt_fence_alloc(). * @pfence: The struct xe_preempt_fence pointer returned from * xe_preempt_fence_alloc(). - * @e: The struct xe_engine used for arming. + * @e: The struct xe_exec_queue used for arming. * @context: The dma-fence context used for arming. * @seqno: The dma-fence seqno used for arming. * * Inserts the preempt fence into @context's timeline, takes @link off any - * list, and registers the struct xe_engine as the xe_engine to be preempted. + * list, and registers the struct xe_exec_queue as the xe_engine to be preempted. * * Return: A pointer to a struct dma_fence embedded into the preempt fence. * This function doesn't error. */ struct dma_fence * -xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_engine *e, +xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_exec_queue *q, u64 context, u32 seqno) { list_del_init(&pfence->link); - pfence->engine = xe_engine_get(e); + pfence->q = xe_exec_queue_get(q); dma_fence_init(&pfence->base, &preempt_fence_ops, - &e->compute.lock, context, seqno); + &q->compute.lock, context, seqno); return &pfence->base; } /** * xe_preempt_fence_create() - Helper to create and arm a preempt fence. - * @e: The struct xe_engine used for arming. + * @e: The struct xe_exec_queue used for arming. * @context: The dma-fence context used for arming. * @seqno: The dma-fence seqno used for arming. * * Allocates and inserts the preempt fence into @context's timeline, - * and registers @e as the struct xe_engine to be preempted. + * and registers @e as the struct xe_exec_queue to be preempted. * * Return: A pointer to the resulting struct dma_fence on success. An error * pointer on error. In particular if allocation fails it returns * ERR_PTR(-ENOMEM); */ struct dma_fence * -xe_preempt_fence_create(struct xe_engine *e, +xe_preempt_fence_create(struct xe_exec_queue *q, u64 context, u32 seqno) { struct xe_preempt_fence *pfence; @@ -149,7 +149,7 @@ xe_preempt_fence_create(struct xe_engine *e, if (IS_ERR(pfence)) return ERR_CAST(pfence); - return xe_preempt_fence_arm(pfence, e, context, seqno); + return xe_preempt_fence_arm(pfence, q, context, seqno); } bool xe_fence_is_xe_preempt(const struct dma_fence *fence) diff --git a/drivers/gpu/drm/xe/xe_preempt_fence.h b/drivers/gpu/drm/xe/xe_preempt_fence.h index 4f3966103203..9406c6fea525 100644 --- a/drivers/gpu/drm/xe/xe_preempt_fence.h +++ b/drivers/gpu/drm/xe/xe_preempt_fence.h @@ -11,7 +11,7 @@ struct list_head; struct dma_fence * -xe_preempt_fence_create(struct xe_engine *e, +xe_preempt_fence_create(struct xe_exec_queue *q, u64 context, u32 seqno); struct xe_preempt_fence *xe_preempt_fence_alloc(void); @@ -19,7 +19,7 @@ struct xe_preempt_fence *xe_preempt_fence_alloc(void); void xe_preempt_fence_free(struct xe_preempt_fence *pfence); struct dma_fence * -xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_engine *e, +xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_exec_queue *q, u64 context, u32 seqno); static inline struct xe_preempt_fence * diff --git a/drivers/gpu/drm/xe/xe_preempt_fence_types.h b/drivers/gpu/drm/xe/xe_preempt_fence_types.h index 9d9efd8ff0ed..176ea1e9e204 100644 --- a/drivers/gpu/drm/xe/xe_preempt_fence_types.h +++ b/drivers/gpu/drm/xe/xe_preempt_fence_types.h @@ -9,12 +9,11 @@ #include <linux/dma-fence.h> #include <linux/workqueue.h> -struct xe_engine; +struct xe_exec_queue; /** * struct xe_preempt_fence - XE preempt fence * - * A preemption fence which suspends the execution of an xe_engine on the * hardware and triggers a callback once the xe_engine is complete. */ struct xe_preempt_fence { @@ -23,7 +22,7 @@ struct xe_preempt_fence { /** @link: link into list of pending preempt fences */ struct list_head link; /** @engine: xe engine for this preempt fence */ - struct xe_engine *engine; + struct xe_exec_queue *q; /** @preempt_work: work struct which issues preemption */ struct work_struct preempt_work; /** @error: preempt fence is in error state */ diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c index 9b034272d82f..5709518e314b 100644 --- a/drivers/gpu/drm/xe/xe_pt.c +++ b/drivers/gpu/drm/xe/xe_pt.c @@ -1307,7 +1307,7 @@ static void xe_pt_calc_rfence_interval(struct xe_vma *vma, * address range. * @tile: The tile to bind for. * @vma: The vma to bind. - * @e: The engine with which to do pipelined page-table updates. + * @q: The exec_queue with which to do pipelined page-table updates. * @syncs: Entries to sync on before binding the built tree to the live vm tree. * @num_syncs: Number of @sync entries. * @rebind: Whether we're rebinding this vma to the same address range without @@ -1325,7 +1325,7 @@ static void xe_pt_calc_rfence_interval(struct xe_vma *vma, * on success, an error pointer on error. */ struct dma_fence * -__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, +__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, struct xe_sync_entry *syncs, u32 num_syncs, bool rebind) { @@ -1351,7 +1351,7 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, vm_dbg(&xe_vma_vm(vma)->xe->drm, "Preparing bind, with range [%llx...%llx) engine %p.\n", - xe_vma_start(vma), xe_vma_end(vma) - 1, e); + xe_vma_start(vma), xe_vma_end(vma) - 1, q); err = xe_pt_prepare_bind(tile, vma, entries, &num_entries, rebind); if (err) @@ -1388,7 +1388,7 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, } fence = xe_migrate_update_pgtables(tile->migrate, - vm, xe_vma_bo(vma), e, + vm, xe_vma_bo(vma), q, entries, num_entries, syncs, num_syncs, &bind_pt_update.base); @@ -1663,7 +1663,7 @@ static const struct xe_migrate_pt_update_ops userptr_unbind_ops = { * address range. * @tile: The tile to unbind for. * @vma: The vma to unbind. - * @e: The engine with which to do pipelined page-table updates. + * @q: The exec_queue with which to do pipelined page-table updates. * @syncs: Entries to sync on before disconnecting the tree to be destroyed. * @num_syncs: Number of @sync entries. * @@ -1679,7 +1679,7 @@ static const struct xe_migrate_pt_update_ops userptr_unbind_ops = { * on success, an error pointer on error. */ struct dma_fence * -__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, +__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, struct xe_sync_entry *syncs, u32 num_syncs) { struct xe_vm_pgtable_update entries[XE_VM_MAX_LEVEL * 2 + 1]; @@ -1704,7 +1704,7 @@ __xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e vm_dbg(&xe_vma_vm(vma)->xe->drm, "Preparing unbind, with range [%llx...%llx) engine %p.\n", - xe_vma_start(vma), xe_vma_end(vma) - 1, e); + xe_vma_start(vma), xe_vma_end(vma) - 1, q); num_entries = xe_pt_stage_unbind(tile, vma, entries); XE_WARN_ON(num_entries > ARRAY_SIZE(entries)); @@ -1729,8 +1729,8 @@ __xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e * lower level, because it needs to be more conservative. */ fence = xe_migrate_update_pgtables(tile->migrate, - vm, NULL, e ? e : - vm->eng[tile->id], + vm, NULL, q ? q : + vm->q[tile->id], entries, num_entries, syncs, num_syncs, &unbind_pt_update.base); diff --git a/drivers/gpu/drm/xe/xe_pt.h b/drivers/gpu/drm/xe/xe_pt.h index bbb00d6461ff..01be7ab08f87 100644 --- a/drivers/gpu/drm/xe/xe_pt.h +++ b/drivers/gpu/drm/xe/xe_pt.h @@ -12,7 +12,7 @@ struct dma_fence; struct xe_bo; struct xe_device; -struct xe_engine; +struct xe_exec_queue; struct xe_sync_entry; struct xe_tile; struct xe_vm; @@ -35,12 +35,12 @@ void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm, void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred); struct dma_fence * -__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, +__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, struct xe_sync_entry *syncs, u32 num_syncs, bool rebind); struct dma_fence * -__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, +__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, struct xe_sync_entry *syncs, u32 num_syncs); bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma); diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c index 6ba7baf7c777..7ea235c71385 100644 --- a/drivers/gpu/drm/xe/xe_query.c +++ b/drivers/gpu/drm/xe/xe_query.c @@ -12,7 +12,7 @@ #include "xe_bo.h" #include "xe_device.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_ggtt.h" #include "xe_gt.h" #include "xe_guc_hwconfig.h" @@ -203,7 +203,7 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query) config->info[XE_QUERY_CONFIG_MEM_REGION_COUNT] = hweight_long(xe->info.mem_region_mask); config->info[XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY] = - xe_engine_device_get_max_priority(xe); + xe_exec_queue_device_get_max_priority(xe); if (copy_to_user(query_ptr, config, size)) { kfree(config); diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c index c9ef44e63772..4a474ab04f96 100644 --- a/drivers/gpu/drm/xe/xe_ring_ops.c +++ b/drivers/gpu/drm/xe/xe_ring_ops.c @@ -10,7 +10,7 @@ #include "regs/xe_gt_regs.h" #include "regs/xe_lrc_layout.h" #include "regs/xe_regs.h" -#include "xe_engine_types.h" +#include "xe_exec_queue_types.h" #include "xe_gt.h" #include "xe_lrc.h" #include "xe_macros.h" @@ -156,7 +156,7 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value, static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i) { - struct xe_gt *gt = job->engine->gt; + struct xe_gt *gt = job->q->gt; bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); u32 flags; @@ -172,7 +172,7 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i) if (lacks_render) flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; - else if (job->engine->class == XE_ENGINE_CLASS_COMPUTE) + else if (job->q->class == XE_ENGINE_CLASS_COMPUTE) flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; dw[i++] = GFX_OP_PIPE_CONTROL(6) | PIPE_CONTROL0_HDC_PIPELINE_FLUSH; @@ -202,7 +202,7 @@ static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw, static u32 get_ppgtt_flag(struct xe_sched_job *job) { - return !(job->engine->flags & ENGINE_FLAG_WA) ? BIT(8) : 0; + return !(job->q->flags & EXEC_QUEUE_FLAG_WA) ? BIT(8) : 0; } static void __emit_job_gen12_copy(struct xe_sched_job *job, struct xe_lrc *lrc, @@ -210,7 +210,7 @@ static void __emit_job_gen12_copy(struct xe_sched_job *job, struct xe_lrc *lrc, { u32 dw[MAX_JOB_SIZE_DW], i = 0; u32 ppgtt_flag = get_ppgtt_flag(job); - struct xe_vm *vm = job->engine->vm; + struct xe_vm *vm = job->q->vm; if (vm->batch_invalidate_tlb) { dw[i++] = preparser_disable(true); @@ -255,10 +255,10 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc, { u32 dw[MAX_JOB_SIZE_DW], i = 0; u32 ppgtt_flag = get_ppgtt_flag(job); - struct xe_gt *gt = job->engine->gt; + struct xe_gt *gt = job->q->gt; struct xe_device *xe = gt_to_xe(gt); - bool decode = job->engine->class == XE_ENGINE_CLASS_VIDEO_DECODE; - struct xe_vm *vm = job->engine->vm; + bool decode = job->q->class == XE_ENGINE_CLASS_VIDEO_DECODE; + struct xe_vm *vm = job->q->vm; dw[i++] = preparser_disable(true); @@ -302,16 +302,16 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job, { u32 dw[MAX_JOB_SIZE_DW], i = 0; u32 ppgtt_flag = get_ppgtt_flag(job); - struct xe_gt *gt = job->engine->gt; + struct xe_gt *gt = job->q->gt; struct xe_device *xe = gt_to_xe(gt); bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); - struct xe_vm *vm = job->engine->vm; + struct xe_vm *vm = job->q->vm; u32 mask_flags = 0; dw[i++] = preparser_disable(true); if (lacks_render) mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS; - else if (job->engine->class == XE_ENGINE_CLASS_COMPUTE) + else if (job->q->class == XE_ENGINE_CLASS_COMPUTE) mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS; /* See __xe_pt_bind_vma() for a discussion on TLB invalidations. */ @@ -378,14 +378,14 @@ static void emit_job_gen12_copy(struct xe_sched_job *job) { int i; - if (xe_sched_job_is_migration(job->engine)) { - emit_migration_job_gen12(job, job->engine->lrc, + if (xe_sched_job_is_migration(job->q)) { + emit_migration_job_gen12(job, job->q->lrc, xe_sched_job_seqno(job)); return; } - for (i = 0; i < job->engine->width; ++i) - __emit_job_gen12_copy(job, job->engine->lrc + i, + for (i = 0; i < job->q->width; ++i) + __emit_job_gen12_copy(job, job->q->lrc + i, job->batch_addr[i], xe_sched_job_seqno(job)); } @@ -395,8 +395,8 @@ static void emit_job_gen12_video(struct xe_sched_job *job) int i; /* FIXME: Not doing parallel handshake for now */ - for (i = 0; i < job->engine->width; ++i) - __emit_job_gen12_video(job, job->engine->lrc + i, + for (i = 0; i < job->q->width; ++i) + __emit_job_gen12_video(job, job->q->lrc + i, job->batch_addr[i], xe_sched_job_seqno(job)); } @@ -405,8 +405,8 @@ static void emit_job_gen12_render_compute(struct xe_sched_job *job) { int i; - for (i = 0; i < job->engine->width; ++i) - __emit_job_gen12_render_compute(job, job->engine->lrc + i, + for (i = 0; i < job->q->width; ++i) + __emit_job_gen12_render_compute(job, job->q->lrc + i, job->batch_addr[i], xe_sched_job_seqno(job)); } diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c index b5bf14b828f9..753aab0cc6f4 100644 --- a/drivers/gpu/drm/xe/xe_sched_job.c +++ b/drivers/gpu/drm/xe/xe_sched_job.c @@ -9,7 +9,7 @@ #include <linux/slab.h> #include "xe_device.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_gt.h" #include "xe_hw_engine_types.h" #include "xe_hw_fence.h" @@ -57,58 +57,58 @@ static struct xe_sched_job *job_alloc(bool parallel) xe_sched_job_slab, GFP_KERNEL); } -bool xe_sched_job_is_migration(struct xe_engine *e) +bool xe_sched_job_is_migration(struct xe_exec_queue *q) { - return e->vm && (e->vm->flags & XE_VM_FLAG_MIGRATION) && - !(e->flags & ENGINE_FLAG_WA); + return q->vm && (q->vm->flags & XE_VM_FLAG_MIGRATION) && + !(q->flags & EXEC_QUEUE_FLAG_WA); } static void job_free(struct xe_sched_job *job) { - struct xe_engine *e = job->engine; - bool is_migration = xe_sched_job_is_migration(e); + struct xe_exec_queue *q = job->q; + bool is_migration = xe_sched_job_is_migration(q); - kmem_cache_free(xe_engine_is_parallel(job->engine) || is_migration ? + kmem_cache_free(xe_exec_queue_is_parallel(job->q) || is_migration ? xe_sched_job_parallel_slab : xe_sched_job_slab, job); } static struct xe_device *job_to_xe(struct xe_sched_job *job) { - return gt_to_xe(job->engine->gt); + return gt_to_xe(job->q->gt); } -struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, +struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q, u64 *batch_addr) { struct xe_sched_job *job; struct dma_fence **fences; - bool is_migration = xe_sched_job_is_migration(e); + bool is_migration = xe_sched_job_is_migration(q); int err; int i, j; u32 width; /* Migration and kernel engines have their own locking */ - if (!(e->flags & (ENGINE_FLAG_KERNEL | ENGINE_FLAG_VM | - ENGINE_FLAG_WA))) { - lockdep_assert_held(&e->vm->lock); - if (!xe_vm_no_dma_fences(e->vm)) - xe_vm_assert_held(e->vm); + if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM | + EXEC_QUEUE_FLAG_WA))) { + lockdep_assert_held(&q->vm->lock); + if (!xe_vm_no_dma_fences(q->vm)) + xe_vm_assert_held(q->vm); } - job = job_alloc(xe_engine_is_parallel(e) || is_migration); + job = job_alloc(xe_exec_queue_is_parallel(q) || is_migration); if (!job) return ERR_PTR(-ENOMEM); - job->engine = e; + job->q = q; kref_init(&job->refcount); - xe_engine_get(job->engine); + xe_exec_queue_get(job->q); - err = drm_sched_job_init(&job->drm, e->entity, NULL); + err = drm_sched_job_init(&job->drm, q->entity, NULL); if (err) goto err_free; - if (!xe_engine_is_parallel(e)) { - job->fence = xe_lrc_create_seqno_fence(e->lrc); + if (!xe_exec_queue_is_parallel(q)) { + job->fence = xe_lrc_create_seqno_fence(q->lrc); if (IS_ERR(job->fence)) { err = PTR_ERR(job->fence); goto err_sched_job; @@ -116,38 +116,38 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, } else { struct dma_fence_array *cf; - fences = kmalloc_array(e->width, sizeof(*fences), GFP_KERNEL); + fences = kmalloc_array(q->width, sizeof(*fences), GFP_KERNEL); if (!fences) { err = -ENOMEM; goto err_sched_job; } - for (j = 0; j < e->width; ++j) { - fences[j] = xe_lrc_create_seqno_fence(e->lrc + j); + for (j = 0; j < q->width; ++j) { + fences[j] = xe_lrc_create_seqno_fence(q->lrc + j); if (IS_ERR(fences[j])) { err = PTR_ERR(fences[j]); goto err_fences; } } - cf = dma_fence_array_create(e->width, fences, - e->parallel.composite_fence_ctx, - e->parallel.composite_fence_seqno++, + cf = dma_fence_array_create(q->width, fences, + q->parallel.composite_fence_ctx, + q->parallel.composite_fence_seqno++, false); if (!cf) { - --e->parallel.composite_fence_seqno; + --q->parallel.composite_fence_seqno; err = -ENOMEM; goto err_fences; } /* Sanity check */ - for (j = 0; j < e->width; ++j) + for (j = 0; j < q->width; ++j) XE_WARN_ON(cf->base.seqno != fences[j]->seqno); job->fence = &cf->base; } - width = e->width; + width = q->width; if (is_migration) width = 2; @@ -155,7 +155,7 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, job->batch_addr[i] = batch_addr[i]; /* All other jobs require a VM to be open which has a ref */ - if (unlikely(e->flags & ENGINE_FLAG_KERNEL)) + if (unlikely(q->flags & EXEC_QUEUE_FLAG_KERNEL)) xe_device_mem_access_get(job_to_xe(job)); xe_device_assert_mem_access(job_to_xe(job)); @@ -164,14 +164,14 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, err_fences: for (j = j - 1; j >= 0; --j) { - --e->lrc[j].fence_ctx.next_seqno; + --q->lrc[j].fence_ctx.next_seqno; dma_fence_put(fences[j]); } kfree(fences); err_sched_job: drm_sched_job_cleanup(&job->drm); err_free: - xe_engine_put(e); + xe_exec_queue_put(q); job_free(job); return ERR_PTR(err); } @@ -188,9 +188,9 @@ void xe_sched_job_destroy(struct kref *ref) struct xe_sched_job *job = container_of(ref, struct xe_sched_job, refcount); - if (unlikely(job->engine->flags & ENGINE_FLAG_KERNEL)) + if (unlikely(job->q->flags & EXEC_QUEUE_FLAG_KERNEL)) xe_device_mem_access_put(job_to_xe(job)); - xe_engine_put(job->engine); + xe_exec_queue_put(job->q); dma_fence_put(job->fence); drm_sched_job_cleanup(&job->drm); job_free(job); @@ -222,12 +222,12 @@ void xe_sched_job_set_error(struct xe_sched_job *job, int error) trace_xe_sched_job_set_error(job); dma_fence_enable_sw_signaling(job->fence); - xe_hw_fence_irq_run(job->engine->fence_irq); + xe_hw_fence_irq_run(job->q->fence_irq); } bool xe_sched_job_started(struct xe_sched_job *job) { - struct xe_lrc *lrc = job->engine->lrc; + struct xe_lrc *lrc = job->q->lrc; return !__dma_fence_is_later(xe_sched_job_seqno(job), xe_lrc_start_seqno(lrc), @@ -236,7 +236,7 @@ bool xe_sched_job_started(struct xe_sched_job *job) bool xe_sched_job_completed(struct xe_sched_job *job) { - struct xe_lrc *lrc = job->engine->lrc; + struct xe_lrc *lrc = job->q->lrc; /* * Can safely check just LRC[0] seqno as that is last seqno written when diff --git a/drivers/gpu/drm/xe/xe_sched_job.h b/drivers/gpu/drm/xe/xe_sched_job.h index 5315ad8656c2..6ca1d426c036 100644 --- a/drivers/gpu/drm/xe/xe_sched_job.h +++ b/drivers/gpu/drm/xe/xe_sched_job.h @@ -14,7 +14,7 @@ int xe_sched_job_module_init(void); void xe_sched_job_module_exit(void); -struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, +struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q, u64 *batch_addr); void xe_sched_job_destroy(struct kref *ref); @@ -71,6 +71,6 @@ xe_sched_job_add_migrate_flush(struct xe_sched_job *job, u32 flags) job->migrate_flush_flags = flags; } -bool xe_sched_job_is_migration(struct xe_engine *e); +bool xe_sched_job_is_migration(struct xe_exec_queue *q); #endif diff --git a/drivers/gpu/drm/xe/xe_sched_job_types.h b/drivers/gpu/drm/xe/xe_sched_job_types.h index 5534bfacaa16..08db0db7814b 100644 --- a/drivers/gpu/drm/xe/xe_sched_job_types.h +++ b/drivers/gpu/drm/xe/xe_sched_job_types.h @@ -10,7 +10,7 @@ #include <drm/gpu_scheduler.h> -struct xe_engine; +struct xe_exec_queue; /** * struct xe_sched_job - XE schedule job (batch buffer tracking) @@ -18,8 +18,8 @@ struct xe_engine; struct xe_sched_job { /** @drm: base DRM scheduler job */ struct drm_sched_job drm; - /** @engine: XE submission engine */ - struct xe_engine *engine; + /** @exec_queue: Exec queue */ + struct xe_exec_queue *q; /** @refcount: ref count of this job */ struct kref refcount; /** diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h index 463152528281..e32f1cad51d9 100644 --- a/drivers/gpu/drm/xe/xe_trace.h +++ b/drivers/gpu/drm/xe/xe_trace.h @@ -13,10 +13,10 @@ #include <linux/types.h> #include "xe_bo_types.h" -#include "xe_engine_types.h" +#include "xe_exec_queue_types.h" #include "xe_gt_tlb_invalidation_types.h" #include "xe_gt_types.h" -#include "xe_guc_engine_types.h" +#include "xe_guc_exec_queue_types.h" #include "xe_sched_job.h" #include "xe_vm.h" @@ -104,9 +104,9 @@ DEFINE_EVENT(xe_bo, xe_bo_move, TP_ARGS(bo) ); -DECLARE_EVENT_CLASS(xe_engine, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e), +DECLARE_EVENT_CLASS(xe_exec_queue, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q), TP_STRUCT__entry( __field(enum xe_engine_class, class) @@ -119,13 +119,13 @@ DECLARE_EVENT_CLASS(xe_engine, ), TP_fast_assign( - __entry->class = e->class; - __entry->logical_mask = e->logical_mask; - __entry->gt_id = e->gt->info.id; - __entry->width = e->width; - __entry->guc_id = e->guc->id; - __entry->guc_state = atomic_read(&e->guc->state); - __entry->flags = e->flags; + __entry->class = q->class; + __entry->logical_mask = q->logical_mask; + __entry->gt_id = q->gt->info.id; + __entry->width = q->width; + __entry->guc_id = q->guc->id; + __entry->guc_state = atomic_read(&q->guc->state); + __entry->flags = q->flags; ), TP_printk("%d:0x%x, gt=%d, width=%d, guc_id=%d, guc_state=0x%x, flags=0x%x", @@ -134,94 +134,94 @@ DECLARE_EVENT_CLASS(xe_engine, __entry->guc_state, __entry->flags) ); -DEFINE_EVENT(xe_engine, xe_engine_create, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_create, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_supress_resume, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_supress_resume, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_submit, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_submit, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_scheduling_enable, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_enable, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_scheduling_disable, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_disable, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_scheduling_done, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_done, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_register, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_register, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_deregister, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_deregister, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_deregister_done, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_deregister_done, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_close, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_close, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_kill, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_kill, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_cleanup_entity, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_cleanup_entity, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_destroy, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_destroy, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_reset, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_reset, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_memory_cat_error, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_memory_cat_error, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_stop, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_stop, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_resubmit, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_resubmit, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); -DEFINE_EVENT(xe_engine, xe_engine_lr_cleanup, - TP_PROTO(struct xe_engine *e), - TP_ARGS(e) +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_lr_cleanup, + TP_PROTO(struct xe_exec_queue *q), + TP_ARGS(q) ); DECLARE_EVENT_CLASS(xe_sched_job, @@ -240,10 +240,10 @@ DECLARE_EVENT_CLASS(xe_sched_job, TP_fast_assign( __entry->seqno = xe_sched_job_seqno(job); - __entry->guc_id = job->engine->guc->id; + __entry->guc_id = job->q->guc->id; __entry->guc_state = - atomic_read(&job->engine->guc->state); - __entry->flags = job->engine->flags; + atomic_read(&job->q->guc->state); + __entry->flags = job->q->flags; __entry->error = job->fence->error; __entry->fence = (unsigned long)job->fence; __entry->batch_addr = (u64)job->batch_addr[0]; @@ -302,7 +302,7 @@ DECLARE_EVENT_CLASS(drm_sched_msg, TP_fast_assign( __entry->opcode = msg->opcode; __entry->guc_id = - ((struct xe_engine *)msg->private_data)->guc->id; + ((struct xe_exec_queue *)msg->private_data)->guc->id; ), TP_printk("guc_id=%d, opcode=%u", __entry->guc_id, diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c index 44df7b9d801e..cb28dbc2bdbb 100644 --- a/drivers/gpu/drm/xe/xe_vm.c +++ b/drivers/gpu/drm/xe/xe_vm.c @@ -18,7 +18,7 @@ #include "xe_bo.h" #include "xe_device.h" -#include "xe_engine.h" +#include "xe_exec_queue.h" #include "xe_gt.h" #include "xe_gt_pagefault.h" #include "xe_gt_tlb_invalidation.h" @@ -165,15 +165,15 @@ int xe_vma_userptr_pin_pages(struct xe_vma *vma) static bool preempt_fences_waiting(struct xe_vm *vm) { - struct xe_engine *e; + struct xe_exec_queue *q; lockdep_assert_held(&vm->lock); xe_vm_assert_held(vm); - list_for_each_entry(e, &vm->preempt.engines, compute.link) { - if (!e->compute.pfence || (e->compute.pfence && - test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, - &e->compute.pfence->flags))) { + list_for_each_entry(q, &vm->preempt.engines, compute.link) { + if (!q->compute.pfence || + (q->compute.pfence && test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, + &q->compute.pfence->flags))) { return true; } } @@ -212,18 +212,18 @@ static int alloc_preempt_fences(struct xe_vm *vm, struct list_head *list, static int wait_for_existing_preempt_fences(struct xe_vm *vm) { - struct xe_engine *e; + struct xe_exec_queue *q; xe_vm_assert_held(vm); - list_for_each_entry(e, &vm->preempt.engines, compute.link) { - if (e->compute.pfence) { - long timeout = dma_fence_wait(e->compute.pfence, false); + list_for_each_entry(q, &vm->preempt.engines, compute.link) { + if (q->compute.pfence) { + long timeout = dma_fence_wait(q->compute.pfence, false); if (timeout < 0) return -ETIME; - dma_fence_put(e->compute.pfence); - e->compute.pfence = NULL; + dma_fence_put(q->compute.pfence); + q->compute.pfence = NULL; } } @@ -232,11 +232,11 @@ static int wait_for_existing_preempt_fences(struct xe_vm *vm) static bool xe_vm_is_idle(struct xe_vm *vm) { - struct xe_engine *e; + struct xe_exec_queue *q; xe_vm_assert_held(vm); - list_for_each_entry(e, &vm->preempt.engines, compute.link) { - if (!xe_engine_is_idle(e)) + list_for_each_entry(q, &vm->preempt.engines, compute.link) { + if (!xe_exec_queue_is_idle(q)) return false; } @@ -246,25 +246,25 @@ static bool xe_vm_is_idle(struct xe_vm *vm) static void arm_preempt_fences(struct xe_vm *vm, struct list_head *list) { struct list_head *link; - struct xe_engine *e; + struct xe_exec_queue *q; - list_for_each_entry(e, &vm->preempt.engines, compute.link) { + list_for_each_entry(q, &vm->preempt.engines, compute.link) { struct dma_fence *fence; link = list->next; XE_WARN_ON(link == list); fence = xe_preempt_fence_arm(to_preempt_fence_from_link(link), - e, e->compute.context, - ++e->compute.seqno); - dma_fence_put(e->compute.pfence); - e->compute.pfence = fence; + q, q->compute.context, + ++q->compute.seqno); + dma_fence_put(q->compute.pfence); + q->compute.pfence = fence; } } static int add_preempt_fences(struct xe_vm *vm, struct xe_bo *bo) { - struct xe_engine *e; + struct xe_exec_queue *q; struct ww_acquire_ctx ww; int err; @@ -272,10 +272,10 @@ static int add_preempt_fences(struct xe_vm *vm, struct xe_bo *bo) if (err) return err; - list_for_each_entry(e, &vm->preempt.engines, compute.link) - if (e->compute.pfence) { + list_for_each_entry(q, &vm->preempt.engines, compute.link) + if (q->compute.pfence) { dma_resv_add_fence(bo->ttm.base.resv, - e->compute.pfence, + q->compute.pfence, DMA_RESV_USAGE_BOOKKEEP); } @@ -304,22 +304,22 @@ void xe_vm_fence_all_extobjs(struct xe_vm *vm, struct dma_fence *fence, static void resume_and_reinstall_preempt_fences(struct xe_vm *vm) { - struct xe_engine *e; + struct xe_exec_queue *q; lockdep_assert_held(&vm->lock); xe_vm_assert_held(vm); - list_for_each_entry(e, &vm->preempt.engines, compute.link) { - e->ops->resume(e); + list_for_each_entry(q, &vm->preempt.engines, compute.link) { + q->ops->resume(q); - dma_resv_add_fence(&vm->resv, e->compute.pfence, + dma_resv_add_fence(&vm->resv, q->compute.pfence, DMA_RESV_USAGE_BOOKKEEP); - xe_vm_fence_all_extobjs(vm, e->compute.pfence, + xe_vm_fence_all_extobjs(vm, q->compute.pfence, DMA_RESV_USAGE_BOOKKEEP); } } -int xe_vm_add_compute_engine(struct xe_vm *vm, struct xe_engine *e) +int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q) { struct ttm_validate_buffer tv_onstack[XE_ONSTACK_TV]; struct ttm_validate_buffer *tv; @@ -337,16 +337,16 @@ int xe_vm_add_compute_engine(struct xe_vm *vm, struct xe_engine *e) if (err) goto out_unlock_outer; - pfence = xe_preempt_fence_create(e, e->compute.context, - ++e->compute.seqno); + pfence = xe_preempt_fence_create(q, q->compute.context, + ++q->compute.seqno); if (!pfence) { err = -ENOMEM; goto out_unlock; } - list_add(&e->compute.link, &vm->preempt.engines); + list_add(&q->compute.link, &vm->preempt.engines); ++vm->preempt.num_engines; - e->compute.pfence = pfence; + q->compute.pfence = pfence; down_read(&vm->userptr.notifier_lock); @@ -518,7 +518,7 @@ void xe_vm_unlock_dma_resv(struct xe_vm *vm, static void xe_vm_kill(struct xe_vm *vm) { struct ww_acquire_ctx ww; - struct xe_engine *e; + struct xe_exec_queue *q; lockdep_assert_held(&vm->lock); @@ -526,8 +526,8 @@ static void xe_vm_kill(struct xe_vm *vm) vm->flags |= XE_VM_FLAG_BANNED; trace_xe_vm_kill(vm); - list_for_each_entry(e, &vm->preempt.engines, compute.link) - e->ops->kill(e); + list_for_each_entry(q, &vm->preempt.engines, compute.link) + q->ops->kill(q); xe_vm_unlock(vm, &ww); /* TODO: Inform user the VM is banned */ @@ -833,7 +833,7 @@ int xe_vm_userptr_check_repin(struct xe_vm *vm) } static struct dma_fence * -xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, +xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q, struct xe_sync_entry *syncs, u32 num_syncs, bool first_op, bool last_op); @@ -1297,21 +1297,21 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags) for_each_tile(tile, xe, id) { struct xe_gt *gt = tile->primary_gt; struct xe_vm *migrate_vm; - struct xe_engine *eng; + struct xe_exec_queue *q; if (!vm->pt_root[id]) continue; migrate_vm = xe_migrate_get_vm(tile->migrate); - eng = xe_engine_create_class(xe, gt, migrate_vm, - XE_ENGINE_CLASS_COPY, - ENGINE_FLAG_VM); + q = xe_exec_queue_create_class(xe, gt, migrate_vm, + XE_ENGINE_CLASS_COPY, + EXEC_QUEUE_FLAG_VM); xe_vm_put(migrate_vm); - if (IS_ERR(eng)) { + if (IS_ERR(q)) { xe_vm_close_and_put(vm); - return ERR_CAST(eng); + return ERR_CAST(q); } - vm->eng[id] = eng; + vm->q[id] = q; number_tiles++; } } @@ -1422,10 +1422,10 @@ void xe_vm_close_and_put(struct xe_vm *vm) flush_work(&vm->preempt.rebind_work); for_each_tile(tile, xe, id) { - if (vm->eng[id]) { - xe_engine_kill(vm->eng[id]); - xe_engine_put(vm->eng[id]); - vm->eng[id] = NULL; + if (vm->q[id]) { + xe_exec_queue_kill(vm->q[id]); + xe_exec_queue_put(vm->q[id]); + vm->q[id] = NULL; } } @@ -1576,7 +1576,7 @@ u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile) } static struct dma_fence * -xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, +xe_vm_unbind_vma(struct xe_vma *vma, struct xe_exec_queue *q, struct xe_sync_entry *syncs, u32 num_syncs, bool first_op, bool last_op) { @@ -1603,7 +1603,7 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, if (!(vma->tile_present & BIT(id))) goto next; - fence = __xe_pt_unbind_vma(tile, vma, e, first_op ? syncs : NULL, + fence = __xe_pt_unbind_vma(tile, vma, q, first_op ? syncs : NULL, first_op ? num_syncs : 0); if (IS_ERR(fence)) { err = PTR_ERR(fence); @@ -1614,8 +1614,8 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, fences[cur_fence++] = fence; next: - if (e && vm->pt_root[id] && !list_empty(&e->multi_gt_list)) - e = list_next_entry(e, multi_gt_list); + if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list)) + q = list_next_entry(q, multi_gt_list); } if (fences) { @@ -1651,7 +1651,7 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, } static struct dma_fence * -xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, +xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q, struct xe_sync_entry *syncs, u32 num_syncs, bool first_op, bool last_op) { @@ -1678,7 +1678,7 @@ xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, if (!(vma->tile_mask & BIT(id))) goto next; - fence = __xe_pt_bind_vma(tile, vma, e ? e : vm->eng[id], + fence = __xe_pt_bind_vma(tile, vma, q ? q : vm->q[id], first_op ? syncs : NULL, first_op ? num_syncs : 0, vma->tile_present & BIT(id)); @@ -1691,8 +1691,8 @@ xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, fences[cur_fence++] = fence; next: - if (e && vm->pt_root[id] && !list_empty(&e->multi_gt_list)) - e = list_next_entry(e, multi_gt_list); + if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list)) + q = list_next_entry(q, multi_gt_list); } if (fences) { @@ -1808,7 +1808,7 @@ int xe_vm_async_fence_wait_start(struct dma_fence *fence) } static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, - struct xe_engine *e, struct xe_sync_entry *syncs, + struct xe_exec_queue *q, struct xe_sync_entry *syncs, u32 num_syncs, struct async_op_fence *afence, bool immediate, bool first_op, bool last_op) { @@ -1817,7 +1817,7 @@ static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, xe_vm_assert_held(vm); if (immediate) { - fence = xe_vm_bind_vma(vma, e, syncs, num_syncs, first_op, + fence = xe_vm_bind_vma(vma, q, syncs, num_syncs, first_op, last_op); if (IS_ERR(fence)) return PTR_ERR(fence); @@ -1839,7 +1839,7 @@ static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, return 0; } -static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_engine *e, +static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_exec_queue *q, struct xe_bo *bo, struct xe_sync_entry *syncs, u32 num_syncs, struct async_op_fence *afence, bool immediate, bool first_op, bool last_op) @@ -1855,12 +1855,12 @@ static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_engine *e, return err; } - return __xe_vm_bind(vm, vma, e, syncs, num_syncs, afence, immediate, + return __xe_vm_bind(vm, vma, q, syncs, num_syncs, afence, immediate, first_op, last_op); } static int xe_vm_unbind(struct xe_vm *vm, struct xe_vma *vma, - struct xe_engine *e, struct xe_sync_entry *syncs, + struct xe_exec_queue *q, struct xe_sync_entry *syncs, u32 num_syncs, struct async_op_fence *afence, bool first_op, bool last_op) { @@ -1869,7 +1869,7 @@ static int xe_vm_unbind(struct xe_vm *vm, struct xe_vma *vma, xe_vm_assert_held(vm); xe_bo_assert_held(xe_vma_bo(vma)); - fence = xe_vm_unbind_vma(vma, e, syncs, num_syncs, first_op, last_op); + fence = xe_vm_unbind_vma(vma, q, syncs, num_syncs, first_op, last_op); if (IS_ERR(fence)) return PTR_ERR(fence); if (afence) @@ -2096,7 +2096,7 @@ static const u32 region_to_mem_type[] = { }; static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma, - struct xe_engine *e, u32 region, + struct xe_exec_queue *q, u32 region, struct xe_sync_entry *syncs, u32 num_syncs, struct async_op_fence *afence, bool first_op, bool last_op) @@ -2112,7 +2112,7 @@ static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma, } if (vma->tile_mask != (vma->tile_present & ~vma->usm.tile_invalidated)) { - return xe_vm_bind(vm, vma, e, xe_vma_bo(vma), syncs, num_syncs, + return xe_vm_bind(vm, vma, q, xe_vma_bo(vma), syncs, num_syncs, afence, true, first_op, last_op); } else { int i; @@ -2410,7 +2410,7 @@ static u64 xe_vma_max_pte_size(struct xe_vma *vma) * Parse operations list and create any resources needed for the operations * prior to fully committing to the operations. This setup can fail. */ -static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_engine *e, +static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_exec_queue *q, struct drm_gpuva_ops **ops, int num_ops_list, struct xe_sync_entry *syncs, u32 num_syncs, struct list_head *ops_list, bool async) @@ -2430,9 +2430,9 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_engine *e, if (!fence) return -ENOMEM; - seqno = e ? ++e->bind.fence_seqno : ++vm->async_ops.fence.seqno; + seqno = q ? ++q->bind.fence_seqno : ++vm->async_ops.fence.seqno; dma_fence_init(&fence->fence, &async_op_fence_ops, - &vm->async_ops.lock, e ? e->bind.fence_ctx : + &vm->async_ops.lock, q ? q->bind.fence_ctx : vm->async_ops.fence.context, seqno); if (!xe_vm_no_dma_fences(vm)) { @@ -2463,7 +2463,7 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_engine *e, op->syncs = syncs; } - op->engine = e; + op->q = q; switch (op->base.op) { case DRM_GPUVA_OP_MAP: @@ -2673,7 +2673,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, switch (op->base.op) { case DRM_GPUVA_OP_MAP: - err = xe_vm_bind(vm, vma, op->engine, xe_vma_bo(vma), + err = xe_vm_bind(vm, vma, op->q, xe_vma_bo(vma), op->syncs, op->num_syncs, op->fence, op->map.immediate || !xe_vm_in_fault_mode(vm), op->flags & XE_VMA_OP_FIRST, @@ -2689,7 +2689,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, vm->async_ops.munmap_rebind_inflight = true; vma->gpuva.flags |= XE_VMA_FIRST_REBIND; } - err = xe_vm_unbind(vm, vma, op->engine, op->syncs, + err = xe_vm_unbind(vm, vma, op->q, op->syncs, op->num_syncs, !prev && !next ? op->fence : NULL, op->flags & XE_VMA_OP_FIRST, @@ -2702,7 +2702,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, if (prev) { op->remap.prev->gpuva.flags |= XE_VMA_LAST_REBIND; - err = xe_vm_bind(vm, op->remap.prev, op->engine, + err = xe_vm_bind(vm, op->remap.prev, op->q, xe_vma_bo(op->remap.prev), op->syncs, op->num_syncs, !next ? op->fence : NULL, true, false, @@ -2715,7 +2715,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, if (next) { op->remap.next->gpuva.flags |= XE_VMA_LAST_REBIND; - err = xe_vm_bind(vm, op->remap.next, op->engine, + err = xe_vm_bind(vm, op->remap.next, op->q, xe_vma_bo(op->remap.next), op->syncs, op->num_syncs, op->fence, true, false, @@ -2730,13 +2730,13 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, break; } case DRM_GPUVA_OP_UNMAP: - err = xe_vm_unbind(vm, vma, op->engine, op->syncs, + err = xe_vm_unbind(vm, vma, op->q, op->syncs, op->num_syncs, op->fence, op->flags & XE_VMA_OP_FIRST, op->flags & XE_VMA_OP_LAST); break; case DRM_GPUVA_OP_PREFETCH: - err = xe_vm_prefetch(vm, vma, op->engine, op->prefetch.region, + err = xe_vm_prefetch(vm, vma, op->q, op->prefetch.region, op->syncs, op->num_syncs, op->fence, op->flags & XE_VMA_OP_FIRST, op->flags & XE_VMA_OP_LAST); @@ -2815,8 +2815,8 @@ static void xe_vma_op_cleanup(struct xe_vm *vm, struct xe_vma_op *op) while (op->num_syncs--) xe_sync_entry_cleanup(&op->syncs[op->num_syncs]); kfree(op->syncs); - if (op->engine) - xe_engine_put(op->engine); + if (op->q) + xe_exec_queue_put(op->q); if (op->fence) dma_fence_put(&op->fence->fence); } @@ -3170,7 +3170,7 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) struct xe_bo **bos = NULL; struct drm_gpuva_ops **ops = NULL; struct xe_vm *vm; - struct xe_engine *e = NULL; + struct xe_exec_queue *q = NULL; u32 num_syncs; struct xe_sync_entry *syncs = NULL; struct drm_xe_vm_bind_op *bind_ops; @@ -3183,23 +3183,23 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) if (err) return err; - if (args->engine_id) { - e = xe_engine_lookup(xef, args->engine_id); - if (XE_IOCTL_DBG(xe, !e)) { + if (args->exec_queue_id) { + q = xe_exec_queue_lookup(xef, args->exec_queue_id); + if (XE_IOCTL_DBG(xe, !q)) { err = -ENOENT; goto free_objs; } - if (XE_IOCTL_DBG(xe, !(e->flags & ENGINE_FLAG_VM))) { + if (XE_IOCTL_DBG(xe, !(q->flags & EXEC_QUEUE_FLAG_VM))) { err = -EINVAL; - goto put_engine; + goto put_exec_queue; } } vm = xe_vm_lookup(xef, args->vm_id); if (XE_IOCTL_DBG(xe, !vm)) { err = -EINVAL; - goto put_engine; + goto put_exec_queue; } err = down_write_killable(&vm->lock); @@ -3353,7 +3353,7 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) } } - err = vm_bind_ioctl_ops_parse(vm, e, ops, args->num_binds, + err = vm_bind_ioctl_ops_parse(vm, q, ops, args->num_binds, syncs, num_syncs, &ops_list, async); if (err) goto unwind_ops; @@ -3387,9 +3387,9 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) up_write(&vm->lock); put_vm: xe_vm_put(vm); -put_engine: - if (e) - xe_engine_put(e); +put_exec_queue: + if (q) + xe_exec_queue_put(q); free_objs: kfree(bos); kfree(ops); diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h index 4db777d7e375..6de6e3edb24a 100644 --- a/drivers/gpu/drm/xe/xe_vm.h +++ b/drivers/gpu/drm/xe/xe_vm.h @@ -18,7 +18,7 @@ struct drm_file; struct ttm_buffer_object; struct ttm_validate_buffer; -struct xe_engine; +struct xe_exec_queue; struct xe_file; struct xe_sync_entry; @@ -167,7 +167,7 @@ static inline bool xe_vm_no_dma_fences(struct xe_vm *vm) return xe_vm_in_compute_mode(vm) || xe_vm_in_fault_mode(vm); } -int xe_vm_add_compute_engine(struct xe_vm *vm, struct xe_engine *e); +int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q); int xe_vm_userptr_pin(struct xe_vm *vm); diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h index 261a4b0e8570..3681a5ff588b 100644 --- a/drivers/gpu/drm/xe/xe_vm_types.h +++ b/drivers/gpu/drm/xe/xe_vm_types.h @@ -142,8 +142,8 @@ struct xe_vm { struct kref refcount; - /* engine used for (un)binding vma's */ - struct xe_engine *eng[XE_MAX_TILES_PER_DEVICE]; + /* exec queue used for (un)binding vma's */ + struct xe_exec_queue *q[XE_MAX_TILES_PER_DEVICE]; /** Protects @rebind_list and the page-table structures */ struct dma_resv resv; @@ -394,7 +394,7 @@ struct xe_vma_op { */ struct drm_gpuva_ops *ops; /** @engine: engine for this operation */ - struct xe_engine *engine; + struct xe_exec_queue *q; /** * @syncs: syncs for this operation, only used on first and last * operation diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h index 3d09e9e9267b..86f16d50e9cc 100644 --- a/include/uapi/drm/xe_drm.h +++ b/include/uapi/drm/xe_drm.h @@ -103,14 +103,14 @@ struct xe_user_extension { #define DRM_XE_VM_CREATE 0x03 #define DRM_XE_VM_DESTROY 0x04 #define DRM_XE_VM_BIND 0x05 -#define DRM_XE_ENGINE_CREATE 0x06 -#define DRM_XE_ENGINE_DESTROY 0x07 +#define DRM_XE_EXEC_QUEUE_CREATE 0x06 +#define DRM_XE_EXEC_QUEUE_DESTROY 0x07 #define DRM_XE_EXEC 0x08 #define DRM_XE_MMIO 0x09 -#define DRM_XE_ENGINE_SET_PROPERTY 0x0a +#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0a #define DRM_XE_WAIT_USER_FENCE 0x0b #define DRM_XE_VM_MADVISE 0x0c -#define DRM_XE_ENGINE_GET_PROPERTY 0x0d +#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x0d /* Must be kept compact -- no holes */ #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) @@ -119,12 +119,12 @@ struct xe_user_extension { #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) -#define DRM_IOCTL_XE_ENGINE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_CREATE, struct drm_xe_engine_create) -#define DRM_IOCTL_XE_ENGINE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_GET_PROPERTY, struct drm_xe_engine_get_property) -#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy) +#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) +#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) +#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) #define DRM_IOCTL_XE_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_MMIO, struct drm_xe_mmio) -#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property) +#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property) #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) #define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise) @@ -649,11 +649,11 @@ struct drm_xe_vm_bind { __u32 vm_id; /** - * @engine_id: engine_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND - * and engine must have same vm_id. If zero, the default VM bind engine + * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND + * and exec queue must have same vm_id. If zero, the default VM bind engine * is used. */ - __u32 engine_id; + __u32 exec_queue_id; /** @num_binds: number of binds in this IOCTL */ __u32 num_binds; @@ -685,8 +685,8 @@ struct drm_xe_vm_bind { __u64 reserved[2]; }; -/** struct drm_xe_ext_engine_set_property - engine set property extension */ -struct drm_xe_ext_engine_set_property { +/** struct drm_xe_ext_exec_queue_set_property - exec queue set property extension */ +struct drm_xe_ext_exec_queue_set_property { /** @base: base user extension */ struct xe_user_extension base; @@ -701,32 +701,32 @@ struct drm_xe_ext_engine_set_property { }; /** - * struct drm_xe_engine_set_property - engine set property + * struct drm_xe_exec_queue_set_property - exec queue set property * - * Same namespace for extensions as drm_xe_engine_create + * Same namespace for extensions as drm_xe_exec_queue_create */ -struct drm_xe_engine_set_property { +struct drm_xe_exec_queue_set_property { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; - /** @engine_id: Engine ID */ - __u32 engine_id; + /** @exec_queue_id: Exec queue ID */ + __u32 exec_queue_id; -#define XE_ENGINE_SET_PROPERTY_PRIORITY 0 -#define XE_ENGINE_SET_PROPERTY_TIMESLICE 1 -#define XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT 2 +#define XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 +#define XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 +#define XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2 /* * Long running or ULLS engine mode. DMA fences not allowed in this * mode. Must match the value of DRM_XE_VM_CREATE_COMPUTE_MODE, serves * as a sanity check the UMD knows what it is doing. Can only be set at * engine create time. */ -#define XE_ENGINE_SET_PROPERTY_COMPUTE_MODE 3 -#define XE_ENGINE_SET_PROPERTY_PERSISTENCE 4 -#define XE_ENGINE_SET_PROPERTY_JOB_TIMEOUT 5 -#define XE_ENGINE_SET_PROPERTY_ACC_TRIGGER 6 -#define XE_ENGINE_SET_PROPERTY_ACC_NOTIFY 7 -#define XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY 8 +#define XE_EXEC_QUEUE_SET_PROPERTY_COMPUTE_MODE 3 +#define XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 4 +#define XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 5 +#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 6 +#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 7 +#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 8 /** @property: property to set */ __u32 property; @@ -755,25 +755,25 @@ struct drm_xe_engine_class_instance { __u16 gt_id; }; -struct drm_xe_engine_create { -#define XE_ENGINE_EXTENSION_SET_PROPERTY 0 +struct drm_xe_exec_queue_create { +#define XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; - /** @width: submission width (number BB per exec) for this engine */ + /** @width: submission width (number BB per exec) for this exec queue */ __u16 width; - /** @num_placements: number of valid placements for this engine */ + /** @num_placements: number of valid placements for this exec queue */ __u16 num_placements; - /** @vm_id: VM to use for this engine */ + /** @vm_id: VM to use for this exec queue */ __u32 vm_id; /** @flags: MBZ */ __u32 flags; - /** @engine_id: Returned engine ID */ - __u32 engine_id; + /** @exec_queue_id: Returned exec queue ID */ + __u32 exec_queue_id; /** * @instances: user pointer to a 2-d array of struct @@ -788,14 +788,14 @@ struct drm_xe_engine_create { __u64 reserved[2]; }; -struct drm_xe_engine_get_property { +struct drm_xe_exec_queue_get_property { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; - /** @engine_id: Engine ID */ - __u32 engine_id; + /** @exec_queue_id: Exec queue ID */ + __u32 exec_queue_id; -#define XE_ENGINE_GET_PROPERTY_BAN 0 +#define XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 /** @property: property to get */ __u32 property; @@ -806,9 +806,9 @@ struct drm_xe_engine_get_property { __u64 reserved[2]; }; -struct drm_xe_engine_destroy { - /** @engine_id: Engine ID */ - __u32 engine_id; +struct drm_xe_exec_queue_destroy { + /** @exec_queue_id: Exec queue ID */ + __u32 exec_queue_id; /** @pad: MBZ */ __u32 pad; @@ -855,8 +855,8 @@ struct drm_xe_exec { /** @extensions: Pointer to the first extension struct, if any */ __u64 extensions; - /** @engine_id: Engine ID for the batch buffer */ - __u32 engine_id; + /** @exec_queue_id: Exec queue ID for the batch buffer */ + __u32 exec_queue_id; /** @num_syncs: Amount of struct drm_xe_sync in array. */ __u32 num_syncs; -- 2.34.1 ^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [Intel-xe] [RFC PATCH 1/1] drm/xe: Rename engine to exec_queue 2023-07-31 16:08 ` [Intel-xe] [RFC PATCH 1/1] drm/xe: " Francois Dugast @ 2023-07-31 18:03 ` Rodrigo Vivi 2023-07-31 19:19 ` Francois Dugast 0 siblings, 1 reply; 9+ messages in thread From: Rodrigo Vivi @ 2023-07-31 18:03 UTC (permalink / raw) To: Francois Dugast; +Cc: intel-xe On Mon, Jul 31, 2023 at 04:08:49PM +0000, Francois Dugast wrote: > Engine was inappropriately used to refer to execution queues and exec_queue is much better than engine here indeed. > it also created some confusion with hardware engines. Where it applies > the exec_queue variable name is changed to q and comments are also > updated. my only bikeshed on this is on the 'q'... could we make that 'eq' instead? it will be very hard to run a detailed review, but based on what I saw so far everything looks correct. So, we should probably move fast with this after passing CI. Anyone else conflicting with this would have to rebase and resubmit. Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> > > Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/162 > Signed-off-by: Francois Dugast <francois.dugast@intel.com> > --- > drivers/gpu/drm/xe/Makefile | 2 +- > drivers/gpu/drm/xe/tests/xe_migrate.c | 18 +- > drivers/gpu/drm/xe/xe_bb.c | 26 +- > drivers/gpu/drm/xe/xe_bb.h | 8 +- > drivers/gpu/drm/xe/xe_devcoredump.c | 40 +- > drivers/gpu/drm/xe/xe_devcoredump.h | 6 +- > drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 +- > drivers/gpu/drm/xe/xe_device.c | 62 +- > drivers/gpu/drm/xe/xe_device.h | 8 +- > drivers/gpu/drm/xe/xe_device_types.h | 2 +- > drivers/gpu/drm/xe/xe_engine.c | 850 ------------- > drivers/gpu/drm/xe/xe_engine.h | 63 - > drivers/gpu/drm/xe/xe_exec.c | 62 +- > drivers/gpu/drm/xe/xe_exec_queue.c | 850 +++++++++++++ > drivers/gpu/drm/xe/xe_exec_queue.h | 63 + > ...e_engine_types.h => xe_exec_queue_types.h} | 110 +- > drivers/gpu/drm/xe/xe_execlist.c | 126 +- > drivers/gpu/drm/xe/xe_execlist_types.h | 8 +- > drivers/gpu/drm/xe/xe_gt.c | 72 +- > drivers/gpu/drm/xe/xe_gt_types.h | 6 +- > drivers/gpu/drm/xe/xe_guc_ads.c | 2 +- > drivers/gpu/drm/xe/xe_guc_ct.c | 10 +- > ...gine_types.h => xe_guc_exec_queue_types.h} | 10 +- > drivers/gpu/drm/xe/xe_guc_fwif.h | 6 +- > drivers/gpu/drm/xe/xe_guc_submit.c | 1074 ++++++++--------- > drivers/gpu/drm/xe/xe_guc_submit.h | 20 +- > drivers/gpu/drm/xe/xe_guc_submit_types.h | 20 +- > drivers/gpu/drm/xe/xe_guc_types.h | 4 +- > drivers/gpu/drm/xe/xe_lrc.c | 10 +- > drivers/gpu/drm/xe/xe_lrc.h | 4 +- > drivers/gpu/drm/xe/xe_migrate.c | 62 +- > drivers/gpu/drm/xe/xe_migrate.h | 6 +- > drivers/gpu/drm/xe/xe_mocs.c | 2 +- > drivers/gpu/drm/xe/xe_mocs.h | 2 +- > drivers/gpu/drm/xe/xe_preempt_fence.c | 32 +- > drivers/gpu/drm/xe/xe_preempt_fence.h | 4 +- > drivers/gpu/drm/xe/xe_preempt_fence_types.h | 5 +- > drivers/gpu/drm/xe/xe_pt.c | 18 +- > drivers/gpu/drm/xe/xe_pt.h | 6 +- > drivers/gpu/drm/xe/xe_query.c | 4 +- > drivers/gpu/drm/xe/xe_ring_ops.c | 38 +- > drivers/gpu/drm/xe/xe_sched_job.c | 76 +- > drivers/gpu/drm/xe/xe_sched_job.h | 4 +- > drivers/gpu/drm/xe/xe_sched_job_types.h | 6 +- > drivers/gpu/drm/xe/xe_trace.h | 140 +-- > drivers/gpu/drm/xe/xe_vm.c | 178 +-- > drivers/gpu/drm/xe/xe_vm.h | 4 +- > drivers/gpu/drm/xe/xe_vm_types.h | 6 +- > include/uapi/drm/xe_drm.h | 86 +- > 49 files changed, 2111 insertions(+), 2112 deletions(-) > delete mode 100644 drivers/gpu/drm/xe/xe_engine.c > delete mode 100644 drivers/gpu/drm/xe/xe_engine.h > create mode 100644 drivers/gpu/drm/xe/xe_exec_queue.c > create mode 100644 drivers/gpu/drm/xe/xe_exec_queue.h > rename drivers/gpu/drm/xe/{xe_engine_types.h => xe_exec_queue_types.h} (52%) > rename drivers/gpu/drm/xe/{xe_guc_engine_types.h => xe_guc_exec_queue_types.h} (88%) > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile > index 4ea9e3150c20..e79624ab2cb3 100644 > --- a/drivers/gpu/drm/xe/Makefile > +++ b/drivers/gpu/drm/xe/Makefile > @@ -51,9 +51,9 @@ xe-y += xe_bb.o \ > xe_device.o \ > xe_device_sysfs.o \ > xe_dma_buf.o \ > - xe_engine.o \ > xe_exec.o \ > xe_execlist.o \ > + xe_exec_queue.o \ > xe_force_wake.o \ > xe_ggtt.o \ > xe_gt.o \ > diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c > index 9e9b228fe315..5c8d5e78d9bc 100644 > --- a/drivers/gpu/drm/xe/tests/xe_migrate.c > +++ b/drivers/gpu/drm/xe/tests/xe_migrate.c > @@ -38,7 +38,7 @@ static int run_sanity_job(struct xe_migrate *m, struct xe_device *xe, > struct kunit *test) > { > u64 batch_base = xe_migrate_batch_base(m, xe->info.supports_usm); > - struct xe_sched_job *job = xe_bb_create_migration_job(m->eng, bb, > + struct xe_sched_job *job = xe_bb_create_migration_job(m->q, bb, > batch_base, > second_idx); > struct dma_fence *fence; > @@ -215,7 +215,7 @@ static void test_pt_update(struct xe_migrate *m, struct xe_bo *pt, > xe_map_memset(xe, &pt->vmap, 0, (u8)expected, pt->size); > > then = ktime_get(); > - fence = xe_migrate_update_pgtables(m, NULL, NULL, m->eng, &update, 1, > + fence = xe_migrate_update_pgtables(m, NULL, NULL, m->q, &update, 1, > NULL, 0, &pt_update); > now = ktime_get(); > if (sanity_fence_failed(xe, fence, "Migration pagetable update", test)) > @@ -257,7 +257,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) > return; > } > > - big = xe_bo_create_pin_map(xe, tile, m->eng->vm, SZ_4M, > + big = xe_bo_create_pin_map(xe, tile, m->q->vm, SZ_4M, > ttm_bo_type_kernel, > XE_BO_CREATE_VRAM_IF_DGFX(tile) | > XE_BO_CREATE_PINNED_BIT); > @@ -266,7 +266,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) > goto vunmap; > } > > - pt = xe_bo_create_pin_map(xe, tile, m->eng->vm, XE_PAGE_SIZE, > + pt = xe_bo_create_pin_map(xe, tile, m->q->vm, XE_PAGE_SIZE, > ttm_bo_type_kernel, > XE_BO_CREATE_VRAM_IF_DGFX(tile) | > XE_BO_CREATE_PINNED_BIT); > @@ -276,7 +276,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) > goto free_big; > } > > - tiny = xe_bo_create_pin_map(xe, tile, m->eng->vm, > + tiny = xe_bo_create_pin_map(xe, tile, m->q->vm, > 2 * SZ_4K, > ttm_bo_type_kernel, > XE_BO_CREATE_VRAM_IF_DGFX(tile) | > @@ -295,14 +295,14 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) > } > > kunit_info(test, "Starting tests, top level PT addr: %lx, special pagetable base addr: %lx\n", > - (unsigned long)xe_bo_main_addr(m->eng->vm->pt_root[id]->bo, XE_PAGE_SIZE), > + (unsigned long)xe_bo_main_addr(m->q->vm->pt_root[id]->bo, XE_PAGE_SIZE), > (unsigned long)xe_bo_main_addr(m->pt_bo, XE_PAGE_SIZE)); > > /* First part of the test, are we updating our pagetable bo with a new entry? */ > xe_map_wr(xe, &bo->vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1), u64, > 0xdeaddeadbeefbeef); > expected = xe_pte_encode(pt, 0, XE_CACHE_WB, 0); > - if (m->eng->vm->flags & XE_VM_FLAG_64K) > + if (m->q->vm->flags & XE_VM_FLAG_64K) > expected |= XE_PTE_PS64; > if (xe_bo_is_vram(pt)) > xe_res_first(pt->ttm.resource, 0, pt->size, &src_it); > @@ -399,11 +399,11 @@ static int migrate_test_run_device(struct xe_device *xe) > struct ww_acquire_ctx ww; > > kunit_info(test, "Testing tile id %d.\n", id); > - xe_vm_lock(m->eng->vm, &ww, 0, true); > + xe_vm_lock(m->q->vm, &ww, 0, true); > xe_device_mem_access_get(xe); > xe_migrate_sanity_test(m, test); > xe_device_mem_access_put(xe); > - xe_vm_unlock(m->eng->vm, &ww); > + xe_vm_unlock(m->q->vm, &ww); > } > > return 0; > diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c > index b15a7cb7db4c..38f4ce83a207 100644 > --- a/drivers/gpu/drm/xe/xe_bb.c > +++ b/drivers/gpu/drm/xe/xe_bb.c > @@ -7,7 +7,7 @@ > > #include "regs/xe_gpu_commands.h" > #include "xe_device.h" > -#include "xe_engine_types.h" > +#include "xe_exec_queue_types.h" > #include "xe_gt.h" > #include "xe_hw_fence.h" > #include "xe_sa.h" > @@ -60,30 +60,30 @@ struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm) > } > > static struct xe_sched_job * > -__xe_bb_create_job(struct xe_engine *kernel_eng, struct xe_bb *bb, u64 *addr) > +__xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 *addr) > { > u32 size = drm_suballoc_size(bb->bo); > > bb->cs[bb->len++] = MI_BATCH_BUFFER_END; > > - WARN_ON(bb->len * 4 + bb_prefetch(kernel_eng->gt) > size); > + WARN_ON(bb->len * 4 + bb_prefetch(q->gt) > size); > > xe_sa_bo_flush_write(bb->bo); > > - return xe_sched_job_create(kernel_eng, addr); > + return xe_sched_job_create(q, addr); > } > > -struct xe_sched_job *xe_bb_create_wa_job(struct xe_engine *wa_eng, > +struct xe_sched_job *xe_bb_create_wa_job(struct xe_exec_queue *q, > struct xe_bb *bb, u64 batch_base_ofs) > { > u64 addr = batch_base_ofs + drm_suballoc_soffset(bb->bo); > > - XE_WARN_ON(!(wa_eng->vm->flags & XE_VM_FLAG_MIGRATION)); > + XE_WARN_ON(!(q->vm->flags & XE_VM_FLAG_MIGRATION)); > > - return __xe_bb_create_job(wa_eng, bb, &addr); > + return __xe_bb_create_job(q, bb, &addr); > } > > -struct xe_sched_job *xe_bb_create_migration_job(struct xe_engine *kernel_eng, > +struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q, > struct xe_bb *bb, > u64 batch_base_ofs, > u32 second_idx) > @@ -95,18 +95,18 @@ struct xe_sched_job *xe_bb_create_migration_job(struct xe_engine *kernel_eng, > }; > > XE_WARN_ON(second_idx > bb->len); > - XE_WARN_ON(!(kernel_eng->vm->flags & XE_VM_FLAG_MIGRATION)); > + XE_WARN_ON(!(q->vm->flags & XE_VM_FLAG_MIGRATION)); > > - return __xe_bb_create_job(kernel_eng, bb, addr); > + return __xe_bb_create_job(q, bb, addr); > } > > -struct xe_sched_job *xe_bb_create_job(struct xe_engine *kernel_eng, > +struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q, > struct xe_bb *bb) > { > u64 addr = xe_sa_bo_gpu_addr(bb->bo); > > - XE_WARN_ON(kernel_eng->vm && kernel_eng->vm->flags & XE_VM_FLAG_MIGRATION); > - return __xe_bb_create_job(kernel_eng, bb, &addr); > + XE_WARN_ON(q->vm && q->vm->flags & XE_VM_FLAG_MIGRATION); > + return __xe_bb_create_job(q, bb, &addr); > } > > void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence) > diff --git a/drivers/gpu/drm/xe/xe_bb.h b/drivers/gpu/drm/xe/xe_bb.h > index 0cc9260c9634..c5ae0770bab5 100644 > --- a/drivers/gpu/drm/xe/xe_bb.h > +++ b/drivers/gpu/drm/xe/xe_bb.h > @@ -11,16 +11,16 @@ > struct dma_fence; > > struct xe_gt; > -struct xe_engine; > +struct xe_exec_queue; > struct xe_sched_job; > > struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 size, bool usm); > -struct xe_sched_job *xe_bb_create_job(struct xe_engine *kernel_eng, > +struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q, > struct xe_bb *bb); > -struct xe_sched_job *xe_bb_create_migration_job(struct xe_engine *kernel_eng, > +struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q, > struct xe_bb *bb, u64 batch_ofs, > u32 second_idx); > -struct xe_sched_job *xe_bb_create_wa_job(struct xe_engine *wa_eng, > +struct xe_sched_job *xe_bb_create_wa_job(struct xe_exec_queue *q, > struct xe_bb *bb, u64 batch_ofs); > void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence); > > diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c > index f53f4b51233a..68abc0b195be 100644 > --- a/drivers/gpu/drm/xe/xe_devcoredump.c > +++ b/drivers/gpu/drm/xe/xe_devcoredump.c > @@ -10,7 +10,7 @@ > #include <generated/utsrelease.h> > > #include "xe_device.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_force_wake.h" > #include "xe_gt.h" > #include "xe_guc_ct.h" > @@ -53,9 +53,9 @@ static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump) > return container_of(coredump, struct xe_device, devcoredump); > } > > -static struct xe_guc *engine_to_guc(struct xe_engine *e) > +static struct xe_guc *exec_queue_to_guc(struct xe_exec_queue *q) > { > - return &e->gt->uc.guc; > + return &q->gt->uc.guc; > } > > static ssize_t xe_devcoredump_read(char *buffer, loff_t offset, > @@ -91,7 +91,7 @@ static ssize_t xe_devcoredump_read(char *buffer, loff_t offset, > > drm_printf(&p, "\n**** GuC CT ****\n"); > xe_guc_ct_snapshot_print(coredump->snapshot.ct, &p); > - xe_guc_engine_snapshot_print(coredump->snapshot.ge, &p); > + xe_guc_exec_queue_snapshot_print(coredump->snapshot.ge, &p); > > drm_printf(&p, "\n**** HW Engines ****\n"); > for (i = 0; i < XE_NUM_HW_ENGINES; i++) > @@ -112,7 +112,7 @@ static void xe_devcoredump_free(void *data) > return; > > xe_guc_ct_snapshot_free(coredump->snapshot.ct); > - xe_guc_engine_snapshot_free(coredump->snapshot.ge); > + xe_guc_exec_queue_snapshot_free(coredump->snapshot.ge); > for (i = 0; i < XE_NUM_HW_ENGINES; i++) > if (coredump->snapshot.hwe[i]) > xe_hw_engine_snapshot_free(coredump->snapshot.hwe[i]); > @@ -123,14 +123,14 @@ static void xe_devcoredump_free(void *data) > } > > static void devcoredump_snapshot(struct xe_devcoredump *coredump, > - struct xe_engine *e) > + struct xe_exec_queue *q) > { > struct xe_devcoredump_snapshot *ss = &coredump->snapshot; > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > struct xe_hw_engine *hwe; > enum xe_hw_engine_id id; > - u32 adj_logical_mask = e->logical_mask; > - u32 width_mask = (0x1 << e->width) - 1; > + u32 adj_logical_mask = q->logical_mask; > + u32 width_mask = (0x1 << q->width) - 1; > int i; > bool cookie; > > @@ -138,22 +138,22 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump, > ss->boot_time = ktime_get_boottime(); > > cookie = dma_fence_begin_signalling(); > - for (i = 0; e->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { > + for (i = 0; q->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { > if (adj_logical_mask & BIT(i)) { > adj_logical_mask |= width_mask << i; > - i += e->width; > + i += q->width; > } else { > ++i; > } > } > > - xe_force_wake_get(gt_to_fw(e->gt), XE_FORCEWAKE_ALL); > + xe_force_wake_get(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); > > coredump->snapshot.ct = xe_guc_ct_snapshot_capture(&guc->ct, true); > - coredump->snapshot.ge = xe_guc_engine_snapshot_capture(e); > + coredump->snapshot.ge = xe_guc_exec_queue_snapshot_capture(q); > > - for_each_hw_engine(hwe, e->gt, id) { > - if (hwe->class != e->hwe->class || > + for_each_hw_engine(hwe, q->gt, id) { > + if (hwe->class != q->hwe->class || > !(BIT(hwe->logical_instance) & adj_logical_mask)) { > coredump->snapshot.hwe[id] = NULL; > continue; > @@ -161,21 +161,21 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump, > coredump->snapshot.hwe[id] = xe_hw_engine_snapshot_capture(hwe); > } > > - xe_force_wake_put(gt_to_fw(e->gt), XE_FORCEWAKE_ALL); > + xe_force_wake_put(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); > dma_fence_end_signalling(cookie); > } > > /** > * xe_devcoredump - Take the required snapshots and initialize coredump device. > - * @e: The faulty xe_engine, where the issue was detected. > + * @q: The faulty xe_exec_queue, where the issue was detected. > * > * This function should be called at the crash time within the serialized > * gt_reset. It is skipped if we still have the core dump device available > * with the information of the 'first' snapshot. > */ > -void xe_devcoredump(struct xe_engine *e) > +void xe_devcoredump(struct xe_exec_queue *q) > { > - struct xe_device *xe = gt_to_xe(e->gt); > + struct xe_device *xe = gt_to_xe(q->gt); > struct xe_devcoredump *coredump = &xe->devcoredump; > > if (coredump->captured) { > @@ -184,7 +184,7 @@ void xe_devcoredump(struct xe_engine *e) > } > > coredump->captured = true; > - devcoredump_snapshot(coredump, e); > + devcoredump_snapshot(coredump, q); > > drm_info(&xe->drm, "Xe device coredump has been created\n"); > drm_info(&xe->drm, "Check your /sys/class/drm/card%d/device/devcoredump/data\n", > diff --git a/drivers/gpu/drm/xe/xe_devcoredump.h b/drivers/gpu/drm/xe/xe_devcoredump.h > index 854882129227..6ac218a5c194 100644 > --- a/drivers/gpu/drm/xe/xe_devcoredump.h > +++ b/drivers/gpu/drm/xe/xe_devcoredump.h > @@ -7,12 +7,12 @@ > #define _XE_DEVCOREDUMP_H_ > > struct xe_device; > -struct xe_engine; > +struct xe_exec_queue; > > #ifdef CONFIG_DEV_COREDUMP > -void xe_devcoredump(struct xe_engine *e); > +void xe_devcoredump(struct xe_exec_queue *q); > #else > -static inline void xe_devcoredump(struct xe_engine *e) > +static inline void xe_devcoredump(struct xe_exec_queue *q) > { > } > #endif > diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h > index c0d711eb6ab3..7fdad9c3d3dd 100644 > --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h > +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h > @@ -30,7 +30,7 @@ struct xe_devcoredump_snapshot { > /** @ct: GuC CT snapshot */ > struct xe_guc_ct_snapshot *ct; > /** @ge: Guc Engine snapshot */ > - struct xe_guc_submit_engine_snapshot *ge; > + struct xe_guc_submit_exec_queue_snapshot *ge; > /** @hwe: HW Engine snapshot array */ > struct xe_hw_engine_snapshot *hwe[XE_NUM_HW_ENGINES]; > }; > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c > index 5409cf7895d3..766df07de979 100644 > --- a/drivers/gpu/drm/xe/xe_device.c > +++ b/drivers/gpu/drm/xe/xe_device.c > @@ -19,7 +19,7 @@ > #include "xe_display.h" > #include "xe_dma_buf.h" > #include "xe_drv.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_exec.h" > #include "xe_gt.h" > #include "xe_irq.h" > @@ -54,33 +54,33 @@ static int xe_file_open(struct drm_device *dev, struct drm_file *file) > mutex_init(&xef->vm.lock); > xa_init_flags(&xef->vm.xa, XA_FLAGS_ALLOC1); > > - mutex_init(&xef->engine.lock); > - xa_init_flags(&xef->engine.xa, XA_FLAGS_ALLOC1); > + mutex_init(&xef->exec_queue.lock); > + xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1); > > file->driver_priv = xef; > return 0; > } > > -static void device_kill_persistent_engines(struct xe_device *xe, > - struct xe_file *xef); > +static void device_kill_persistent_exec_queues(struct xe_device *xe, > + struct xe_file *xef); > > static void xe_file_close(struct drm_device *dev, struct drm_file *file) > { > struct xe_device *xe = to_xe_device(dev); > struct xe_file *xef = file->driver_priv; > struct xe_vm *vm; > - struct xe_engine *e; > + struct xe_exec_queue *q; > unsigned long idx; > > - mutex_lock(&xef->engine.lock); > - xa_for_each(&xef->engine.xa, idx, e) { > - xe_engine_kill(e); > - xe_engine_put(e); > + mutex_lock(&xef->exec_queue.lock); > + xa_for_each(&xef->exec_queue.xa, idx, q) { > + xe_exec_queue_kill(q); > + xe_exec_queue_put(q); > } > - mutex_unlock(&xef->engine.lock); > - xa_destroy(&xef->engine.xa); > - mutex_destroy(&xef->engine.lock); > - device_kill_persistent_engines(xe, xef); > + mutex_unlock(&xef->exec_queue.lock); > + xa_destroy(&xef->exec_queue.xa); > + mutex_destroy(&xef->exec_queue.lock); > + device_kill_persistent_exec_queues(xe, xef); > > mutex_lock(&xef->vm.lock); > xa_for_each(&xef->vm.xa, idx, vm) > @@ -100,15 +100,15 @@ static const struct drm_ioctl_desc xe_ioctls[] = { > DRM_IOCTL_DEF_DRV(XE_VM_CREATE, xe_vm_create_ioctl, DRM_RENDER_ALLOW), > DRM_IOCTL_DEF_DRV(XE_VM_DESTROY, xe_vm_destroy_ioctl, DRM_RENDER_ALLOW), > DRM_IOCTL_DEF_DRV(XE_VM_BIND, xe_vm_bind_ioctl, DRM_RENDER_ALLOW), > - DRM_IOCTL_DEF_DRV(XE_ENGINE_CREATE, xe_engine_create_ioctl, > + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_CREATE, xe_exec_queue_create_ioctl, > DRM_RENDER_ALLOW), > - DRM_IOCTL_DEF_DRV(XE_ENGINE_GET_PROPERTY, xe_engine_get_property_ioctl, > + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_GET_PROPERTY, xe_exec_queue_get_property_ioctl, > DRM_RENDER_ALLOW), > - DRM_IOCTL_DEF_DRV(XE_ENGINE_DESTROY, xe_engine_destroy_ioctl, > + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_DESTROY, xe_exec_queue_destroy_ioctl, > DRM_RENDER_ALLOW), > DRM_IOCTL_DEF_DRV(XE_EXEC, xe_exec_ioctl, DRM_RENDER_ALLOW), > DRM_IOCTL_DEF_DRV(XE_MMIO, xe_mmio_ioctl, DRM_RENDER_ALLOW), > - DRM_IOCTL_DEF_DRV(XE_ENGINE_SET_PROPERTY, xe_engine_set_property_ioctl, > + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_SET_PROPERTY, xe_exec_queue_set_property_ioctl, > DRM_RENDER_ALLOW), > DRM_IOCTL_DEF_DRV(XE_WAIT_USER_FENCE, xe_wait_user_fence_ioctl, > DRM_RENDER_ALLOW), > @@ -372,33 +372,33 @@ void xe_device_shutdown(struct xe_device *xe) > { > } > > -void xe_device_add_persistent_engines(struct xe_device *xe, struct xe_engine *e) > +void xe_device_add_persistent_exec_queues(struct xe_device *xe, struct xe_exec_queue *q) > { > mutex_lock(&xe->persistent_engines.lock); > - list_add_tail(&e->persistent.link, &xe->persistent_engines.list); > + list_add_tail(&q->persistent.link, &xe->persistent_engines.list); > mutex_unlock(&xe->persistent_engines.lock); > } > > -void xe_device_remove_persistent_engines(struct xe_device *xe, > - struct xe_engine *e) > +void xe_device_remove_persistent_exec_queues(struct xe_device *xe, > + struct xe_exec_queue *q) > { > mutex_lock(&xe->persistent_engines.lock); > - if (!list_empty(&e->persistent.link)) > - list_del(&e->persistent.link); > + if (!list_empty(&q->persistent.link)) > + list_del(&q->persistent.link); > mutex_unlock(&xe->persistent_engines.lock); > } > > -static void device_kill_persistent_engines(struct xe_device *xe, > - struct xe_file *xef) > +static void device_kill_persistent_exec_queues(struct xe_device *xe, > + struct xe_file *xef) > { > - struct xe_engine *e, *next; > + struct xe_exec_queue *q, *next; > > mutex_lock(&xe->persistent_engines.lock); > - list_for_each_entry_safe(e, next, &xe->persistent_engines.list, > + list_for_each_entry_safe(q, next, &xe->persistent_engines.list, > persistent.link) > - if (e->persistent.xef == xef) { > - xe_engine_kill(e); > - list_del_init(&e->persistent.link); > + if (q->persistent.xef == xef) { > + xe_exec_queue_kill(q); > + list_del_init(&q->persistent.link); > } > mutex_unlock(&xe->persistent_engines.lock); > } > diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h > index 61a5cf1f7300..71582094834c 100644 > --- a/drivers/gpu/drm/xe/xe_device.h > +++ b/drivers/gpu/drm/xe/xe_device.h > @@ -6,7 +6,7 @@ > #ifndef _XE_DEVICE_H_ > #define _XE_DEVICE_H_ > > -struct xe_engine; > +struct xe_exec_queue; > struct xe_file; > > #include <drm/drm_util.h> > @@ -41,9 +41,9 @@ int xe_device_probe(struct xe_device *xe); > void xe_device_remove(struct xe_device *xe); > void xe_device_shutdown(struct xe_device *xe); > > -void xe_device_add_persistent_engines(struct xe_device *xe, struct xe_engine *e); > -void xe_device_remove_persistent_engines(struct xe_device *xe, > - struct xe_engine *e); > +void xe_device_add_persistent_exec_queues(struct xe_device *xe, struct xe_exec_queue *q); > +void xe_device_remove_persistent_exec_queues(struct xe_device *xe, > + struct xe_exec_queue *q); > > void xe_device_wmb(struct xe_device *xe); > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h > index b156f69d7320..f6665cd16a66 100644 > --- a/drivers/gpu/drm/xe/xe_device_types.h > +++ b/drivers/gpu/drm/xe/xe_device_types.h > @@ -494,7 +494,7 @@ struct xe_file { > struct xarray xa; > /** @lock: protects file engine state */ > struct mutex lock; > - } engine; > + } exec_queue; > }; > > #endif > diff --git a/drivers/gpu/drm/xe/xe_engine.c b/drivers/gpu/drm/xe/xe_engine.c > deleted file mode 100644 > index c30810a687b1..000000000000 > --- a/drivers/gpu/drm/xe/xe_engine.c > +++ /dev/null > @@ -1,850 +0,0 @@ > -// SPDX-License-Identifier: MIT > -/* > - * Copyright © 2021 Intel Corporation > - */ > - > -#include "xe_engine.h" > - > -#include <linux/nospec.h> > - > -#include <drm/drm_device.h> > -#include <drm/drm_file.h> > -#include <drm/xe_drm.h> > - > -#include "xe_device.h" > -#include "xe_gt.h" > -#include "xe_hw_fence.h" > -#include "xe_lrc.h" > -#include "xe_macros.h" > -#include "xe_migrate.h" > -#include "xe_pm.h" > -#include "xe_ring_ops_types.h" > -#include "xe_trace.h" > -#include "xe_vm.h" > - > -static struct xe_engine *__xe_engine_create(struct xe_device *xe, > - struct xe_vm *vm, > - u32 logical_mask, > - u16 width, struct xe_hw_engine *hwe, > - u32 flags) > -{ > - struct xe_engine *e; > - struct xe_gt *gt = hwe->gt; > - int err; > - int i; > - > - e = kzalloc(sizeof(*e) + sizeof(struct xe_lrc) * width, GFP_KERNEL); > - if (!e) > - return ERR_PTR(-ENOMEM); > - > - kref_init(&e->refcount); > - e->flags = flags; > - e->hwe = hwe; > - e->gt = gt; > - if (vm) > - e->vm = xe_vm_get(vm); > - e->class = hwe->class; > - e->width = width; > - e->logical_mask = logical_mask; > - e->fence_irq = >->fence_irq[hwe->class]; > - e->ring_ops = gt->ring_ops[hwe->class]; > - e->ops = gt->engine_ops; > - INIT_LIST_HEAD(&e->persistent.link); > - INIT_LIST_HEAD(&e->compute.link); > - INIT_LIST_HEAD(&e->multi_gt_link); > - > - /* FIXME: Wire up to configurable default value */ > - e->sched_props.timeslice_us = 1 * 1000; > - e->sched_props.preempt_timeout_us = 640 * 1000; > - > - if (xe_engine_is_parallel(e)) { > - e->parallel.composite_fence_ctx = dma_fence_context_alloc(1); > - e->parallel.composite_fence_seqno = XE_FENCE_INITIAL_SEQNO; > - } > - if (e->flags & ENGINE_FLAG_VM) { > - e->bind.fence_ctx = dma_fence_context_alloc(1); > - e->bind.fence_seqno = XE_FENCE_INITIAL_SEQNO; > - } > - > - for (i = 0; i < width; ++i) { > - err = xe_lrc_init(e->lrc + i, hwe, e, vm, SZ_16K); > - if (err) > - goto err_lrc; > - } > - > - err = e->ops->init(e); > - if (err) > - goto err_lrc; > - > - /* > - * Normally the user vm holds an rpm ref to keep the device > - * awake, and the context holds a ref for the vm, however for > - * some engines we use the kernels migrate vm underneath which > - * offers no such rpm ref. Make sure we keep a ref here, so we > - * can perform GuC CT actions when needed. Caller is expected to > - * have already grabbed the rpm ref outside any sensitive locks. > - */ > - if (e->flags & ENGINE_FLAG_VM) > - drm_WARN_ON(&xe->drm, !xe_device_mem_access_get_if_ongoing(xe)); > - > - return e; > - > -err_lrc: > - for (i = i - 1; i >= 0; --i) > - xe_lrc_finish(e->lrc + i); > - kfree(e); > - return ERR_PTR(err); > -} > - > -struct xe_engine *xe_engine_create(struct xe_device *xe, struct xe_vm *vm, > - u32 logical_mask, u16 width, > - struct xe_hw_engine *hwe, u32 flags) > -{ > - struct ww_acquire_ctx ww; > - struct xe_engine *e; > - int err; > - > - if (vm) { > - err = xe_vm_lock(vm, &ww, 0, true); > - if (err) > - return ERR_PTR(err); > - } > - e = __xe_engine_create(xe, vm, logical_mask, width, hwe, flags); > - if (vm) > - xe_vm_unlock(vm, &ww); > - > - return e; > -} > - > -struct xe_engine *xe_engine_create_class(struct xe_device *xe, struct xe_gt *gt, > - struct xe_vm *vm, > - enum xe_engine_class class, u32 flags) > -{ > - struct xe_hw_engine *hwe, *hwe0 = NULL; > - enum xe_hw_engine_id id; > - u32 logical_mask = 0; > - > - for_each_hw_engine(hwe, gt, id) { > - if (xe_hw_engine_is_reserved(hwe)) > - continue; > - > - if (hwe->class == class) { > - logical_mask |= BIT(hwe->logical_instance); > - if (!hwe0) > - hwe0 = hwe; > - } > - } > - > - if (!logical_mask) > - return ERR_PTR(-ENODEV); > - > - return xe_engine_create(xe, vm, logical_mask, 1, hwe0, flags); > -} > - > -void xe_engine_destroy(struct kref *ref) > -{ > - struct xe_engine *e = container_of(ref, struct xe_engine, refcount); > - struct xe_engine *engine, *next; > - > - if (!(e->flags & ENGINE_FLAG_BIND_ENGINE_CHILD)) { > - list_for_each_entry_safe(engine, next, &e->multi_gt_list, > - multi_gt_link) > - xe_engine_put(engine); > - } > - > - e->ops->fini(e); > -} > - > -void xe_engine_fini(struct xe_engine *e) > -{ > - int i; > - > - for (i = 0; i < e->width; ++i) > - xe_lrc_finish(e->lrc + i); > - if (e->vm) > - xe_vm_put(e->vm); > - if (e->flags & ENGINE_FLAG_VM) > - xe_device_mem_access_put(gt_to_xe(e->gt)); > - > - kfree(e); > -} > - > -struct xe_engine *xe_engine_lookup(struct xe_file *xef, u32 id) > -{ > - struct xe_engine *e; > - > - mutex_lock(&xef->engine.lock); > - e = xa_load(&xef->engine.xa, id); > - if (e) > - xe_engine_get(e); > - mutex_unlock(&xef->engine.lock); > - > - return e; > -} > - > -enum drm_sched_priority > -xe_engine_device_get_max_priority(struct xe_device *xe) > -{ > - return capable(CAP_SYS_NICE) ? DRM_SCHED_PRIORITY_HIGH : > - DRM_SCHED_PRIORITY_NORMAL; > -} > - > -static int engine_set_priority(struct xe_device *xe, struct xe_engine *e, > - u64 value, bool create) > -{ > - if (XE_IOCTL_DBG(xe, value > DRM_SCHED_PRIORITY_HIGH)) > - return -EINVAL; > - > - if (XE_IOCTL_DBG(xe, value > xe_engine_device_get_max_priority(xe))) > - return -EPERM; > - > - return e->ops->set_priority(e, value); > -} > - > -static int engine_set_timeslice(struct xe_device *xe, struct xe_engine *e, > - u64 value, bool create) > -{ > - if (!capable(CAP_SYS_NICE)) > - return -EPERM; > - > - return e->ops->set_timeslice(e, value); > -} > - > -static int engine_set_preemption_timeout(struct xe_device *xe, > - struct xe_engine *e, u64 value, > - bool create) > -{ > - if (!capable(CAP_SYS_NICE)) > - return -EPERM; > - > - return e->ops->set_preempt_timeout(e, value); > -} > - > -static int engine_set_compute_mode(struct xe_device *xe, struct xe_engine *e, > - u64 value, bool create) > -{ > - if (XE_IOCTL_DBG(xe, !create)) > - return -EINVAL; > - > - if (XE_IOCTL_DBG(xe, e->flags & ENGINE_FLAG_COMPUTE_MODE)) > - return -EINVAL; > - > - if (XE_IOCTL_DBG(xe, e->flags & ENGINE_FLAG_VM)) > - return -EINVAL; > - > - if (value) { > - struct xe_vm *vm = e->vm; > - int err; > - > - if (XE_IOCTL_DBG(xe, xe_vm_in_fault_mode(vm))) > - return -EOPNOTSUPP; > - > - if (XE_IOCTL_DBG(xe, !xe_vm_in_compute_mode(vm))) > - return -EOPNOTSUPP; > - > - if (XE_IOCTL_DBG(xe, e->width != 1)) > - return -EINVAL; > - > - e->compute.context = dma_fence_context_alloc(1); > - spin_lock_init(&e->compute.lock); > - > - err = xe_vm_add_compute_engine(vm, e); > - if (XE_IOCTL_DBG(xe, err)) > - return err; > - > - e->flags |= ENGINE_FLAG_COMPUTE_MODE; > - e->flags &= ~ENGINE_FLAG_PERSISTENT; > - } > - > - return 0; > -} > - > -static int engine_set_persistence(struct xe_device *xe, struct xe_engine *e, > - u64 value, bool create) > -{ > - if (XE_IOCTL_DBG(xe, !create)) > - return -EINVAL; > - > - if (XE_IOCTL_DBG(xe, e->flags & ENGINE_FLAG_COMPUTE_MODE)) > - return -EINVAL; > - > - if (value) > - e->flags |= ENGINE_FLAG_PERSISTENT; > - else > - e->flags &= ~ENGINE_FLAG_PERSISTENT; > - > - return 0; > -} > - > -static int engine_set_job_timeout(struct xe_device *xe, struct xe_engine *e, > - u64 value, bool create) > -{ > - if (XE_IOCTL_DBG(xe, !create)) > - return -EINVAL; > - > - if (!capable(CAP_SYS_NICE)) > - return -EPERM; > - > - return e->ops->set_job_timeout(e, value); > -} > - > -static int engine_set_acc_trigger(struct xe_device *xe, struct xe_engine *e, > - u64 value, bool create) > -{ > - if (XE_IOCTL_DBG(xe, !create)) > - return -EINVAL; > - > - if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > - return -EINVAL; > - > - e->usm.acc_trigger = value; > - > - return 0; > -} > - > -static int engine_set_acc_notify(struct xe_device *xe, struct xe_engine *e, > - u64 value, bool create) > -{ > - if (XE_IOCTL_DBG(xe, !create)) > - return -EINVAL; > - > - if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > - return -EINVAL; > - > - e->usm.acc_notify = value; > - > - return 0; > -} > - > -static int engine_set_acc_granularity(struct xe_device *xe, struct xe_engine *e, > - u64 value, bool create) > -{ > - if (XE_IOCTL_DBG(xe, !create)) > - return -EINVAL; > - > - if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > - return -EINVAL; > - > - e->usm.acc_granularity = value; > - > - return 0; > -} > - > -typedef int (*xe_engine_set_property_fn)(struct xe_device *xe, > - struct xe_engine *e, > - u64 value, bool create); > - > -static const xe_engine_set_property_fn engine_set_property_funcs[] = { > - [XE_ENGINE_SET_PROPERTY_PRIORITY] = engine_set_priority, > - [XE_ENGINE_SET_PROPERTY_TIMESLICE] = engine_set_timeslice, > - [XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT] = engine_set_preemption_timeout, > - [XE_ENGINE_SET_PROPERTY_COMPUTE_MODE] = engine_set_compute_mode, > - [XE_ENGINE_SET_PROPERTY_PERSISTENCE] = engine_set_persistence, > - [XE_ENGINE_SET_PROPERTY_JOB_TIMEOUT] = engine_set_job_timeout, > - [XE_ENGINE_SET_PROPERTY_ACC_TRIGGER] = engine_set_acc_trigger, > - [XE_ENGINE_SET_PROPERTY_ACC_NOTIFY] = engine_set_acc_notify, > - [XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY] = engine_set_acc_granularity, > -}; > - > -static int engine_user_ext_set_property(struct xe_device *xe, > - struct xe_engine *e, > - u64 extension, > - bool create) > -{ > - u64 __user *address = u64_to_user_ptr(extension); > - struct drm_xe_ext_engine_set_property ext; > - int err; > - u32 idx; > - > - err = __copy_from_user(&ext, address, sizeof(ext)); > - if (XE_IOCTL_DBG(xe, err)) > - return -EFAULT; > - > - if (XE_IOCTL_DBG(xe, ext.property >= > - ARRAY_SIZE(engine_set_property_funcs)) || > - XE_IOCTL_DBG(xe, ext.pad)) > - return -EINVAL; > - > - idx = array_index_nospec(ext.property, ARRAY_SIZE(engine_set_property_funcs)); > - return engine_set_property_funcs[idx](xe, e, ext.value, create); > -} > - > -typedef int (*xe_engine_user_extension_fn)(struct xe_device *xe, > - struct xe_engine *e, > - u64 extension, > - bool create); > - > -static const xe_engine_set_property_fn engine_user_extension_funcs[] = { > - [XE_ENGINE_EXTENSION_SET_PROPERTY] = engine_user_ext_set_property, > -}; > - > -#define MAX_USER_EXTENSIONS 16 > -static int engine_user_extensions(struct xe_device *xe, struct xe_engine *e, > - u64 extensions, int ext_number, bool create) > -{ > - u64 __user *address = u64_to_user_ptr(extensions); > - struct xe_user_extension ext; > - int err; > - u32 idx; > - > - if (XE_IOCTL_DBG(xe, ext_number >= MAX_USER_EXTENSIONS)) > - return -E2BIG; > - > - err = __copy_from_user(&ext, address, sizeof(ext)); > - if (XE_IOCTL_DBG(xe, err)) > - return -EFAULT; > - > - if (XE_IOCTL_DBG(xe, ext.pad) || > - XE_IOCTL_DBG(xe, ext.name >= > - ARRAY_SIZE(engine_user_extension_funcs))) > - return -EINVAL; > - > - idx = array_index_nospec(ext.name, > - ARRAY_SIZE(engine_user_extension_funcs)); > - err = engine_user_extension_funcs[idx](xe, e, extensions, create); > - if (XE_IOCTL_DBG(xe, err)) > - return err; > - > - if (ext.next_extension) > - return engine_user_extensions(xe, e, ext.next_extension, > - ++ext_number, create); > - > - return 0; > -} > - > -static const enum xe_engine_class user_to_xe_engine_class[] = { > - [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, > - [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, > - [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, > - [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, > - [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, > -}; > - > -static struct xe_hw_engine * > -find_hw_engine(struct xe_device *xe, > - struct drm_xe_engine_class_instance eci) > -{ > - u32 idx; > - > - if (eci.engine_class > ARRAY_SIZE(user_to_xe_engine_class)) > - return NULL; > - > - if (eci.gt_id >= xe->info.gt_count) > - return NULL; > - > - idx = array_index_nospec(eci.engine_class, > - ARRAY_SIZE(user_to_xe_engine_class)); > - > - return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id), > - user_to_xe_engine_class[idx], > - eci.engine_instance, true); > -} > - > -static u32 bind_engine_logical_mask(struct xe_device *xe, struct xe_gt *gt, > - struct drm_xe_engine_class_instance *eci, > - u16 width, u16 num_placements) > -{ > - struct xe_hw_engine *hwe; > - enum xe_hw_engine_id id; > - u32 logical_mask = 0; > - > - if (XE_IOCTL_DBG(xe, width != 1)) > - return 0; > - if (XE_IOCTL_DBG(xe, num_placements != 1)) > - return 0; > - if (XE_IOCTL_DBG(xe, eci[0].engine_instance != 0)) > - return 0; > - > - eci[0].engine_class = DRM_XE_ENGINE_CLASS_COPY; > - > - for_each_hw_engine(hwe, gt, id) { > - if (xe_hw_engine_is_reserved(hwe)) > - continue; > - > - if (hwe->class == > - user_to_xe_engine_class[DRM_XE_ENGINE_CLASS_COPY]) > - logical_mask |= BIT(hwe->logical_instance); > - } > - > - return logical_mask; > -} > - > -static u32 calc_validate_logical_mask(struct xe_device *xe, struct xe_gt *gt, > - struct drm_xe_engine_class_instance *eci, > - u16 width, u16 num_placements) > -{ > - int len = width * num_placements; > - int i, j, n; > - u16 class; > - u16 gt_id; > - u32 return_mask = 0, prev_mask; > - > - if (XE_IOCTL_DBG(xe, !xe_device_guc_submission_enabled(xe) && > - len > 1)) > - return 0; > - > - for (i = 0; i < width; ++i) { > - u32 current_mask = 0; > - > - for (j = 0; j < num_placements; ++j) { > - struct xe_hw_engine *hwe; > - > - n = j * width + i; > - > - hwe = find_hw_engine(xe, eci[n]); > - if (XE_IOCTL_DBG(xe, !hwe)) > - return 0; > - > - if (XE_IOCTL_DBG(xe, xe_hw_engine_is_reserved(hwe))) > - return 0; > - > - if (XE_IOCTL_DBG(xe, n && eci[n].gt_id != gt_id) || > - XE_IOCTL_DBG(xe, n && eci[n].engine_class != class)) > - return 0; > - > - class = eci[n].engine_class; > - gt_id = eci[n].gt_id; > - > - if (width == 1 || !i) > - return_mask |= BIT(eci[n].engine_instance); > - current_mask |= BIT(eci[n].engine_instance); > - } > - > - /* Parallel submissions must be logically contiguous */ > - if (i && XE_IOCTL_DBG(xe, current_mask != prev_mask << 1)) > - return 0; > - > - prev_mask = current_mask; > - } > - > - return return_mask; > -} > - > -int xe_engine_create_ioctl(struct drm_device *dev, void *data, > - struct drm_file *file) > -{ > - struct xe_device *xe = to_xe_device(dev); > - struct xe_file *xef = to_xe_file(file); > - struct drm_xe_engine_create *args = data; > - struct drm_xe_engine_class_instance eci[XE_HW_ENGINE_MAX_INSTANCE]; > - struct drm_xe_engine_class_instance __user *user_eci = > - u64_to_user_ptr(args->instances); > - struct xe_hw_engine *hwe; > - struct xe_vm *vm, *migrate_vm; > - struct xe_gt *gt; > - struct xe_engine *e = NULL; > - u32 logical_mask; > - u32 id; > - u32 len; > - int err; > - > - if (XE_IOCTL_DBG(xe, args->flags) || > - XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > - return -EINVAL; > - > - len = args->width * args->num_placements; > - if (XE_IOCTL_DBG(xe, !len || len > XE_HW_ENGINE_MAX_INSTANCE)) > - return -EINVAL; > - > - err = __copy_from_user(eci, user_eci, > - sizeof(struct drm_xe_engine_class_instance) * > - len); > - if (XE_IOCTL_DBG(xe, err)) > - return -EFAULT; > - > - if (XE_IOCTL_DBG(xe, eci[0].gt_id >= xe->info.gt_count)) > - return -EINVAL; > - > - if (eci[0].engine_class == DRM_XE_ENGINE_CLASS_VM_BIND) { > - for_each_gt(gt, xe, id) { > - struct xe_engine *new; > - > - if (xe_gt_is_media_type(gt)) > - continue; > - > - eci[0].gt_id = gt->info.id; > - logical_mask = bind_engine_logical_mask(xe, gt, eci, > - args->width, > - args->num_placements); > - if (XE_IOCTL_DBG(xe, !logical_mask)) > - return -EINVAL; > - > - hwe = find_hw_engine(xe, eci[0]); > - if (XE_IOCTL_DBG(xe, !hwe)) > - return -EINVAL; > - > - /* The migration vm doesn't hold rpm ref */ > - xe_device_mem_access_get(xe); > - > - migrate_vm = xe_migrate_get_vm(gt_to_tile(gt)->migrate); > - new = xe_engine_create(xe, migrate_vm, logical_mask, > - args->width, hwe, > - ENGINE_FLAG_PERSISTENT | > - ENGINE_FLAG_VM | > - (id ? > - ENGINE_FLAG_BIND_ENGINE_CHILD : > - 0)); > - > - xe_device_mem_access_put(xe); /* now held by engine */ > - > - xe_vm_put(migrate_vm); > - if (IS_ERR(new)) { > - err = PTR_ERR(new); > - if (e) > - goto put_engine; > - return err; > - } > - if (id == 0) > - e = new; > - else > - list_add_tail(&new->multi_gt_list, > - &e->multi_gt_link); > - } > - } else { > - gt = xe_device_get_gt(xe, eci[0].gt_id); > - logical_mask = calc_validate_logical_mask(xe, gt, eci, > - args->width, > - args->num_placements); > - if (XE_IOCTL_DBG(xe, !logical_mask)) > - return -EINVAL; > - > - hwe = find_hw_engine(xe, eci[0]); > - if (XE_IOCTL_DBG(xe, !hwe)) > - return -EINVAL; > - > - vm = xe_vm_lookup(xef, args->vm_id); > - if (XE_IOCTL_DBG(xe, !vm)) > - return -ENOENT; > - > - err = down_read_interruptible(&vm->lock); > - if (err) { > - xe_vm_put(vm); > - return err; > - } > - > - if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) { > - up_read(&vm->lock); > - xe_vm_put(vm); > - return -ENOENT; > - } > - > - e = xe_engine_create(xe, vm, logical_mask, > - args->width, hwe, > - xe_vm_no_dma_fences(vm) ? 0 : > - ENGINE_FLAG_PERSISTENT); > - up_read(&vm->lock); > - xe_vm_put(vm); > - if (IS_ERR(e)) > - return PTR_ERR(e); > - } > - > - if (args->extensions) { > - err = engine_user_extensions(xe, e, args->extensions, 0, true); > - if (XE_IOCTL_DBG(xe, err)) > - goto put_engine; > - } > - > - if (XE_IOCTL_DBG(xe, e->vm && xe_vm_in_compute_mode(e->vm) != > - !!(e->flags & ENGINE_FLAG_COMPUTE_MODE))) { > - err = -EOPNOTSUPP; > - goto put_engine; > - } > - > - e->persistent.xef = xef; > - > - mutex_lock(&xef->engine.lock); > - err = xa_alloc(&xef->engine.xa, &id, e, xa_limit_32b, GFP_KERNEL); > - mutex_unlock(&xef->engine.lock); > - if (err) > - goto put_engine; > - > - args->engine_id = id; > - > - return 0; > - > -put_engine: > - xe_engine_kill(e); > - xe_engine_put(e); > - return err; > -} > - > -int xe_engine_get_property_ioctl(struct drm_device *dev, void *data, > - struct drm_file *file) > -{ > - struct xe_device *xe = to_xe_device(dev); > - struct xe_file *xef = to_xe_file(file); > - struct drm_xe_engine_get_property *args = data; > - struct xe_engine *e; > - int ret; > - > - if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > - return -EINVAL; > - > - e = xe_engine_lookup(xef, args->engine_id); > - if (XE_IOCTL_DBG(xe, !e)) > - return -ENOENT; > - > - switch (args->property) { > - case XE_ENGINE_GET_PROPERTY_BAN: > - args->value = !!(e->flags & ENGINE_FLAG_BANNED); > - ret = 0; > - break; > - default: > - ret = -EINVAL; > - } > - > - xe_engine_put(e); > - > - return ret; > -} > - > -static void engine_kill_compute(struct xe_engine *e) > -{ > - if (!xe_vm_in_compute_mode(e->vm)) > - return; > - > - down_write(&e->vm->lock); > - list_del(&e->compute.link); > - --e->vm->preempt.num_engines; > - if (e->compute.pfence) { > - dma_fence_enable_sw_signaling(e->compute.pfence); > - dma_fence_put(e->compute.pfence); > - e->compute.pfence = NULL; > - } > - up_write(&e->vm->lock); > -} > - > -/** > - * xe_engine_is_lr() - Whether an engine is long-running > - * @e: The engine > - * > - * Return: True if the engine is long-running, false otherwise. > - */ > -bool xe_engine_is_lr(struct xe_engine *e) > -{ > - return e->vm && xe_vm_no_dma_fences(e->vm) && > - !(e->flags & ENGINE_FLAG_VM); > -} > - > -static s32 xe_engine_num_job_inflight(struct xe_engine *e) > -{ > - return e->lrc->fence_ctx.next_seqno - xe_lrc_seqno(e->lrc) - 1; > -} > - > -/** > - * xe_engine_ring_full() - Whether an engine's ring is full > - * @e: The engine > - * > - * Return: True if the engine's ring is full, false otherwise. > - */ > -bool xe_engine_ring_full(struct xe_engine *e) > -{ > - struct xe_lrc *lrc = e->lrc; > - s32 max_job = lrc->ring.size / MAX_JOB_SIZE_BYTES; > - > - return xe_engine_num_job_inflight(e) >= max_job; > -} > - > -/** > - * xe_engine_is_idle() - Whether an engine is idle. > - * @engine: The engine > - * > - * FIXME: Need to determine what to use as the short-lived > - * timeline lock for the engines, so that the return value > - * of this function becomes more than just an advisory > - * snapshot in time. The timeline lock must protect the > - * seqno from racing submissions on the same engine. > - * Typically vm->resv, but user-created timeline locks use the migrate vm > - * and never grabs the migrate vm->resv so we have a race there. > - * > - * Return: True if the engine is idle, false otherwise. > - */ > -bool xe_engine_is_idle(struct xe_engine *engine) > -{ > - if (XE_WARN_ON(xe_engine_is_parallel(engine))) > - return false; > - > - return xe_lrc_seqno(&engine->lrc[0]) == > - engine->lrc[0].fence_ctx.next_seqno - 1; > -} > - > -void xe_engine_kill(struct xe_engine *e) > -{ > - struct xe_engine *engine = e, *next; > - > - list_for_each_entry_safe(engine, next, &engine->multi_gt_list, > - multi_gt_link) { > - e->ops->kill(engine); > - engine_kill_compute(engine); > - } > - > - e->ops->kill(e); > - engine_kill_compute(e); > -} > - > -int xe_engine_destroy_ioctl(struct drm_device *dev, void *data, > - struct drm_file *file) > -{ > - struct xe_device *xe = to_xe_device(dev); > - struct xe_file *xef = to_xe_file(file); > - struct drm_xe_engine_destroy *args = data; > - struct xe_engine *e; > - > - if (XE_IOCTL_DBG(xe, args->pad) || > - XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > - return -EINVAL; > - > - mutex_lock(&xef->engine.lock); > - e = xa_erase(&xef->engine.xa, args->engine_id); > - mutex_unlock(&xef->engine.lock); > - if (XE_IOCTL_DBG(xe, !e)) > - return -ENOENT; > - > - if (!(e->flags & ENGINE_FLAG_PERSISTENT)) > - xe_engine_kill(e); > - else > - xe_device_add_persistent_engines(xe, e); > - > - trace_xe_engine_close(e); > - xe_engine_put(e); > - > - return 0; > -} > - > -int xe_engine_set_property_ioctl(struct drm_device *dev, void *data, > - struct drm_file *file) > -{ > - struct xe_device *xe = to_xe_device(dev); > - struct xe_file *xef = to_xe_file(file); > - struct drm_xe_engine_set_property *args = data; > - struct xe_engine *e; > - int ret; > - u32 idx; > - > - if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > - return -EINVAL; > - > - e = xe_engine_lookup(xef, args->engine_id); > - if (XE_IOCTL_DBG(xe, !e)) > - return -ENOENT; > - > - if (XE_IOCTL_DBG(xe, args->property >= > - ARRAY_SIZE(engine_set_property_funcs))) { > - ret = -EINVAL; > - goto out; > - } > - > - idx = array_index_nospec(args->property, > - ARRAY_SIZE(engine_set_property_funcs)); > - ret = engine_set_property_funcs[idx](xe, e, args->value, false); > - if (XE_IOCTL_DBG(xe, ret)) > - goto out; > - > - if (args->extensions) > - ret = engine_user_extensions(xe, e, args->extensions, 0, > - false); > -out: > - xe_engine_put(e); > - > - return ret; > -} > diff --git a/drivers/gpu/drm/xe/xe_engine.h b/drivers/gpu/drm/xe/xe_engine.h > deleted file mode 100644 > index 2e60f6d90226..000000000000 > --- a/drivers/gpu/drm/xe/xe_engine.h > +++ /dev/null > @@ -1,63 +0,0 @@ > -/* SPDX-License-Identifier: MIT */ > -/* > - * Copyright © 2021 Intel Corporation > - */ > - > -#ifndef _XE_ENGINE_H_ > -#define _XE_ENGINE_H_ > - > -#include "xe_engine_types.h" > -#include "xe_vm_types.h" > - > -struct drm_device; > -struct drm_file; > -struct xe_device; > -struct xe_file; > - > -struct xe_engine *xe_engine_create(struct xe_device *xe, struct xe_vm *vm, > - u32 logical_mask, u16 width, > - struct xe_hw_engine *hw_engine, u32 flags); > -struct xe_engine *xe_engine_create_class(struct xe_device *xe, struct xe_gt *gt, > - struct xe_vm *vm, > - enum xe_engine_class class, u32 flags); > - > -void xe_engine_fini(struct xe_engine *e); > -void xe_engine_destroy(struct kref *ref); > - > -struct xe_engine *xe_engine_lookup(struct xe_file *xef, u32 id); > - > -static inline struct xe_engine *xe_engine_get(struct xe_engine *engine) > -{ > - kref_get(&engine->refcount); > - return engine; > -} > - > -static inline void xe_engine_put(struct xe_engine *engine) > -{ > - kref_put(&engine->refcount, xe_engine_destroy); > -} > - > -static inline bool xe_engine_is_parallel(struct xe_engine *engine) > -{ > - return engine->width > 1; > -} > - > -bool xe_engine_is_lr(struct xe_engine *e); > - > -bool xe_engine_ring_full(struct xe_engine *e); > - > -bool xe_engine_is_idle(struct xe_engine *engine); > - > -void xe_engine_kill(struct xe_engine *e); > - > -int xe_engine_create_ioctl(struct drm_device *dev, void *data, > - struct drm_file *file); > -int xe_engine_destroy_ioctl(struct drm_device *dev, void *data, > - struct drm_file *file); > -int xe_engine_set_property_ioctl(struct drm_device *dev, void *data, > - struct drm_file *file); > -int xe_engine_get_property_ioctl(struct drm_device *dev, void *data, > - struct drm_file *file); > -enum drm_sched_priority xe_engine_device_get_max_priority(struct xe_device *xe); > - > -#endif > diff --git a/drivers/gpu/drm/xe/xe_exec.c b/drivers/gpu/drm/xe/xe_exec.c > index fff4a9d9d12a..8a5b614df090 100644 > --- a/drivers/gpu/drm/xe/xe_exec.c > +++ b/drivers/gpu/drm/xe/xe_exec.c > @@ -12,7 +12,7 @@ > > #include "xe_bo.h" > #include "xe_device.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_macros.h" > #include "xe_ring_ops_types.h" > #include "xe_sched_job.h" > @@ -95,19 +95,19 @@ > > #define XE_EXEC_BIND_RETRY_TIMEOUT_MS 1000 > > -static int xe_exec_begin(struct xe_engine *e, struct ww_acquire_ctx *ww, > +static int xe_exec_begin(struct xe_exec_queue *q, struct ww_acquire_ctx *ww, > struct ttm_validate_buffer tv_onstack[], > struct ttm_validate_buffer **tv, > struct list_head *objs) > { > - struct xe_vm *vm = e->vm; > + struct xe_vm *vm = q->vm; > struct xe_vma *vma; > LIST_HEAD(dups); > ktime_t end = 0; > int err = 0; > > *tv = NULL; > - if (xe_vm_no_dma_fences(e->vm)) > + if (xe_vm_no_dma_fences(q->vm)) > return 0; > > retry: > @@ -153,14 +153,14 @@ static int xe_exec_begin(struct xe_engine *e, struct ww_acquire_ctx *ww, > return err; > } > > -static void xe_exec_end(struct xe_engine *e, > +static void xe_exec_end(struct xe_exec_queue *q, > struct ttm_validate_buffer *tv_onstack, > struct ttm_validate_buffer *tv, > struct ww_acquire_ctx *ww, > struct list_head *objs) > { > - if (!xe_vm_no_dma_fences(e->vm)) > - xe_vm_unlock_dma_resv(e->vm, tv_onstack, tv, ww, objs); > + if (!xe_vm_no_dma_fences(q->vm)) > + xe_vm_unlock_dma_resv(q->vm, tv_onstack, tv, ww, objs); > } > > int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > @@ -170,7 +170,7 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > struct drm_xe_exec *args = data; > struct drm_xe_sync __user *syncs_user = u64_to_user_ptr(args->syncs); > u64 __user *addresses_user = u64_to_user_ptr(args->address); > - struct xe_engine *engine; > + struct xe_exec_queue *q; > struct xe_sync_entry *syncs = NULL; > u64 addresses[XE_HW_ENGINE_MAX_INSTANCE]; > struct ttm_validate_buffer tv_onstack[XE_ONSTACK_TV]; > @@ -189,30 +189,30 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > return -EINVAL; > > - engine = xe_engine_lookup(xef, args->engine_id); > - if (XE_IOCTL_DBG(xe, !engine)) > + q = xe_exec_queue_lookup(xef, args->exec_queue_id); > + if (XE_IOCTL_DBG(xe, !q)) > return -ENOENT; > > - if (XE_IOCTL_DBG(xe, engine->flags & ENGINE_FLAG_VM)) > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_VM)) > return -EINVAL; > > - if (XE_IOCTL_DBG(xe, engine->width != args->num_batch_buffer)) > + if (XE_IOCTL_DBG(xe, q->width != args->num_batch_buffer)) > return -EINVAL; > > - if (XE_IOCTL_DBG(xe, engine->flags & ENGINE_FLAG_BANNED)) { > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_BANNED)) { > err = -ECANCELED; > - goto err_engine; > + goto err_exec_queue; > } > > if (args->num_syncs) { > syncs = kcalloc(args->num_syncs, sizeof(*syncs), GFP_KERNEL); > if (!syncs) { > err = -ENOMEM; > - goto err_engine; > + goto err_exec_queue; > } > } > > - vm = engine->vm; > + vm = q->vm; > > for (i = 0; i < args->num_syncs; i++) { > err = xe_sync_entry_parse(xe, xef, &syncs[num_syncs++], > @@ -222,9 +222,9 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > goto err_syncs; > } > > - if (xe_engine_is_parallel(engine)) { > + if (xe_exec_queue_is_parallel(q)) { > err = __copy_from_user(addresses, addresses_user, sizeof(u64) * > - engine->width); > + q->width); > if (err) { > err = -EFAULT; > goto err_syncs; > @@ -294,26 +294,26 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > goto err_unlock_list; > } > > - err = xe_exec_begin(engine, &ww, tv_onstack, &tv, &objs); > + err = xe_exec_begin(q, &ww, tv_onstack, &tv, &objs); > if (err) > goto err_unlock_list; > > - if (xe_vm_is_closed_or_banned(engine->vm)) { > + if (xe_vm_is_closed_or_banned(q->vm)) { > drm_warn(&xe->drm, "Trying to schedule after vm is closed or banned\n"); > err = -ECANCELED; > - goto err_engine_end; > + goto err_exec_queue_end; > } > > - if (xe_engine_is_lr(engine) && xe_engine_ring_full(engine)) { > + if (xe_exec_queue_is_lr(q) && xe_exec_queue_ring_full(q)) { > err = -EWOULDBLOCK; > - goto err_engine_end; > + goto err_exec_queue_end; > } > > - job = xe_sched_job_create(engine, xe_engine_is_parallel(engine) ? > + job = xe_sched_job_create(q, xe_exec_queue_is_parallel(q) ? > addresses : &args->address); > if (IS_ERR(job)) { > err = PTR_ERR(job); > - goto err_engine_end; > + goto err_exec_queue_end; > } > > /* > @@ -395,8 +395,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > xe_sync_entry_signal(&syncs[i], job, > &job->drm.s_fence->finished); > > - if (xe_engine_is_lr(engine)) > - engine->ring_ops->emit_job(job); > + if (xe_exec_queue_is_lr(q)) > + q->ring_ops->emit_job(job); > xe_sched_job_push(job); > xe_vm_reactivate_rebind(vm); > > @@ -412,8 +412,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > err_put_job: > if (err) > xe_sched_job_put(job); > -err_engine_end: > - xe_exec_end(engine, tv_onstack, tv, &ww, &objs); > +err_exec_queue_end: > + xe_exec_end(q, tv_onstack, tv, &ww, &objs); > err_unlock_list: > if (write_locked) > up_write(&vm->lock); > @@ -425,8 +425,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > for (i = 0; i < num_syncs; i++) > xe_sync_entry_cleanup(&syncs[i]); > kfree(syncs); > -err_engine: > - xe_engine_put(engine); > +err_exec_queue: > + xe_exec_queue_put(q); > > return err; > } > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c > new file mode 100644 > index 000000000000..49cff0dd2bc7 > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c > @@ -0,0 +1,850 @@ > +// SPDX-License-Identifier: MIT > +/* > + * Copyright © 2021 Intel Corporation > + */ > + > +#include "xe_exec_queue.h" > + > +#include <linux/nospec.h> > + > +#include <drm/drm_device.h> > +#include <drm/drm_file.h> > +#include <drm/xe_drm.h> > + > +#include "xe_device.h" > +#include "xe_gt.h" > +#include "xe_hw_fence.h" > +#include "xe_lrc.h" > +#include "xe_macros.h" > +#include "xe_migrate.h" > +#include "xe_pm.h" > +#include "xe_ring_ops_types.h" > +#include "xe_trace.h" > +#include "xe_vm.h" > + > +static struct xe_exec_queue *__xe_exec_queue_create(struct xe_device *xe, > + struct xe_vm *vm, > + u32 logical_mask, > + u16 width, struct xe_hw_engine *hwe, > + u32 flags) > +{ > + struct xe_exec_queue *q; > + struct xe_gt *gt = hwe->gt; > + int err; > + int i; > + > + q = kzalloc(sizeof(*q) + sizeof(struct xe_lrc) * width, GFP_KERNEL); > + if (!q) > + return ERR_PTR(-ENOMEM); > + > + kref_init(&q->refcount); > + q->flags = flags; > + q->hwe = hwe; > + q->gt = gt; > + if (vm) > + q->vm = xe_vm_get(vm); > + q->class = hwe->class; > + q->width = width; > + q->logical_mask = logical_mask; > + q->fence_irq = >->fence_irq[hwe->class]; > + q->ring_ops = gt->ring_ops[hwe->class]; > + q->ops = gt->exec_queue_ops; > + INIT_LIST_HEAD(&q->persistent.link); > + INIT_LIST_HEAD(&q->compute.link); > + INIT_LIST_HEAD(&q->multi_gt_link); > + > + /* FIXME: Wire up to configurable default value */ > + q->sched_props.timeslice_us = 1 * 1000; > + q->sched_props.preempt_timeout_us = 640 * 1000; > + > + if (xe_exec_queue_is_parallel(q)) { > + q->parallel.composite_fence_ctx = dma_fence_context_alloc(1); > + q->parallel.composite_fence_seqno = XE_FENCE_INITIAL_SEQNO; > + } > + if (q->flags & EXEC_QUEUE_FLAG_VM) { > + q->bind.fence_ctx = dma_fence_context_alloc(1); > + q->bind.fence_seqno = XE_FENCE_INITIAL_SEQNO; > + } > + > + for (i = 0; i < width; ++i) { > + err = xe_lrc_init(q->lrc + i, hwe, q, vm, SZ_16K); > + if (err) > + goto err_lrc; > + } > + > + err = q->ops->init(q); > + if (err) > + goto err_lrc; > + > + /* > + * Normally the user vm holds an rpm ref to keep the device > + * awake, and the context holds a ref for the vm, however for > + * some engines we use the kernels migrate vm underneath which > + * offers no such rpm ref. Make sure we keep a ref here, so we > + * can perform GuC CT actions when needed. Caller is expected to > + * have already grabbed the rpm ref outside any sensitive locks. > + */ > + if (q->flags & EXEC_QUEUE_FLAG_VM) > + drm_WARN_ON(&xe->drm, !xe_device_mem_access_get_if_ongoing(xe)); > + > + return q; > + > +err_lrc: > + for (i = i - 1; i >= 0; --i) > + xe_lrc_finish(q->lrc + i); > + kfree(q); > + return ERR_PTR(err); > +} > + > +struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm, > + u32 logical_mask, u16 width, > + struct xe_hw_engine *hwe, u32 flags) > +{ > + struct ww_acquire_ctx ww; > + struct xe_exec_queue *q; > + int err; > + > + if (vm) { > + err = xe_vm_lock(vm, &ww, 0, true); > + if (err) > + return ERR_PTR(err); > + } > + q = __xe_exec_queue_create(xe, vm, logical_mask, width, hwe, flags); > + if (vm) > + xe_vm_unlock(vm, &ww); > + > + return q; > +} > + > +struct xe_exec_queue *xe_exec_queue_create_class(struct xe_device *xe, struct xe_gt *gt, > + struct xe_vm *vm, > + enum xe_engine_class class, u32 flags) > +{ > + struct xe_hw_engine *hwe, *hwe0 = NULL; > + enum xe_hw_engine_id id; > + u32 logical_mask = 0; > + > + for_each_hw_engine(hwe, gt, id) { > + if (xe_hw_engine_is_reserved(hwe)) > + continue; > + > + if (hwe->class == class) { > + logical_mask |= BIT(hwe->logical_instance); > + if (!hwe0) > + hwe0 = hwe; > + } > + } > + > + if (!logical_mask) > + return ERR_PTR(-ENODEV); > + > + return xe_exec_queue_create(xe, vm, logical_mask, 1, hwe0, flags); > +} > + > +void xe_exec_queue_destroy(struct kref *ref) > +{ > + struct xe_exec_queue *q = container_of(ref, struct xe_exec_queue, refcount); > + struct xe_exec_queue *eq, *next; > + > + if (!(q->flags & EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD)) { > + list_for_each_entry_safe(eq, next, &q->multi_gt_list, > + multi_gt_link) > + xe_exec_queue_put(eq); > + } > + > + q->ops->fini(q); > +} > + > +void xe_exec_queue_fini(struct xe_exec_queue *q) > +{ > + int i; > + > + for (i = 0; i < q->width; ++i) > + xe_lrc_finish(q->lrc + i); > + if (q->vm) > + xe_vm_put(q->vm); > + if (q->flags & EXEC_QUEUE_FLAG_VM) > + xe_device_mem_access_put(gt_to_xe(q->gt)); > + > + kfree(q); > +} > + > +struct xe_exec_queue *xe_exec_queue_lookup(struct xe_file *xef, u32 id) > +{ > + struct xe_exec_queue *q; > + > + mutex_lock(&xef->exec_queue.lock); > + q = xa_load(&xef->exec_queue.xa, id); > + if (q) > + xe_exec_queue_get(q); > + mutex_unlock(&xef->exec_queue.lock); > + > + return q; > +} > + > +enum drm_sched_priority > +xe_exec_queue_device_get_max_priority(struct xe_device *xe) > +{ > + return capable(CAP_SYS_NICE) ? DRM_SCHED_PRIORITY_HIGH : > + DRM_SCHED_PRIORITY_NORMAL; > +} > + > +static int exec_queue_set_priority(struct xe_device *xe, struct xe_exec_queue *q, > + u64 value, bool create) > +{ > + if (XE_IOCTL_DBG(xe, value > DRM_SCHED_PRIORITY_HIGH)) > + return -EINVAL; > + > + if (XE_IOCTL_DBG(xe, value > xe_exec_queue_device_get_max_priority(xe))) > + return -EPERM; > + > + return q->ops->set_priority(q, value); > +} > + > +static int exec_queue_set_timeslice(struct xe_device *xe, struct xe_exec_queue *q, > + u64 value, bool create) > +{ > + if (!capable(CAP_SYS_NICE)) > + return -EPERM; > + > + return q->ops->set_timeslice(q, value); > +} > + > +static int exec_queue_set_preemption_timeout(struct xe_device *xe, > + struct xe_exec_queue *q, u64 value, > + bool create) > +{ > + if (!capable(CAP_SYS_NICE)) > + return -EPERM; > + > + return q->ops->set_preempt_timeout(q, value); > +} > + > +static int exec_queue_set_compute_mode(struct xe_device *xe, struct xe_exec_queue *q, > + u64 value, bool create) > +{ > + if (XE_IOCTL_DBG(xe, !create)) > + return -EINVAL; > + > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_COMPUTE_MODE)) > + return -EINVAL; > + > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_VM)) > + return -EINVAL; > + > + if (value) { > + struct xe_vm *vm = q->vm; > + int err; > + > + if (XE_IOCTL_DBG(xe, xe_vm_in_fault_mode(vm))) > + return -EOPNOTSUPP; > + > + if (XE_IOCTL_DBG(xe, !xe_vm_in_compute_mode(vm))) > + return -EOPNOTSUPP; > + > + if (XE_IOCTL_DBG(xe, q->width != 1)) > + return -EINVAL; > + > + q->compute.context = dma_fence_context_alloc(1); > + spin_lock_init(&q->compute.lock); > + > + err = xe_vm_add_compute_exec_queue(vm, q); > + if (XE_IOCTL_DBG(xe, err)) > + return err; > + > + q->flags |= EXEC_QUEUE_FLAG_COMPUTE_MODE; > + q->flags &= ~EXEC_QUEUE_FLAG_PERSISTENT; > + } > + > + return 0; > +} > + > +static int exec_queue_set_persistence(struct xe_device *xe, struct xe_exec_queue *q, > + u64 value, bool create) > +{ > + if (XE_IOCTL_DBG(xe, !create)) > + return -EINVAL; > + > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_COMPUTE_MODE)) > + return -EINVAL; > + > + if (value) > + q->flags |= EXEC_QUEUE_FLAG_PERSISTENT; > + else > + q->flags &= ~EXEC_QUEUE_FLAG_PERSISTENT; > + > + return 0; > +} > + > +static int exec_queue_set_job_timeout(struct xe_device *xe, struct xe_exec_queue *q, > + u64 value, bool create) > +{ > + if (XE_IOCTL_DBG(xe, !create)) > + return -EINVAL; > + > + if (!capable(CAP_SYS_NICE)) > + return -EPERM; > + > + return q->ops->set_job_timeout(q, value); > +} > + > +static int exec_queue_set_acc_trigger(struct xe_device *xe, struct xe_exec_queue *q, > + u64 value, bool create) > +{ > + if (XE_IOCTL_DBG(xe, !create)) > + return -EINVAL; > + > + if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > + return -EINVAL; > + > + q->usm.acc_trigger = value; > + > + return 0; > +} > + > +static int exec_queue_set_acc_notify(struct xe_device *xe, struct xe_exec_queue *q, > + u64 value, bool create) > +{ > + if (XE_IOCTL_DBG(xe, !create)) > + return -EINVAL; > + > + if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > + return -EINVAL; > + > + q->usm.acc_notify = value; > + > + return 0; > +} > + > +static int exec_queue_set_acc_granularity(struct xe_device *xe, struct xe_exec_queue *q, > + u64 value, bool create) > +{ > + if (XE_IOCTL_DBG(xe, !create)) > + return -EINVAL; > + > + if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > + return -EINVAL; > + > + q->usm.acc_granularity = value; > + > + return 0; > +} > + > +typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe, > + struct xe_exec_queue *q, > + u64 value, bool create); > + > +static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = { > + [XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY] = exec_queue_set_priority, > + [XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice, > + [XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT] = exec_queue_set_preemption_timeout, > + [XE_EXEC_QUEUE_SET_PROPERTY_COMPUTE_MODE] = exec_queue_set_compute_mode, > + [XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE] = exec_queue_set_persistence, > + [XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT] = exec_queue_set_job_timeout, > + [XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER] = exec_queue_set_acc_trigger, > + [XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY] = exec_queue_set_acc_notify, > + [XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY] = exec_queue_set_acc_granularity, > +}; > + > +static int exec_queue_user_ext_set_property(struct xe_device *xe, > + struct xe_exec_queue *q, > + u64 extension, > + bool create) > +{ > + u64 __user *address = u64_to_user_ptr(extension); > + struct drm_xe_ext_exec_queue_set_property ext; > + int err; > + u32 idx; > + > + err = __copy_from_user(&ext, address, sizeof(ext)); > + if (XE_IOCTL_DBG(xe, err)) > + return -EFAULT; > + > + if (XE_IOCTL_DBG(xe, ext.property >= > + ARRAY_SIZE(exec_queue_set_property_funcs)) || > + XE_IOCTL_DBG(xe, ext.pad)) > + return -EINVAL; > + > + idx = array_index_nospec(ext.property, ARRAY_SIZE(exec_queue_set_property_funcs)); > + return exec_queue_set_property_funcs[idx](xe, q, ext.value, create); > +} > + > +typedef int (*xe_exec_queue_user_extension_fn)(struct xe_device *xe, > + struct xe_exec_queue *q, > + u64 extension, > + bool create); > + > +static const xe_exec_queue_set_property_fn exec_queue_user_extension_funcs[] = { > + [XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY] = exec_queue_user_ext_set_property, > +}; > + > +#define MAX_USER_EXTENSIONS 16 > +static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q, > + u64 extensions, int ext_number, bool create) > +{ > + u64 __user *address = u64_to_user_ptr(extensions); > + struct xe_user_extension ext; > + int err; > + u32 idx; > + > + if (XE_IOCTL_DBG(xe, ext_number >= MAX_USER_EXTENSIONS)) > + return -E2BIG; > + > + err = __copy_from_user(&ext, address, sizeof(ext)); > + if (XE_IOCTL_DBG(xe, err)) > + return -EFAULT; > + > + if (XE_IOCTL_DBG(xe, ext.pad) || > + XE_IOCTL_DBG(xe, ext.name >= > + ARRAY_SIZE(exec_queue_user_extension_funcs))) > + return -EINVAL; > + > + idx = array_index_nospec(ext.name, > + ARRAY_SIZE(exec_queue_user_extension_funcs)); > + err = exec_queue_user_extension_funcs[idx](xe, q, extensions, create); > + if (XE_IOCTL_DBG(xe, err)) > + return err; > + > + if (ext.next_extension) > + return exec_queue_user_extensions(xe, q, ext.next_extension, > + ++ext_number, create); > + > + return 0; > +} > + > +static const enum xe_engine_class user_to_xe_engine_class[] = { > + [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, > + [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, > + [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, > + [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, > + [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, > +}; > + > +static struct xe_hw_engine * > +find_hw_engine(struct xe_device *xe, > + struct drm_xe_engine_class_instance eci) > +{ > + u32 idx; > + > + if (eci.engine_class > ARRAY_SIZE(user_to_xe_engine_class)) > + return NULL; > + > + if (eci.gt_id >= xe->info.gt_count) > + return NULL; > + > + idx = array_index_nospec(eci.engine_class, > + ARRAY_SIZE(user_to_xe_engine_class)); > + > + return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id), > + user_to_xe_engine_class[idx], > + eci.engine_instance, true); > +} > + > +static u32 bind_exec_queue_logical_mask(struct xe_device *xe, struct xe_gt *gt, > + struct drm_xe_engine_class_instance *eci, > + u16 width, u16 num_placements) > +{ > + struct xe_hw_engine *hwe; > + enum xe_hw_engine_id id; > + u32 logical_mask = 0; > + > + if (XE_IOCTL_DBG(xe, width != 1)) > + return 0; > + if (XE_IOCTL_DBG(xe, num_placements != 1)) > + return 0; > + if (XE_IOCTL_DBG(xe, eci[0].engine_instance != 0)) > + return 0; > + > + eci[0].engine_class = DRM_XE_ENGINE_CLASS_COPY; > + > + for_each_hw_engine(hwe, gt, id) { > + if (xe_hw_engine_is_reserved(hwe)) > + continue; > + > + if (hwe->class == > + user_to_xe_engine_class[DRM_XE_ENGINE_CLASS_COPY]) > + logical_mask |= BIT(hwe->logical_instance); > + } > + > + return logical_mask; > +} > + > +static u32 calc_validate_logical_mask(struct xe_device *xe, struct xe_gt *gt, > + struct drm_xe_engine_class_instance *eci, > + u16 width, u16 num_placements) > +{ > + int len = width * num_placements; > + int i, j, n; > + u16 class; > + u16 gt_id; > + u32 return_mask = 0, prev_mask; > + > + if (XE_IOCTL_DBG(xe, !xe_device_guc_submission_enabled(xe) && > + len > 1)) > + return 0; > + > + for (i = 0; i < width; ++i) { > + u32 current_mask = 0; > + > + for (j = 0; j < num_placements; ++j) { > + struct xe_hw_engine *hwe; > + > + n = j * width + i; > + > + hwe = find_hw_engine(xe, eci[n]); > + if (XE_IOCTL_DBG(xe, !hwe)) > + return 0; > + > + if (XE_IOCTL_DBG(xe, xe_hw_engine_is_reserved(hwe))) > + return 0; > + > + if (XE_IOCTL_DBG(xe, n && eci[n].gt_id != gt_id) || > + XE_IOCTL_DBG(xe, n && eci[n].engine_class != class)) > + return 0; > + > + class = eci[n].engine_class; > + gt_id = eci[n].gt_id; > + > + if (width == 1 || !i) > + return_mask |= BIT(eci[n].engine_instance); > + current_mask |= BIT(eci[n].engine_instance); > + } > + > + /* Parallel submissions must be logically contiguous */ > + if (i && XE_IOCTL_DBG(xe, current_mask != prev_mask << 1)) > + return 0; > + > + prev_mask = current_mask; > + } > + > + return return_mask; > +} > + > +int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data, > + struct drm_file *file) > +{ > + struct xe_device *xe = to_xe_device(dev); > + struct xe_file *xef = to_xe_file(file); > + struct drm_xe_exec_queue_create *args = data; > + struct drm_xe_engine_class_instance eci[XE_HW_ENGINE_MAX_INSTANCE]; > + struct drm_xe_engine_class_instance __user *user_eci = > + u64_to_user_ptr(args->instances); > + struct xe_hw_engine *hwe; > + struct xe_vm *vm, *migrate_vm; > + struct xe_gt *gt; > + struct xe_exec_queue *q = NULL; > + u32 logical_mask; > + u32 id; > + u32 len; > + int err; > + > + if (XE_IOCTL_DBG(xe, args->flags) || > + XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > + return -EINVAL; > + > + len = args->width * args->num_placements; > + if (XE_IOCTL_DBG(xe, !len || len > XE_HW_ENGINE_MAX_INSTANCE)) > + return -EINVAL; > + > + err = __copy_from_user(eci, user_eci, > + sizeof(struct drm_xe_engine_class_instance) * > + len); > + if (XE_IOCTL_DBG(xe, err)) > + return -EFAULT; > + > + if (XE_IOCTL_DBG(xe, eci[0].gt_id >= xe->info.gt_count)) > + return -EINVAL; > + > + if (eci[0].engine_class == DRM_XE_ENGINE_CLASS_VM_BIND) { > + for_each_gt(gt, xe, id) { > + struct xe_exec_queue *new; > + > + if (xe_gt_is_media_type(gt)) > + continue; > + > + eci[0].gt_id = gt->info.id; > + logical_mask = bind_exec_queue_logical_mask(xe, gt, eci, > + args->width, > + args->num_placements); > + if (XE_IOCTL_DBG(xe, !logical_mask)) > + return -EINVAL; > + > + hwe = find_hw_engine(xe, eci[0]); > + if (XE_IOCTL_DBG(xe, !hwe)) > + return -EINVAL; > + > + /* The migration vm doesn't hold rpm ref */ > + xe_device_mem_access_get(xe); > + > + migrate_vm = xe_migrate_get_vm(gt_to_tile(gt)->migrate); > + new = xe_exec_queue_create(xe, migrate_vm, logical_mask, > + args->width, hwe, > + EXEC_QUEUE_FLAG_PERSISTENT | > + EXEC_QUEUE_FLAG_VM | > + (id ? > + EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD : > + 0)); > + > + xe_device_mem_access_put(xe); /* now held by engine */ > + > + xe_vm_put(migrate_vm); > + if (IS_ERR(new)) { > + err = PTR_ERR(new); > + if (q) > + goto put_exec_queue; > + return err; > + } > + if (id == 0) > + q = new; > + else > + list_add_tail(&new->multi_gt_list, > + &q->multi_gt_link); > + } > + } else { > + gt = xe_device_get_gt(xe, eci[0].gt_id); > + logical_mask = calc_validate_logical_mask(xe, gt, eci, > + args->width, > + args->num_placements); > + if (XE_IOCTL_DBG(xe, !logical_mask)) > + return -EINVAL; > + > + hwe = find_hw_engine(xe, eci[0]); > + if (XE_IOCTL_DBG(xe, !hwe)) > + return -EINVAL; > + > + vm = xe_vm_lookup(xef, args->vm_id); > + if (XE_IOCTL_DBG(xe, !vm)) > + return -ENOENT; > + > + err = down_read_interruptible(&vm->lock); > + if (err) { > + xe_vm_put(vm); > + return err; > + } > + > + if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) { > + up_read(&vm->lock); > + xe_vm_put(vm); > + return -ENOENT; > + } > + > + q = xe_exec_queue_create(xe, vm, logical_mask, > + args->width, hwe, > + xe_vm_no_dma_fences(vm) ? 0 : > + EXEC_QUEUE_FLAG_PERSISTENT); > + up_read(&vm->lock); > + xe_vm_put(vm); > + if (IS_ERR(q)) > + return PTR_ERR(q); > + } > + > + if (args->extensions) { > + err = exec_queue_user_extensions(xe, q, args->extensions, 0, true); > + if (XE_IOCTL_DBG(xe, err)) > + goto put_exec_queue; > + } > + > + if (XE_IOCTL_DBG(xe, q->vm && xe_vm_in_compute_mode(q->vm) != > + !!(q->flags & EXEC_QUEUE_FLAG_COMPUTE_MODE))) { > + err = -EOPNOTSUPP; > + goto put_exec_queue; > + } > + > + q->persistent.xef = xef; > + > + mutex_lock(&xef->exec_queue.lock); > + err = xa_alloc(&xef->exec_queue.xa, &id, q, xa_limit_32b, GFP_KERNEL); > + mutex_unlock(&xef->exec_queue.lock); > + if (err) > + goto put_exec_queue; > + > + args->exec_queue_id = id; > + > + return 0; > + > +put_exec_queue: > + xe_exec_queue_kill(q); > + xe_exec_queue_put(q); > + return err; > +} > + > +int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data, > + struct drm_file *file) > +{ > + struct xe_device *xe = to_xe_device(dev); > + struct xe_file *xef = to_xe_file(file); > + struct drm_xe_exec_queue_get_property *args = data; > + struct xe_exec_queue *q; > + int ret; > + > + if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > + return -EINVAL; > + > + q = xe_exec_queue_lookup(xef, args->exec_queue_id); > + if (XE_IOCTL_DBG(xe, !q)) > + return -ENOENT; > + > + switch (args->property) { > + case XE_EXEC_QUEUE_GET_PROPERTY_BAN: > + args->value = !!(q->flags & EXEC_QUEUE_FLAG_BANNED); > + ret = 0; > + break; > + default: > + ret = -EINVAL; > + } > + > + xe_exec_queue_put(q); > + > + return ret; > +} > + > +static void exec_queue_kill_compute(struct xe_exec_queue *q) > +{ > + if (!xe_vm_in_compute_mode(q->vm)) > + return; > + > + down_write(&q->vm->lock); > + list_del(&q->compute.link); > + --q->vm->preempt.num_engines; > + if (q->compute.pfence) { > + dma_fence_enable_sw_signaling(q->compute.pfence); > + dma_fence_put(q->compute.pfence); > + q->compute.pfence = NULL; > + } > + up_write(&q->vm->lock); > +} > + > +/** > + * xe_exec_queue_is_lr() - Whether an exec_queue is long-running > + * @q: The exec_queue > + * > + * Return: True if the exec_queue is long-running, false otherwise. > + */ > +bool xe_exec_queue_is_lr(struct xe_exec_queue *q) > +{ > + return q->vm && xe_vm_no_dma_fences(q->vm) && > + !(q->flags & EXEC_QUEUE_FLAG_VM); > +} > + > +static s32 xe_exec_queue_num_job_inflight(struct xe_exec_queue *q) > +{ > + return q->lrc->fence_ctx.next_seqno - xe_lrc_seqno(q->lrc) - 1; > +} > + > +/** > + * xe_exec_queue_ring_full() - Whether an exec_queue's ring is full > + * @q: The exec_queue > + * > + * Return: True if the exec_queue's ring is full, false otherwise. > + */ > +bool xe_exec_queue_ring_full(struct xe_exec_queue *q) > +{ > + struct xe_lrc *lrc = q->lrc; > + s32 max_job = lrc->ring.size / MAX_JOB_SIZE_BYTES; > + > + return xe_exec_queue_num_job_inflight(q) >= max_job; > +} > + > +/** > + * xe_exec_queue_is_idle() - Whether an exec_queue is idle. > + * @q: The exec_queue > + * > + * FIXME: Need to determine what to use as the short-lived > + * timeline lock for the exec_queues, so that the return value > + * of this function becomes more than just an advisory > + * snapshot in time. The timeline lock must protect the > + * seqno from racing submissions on the same exec_queue. > + * Typically vm->resv, but user-created timeline locks use the migrate vm > + * and never grabs the migrate vm->resv so we have a race there. > + * > + * Return: True if the exec_queue is idle, false otherwise. > + */ > +bool xe_exec_queue_is_idle(struct xe_exec_queue *q) > +{ > + if (XE_WARN_ON(xe_exec_queue_is_parallel(q))) > + return false; > + > + return xe_lrc_seqno(&q->lrc[0]) == > + q->lrc[0].fence_ctx.next_seqno - 1; > +} > + > +void xe_exec_queue_kill(struct xe_exec_queue *q) > +{ > + struct xe_exec_queue *eq = q, *next; > + > + list_for_each_entry_safe(eq, next, &eq->multi_gt_list, > + multi_gt_link) { > + q->ops->kill(eq); > + exec_queue_kill_compute(eq); > + } > + > + q->ops->kill(q); > + exec_queue_kill_compute(q); > +} > + > +int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data, > + struct drm_file *file) > +{ > + struct xe_device *xe = to_xe_device(dev); > + struct xe_file *xef = to_xe_file(file); > + struct drm_xe_exec_queue_destroy *args = data; > + struct xe_exec_queue *q; > + > + if (XE_IOCTL_DBG(xe, args->pad) || > + XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > + return -EINVAL; > + > + mutex_lock(&xef->exec_queue.lock); > + q = xa_erase(&xef->exec_queue.xa, args->exec_queue_id); > + mutex_unlock(&xef->exec_queue.lock); > + if (XE_IOCTL_DBG(xe, !q)) > + return -ENOENT; > + > + if (!(q->flags & EXEC_QUEUE_FLAG_PERSISTENT)) > + xe_exec_queue_kill(q); > + else > + xe_device_add_persistent_exec_queues(xe, q); > + > + trace_xe_exec_queue_close(q); > + xe_exec_queue_put(q); > + > + return 0; > +} > + > +int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data, > + struct drm_file *file) > +{ > + struct xe_device *xe = to_xe_device(dev); > + struct xe_file *xef = to_xe_file(file); > + struct drm_xe_exec_queue_set_property *args = data; > + struct xe_exec_queue *q; > + int ret; > + u32 idx; > + > + if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > + return -EINVAL; > + > + q = xe_exec_queue_lookup(xef, args->exec_queue_id); > + if (XE_IOCTL_DBG(xe, !q)) > + return -ENOENT; > + > + if (XE_IOCTL_DBG(xe, args->property >= > + ARRAY_SIZE(exec_queue_set_property_funcs))) { > + ret = -EINVAL; > + goto out; > + } > + > + idx = array_index_nospec(args->property, > + ARRAY_SIZE(exec_queue_set_property_funcs)); > + ret = exec_queue_set_property_funcs[idx](xe, q, args->value, false); > + if (XE_IOCTL_DBG(xe, ret)) > + goto out; > + > + if (args->extensions) > + ret = exec_queue_user_extensions(xe, q, args->extensions, 0, > + false); > +out: > + xe_exec_queue_put(q); > + > + return ret; > +} > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h > new file mode 100644 > index 000000000000..024bc26a7006 > --- /dev/null > +++ b/drivers/gpu/drm/xe/xe_exec_queue.h > @@ -0,0 +1,63 @@ > +/* SPDX-License-Identifier: MIT */ > +/* > + * Copyright © 2021 Intel Corporation > + */ > + > +#ifndef _XE_EXEC_QUEUE_H_ > +#define _XE_EXEC_QUEUE_H_ > + > +#include "xe_exec_queue_types.h" > +#include "xe_vm_types.h" > + > +struct drm_device; > +struct drm_file; > +struct xe_device; > +struct xe_file; > + > +struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm, > + u32 logical_mask, u16 width, > + struct xe_hw_engine *hw_engine, u32 flags); > +struct xe_exec_queue *xe_exec_queue_create_class(struct xe_device *xe, struct xe_gt *gt, > + struct xe_vm *vm, > + enum xe_engine_class class, u32 flags); > + > +void xe_exec_queue_fini(struct xe_exec_queue *q); > +void xe_exec_queue_destroy(struct kref *ref); > + > +struct xe_exec_queue *xe_exec_queue_lookup(struct xe_file *xef, u32 id); > + > +static inline struct xe_exec_queue *xe_exec_queue_get(struct xe_exec_queue *q) > +{ > + kref_get(&q->refcount); > + return q; > +} > + > +static inline void xe_exec_queue_put(struct xe_exec_queue *q) > +{ > + kref_put(&q->refcount, xe_exec_queue_destroy); > +} > + > +static inline bool xe_exec_queue_is_parallel(struct xe_exec_queue *q) > +{ > + return q->width > 1; > +} > + > +bool xe_exec_queue_is_lr(struct xe_exec_queue *q); > + > +bool xe_exec_queue_ring_full(struct xe_exec_queue *q); > + > +bool xe_exec_queue_is_idle(struct xe_exec_queue *q); > + > +void xe_exec_queue_kill(struct xe_exec_queue *q); > + > +int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data, > + struct drm_file *file); > +int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data, > + struct drm_file *file); > +int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data, > + struct drm_file *file); > +int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data, > + struct drm_file *file); > +enum drm_sched_priority xe_exec_queue_device_get_max_priority(struct xe_device *xe); > + > +#endif > diff --git a/drivers/gpu/drm/xe/xe_engine_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h > similarity index 52% > rename from drivers/gpu/drm/xe/xe_engine_types.h > rename to drivers/gpu/drm/xe/xe_exec_queue_types.h > index 7aa5d9ef7896..e3ae11b63e4a 100644 > --- a/drivers/gpu/drm/xe/xe_engine_types.h > +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h > @@ -3,8 +3,8 @@ > * Copyright © 2022 Intel Corporation > */ > > -#ifndef _XE_ENGINE_TYPES_H_ > -#define _XE_ENGINE_TYPES_H_ > +#ifndef _XE_EXEC_QUEUE_TYPES_H_ > +#define _XE_EXEC_QUEUE_TYPES_H_ > > #include <linux/kref.h> > > @@ -14,20 +14,20 @@ > #include "xe_hw_fence_types.h" > #include "xe_lrc_types.h" > > -struct xe_execlist_engine; > +struct xe_execlist_exec_queue; > struct xe_gt; > -struct xe_guc_engine; > +struct xe_guc_exec_queue; > struct xe_hw_engine; > struct xe_vm; > > /** > - * struct xe_engine - Submission engine > + * struct xe_exec_queue - Execution queue > * > * Contains all state necessary for submissions. Can either be a user object or > * a kernel object. > */ > -struct xe_engine { > - /** @gt: graphics tile this engine can submit to */ > +struct xe_exec_queue { > + /** @gt: graphics tile this exec queue can submit to */ > struct xe_gt *gt; > /** > * @hwe: A hardware of the same class. May (physical engine) or may not > @@ -35,34 +35,34 @@ struct xe_engine { > * really be used for submissions. > */ > struct xe_hw_engine *hwe; > - /** @refcount: ref count of this engine */ > + /** @refcount: ref count of this exec queue */ > struct kref refcount; > - /** @vm: VM (address space) for this engine */ > + /** @vm: VM (address space) for this exec queue */ > struct xe_vm *vm; > - /** @class: class of this engine */ > + /** @class: class of this exec queue */ > enum xe_engine_class class; > /** > - * @logical_mask: logical mask of where job submitted to engine can run > + * @logical_mask: logical mask of where job submitted to exec queue can run > */ > u32 logical_mask; > - /** @name: name of this engine */ > + /** @name: name of this exec queue */ > char name[MAX_FENCE_NAME_LEN]; > - /** @width: width (number BB submitted per exec) of this engine */ > + /** @width: width (number BB submitted per exec) of this exec queue */ > u16 width; > /** @fence_irq: fence IRQ used to signal job completion */ > struct xe_hw_fence_irq *fence_irq; > > -#define ENGINE_FLAG_BANNED BIT(0) > -#define ENGINE_FLAG_KERNEL BIT(1) > -#define ENGINE_FLAG_PERSISTENT BIT(2) > -#define ENGINE_FLAG_COMPUTE_MODE BIT(3) > -/* Caller needs to hold rpm ref when creating engine with ENGINE_FLAG_VM */ > -#define ENGINE_FLAG_VM BIT(4) > -#define ENGINE_FLAG_BIND_ENGINE_CHILD BIT(5) > -#define ENGINE_FLAG_WA BIT(6) > +#define EXEC_QUEUE_FLAG_BANNED BIT(0) > +#define EXEC_QUEUE_FLAG_KERNEL BIT(1) > +#define EXEC_QUEUE_FLAG_PERSISTENT BIT(2) > +#define EXEC_QUEUE_FLAG_COMPUTE_MODE BIT(3) > +/* Caller needs to hold rpm ref when creating engine with EXEC_QUEUE_FLAG_VM */ > +#define EXEC_QUEUE_FLAG_VM BIT(4) > +#define EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD BIT(5) > +#define EXEC_QUEUE_FLAG_WA BIT(6) > > /** > - * @flags: flags for this engine, should statically setup aside from ban > + * @flags: flags for this exec queue, should statically setup aside from ban > * bit > */ > unsigned long flags; > @@ -75,19 +75,19 @@ struct xe_engine { > }; > > union { > - /** @execlist: execlist backend specific state for engine */ > - struct xe_execlist_engine *execlist; > - /** @guc: GuC backend specific state for engine */ > - struct xe_guc_engine *guc; > + /** @execlist: execlist backend specific state for exec queue */ > + struct xe_execlist_exec_queue *execlist; > + /** @guc: GuC backend specific state for exec queue */ > + struct xe_guc_exec_queue *guc; > }; > > /** > - * @persistent: persistent engine state > + * @persistent: persistent exec queue state > */ > struct { > - /** @xef: file which this engine belongs to */ > + /** @xef: file which this exec queue belongs to */ > struct xe_file *xef; > - /** @link: link in list of persistent engines */ > + /** @link: link in list of persistent exec queues */ > struct list_head link; > } persistent; > > @@ -144,53 +144,53 @@ struct xe_engine { > u32 acc_granularity; > } usm; > > - /** @ops: submission backend engine operations */ > - const struct xe_engine_ops *ops; > + /** @ops: submission backend exec queue operations */ > + const struct xe_exec_queue_ops *ops; > > - /** @ring_ops: ring operations for this engine */ > + /** @ring_ops: ring operations for this exec queue */ > const struct xe_ring_ops *ring_ops; > - /** @entity: DRM sched entity for this engine (1 to 1 relationship) */ > + /** @entity: DRM sched entity for this exec queue (1 to 1 relationship) */ > struct drm_sched_entity *entity; > - /** @lrc: logical ring context for this engine */ > + /** @lrc: logical ring context for this exec queue */ > struct xe_lrc lrc[]; > }; > > /** > - * struct xe_engine_ops - Submission backend engine operations > + * struct xe_exec_queue_ops - Submission backend exec queue operations > */ > -struct xe_engine_ops { > - /** @init: Initialize engine for submission backend */ > - int (*init)(struct xe_engine *e); > +struct xe_exec_queue_ops { > + /** @init: Initialize exec queue for submission backend */ > + int (*init)(struct xe_exec_queue *q); > /** @kill: Kill inflight submissions for backend */ > - void (*kill)(struct xe_engine *e); > - /** @fini: Fini engine for submission backend */ > - void (*fini)(struct xe_engine *e); > - /** @set_priority: Set priority for engine */ > - int (*set_priority)(struct xe_engine *e, > + void (*kill)(struct xe_exec_queue *q); > + /** @fini: Fini exec queue for submission backend */ > + void (*fini)(struct xe_exec_queue *q); > + /** @set_priority: Set priority for exec queue */ > + int (*set_priority)(struct xe_exec_queue *q, > enum drm_sched_priority priority); > - /** @set_timeslice: Set timeslice for engine */ > - int (*set_timeslice)(struct xe_engine *e, u32 timeslice_us); > - /** @set_preempt_timeout: Set preemption timeout for engine */ > - int (*set_preempt_timeout)(struct xe_engine *e, u32 preempt_timeout_us); > - /** @set_job_timeout: Set job timeout for engine */ > - int (*set_job_timeout)(struct xe_engine *e, u32 job_timeout_ms); > + /** @set_timeslice: Set timeslice for exec queue */ > + int (*set_timeslice)(struct xe_exec_queue *q, u32 timeslice_us); > + /** @set_preempt_timeout: Set preemption timeout for exec queue */ > + int (*set_preempt_timeout)(struct xe_exec_queue *q, u32 preempt_timeout_us); > + /** @set_job_timeout: Set job timeout for exec queue */ > + int (*set_job_timeout)(struct xe_exec_queue *q, u32 job_timeout_ms); > /** > - * @suspend: Suspend engine from executing, allowed to be called > + * @suspend: Suspend exec queue from executing, allowed to be called > * multiple times in a row before resume with the caveat that > * suspend_wait returns before calling suspend again. > */ > - int (*suspend)(struct xe_engine *e); > + int (*suspend)(struct xe_exec_queue *q); > /** > - * @suspend_wait: Wait for an engine to suspend executing, should be > + * @suspend_wait: Wait for an exec queue to suspend executing, should be > * call after suspend. > */ > - void (*suspend_wait)(struct xe_engine *e); > + void (*suspend_wait)(struct xe_exec_queue *q); > /** > - * @resume: Resume engine execution, engine must be in a suspended > + * @resume: Resume exec queue execution, exec queue must be in a suspended > * state and dma fence returned from most recent suspend call must be > * signalled when this function is called. > */ > - void (*resume)(struct xe_engine *e); > + void (*resume)(struct xe_exec_queue *q); > }; > > #endif > diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c > index 0f9d919405b0..8ef98c7fd8e2 100644 > --- a/drivers/gpu/drm/xe/xe_execlist.c > +++ b/drivers/gpu/drm/xe/xe_execlist.c > @@ -14,7 +14,7 @@ > #include "regs/xe_regs.h" > #include "xe_bo.h" > #include "xe_device.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_gt.h" > #include "xe_hw_fence.h" > #include "xe_lrc.h" > @@ -91,7 +91,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, > } > > static void __xe_execlist_port_start(struct xe_execlist_port *port, > - struct xe_execlist_engine *exl) > + struct xe_execlist_exec_queue *exl) > { > struct xe_device *xe = gt_to_xe(port->hwe->gt); > int max_ctx = FIELD_MAX(GEN11_SW_CTX_ID); > @@ -109,7 +109,7 @@ static void __xe_execlist_port_start(struct xe_execlist_port *port, > port->last_ctx_id = 1; > } > > - __start_lrc(port->hwe, exl->engine->lrc, port->last_ctx_id); > + __start_lrc(port->hwe, exl->q->lrc, port->last_ctx_id); > port->running_exl = exl; > exl->has_run = true; > } > @@ -128,16 +128,16 @@ static void __xe_execlist_port_idle(struct xe_execlist_port *port) > port->running_exl = NULL; > } > > -static bool xe_execlist_is_idle(struct xe_execlist_engine *exl) > +static bool xe_execlist_is_idle(struct xe_execlist_exec_queue *exl) > { > - struct xe_lrc *lrc = exl->engine->lrc; > + struct xe_lrc *lrc = exl->q->lrc; > > return lrc->ring.tail == lrc->ring.old_tail; > } > > static void __xe_execlist_port_start_next_active(struct xe_execlist_port *port) > { > - struct xe_execlist_engine *exl = NULL; > + struct xe_execlist_exec_queue *exl = NULL; > int i; > > xe_execlist_port_assert_held(port); > @@ -145,7 +145,7 @@ static void __xe_execlist_port_start_next_active(struct xe_execlist_port *port) > for (i = ARRAY_SIZE(port->active) - 1; i >= 0; i--) { > while (!list_empty(&port->active[i])) { > exl = list_first_entry(&port->active[i], > - struct xe_execlist_engine, > + struct xe_execlist_exec_queue, > active_link); > list_del(&exl->active_link); > > @@ -208,7 +208,7 @@ static void xe_execlist_port_wake_locked(struct xe_execlist_port *port, > __xe_execlist_port_start_next_active(port); > } > > -static void xe_execlist_make_active(struct xe_execlist_engine *exl) > +static void xe_execlist_make_active(struct xe_execlist_exec_queue *exl) > { > struct xe_execlist_port *port = exl->port; > enum drm_sched_priority priority = exl->entity.priority; > @@ -293,10 +293,10 @@ static struct dma_fence * > execlist_run_job(struct drm_sched_job *drm_job) > { > struct xe_sched_job *job = to_xe_sched_job(drm_job); > - struct xe_engine *e = job->engine; > - struct xe_execlist_engine *exl = job->engine->execlist; > + struct xe_exec_queue *q = job->q; > + struct xe_execlist_exec_queue *exl = job->q->execlist; > > - e->ring_ops->emit_job(job); > + q->ring_ops->emit_job(job); > xe_execlist_make_active(exl); > > return dma_fence_get(job->fence); > @@ -314,11 +314,11 @@ static const struct drm_sched_backend_ops drm_sched_ops = { > .free_job = execlist_job_free, > }; > > -static int execlist_engine_init(struct xe_engine *e) > +static int execlist_exec_queue_init(struct xe_exec_queue *q) > { > struct drm_gpu_scheduler *sched; > - struct xe_execlist_engine *exl; > - struct xe_device *xe = gt_to_xe(e->gt); > + struct xe_execlist_exec_queue *exl; > + struct xe_device *xe = gt_to_xe(q->gt); > int err; > > XE_WARN_ON(xe_device_guc_submission_enabled(xe)); > @@ -329,14 +329,14 @@ static int execlist_engine_init(struct xe_engine *e) > if (!exl) > return -ENOMEM; > > - exl->engine = e; > + exl->q = q; > > err = drm_sched_init(&exl->sched, &drm_sched_ops, NULL, > - e->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, > + q->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, > XE_SCHED_HANG_LIMIT, XE_SCHED_JOB_TIMEOUT, > - NULL, NULL, e->hwe->name, > + NULL, NULL, q->hwe->name, > DRM_SCHED_POLICY_SINGLE_ENTITY, > - gt_to_xe(e->gt)->drm.dev); > + gt_to_xe(q->gt)->drm.dev); > if (err) > goto err_free; > > @@ -346,30 +346,30 @@ static int execlist_engine_init(struct xe_engine *e) > if (err) > goto err_sched; > > - exl->port = e->hwe->exl_port; > + exl->port = q->hwe->exl_port; > exl->has_run = false; > exl->active_priority = DRM_SCHED_PRIORITY_UNSET; > - e->execlist = exl; > - e->entity = &exl->entity; > + q->execlist = exl; > + q->entity = &exl->entity; > > - switch (e->class) { > + switch (q->class) { > case XE_ENGINE_CLASS_RENDER: > - sprintf(e->name, "rcs%d", ffs(e->logical_mask) - 1); > + sprintf(q->name, "rcs%d", ffs(q->logical_mask) - 1); > break; > case XE_ENGINE_CLASS_VIDEO_DECODE: > - sprintf(e->name, "vcs%d", ffs(e->logical_mask) - 1); > + sprintf(q->name, "vcs%d", ffs(q->logical_mask) - 1); > break; > case XE_ENGINE_CLASS_VIDEO_ENHANCE: > - sprintf(e->name, "vecs%d", ffs(e->logical_mask) - 1); > + sprintf(q->name, "vecs%d", ffs(q->logical_mask) - 1); > break; > case XE_ENGINE_CLASS_COPY: > - sprintf(e->name, "bcs%d", ffs(e->logical_mask) - 1); > + sprintf(q->name, "bcs%d", ffs(q->logical_mask) - 1); > break; > case XE_ENGINE_CLASS_COMPUTE: > - sprintf(e->name, "ccs%d", ffs(e->logical_mask) - 1); > + sprintf(q->name, "ccs%d", ffs(q->logical_mask) - 1); > break; > default: > - XE_WARN_ON(e->class); > + XE_WARN_ON(q->class); > } > > return 0; > @@ -381,96 +381,96 @@ static int execlist_engine_init(struct xe_engine *e) > return err; > } > > -static void execlist_engine_fini_async(struct work_struct *w) > +static void execlist_exec_queue_fini_async(struct work_struct *w) > { > - struct xe_execlist_engine *ee = > - container_of(w, struct xe_execlist_engine, fini_async); > - struct xe_engine *e = ee->engine; > - struct xe_execlist_engine *exl = e->execlist; > + struct xe_execlist_exec_queue *ee = > + container_of(w, struct xe_execlist_exec_queue, fini_async); > + struct xe_exec_queue *q = ee->q; > + struct xe_execlist_exec_queue *exl = q->execlist; > unsigned long flags; > > - XE_WARN_ON(xe_device_guc_submission_enabled(gt_to_xe(e->gt))); > + XE_WARN_ON(xe_device_guc_submission_enabled(gt_to_xe(q->gt))); > > spin_lock_irqsave(&exl->port->lock, flags); > if (WARN_ON(exl->active_priority != DRM_SCHED_PRIORITY_UNSET)) > list_del(&exl->active_link); > spin_unlock_irqrestore(&exl->port->lock, flags); > > - if (e->flags & ENGINE_FLAG_PERSISTENT) > - xe_device_remove_persistent_engines(gt_to_xe(e->gt), e); > + if (q->flags & EXEC_QUEUE_FLAG_PERSISTENT) > + xe_device_remove_persistent_exec_queues(gt_to_xe(q->gt), q); > drm_sched_entity_fini(&exl->entity); > drm_sched_fini(&exl->sched); > kfree(exl); > > - xe_engine_fini(e); > + xe_exec_queue_fini(q); > } > > -static void execlist_engine_kill(struct xe_engine *e) > +static void execlist_exec_queue_kill(struct xe_exec_queue *q) > { > /* NIY */ > } > > -static void execlist_engine_fini(struct xe_engine *e) > +static void execlist_exec_queue_fini(struct xe_exec_queue *q) > { > - INIT_WORK(&e->execlist->fini_async, execlist_engine_fini_async); > - queue_work(system_unbound_wq, &e->execlist->fini_async); > + INIT_WORK(&q->execlist->fini_async, execlist_exec_queue_fini_async); > + queue_work(system_unbound_wq, &q->execlist->fini_async); > } > > -static int execlist_engine_set_priority(struct xe_engine *e, > - enum drm_sched_priority priority) > +static int execlist_exec_queue_set_priority(struct xe_exec_queue *q, > + enum drm_sched_priority priority) > { > /* NIY */ > return 0; > } > > -static int execlist_engine_set_timeslice(struct xe_engine *e, u32 timeslice_us) > +static int execlist_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us) > { > /* NIY */ > return 0; > } > > -static int execlist_engine_set_preempt_timeout(struct xe_engine *e, > - u32 preempt_timeout_us) > +static int execlist_exec_queue_set_preempt_timeout(struct xe_exec_queue *q, > + u32 preempt_timeout_us) > { > /* NIY */ > return 0; > } > > -static int execlist_engine_set_job_timeout(struct xe_engine *e, > - u32 job_timeout_ms) > +static int execlist_exec_queue_set_job_timeout(struct xe_exec_queue *q, > + u32 job_timeout_ms) > { > /* NIY */ > return 0; > } > > -static int execlist_engine_suspend(struct xe_engine *e) > +static int execlist_exec_queue_suspend(struct xe_exec_queue *q) > { > /* NIY */ > return 0; > } > > -static void execlist_engine_suspend_wait(struct xe_engine *e) > +static void execlist_exec_queue_suspend_wait(struct xe_exec_queue *q) > > { > /* NIY */ > } > > -static void execlist_engine_resume(struct xe_engine *e) > +static void execlist_exec_queue_resume(struct xe_exec_queue *q) > { > /* NIY */ > } > > -static const struct xe_engine_ops execlist_engine_ops = { > - .init = execlist_engine_init, > - .kill = execlist_engine_kill, > - .fini = execlist_engine_fini, > - .set_priority = execlist_engine_set_priority, > - .set_timeslice = execlist_engine_set_timeslice, > - .set_preempt_timeout = execlist_engine_set_preempt_timeout, > - .set_job_timeout = execlist_engine_set_job_timeout, > - .suspend = execlist_engine_suspend, > - .suspend_wait = execlist_engine_suspend_wait, > - .resume = execlist_engine_resume, > +static const struct xe_exec_queue_ops execlist_exec_queue_ops = { > + .init = execlist_exec_queue_init, > + .kill = execlist_exec_queue_kill, > + .fini = execlist_exec_queue_fini, > + .set_priority = execlist_exec_queue_set_priority, > + .set_timeslice = execlist_exec_queue_set_timeslice, > + .set_preempt_timeout = execlist_exec_queue_set_preempt_timeout, > + .set_job_timeout = execlist_exec_queue_set_job_timeout, > + .suspend = execlist_exec_queue_suspend, > + .suspend_wait = execlist_exec_queue_suspend_wait, > + .resume = execlist_exec_queue_resume, > }; > > int xe_execlist_init(struct xe_gt *gt) > @@ -479,7 +479,7 @@ int xe_execlist_init(struct xe_gt *gt) > if (xe_device_guc_submission_enabled(gt_to_xe(gt))) > return 0; > > - gt->engine_ops = &execlist_engine_ops; > + gt->exec_queue_ops = &execlist_exec_queue_ops; > > return 0; > } > diff --git a/drivers/gpu/drm/xe/xe_execlist_types.h b/drivers/gpu/drm/xe/xe_execlist_types.h > index 05a620940209..ee1fccd4ee8b 100644 > --- a/drivers/gpu/drm/xe/xe_execlist_types.h > +++ b/drivers/gpu/drm/xe/xe_execlist_types.h > @@ -13,7 +13,7 @@ > #include <drm/gpu_scheduler.h> > > struct xe_hw_engine; > -struct xe_execlist_engine; > +struct xe_execlist_exec_queue; > > struct xe_execlist_port { > struct xe_hw_engine *hwe; > @@ -24,13 +24,13 @@ struct xe_execlist_port { > > u32 last_ctx_id; > > - struct xe_execlist_engine *running_exl; > + struct xe_execlist_exec_queue *running_exl; > > struct timer_list irq_fail; > }; > > -struct xe_execlist_engine { > - struct xe_engine *engine; > +struct xe_execlist_exec_queue { > + struct xe_exec_queue *q; > > struct drm_gpu_scheduler sched; > > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c > index 28bf577c7bf2..3077faa1e792 100644 > --- a/drivers/gpu/drm/xe/xe_gt.c > +++ b/drivers/gpu/drm/xe/xe_gt.c > @@ -14,7 +14,7 @@ > #include "xe_bb.h" > #include "xe_bo.h" > #include "xe_device.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_execlist.h" > #include "xe_force_wake.h" > #include "xe_ggtt.h" > @@ -26,7 +26,7 @@ > #include "xe_gt_sysfs.h" > #include "xe_gt_tlb_invalidation.h" > #include "xe_gt_topology.h" > -#include "xe_guc_engine_types.h" > +#include "xe_guc_exec_queue_types.h" > #include "xe_hw_fence.h" > #include "xe_irq.h" > #include "xe_lrc.h" > @@ -81,7 +81,7 @@ static void gt_fini(struct drm_device *drm, void *arg) > > static void gt_reset_worker(struct work_struct *w); > > -static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e) > +static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) > { > struct xe_sched_job *job; > struct xe_bb *bb; > @@ -94,7 +94,7 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e) > return PTR_ERR(bb); > > batch_ofs = xe_bo_ggtt_addr(gt_to_tile(gt)->mem.kernel_bb_pool->bo); > - job = xe_bb_create_wa_job(e, bb, batch_ofs); > + job = xe_bb_create_wa_job(q, bb, batch_ofs); > if (IS_ERR(job)) { > xe_bb_free(bb, NULL); > return PTR_ERR(job); > @@ -115,9 +115,9 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e) > return 0; > } > > -static int emit_wa_job(struct xe_gt *gt, struct xe_engine *e) > +static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) > { > - struct xe_reg_sr *sr = &e->hwe->reg_lrc; > + struct xe_reg_sr *sr = &q->hwe->reg_lrc; > struct xe_reg_sr_entry *entry; > unsigned long reg; > struct xe_sched_job *job; > @@ -143,7 +143,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_engine *e) > } > > batch_ofs = xe_bo_ggtt_addr(gt_to_tile(gt)->mem.kernel_bb_pool->bo); > - job = xe_bb_create_wa_job(e, bb, batch_ofs); > + job = xe_bb_create_wa_job(q, bb, batch_ofs); > if (IS_ERR(job)) { > xe_bb_free(bb, NULL); > return PTR_ERR(job); > @@ -173,7 +173,7 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) > int err = 0; > > for_each_hw_engine(hwe, gt, id) { > - struct xe_engine *e, *nop_e; > + struct xe_exec_queue *q, *nop_q; > struct xe_vm *vm; > void *default_lrc; > > @@ -192,58 +192,58 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) > return -ENOMEM; > > vm = xe_migrate_get_vm(tile->migrate); > - e = xe_engine_create(xe, vm, BIT(hwe->logical_instance), 1, > - hwe, ENGINE_FLAG_WA); > - if (IS_ERR(e)) { > - err = PTR_ERR(e); > - xe_gt_err(gt, "hwe %s: xe_engine_create failed (%pe)\n", > - hwe->name, e); > + q = xe_exec_queue_create(xe, vm, BIT(hwe->logical_instance), 1, > + hwe, EXEC_QUEUE_FLAG_WA); > + if (IS_ERR(q)) { > + err = PTR_ERR(q); > + xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", > + hwe->name, q); > goto put_vm; > } > > /* Prime golden LRC with known good state */ > - err = emit_wa_job(gt, e); > + err = emit_wa_job(gt, q); > if (err) { > xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", > - hwe->name, ERR_PTR(err), e->guc->id); > - goto put_engine; > + hwe->name, ERR_PTR(err), q->guc->id); > + goto put_exec_queue; > } > > - nop_e = xe_engine_create(xe, vm, BIT(hwe->logical_instance), > - 1, hwe, ENGINE_FLAG_WA); > - if (IS_ERR(nop_e)) { > - err = PTR_ERR(nop_e); > - xe_gt_err(gt, "hwe %s: nop xe_engine_create failed (%pe)\n", > - hwe->name, nop_e); > - goto put_engine; > + nop_q = xe_exec_queue_create(xe, vm, BIT(hwe->logical_instance), > + 1, hwe, EXEC_QUEUE_FLAG_WA); > + if (IS_ERR(nop_q)) { > + err = PTR_ERR(nop_q); > + xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", > + hwe->name, nop_q); > + goto put_exec_queue; > } > > /* Switch to different LRC */ > - err = emit_nop_job(gt, nop_e); > + err = emit_nop_job(gt, nop_q); > if (err) { > xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", > - hwe->name, ERR_PTR(err), nop_e->guc->id); > - goto put_nop_e; > + hwe->name, ERR_PTR(err), nop_q->guc->id); > + goto put_nop_q; > } > > /* Reload golden LRC to record the effect of any indirect W/A */ > - err = emit_nop_job(gt, e); > + err = emit_nop_job(gt, q); > if (err) { > xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n", > - hwe->name, ERR_PTR(err), e->guc->id); > - goto put_nop_e; > + hwe->name, ERR_PTR(err), q->guc->id); > + goto put_nop_q; > } > > xe_map_memcpy_from(xe, default_lrc, > - &e->lrc[0].bo->vmap, > - xe_lrc_pphwsp_offset(&e->lrc[0]), > + &q->lrc[0].bo->vmap, > + xe_lrc_pphwsp_offset(&q->lrc[0]), > xe_lrc_size(xe, hwe->class)); > > gt->default_lrc[hwe->class] = default_lrc; > -put_nop_e: > - xe_engine_put(nop_e); > -put_engine: > - xe_engine_put(e); > +put_nop_q: > + xe_exec_queue_put(nop_q); > +put_exec_queue: > + xe_exec_queue_put(q); > put_vm: > xe_vm_put(vm); > if (err) > diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h > index 78a9fe9f0bd3..c326932e53d7 100644 > --- a/drivers/gpu/drm/xe/xe_gt_types.h > +++ b/drivers/gpu/drm/xe/xe_gt_types.h > @@ -14,7 +14,7 @@ > #include "xe_sa_types.h" > #include "xe_uc_types.h" > > -struct xe_engine_ops; > +struct xe_exec_queue_ops; > struct xe_migrate; > struct xe_ring_ops; > > @@ -269,8 +269,8 @@ struct xe_gt { > /** @gtidle: idle properties of GT */ > struct xe_gt_idle gtidle; > > - /** @engine_ops: submission backend engine operations */ > - const struct xe_engine_ops *engine_ops; > + /** @exec_queue_ops: submission backend exec queue operations */ > + const struct xe_exec_queue_ops *exec_queue_ops; > > /** > * @ring_ops: ring operations for this hw engine (1 per engine class) > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c > index a7da29be2e51..7d1244df959d 100644 > --- a/drivers/gpu/drm/xe/xe_guc_ads.c > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c > @@ -495,7 +495,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads) > u8 gc; > > /* > - * 1. Write all MMIO entries for this engine to the table. No > + * 1. Write all MMIO entries for this exec queue to the table. No > * need to worry about fused-off engines and when there are > * entries in the regset: the reg_state_list has been zero'ed > * by xe_guc_ads_populate() > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c > index 7fb2690425f8..3d705c64b85d 100644 > --- a/drivers/gpu/drm/xe/xe_guc_ct.c > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c > @@ -889,11 +889,11 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len) > ret = xe_guc_deregister_done_handler(guc, payload, adj_len); > break; > case XE_GUC_ACTION_CONTEXT_RESET_NOTIFICATION: > - ret = xe_guc_engine_reset_handler(guc, payload, adj_len); > + ret = xe_guc_exec_queue_reset_handler(guc, payload, adj_len); > break; > case XE_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION: > - ret = xe_guc_engine_reset_failure_handler(guc, payload, > - adj_len); > + ret = xe_guc_exec_queue_reset_failure_handler(guc, payload, > + adj_len); > break; > case XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE: > /* Selftest only at the moment */ > @@ -903,8 +903,8 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len) > /* FIXME: Handle this */ > break; > case XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR: > - ret = xe_guc_engine_memory_cat_error_handler(guc, payload, > - adj_len); > + ret = xe_guc_exec_queue_memory_cat_error_handler(guc, payload, > + adj_len); > break; > case XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC: > ret = xe_guc_pagefault_handler(guc, payload, adj_len); > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_types.h b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h > similarity index 88% > rename from drivers/gpu/drm/xe/xe_guc_engine_types.h > rename to drivers/gpu/drm/xe/xe_guc_exec_queue_types.h > index 5d83132034a6..395ed3fba218 100644 > --- a/drivers/gpu/drm/xe/xe_guc_engine_types.h > +++ b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h > @@ -12,14 +12,14 @@ > #include <drm/gpu_scheduler.h> > > struct dma_fence; > -struct xe_engine; > +struct xe_exec_queue; > > /** > - * struct xe_guc_engine - GuC specific state for an xe_engine > + * struct xe_guc_exec_queue - GuC specific state for an xe_engine > */ > -struct xe_guc_engine { > +struct xe_guc_exec_queue { > /** @engine: Backpointer to parent xe_engine */ > - struct xe_engine *engine; > + struct xe_exec_queue *q; > /** @sched: GPU scheduler for this xe_engine */ > struct drm_gpu_scheduler sched; > /** @entity: Scheduler entity for this xe_engine */ > @@ -43,7 +43,7 @@ struct xe_guc_engine { > u32 wqi_head; > /** @wqi_tail: work queue item tail */ > u32 wqi_tail; > - /** @id: GuC id for this xe_engine */ > + /** @id: GuC id for this exec_queue */ > u16 id; > /** @suspend_wait: wait queue used to wait on pending suspends */ > wait_queue_head_t suspend_wait; > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h > index 7515d7fbb723..4216a6d9e478 100644 > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h > @@ -69,13 +69,13 @@ struct guc_klv_generic_dw_t { > } __packed; > > /* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */ > -struct guc_update_engine_policy_header { > +struct guc_update_exec_queue_policy_header { > u32 action; > u32 guc_id; > } __packed; > > -struct guc_update_engine_policy { > - struct guc_update_engine_policy_header header; > +struct guc_update_exec_queue_policy { > + struct guc_update_exec_queue_policy_header header; > struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS]; > } __packed; > > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c > index 8d2b50e03ed2..448075411191 100644 > --- a/drivers/gpu/drm/xe/xe_guc_submit.c > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c > @@ -16,12 +16,12 @@ > #include "regs/xe_lrc_layout.h" > #include "xe_devcoredump.h" > #include "xe_device.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_force_wake.h" > #include "xe_gt.h" > #include "xe_guc.h" > #include "xe_guc_ct.h" > -#include "xe_guc_engine_types.h" > +#include "xe_guc_exec_queue_types.h" > #include "xe_guc_submit_types.h" > #include "xe_hw_engine.h" > #include "xe_hw_fence.h" > @@ -47,9 +47,9 @@ guc_to_xe(struct xe_guc *guc) > } > > static struct xe_guc * > -engine_to_guc(struct xe_engine *e) > +exec_queue_to_guc(struct xe_exec_queue *q) > { > - return &e->gt->uc.guc; > + return &q->gt->uc.guc; > } > > /* > @@ -57,140 +57,140 @@ engine_to_guc(struct xe_engine *e) > * as the same time (e.g. a suspend can be happning at the same time as schedule > * engine done being processed). > */ > -#define ENGINE_STATE_REGISTERED (1 << 0) > +#define EXEC_QUEUE_STATE_REGISTERED (1 << 0) > #define ENGINE_STATE_ENABLED (1 << 1) > -#define ENGINE_STATE_PENDING_ENABLE (1 << 2) > -#define ENGINE_STATE_PENDING_DISABLE (1 << 3) > -#define ENGINE_STATE_DESTROYED (1 << 4) > +#define EXEC_QUEUE_STATE_PENDING_ENABLE (1 << 2) > +#define EXEC_QUEUE_STATE_PENDING_DISABLE (1 << 3) > +#define EXEC_QUEUE_STATE_DESTROYED (1 << 4) > #define ENGINE_STATE_SUSPENDED (1 << 5) > -#define ENGINE_STATE_RESET (1 << 6) > +#define EXEC_QUEUE_STATE_RESET (1 << 6) > #define ENGINE_STATE_KILLED (1 << 7) > > -static bool engine_registered(struct xe_engine *e) > +static bool exec_queue_registered(struct xe_exec_queue *q) > { > - return atomic_read(&e->guc->state) & ENGINE_STATE_REGISTERED; > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_REGISTERED; > } > > -static void set_engine_registered(struct xe_engine *e) > +static void set_exec_queue_registered(struct xe_exec_queue *q) > { > - atomic_or(ENGINE_STATE_REGISTERED, &e->guc->state); > + atomic_or(EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); > } > > -static void clear_engine_registered(struct xe_engine *e) > +static void clear_exec_queue_registered(struct xe_exec_queue *q) > { > - atomic_and(~ENGINE_STATE_REGISTERED, &e->guc->state); > + atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); > } > > -static bool engine_enabled(struct xe_engine *e) > +static bool exec_queue_enabled(struct xe_exec_queue *q) > { > - return atomic_read(&e->guc->state) & ENGINE_STATE_ENABLED; > + return atomic_read(&q->guc->state) & ENGINE_STATE_ENABLED; > } > > -static void set_engine_enabled(struct xe_engine *e) > +static void set_exec_queue_enabled(struct xe_exec_queue *q) > { > - atomic_or(ENGINE_STATE_ENABLED, &e->guc->state); > + atomic_or(ENGINE_STATE_ENABLED, &q->guc->state); > } > > -static void clear_engine_enabled(struct xe_engine *e) > +static void clear_exec_queue_enabled(struct xe_exec_queue *q) > { > - atomic_and(~ENGINE_STATE_ENABLED, &e->guc->state); > + atomic_and(~ENGINE_STATE_ENABLED, &q->guc->state); > } > > -static bool engine_pending_enable(struct xe_engine *e) > +static bool exec_queue_pending_enable(struct xe_exec_queue *q) > { > - return atomic_read(&e->guc->state) & ENGINE_STATE_PENDING_ENABLE; > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_ENABLE; > } > > -static void set_engine_pending_enable(struct xe_engine *e) > +static void set_exec_queue_pending_enable(struct xe_exec_queue *q) > { > - atomic_or(ENGINE_STATE_PENDING_ENABLE, &e->guc->state); > + atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); > } > > -static void clear_engine_pending_enable(struct xe_engine *e) > +static void clear_exec_queue_pending_enable(struct xe_exec_queue *q) > { > - atomic_and(~ENGINE_STATE_PENDING_ENABLE, &e->guc->state); > + atomic_and(~EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); > } > > -static bool engine_pending_disable(struct xe_engine *e) > +static bool exec_queue_pending_disable(struct xe_exec_queue *q) > { > - return atomic_read(&e->guc->state) & ENGINE_STATE_PENDING_DISABLE; > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_DISABLE; > } > > -static void set_engine_pending_disable(struct xe_engine *e) > +static void set_exec_queue_pending_disable(struct xe_exec_queue *q) > { > - atomic_or(ENGINE_STATE_PENDING_DISABLE, &e->guc->state); > + atomic_or(EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); > } > > -static void clear_engine_pending_disable(struct xe_engine *e) > +static void clear_exec_queue_pending_disable(struct xe_exec_queue *q) > { > - atomic_and(~ENGINE_STATE_PENDING_DISABLE, &e->guc->state); > + atomic_and(~EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); > } > > -static bool engine_destroyed(struct xe_engine *e) > +static bool exec_queue_destroyed(struct xe_exec_queue *q) > { > - return atomic_read(&e->guc->state) & ENGINE_STATE_DESTROYED; > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_DESTROYED; > } > > -static void set_engine_destroyed(struct xe_engine *e) > +static void set_exec_queue_destroyed(struct xe_exec_queue *q) > { > - atomic_or(ENGINE_STATE_DESTROYED, &e->guc->state); > + atomic_or(EXEC_QUEUE_STATE_DESTROYED, &q->guc->state); > } > > -static bool engine_banned(struct xe_engine *e) > +static bool exec_queue_banned(struct xe_exec_queue *q) > { > - return (e->flags & ENGINE_FLAG_BANNED); > + return (q->flags & EXEC_QUEUE_FLAG_BANNED); > } > > -static void set_engine_banned(struct xe_engine *e) > +static void set_exec_queue_banned(struct xe_exec_queue *q) > { > - e->flags |= ENGINE_FLAG_BANNED; > + q->flags |= EXEC_QUEUE_FLAG_BANNED; > } > > -static bool engine_suspended(struct xe_engine *e) > +static bool exec_queue_suspended(struct xe_exec_queue *q) > { > - return atomic_read(&e->guc->state) & ENGINE_STATE_SUSPENDED; > + return atomic_read(&q->guc->state) & ENGINE_STATE_SUSPENDED; > } > > -static void set_engine_suspended(struct xe_engine *e) > +static void set_exec_queue_suspended(struct xe_exec_queue *q) > { > - atomic_or(ENGINE_STATE_SUSPENDED, &e->guc->state); > + atomic_or(ENGINE_STATE_SUSPENDED, &q->guc->state); > } > > -static void clear_engine_suspended(struct xe_engine *e) > +static void clear_exec_queue_suspended(struct xe_exec_queue *q) > { > - atomic_and(~ENGINE_STATE_SUSPENDED, &e->guc->state); > + atomic_and(~ENGINE_STATE_SUSPENDED, &q->guc->state); > } > > -static bool engine_reset(struct xe_engine *e) > +static bool exec_queue_reset(struct xe_exec_queue *q) > { > - return atomic_read(&e->guc->state) & ENGINE_STATE_RESET; > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_RESET; > } > > -static void set_engine_reset(struct xe_engine *e) > +static void set_exec_queue_reset(struct xe_exec_queue *q) > { > - atomic_or(ENGINE_STATE_RESET, &e->guc->state); > + atomic_or(EXEC_QUEUE_STATE_RESET, &q->guc->state); > } > > -static bool engine_killed(struct xe_engine *e) > +static bool exec_queue_killed(struct xe_exec_queue *q) > { > - return atomic_read(&e->guc->state) & ENGINE_STATE_KILLED; > + return atomic_read(&q->guc->state) & ENGINE_STATE_KILLED; > } > > -static void set_engine_killed(struct xe_engine *e) > +static void set_exec_queue_killed(struct xe_exec_queue *q) > { > - atomic_or(ENGINE_STATE_KILLED, &e->guc->state); > + atomic_or(ENGINE_STATE_KILLED, &q->guc->state); > } > > -static bool engine_killed_or_banned(struct xe_engine *e) > +static bool exec_queue_killed_or_banned(struct xe_exec_queue *q) > { > - return engine_killed(e) || engine_banned(e); > + return exec_queue_killed(q) || exec_queue_banned(q); > } > > static void guc_submit_fini(struct drm_device *drm, void *arg) > { > struct xe_guc *guc = arg; > > - xa_destroy(&guc->submission_state.engine_lookup); > + xa_destroy(&guc->submission_state.exec_queue_lookup); > ida_destroy(&guc->submission_state.guc_ids); > bitmap_free(guc->submission_state.guc_ids_bitmap); > } > @@ -200,7 +200,7 @@ static void guc_submit_fini(struct drm_device *drm, void *arg) > #define GUC_ID_NUMBER_SLRC (GUC_ID_MAX - GUC_ID_NUMBER_MLRC) > #define GUC_ID_START_MLRC GUC_ID_NUMBER_SLRC > > -static const struct xe_engine_ops guc_engine_ops; > +static const struct xe_exec_queue_ops guc_exec_queue_ops; > > static void primelockdep(struct xe_guc *guc) > { > @@ -227,10 +227,10 @@ int xe_guc_submit_init(struct xe_guc *guc) > if (!guc->submission_state.guc_ids_bitmap) > return -ENOMEM; > > - gt->engine_ops = &guc_engine_ops; > + gt->exec_queue_ops = &guc_exec_queue_ops; > > mutex_init(&guc->submission_state.lock); > - xa_init(&guc->submission_state.engine_lookup); > + xa_init(&guc->submission_state.exec_queue_lookup); > ida_init(&guc->submission_state.guc_ids); > > spin_lock_init(&guc->submission_state.suspend.lock); > @@ -245,7 +245,7 @@ int xe_guc_submit_init(struct xe_guc *guc) > return 0; > } > > -static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) > +static int alloc_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) > { > int ret; > void *ptr; > @@ -259,11 +259,11 @@ static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) > */ > lockdep_assert_held(&guc->submission_state.lock); > > - if (xe_engine_is_parallel(e)) { > + if (xe_exec_queue_is_parallel(q)) { > void *bitmap = guc->submission_state.guc_ids_bitmap; > > ret = bitmap_find_free_region(bitmap, GUC_ID_NUMBER_MLRC, > - order_base_2(e->width)); > + order_base_2(q->width)); > } else { > ret = ida_simple_get(&guc->submission_state.guc_ids, 0, > GUC_ID_NUMBER_SLRC, GFP_NOWAIT); > @@ -271,12 +271,12 @@ static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) > if (ret < 0) > return ret; > > - e->guc->id = ret; > - if (xe_engine_is_parallel(e)) > - e->guc->id += GUC_ID_START_MLRC; > + q->guc->id = ret; > + if (xe_exec_queue_is_parallel(q)) > + q->guc->id += GUC_ID_START_MLRC; > > - ptr = xa_store(&guc->submission_state.engine_lookup, > - e->guc->id, e, GFP_NOWAIT); > + ptr = xa_store(&guc->submission_state.exec_queue_lookup, > + q->guc->id, q, GFP_NOWAIT); > if (IS_ERR(ptr)) { > ret = PTR_ERR(ptr); > goto err_release; > @@ -285,29 +285,29 @@ static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) > return 0; > > err_release: > - ida_simple_remove(&guc->submission_state.guc_ids, e->guc->id); > + ida_simple_remove(&guc->submission_state.guc_ids, q->guc->id); > return ret; > } > > -static void release_guc_id(struct xe_guc *guc, struct xe_engine *e) > +static void release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) > { > mutex_lock(&guc->submission_state.lock); > - xa_erase(&guc->submission_state.engine_lookup, e->guc->id); > - if (xe_engine_is_parallel(e)) > + xa_erase(&guc->submission_state.exec_queue_lookup, q->guc->id); > + if (xe_exec_queue_is_parallel(q)) > bitmap_release_region(guc->submission_state.guc_ids_bitmap, > - e->guc->id - GUC_ID_START_MLRC, > - order_base_2(e->width)); > + q->guc->id - GUC_ID_START_MLRC, > + order_base_2(q->width)); > else > - ida_simple_remove(&guc->submission_state.guc_ids, e->guc->id); > + ida_simple_remove(&guc->submission_state.guc_ids, q->guc->id); > mutex_unlock(&guc->submission_state.lock); > } > > -struct engine_policy { > +struct exec_queue_policy { > u32 count; > - struct guc_update_engine_policy h2g; > + struct guc_update_exec_queue_policy h2g; > }; > > -static u32 __guc_engine_policy_action_size(struct engine_policy *policy) > +static u32 __guc_exec_queue_policy_action_size(struct exec_queue_policy *policy) > { > size_t bytes = sizeof(policy->h2g.header) + > (sizeof(policy->h2g.klv[0]) * policy->count); > @@ -315,8 +315,8 @@ static u32 __guc_engine_policy_action_size(struct engine_policy *policy) > return bytes / sizeof(u32); > } > > -static void __guc_engine_policy_start_klv(struct engine_policy *policy, > - u16 guc_id) > +static void __guc_exec_queue_policy_start_klv(struct exec_queue_policy *policy, > + u16 guc_id) > { > policy->h2g.header.action = > XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES; > @@ -324,8 +324,8 @@ static void __guc_engine_policy_start_klv(struct engine_policy *policy, > policy->count = 0; > } > > -#define MAKE_ENGINE_POLICY_ADD(func, id) \ > -static void __guc_engine_policy_add_##func(struct engine_policy *policy, \ > +#define MAKE_EXEC_QUEUE_POLICY_ADD(func, id) \ > +static void __guc_exec_queue_policy_add_##func(struct exec_queue_policy *policy, \ > u32 data) \ > { \ > XE_WARN_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \ > @@ -338,10 +338,10 @@ static void __guc_engine_policy_add_##func(struct engine_policy *policy, \ > policy->count++; \ > } > > -MAKE_ENGINE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM) > -MAKE_ENGINE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT) > -MAKE_ENGINE_POLICY_ADD(priority, SCHEDULING_PRIORITY) > -#undef MAKE_ENGINE_POLICY_ADD > +MAKE_EXEC_QUEUE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM) > +MAKE_EXEC_QUEUE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT) > +MAKE_EXEC_QUEUE_POLICY_ADD(priority, SCHEDULING_PRIORITY) > +#undef MAKE_EXEC_QUEUE_POLICY_ADD > > static const int drm_sched_prio_to_guc[] = { > [DRM_SCHED_PRIORITY_MIN] = GUC_CLIENT_PRIORITY_NORMAL, > @@ -350,33 +350,33 @@ static const int drm_sched_prio_to_guc[] = { > [DRM_SCHED_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH, > }; > > -static void init_policies(struct xe_guc *guc, struct xe_engine *e) > +static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q) > { > - struct engine_policy policy; > - enum drm_sched_priority prio = e->entity->priority; > - u32 timeslice_us = e->sched_props.timeslice_us; > - u32 preempt_timeout_us = e->sched_props.preempt_timeout_us; > + struct exec_queue_policy policy; > + enum drm_sched_priority prio = q->entity->priority; > + u32 timeslice_us = q->sched_props.timeslice_us; > + u32 preempt_timeout_us = q->sched_props.preempt_timeout_us; > > - XE_WARN_ON(!engine_registered(e)); > + XE_WARN_ON(!exec_queue_registered(q)); > > - __guc_engine_policy_start_klv(&policy, e->guc->id); > - __guc_engine_policy_add_priority(&policy, drm_sched_prio_to_guc[prio]); > - __guc_engine_policy_add_execution_quantum(&policy, timeslice_us); > - __guc_engine_policy_add_preemption_timeout(&policy, preempt_timeout_us); > + __guc_exec_queue_policy_start_klv(&policy, q->guc->id); > + __guc_exec_queue_policy_add_priority(&policy, drm_sched_prio_to_guc[prio]); > + __guc_exec_queue_policy_add_execution_quantum(&policy, timeslice_us); > + __guc_exec_queue_policy_add_preemption_timeout(&policy, preempt_timeout_us); > > xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, > - __guc_engine_policy_action_size(&policy), 0, 0); > + __guc_exec_queue_policy_action_size(&policy), 0, 0); > } > > -static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_engine *e) > +static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue *q) > { > - struct engine_policy policy; > + struct exec_queue_policy policy; > > - __guc_engine_policy_start_klv(&policy, e->guc->id); > - __guc_engine_policy_add_preemption_timeout(&policy, 1); > + __guc_exec_queue_policy_start_klv(&policy, q->guc->id); > + __guc_exec_queue_policy_add_preemption_timeout(&policy, 1); > > xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, > - __guc_engine_policy_action_size(&policy), 0, 0); > + __guc_exec_queue_policy_action_size(&policy), 0, 0); > } > > #define parallel_read(xe_, map_, field_) \ > @@ -387,7 +387,7 @@ static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_engine *e) > field_, val_) > > static void __register_mlrc_engine(struct xe_guc *guc, > - struct xe_engine *e, > + struct xe_exec_queue *q, > struct guc_ctxt_registration_info *info) > { > #define MAX_MLRC_REG_SIZE (13 + XE_HW_ENGINE_MAX_INSTANCE * 2) > @@ -395,7 +395,7 @@ static void __register_mlrc_engine(struct xe_guc *guc, > int len = 0; > int i; > > - XE_WARN_ON(!xe_engine_is_parallel(e)); > + XE_WARN_ON(!xe_exec_queue_is_parallel(q)); > > action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC; > action[len++] = info->flags; > @@ -407,12 +407,12 @@ static void __register_mlrc_engine(struct xe_guc *guc, > action[len++] = info->wq_base_lo; > action[len++] = info->wq_base_hi; > action[len++] = info->wq_size; > - action[len++] = e->width; > + action[len++] = q->width; > action[len++] = info->hwlrca_lo; > action[len++] = info->hwlrca_hi; > > - for (i = 1; i < e->width; ++i) { > - struct xe_lrc *lrc = e->lrc + i; > + for (i = 1; i < q->width; ++i) { > + struct xe_lrc *lrc = q->lrc + i; > > action[len++] = lower_32_bits(xe_lrc_descriptor(lrc)); > action[len++] = upper_32_bits(xe_lrc_descriptor(lrc)); > @@ -445,24 +445,24 @@ static void __register_engine(struct xe_guc *guc, > xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0); > } > > -static void register_engine(struct xe_engine *e) > +static void register_engine(struct xe_exec_queue *q) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > struct xe_device *xe = guc_to_xe(guc); > - struct xe_lrc *lrc = e->lrc; > + struct xe_lrc *lrc = q->lrc; > struct guc_ctxt_registration_info info; > > - XE_WARN_ON(engine_registered(e)); > + XE_WARN_ON(exec_queue_registered(q)); > > memset(&info, 0, sizeof(info)); > - info.context_idx = e->guc->id; > - info.engine_class = xe_engine_class_to_guc_class(e->class); > - info.engine_submit_mask = e->logical_mask; > + info.context_idx = q->guc->id; > + info.engine_class = xe_engine_class_to_guc_class(q->class); > + info.engine_submit_mask = q->logical_mask; > info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc)); > info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc)); > info.flags = CONTEXT_REGISTRATION_FLAG_KMD; > > - if (xe_engine_is_parallel(e)) { > + if (xe_exec_queue_is_parallel(q)) { > u32 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc); > struct iosys_map map = xe_lrc_parallel_map(lrc); > > @@ -476,8 +476,8 @@ static void register_engine(struct xe_engine *e) > offsetof(struct guc_submit_parallel_scratch, wq[0])); > info.wq_size = WQ_SIZE; > > - e->guc->wqi_head = 0; > - e->guc->wqi_tail = 0; > + q->guc->wqi_head = 0; > + q->guc->wqi_tail = 0; > xe_map_memset(xe, &map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE); > parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE); > } > @@ -487,38 +487,38 @@ static void register_engine(struct xe_engine *e) > * the GuC as jobs signal immediately and can't destroy an engine if the > * GuC has a reference to it. > */ > - if (xe_engine_is_lr(e)) > - xe_engine_get(e); > + if (xe_exec_queue_is_lr(q)) > + xe_exec_queue_get(q); > > - set_engine_registered(e); > - trace_xe_engine_register(e); > - if (xe_engine_is_parallel(e)) > - __register_mlrc_engine(guc, e, &info); > + set_exec_queue_registered(q); > + trace_xe_exec_queue_register(q); > + if (xe_exec_queue_is_parallel(q)) > + __register_mlrc_engine(guc, q, &info); > else > __register_engine(guc, &info); > - init_policies(guc, e); > + init_policies(guc, q); > } > > -static u32 wq_space_until_wrap(struct xe_engine *e) > +static u32 wq_space_until_wrap(struct xe_exec_queue *q) > { > - return (WQ_SIZE - e->guc->wqi_tail); > + return (WQ_SIZE - q->guc->wqi_tail); > } > > -static int wq_wait_for_space(struct xe_engine *e, u32 wqi_size) > +static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > struct xe_device *xe = guc_to_xe(guc); > - struct iosys_map map = xe_lrc_parallel_map(e->lrc); > + struct iosys_map map = xe_lrc_parallel_map(q->lrc); > unsigned int sleep_period_ms = 1; > > #define AVAILABLE_SPACE \ > - CIRC_SPACE(e->guc->wqi_tail, e->guc->wqi_head, WQ_SIZE) > + CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE) > if (wqi_size > AVAILABLE_SPACE) { > try_again: > - e->guc->wqi_head = parallel_read(xe, map, wq_desc.head); > + q->guc->wqi_head = parallel_read(xe, map, wq_desc.head); > if (wqi_size > AVAILABLE_SPACE) { > if (sleep_period_ms == 1024) { > - xe_gt_reset_async(e->gt); > + xe_gt_reset_async(q->gt); > return -ENODEV; > } > > @@ -532,52 +532,52 @@ static int wq_wait_for_space(struct xe_engine *e, u32 wqi_size) > return 0; > } > > -static int wq_noop_append(struct xe_engine *e) > +static int wq_noop_append(struct xe_exec_queue *q) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > struct xe_device *xe = guc_to_xe(guc); > - struct iosys_map map = xe_lrc_parallel_map(e->lrc); > - u32 len_dw = wq_space_until_wrap(e) / sizeof(u32) - 1; > + struct iosys_map map = xe_lrc_parallel_map(q->lrc); > + u32 len_dw = wq_space_until_wrap(q) / sizeof(u32) - 1; > > - if (wq_wait_for_space(e, wq_space_until_wrap(e))) > + if (wq_wait_for_space(q, wq_space_until_wrap(q))) > return -ENODEV; > > XE_WARN_ON(!FIELD_FIT(WQ_LEN_MASK, len_dw)); > > - parallel_write(xe, map, wq[e->guc->wqi_tail / sizeof(u32)], > + parallel_write(xe, map, wq[q->guc->wqi_tail / sizeof(u32)], > FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_NOOP) | > FIELD_PREP(WQ_LEN_MASK, len_dw)); > - e->guc->wqi_tail = 0; > + q->guc->wqi_tail = 0; > > return 0; > } > > -static void wq_item_append(struct xe_engine *e) > +static void wq_item_append(struct xe_exec_queue *q) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > struct xe_device *xe = guc_to_xe(guc); > - struct iosys_map map = xe_lrc_parallel_map(e->lrc); > + struct iosys_map map = xe_lrc_parallel_map(q->lrc); > #define WQ_HEADER_SIZE 4 /* Includes 1 LRC address too */ > u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)]; > - u32 wqi_size = (e->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32); > + u32 wqi_size = (q->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32); > u32 len_dw = (wqi_size / sizeof(u32)) - 1; > int i = 0, j; > > - if (wqi_size > wq_space_until_wrap(e)) { > - if (wq_noop_append(e)) > + if (wqi_size > wq_space_until_wrap(q)) { > + if (wq_noop_append(q)) > return; > } > - if (wq_wait_for_space(e, wqi_size)) > + if (wq_wait_for_space(q, wqi_size)) > return; > > wqi[i++] = FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_MULTI_LRC) | > FIELD_PREP(WQ_LEN_MASK, len_dw); > - wqi[i++] = xe_lrc_descriptor(e->lrc); > - wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, e->guc->id) | > - FIELD_PREP(WQ_RING_TAIL_MASK, e->lrc->ring.tail / sizeof(u64)); > + wqi[i++] = xe_lrc_descriptor(q->lrc); > + wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, q->guc->id) | > + FIELD_PREP(WQ_RING_TAIL_MASK, q->lrc->ring.tail / sizeof(u64)); > wqi[i++] = 0; > - for (j = 1; j < e->width; ++j) { > - struct xe_lrc *lrc = e->lrc + j; > + for (j = 1; j < q->width; ++j) { > + struct xe_lrc *lrc = q->lrc + j; > > wqi[i++] = lrc->ring.tail / sizeof(u64); > } > @@ -585,55 +585,55 @@ static void wq_item_append(struct xe_engine *e) > XE_WARN_ON(i != wqi_size / sizeof(u32)); > > iosys_map_incr(&map, offsetof(struct guc_submit_parallel_scratch, > - wq[e->guc->wqi_tail / sizeof(u32)])); > + wq[q->guc->wqi_tail / sizeof(u32)])); > xe_map_memcpy_to(xe, &map, 0, wqi, wqi_size); > - e->guc->wqi_tail += wqi_size; > - XE_WARN_ON(e->guc->wqi_tail > WQ_SIZE); > + q->guc->wqi_tail += wqi_size; > + XE_WARN_ON(q->guc->wqi_tail > WQ_SIZE); > > xe_device_wmb(xe); > > - map = xe_lrc_parallel_map(e->lrc); > - parallel_write(xe, map, wq_desc.tail, e->guc->wqi_tail); > + map = xe_lrc_parallel_map(q->lrc); > + parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail); > } > > #define RESUME_PENDING ~0x0ull > -static void submit_engine(struct xe_engine *e) > +static void submit_exec_queue(struct xe_exec_queue *q) > { > - struct xe_guc *guc = engine_to_guc(e); > - struct xe_lrc *lrc = e->lrc; > + struct xe_guc *guc = exec_queue_to_guc(q); > + struct xe_lrc *lrc = q->lrc; > u32 action[3]; > u32 g2h_len = 0; > u32 num_g2h = 0; > int len = 0; > bool extra_submit = false; > > - XE_WARN_ON(!engine_registered(e)); > + XE_WARN_ON(!exec_queue_registered(q)); > > - if (xe_engine_is_parallel(e)) > - wq_item_append(e); > + if (xe_exec_queue_is_parallel(q)) > + wq_item_append(q); > else > xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); > > - if (engine_suspended(e) && !xe_engine_is_parallel(e)) > + if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q)) > return; > > - if (!engine_enabled(e) && !engine_suspended(e)) { > + if (!exec_queue_enabled(q) && !exec_queue_suspended(q)) { > action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET; > - action[len++] = e->guc->id; > + action[len++] = q->guc->id; > action[len++] = GUC_CONTEXT_ENABLE; > g2h_len = G2H_LEN_DW_SCHED_CONTEXT_MODE_SET; > num_g2h = 1; > - if (xe_engine_is_parallel(e)) > + if (xe_exec_queue_is_parallel(q)) > extra_submit = true; > > - e->guc->resume_time = RESUME_PENDING; > - set_engine_pending_enable(e); > - set_engine_enabled(e); > - trace_xe_engine_scheduling_enable(e); > + q->guc->resume_time = RESUME_PENDING; > + set_exec_queue_pending_enable(q); > + set_exec_queue_enabled(q); > + trace_xe_exec_queue_scheduling_enable(q); > } else { > action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; > - action[len++] = e->guc->id; > - trace_xe_engine_submit(e); > + action[len++] = q->guc->id; > + trace_xe_exec_queue_submit(q); > } > > xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h); > @@ -641,31 +641,31 @@ static void submit_engine(struct xe_engine *e) > if (extra_submit) { > len = 0; > action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; > - action[len++] = e->guc->id; > - trace_xe_engine_submit(e); > + action[len++] = q->guc->id; > + trace_xe_exec_queue_submit(q); > > xe_guc_ct_send(&guc->ct, action, len, 0, 0); > } > } > > static struct dma_fence * > -guc_engine_run_job(struct drm_sched_job *drm_job) > +guc_exec_queue_run_job(struct drm_sched_job *drm_job) > { > struct xe_sched_job *job = to_xe_sched_job(drm_job); > - struct xe_engine *e = job->engine; > - bool lr = xe_engine_is_lr(e); > + struct xe_exec_queue *q = job->q; > + bool lr = xe_exec_queue_is_lr(q); > > - XE_WARN_ON((engine_destroyed(e) || engine_pending_disable(e)) && > - !engine_banned(e) && !engine_suspended(e)); > + XE_WARN_ON((exec_queue_destroyed(q) || exec_queue_pending_disable(q)) && > + !exec_queue_banned(q) && !exec_queue_suspended(q)); > > trace_xe_sched_job_run(job); > > - if (!engine_killed_or_banned(e) && !xe_sched_job_is_error(job)) { > - if (!engine_registered(e)) > - register_engine(e); > + if (!exec_queue_killed_or_banned(q) && !xe_sched_job_is_error(job)) { > + if (!exec_queue_registered(q)) > + register_engine(q); > if (!lr) /* LR jobs are emitted in the exec IOCTL */ > - e->ring_ops->emit_job(job); > - submit_engine(e); > + q->ring_ops->emit_job(job); > + submit_exec_queue(q); > } > > if (lr) { > @@ -678,7 +678,7 @@ guc_engine_run_job(struct drm_sched_job *drm_job) > } > } > > -static void guc_engine_free_job(struct drm_sched_job *drm_job) > +static void guc_exec_queue_free_job(struct drm_sched_job *drm_job) > { > struct xe_sched_job *job = to_xe_sched_job(drm_job); > > @@ -691,38 +691,38 @@ static int guc_read_stopped(struct xe_guc *guc) > return atomic_read(&guc->submission_state.stopped); > } > > -#define MAKE_SCHED_CONTEXT_ACTION(e, enable_disable) \ > +#define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable) \ > u32 action[] = { \ > XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET, \ > - e->guc->id, \ > + q->guc->id, \ > GUC_CONTEXT_##enable_disable, \ > } > #define MIN_SCHED_TIMEOUT 1 > > static void disable_scheduling_deregister(struct xe_guc *guc, > - struct xe_engine *e) > + struct xe_exec_queue *q) > { > - MAKE_SCHED_CONTEXT_ACTION(e, DISABLE); > + MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); > int ret; > > - set_min_preemption_timeout(guc, e); > + set_min_preemption_timeout(guc, q); > smp_rmb(); > - ret = wait_event_timeout(guc->ct.wq, !engine_pending_enable(e) || > + ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_enable(q) || > guc_read_stopped(guc), HZ * 5); > if (!ret) { > - struct drm_gpu_scheduler *sched = &e->guc->sched; > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > XE_WARN_ON("Pending enable failed to respond"); > sched->timeout = MIN_SCHED_TIMEOUT; > drm_sched_run_wq_start(sched); > - xe_gt_reset_async(e->gt); > + xe_gt_reset_async(q->gt); > return; > } > > - clear_engine_enabled(e); > - set_engine_pending_disable(e); > - set_engine_destroyed(e); > - trace_xe_engine_scheduling_disable(e); > + clear_exec_queue_enabled(q); > + set_exec_queue_pending_disable(q); > + set_exec_queue_destroyed(q); > + trace_xe_exec_queue_scheduling_disable(q); > > /* > * Reserve space for both G2H here as the 2nd G2H is sent from a G2H > @@ -733,27 +733,27 @@ static void disable_scheduling_deregister(struct xe_guc *guc, > G2H_LEN_DW_DEREGISTER_CONTEXT, 2); > } > > -static void guc_engine_print(struct xe_engine *e, struct drm_printer *p); > +static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p); > > #if IS_ENABLED(CONFIG_DRM_XE_SIMPLE_ERROR_CAPTURE) > -static void simple_error_capture(struct xe_engine *e) > +static void simple_error_capture(struct xe_exec_queue *q) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > struct drm_printer p = drm_err_printer(""); > struct xe_hw_engine *hwe; > enum xe_hw_engine_id id; > - u32 adj_logical_mask = e->logical_mask; > - u32 width_mask = (0x1 << e->width) - 1; > + u32 adj_logical_mask = q->logical_mask; > + u32 width_mask = (0x1 << q->width) - 1; > int i; > bool cookie; > > - if (e->vm && !e->vm->error_capture.capture_once) { > - e->vm->error_capture.capture_once = true; > + if (q->vm && !q->vm->error_capture.capture_once) { > + q->vm->error_capture.capture_once = true; > cookie = dma_fence_begin_signalling(); > - for (i = 0; e->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { > + for (i = 0; q->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { > if (adj_logical_mask & BIT(i)) { > adj_logical_mask |= width_mask << i; > - i += e->width; > + i += q->width; > } else { > ++i; > } > @@ -761,66 +761,66 @@ static void simple_error_capture(struct xe_engine *e) > > xe_force_wake_get(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL); > xe_guc_ct_print(&guc->ct, &p, true); > - guc_engine_print(e, &p); > + guc_exec_queue_print(q, &p); > for_each_hw_engine(hwe, guc_to_gt(guc), id) { > - if (hwe->class != e->hwe->class || > + if (hwe->class != q->hwe->class || > !(BIT(hwe->logical_instance) & adj_logical_mask)) > continue; > xe_hw_engine_print(hwe, &p); > } > - xe_analyze_vm(&p, e->vm, e->gt->info.id); > + xe_analyze_vm(&p, q->vm, q->gt->info.id); > xe_force_wake_put(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL); > dma_fence_end_signalling(cookie); > } > } > #else > -static void simple_error_capture(struct xe_engine *e) > +static void simple_error_capture(struct xe_exec_queue *q) > { > } > #endif > > -static void xe_guc_engine_trigger_cleanup(struct xe_engine *e) > +static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > > - if (xe_engine_is_lr(e)) > - queue_work(guc_to_gt(guc)->ordered_wq, &e->guc->lr_tdr); > + if (xe_exec_queue_is_lr(q)) > + queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr); > else > - drm_sched_set_timeout(&e->guc->sched, MIN_SCHED_TIMEOUT); > + drm_sched_set_timeout(&q->guc->sched, MIN_SCHED_TIMEOUT); > } > > -static void xe_guc_engine_lr_cleanup(struct work_struct *w) > +static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w) > { > - struct xe_guc_engine *ge = > - container_of(w, struct xe_guc_engine, lr_tdr); > - struct xe_engine *e = ge->engine; > + struct xe_guc_exec_queue *ge = > + container_of(w, struct xe_guc_exec_queue, lr_tdr); > + struct xe_exec_queue *q = ge->q; > struct drm_gpu_scheduler *sched = &ge->sched; > > - XE_WARN_ON(!xe_engine_is_lr(e)); > - trace_xe_engine_lr_cleanup(e); > + XE_WARN_ON(!xe_exec_queue_is_lr(q)); > + trace_xe_exec_queue_lr_cleanup(q); > > /* Kill the run_job / process_msg entry points */ > drm_sched_run_wq_stop(sched); > > /* Engine state now stable, disable scheduling / deregister if needed */ > - if (engine_registered(e)) { > - struct xe_guc *guc = engine_to_guc(e); > + if (exec_queue_registered(q)) { > + struct xe_guc *guc = exec_queue_to_guc(q); > int ret; > > - set_engine_banned(e); > - disable_scheduling_deregister(guc, e); > + set_exec_queue_banned(q); > + disable_scheduling_deregister(guc, q); > > /* > * Must wait for scheduling to be disabled before signalling > * any fences, if GT broken the GT reset code should signal us. > */ > ret = wait_event_timeout(guc->ct.wq, > - !engine_pending_disable(e) || > + !exec_queue_pending_disable(q) || > guc_read_stopped(guc), HZ * 5); > if (!ret) { > XE_WARN_ON("Schedule disable failed to respond"); > drm_sched_run_wq_start(sched); > - xe_gt_reset_async(e->gt); > + xe_gt_reset_async(q->gt); > return; > } > } > @@ -829,27 +829,27 @@ static void xe_guc_engine_lr_cleanup(struct work_struct *w) > } > > static enum drm_gpu_sched_stat > -guc_engine_timedout_job(struct drm_sched_job *drm_job) > +guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) > { > struct xe_sched_job *job = to_xe_sched_job(drm_job); > struct xe_sched_job *tmp_job; > - struct xe_engine *e = job->engine; > - struct drm_gpu_scheduler *sched = &e->guc->sched; > - struct xe_device *xe = guc_to_xe(engine_to_guc(e)); > + struct xe_exec_queue *q = job->q; > + struct drm_gpu_scheduler *sched = &q->guc->sched; > + struct xe_device *xe = guc_to_xe(exec_queue_to_guc(q)); > int err = -ETIME; > int i = 0; > > if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &job->fence->flags)) { > - XE_WARN_ON(e->flags & ENGINE_FLAG_KERNEL); > - XE_WARN_ON(e->flags & ENGINE_FLAG_VM && !engine_killed(e)); > + XE_WARN_ON(q->flags & EXEC_QUEUE_FLAG_KERNEL); > + XE_WARN_ON(q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q)); > > drm_warn(&xe->drm, "Timedout job: seqno=%u, guc_id=%d, flags=0x%lx", > - xe_sched_job_seqno(job), e->guc->id, e->flags); > - simple_error_capture(e); > - xe_devcoredump(e); > + xe_sched_job_seqno(job), q->guc->id, q->flags); > + simple_error_capture(q); > + xe_devcoredump(q); > } else { > drm_dbg(&xe->drm, "Timedout signaled job: seqno=%u, guc_id=%d, flags=0x%lx", > - xe_sched_job_seqno(job), e->guc->id, e->flags); > + xe_sched_job_seqno(job), q->guc->id, q->flags); > } > trace_xe_sched_job_timedout(job); > > @@ -860,26 +860,26 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) > * Kernel jobs should never fail, nor should VM jobs if they do > * somethings has gone wrong and the GT needs a reset > */ > - if (e->flags & ENGINE_FLAG_KERNEL || > - (e->flags & ENGINE_FLAG_VM && !engine_killed(e))) { > + if (q->flags & EXEC_QUEUE_FLAG_KERNEL || > + (q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q))) { > if (!drm_sched_invalidate_job(drm_job, 2)) { > list_add(&drm_job->list, &sched->pending_list); > drm_sched_run_wq_start(sched); > - xe_gt_reset_async(e->gt); > + xe_gt_reset_async(q->gt); > goto out; > } > } > > /* Engine state now stable, disable scheduling if needed */ > - if (engine_enabled(e)) { > - struct xe_guc *guc = engine_to_guc(e); > + if (exec_queue_enabled(q)) { > + struct xe_guc *guc = exec_queue_to_guc(q); > int ret; > > - if (engine_reset(e)) > + if (exec_queue_reset(q)) > err = -EIO; > - set_engine_banned(e); > - xe_engine_get(e); > - disable_scheduling_deregister(guc, e); > + set_exec_queue_banned(q); > + xe_exec_queue_get(q); > + disable_scheduling_deregister(guc, q); > > /* > * Must wait for scheduling to be disabled before signalling > @@ -891,20 +891,20 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) > */ > smp_rmb(); > ret = wait_event_timeout(guc->ct.wq, > - !engine_pending_disable(e) || > + !exec_queue_pending_disable(q) || > guc_read_stopped(guc), HZ * 5); > if (!ret) { > XE_WARN_ON("Schedule disable failed to respond"); > sched->timeout = MIN_SCHED_TIMEOUT; > list_add(&drm_job->list, &sched->pending_list); > drm_sched_run_wq_start(sched); > - xe_gt_reset_async(e->gt); > + xe_gt_reset_async(q->gt); > goto out; > } > } > > /* Stop fence signaling */ > - xe_hw_fence_irq_stop(e->fence_irq); > + xe_hw_fence_irq_stop(q->fence_irq); > > /* > * Fence state now stable, stop / start scheduler which cleans up any > @@ -912,7 +912,7 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) > */ > list_add(&drm_job->list, &sched->pending_list); > drm_sched_run_wq_start(sched); > - xe_guc_engine_trigger_cleanup(e); > + xe_guc_exec_queue_trigger_cleanup(q); > > /* Mark all outstanding jobs as bad, thus completing them */ > spin_lock(&sched->job_list_lock); > @@ -921,53 +921,53 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) > spin_unlock(&sched->job_list_lock); > > /* Start fence signaling */ > - xe_hw_fence_irq_start(e->fence_irq); > + xe_hw_fence_irq_start(q->fence_irq); > > out: > return DRM_GPU_SCHED_STAT_NOMINAL; > } > > -static void __guc_engine_fini_async(struct work_struct *w) > +static void __guc_exec_queue_fini_async(struct work_struct *w) > { > - struct xe_guc_engine *ge = > - container_of(w, struct xe_guc_engine, fini_async); > - struct xe_engine *e = ge->engine; > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc_exec_queue *ge = > + container_of(w, struct xe_guc_exec_queue, fini_async); > + struct xe_exec_queue *q = ge->q; > + struct xe_guc *guc = exec_queue_to_guc(q); > > - trace_xe_engine_destroy(e); > + trace_xe_exec_queue_destroy(q); > > - if (xe_engine_is_lr(e)) > + if (xe_exec_queue_is_lr(q)) > cancel_work_sync(&ge->lr_tdr); > - if (e->flags & ENGINE_FLAG_PERSISTENT) > - xe_device_remove_persistent_engines(gt_to_xe(e->gt), e); > - release_guc_id(guc, e); > + if (q->flags & EXEC_QUEUE_FLAG_PERSISTENT) > + xe_device_remove_persistent_exec_queues(gt_to_xe(q->gt), q); > + release_guc_id(guc, q); > drm_sched_entity_fini(&ge->entity); > drm_sched_fini(&ge->sched); > > - if (!(e->flags & ENGINE_FLAG_KERNEL)) { > + if (!(q->flags & EXEC_QUEUE_FLAG_KERNEL)) { > kfree(ge); > - xe_engine_fini(e); > + xe_exec_queue_fini(q); > } > } > > -static void guc_engine_fini_async(struct xe_engine *e) > +static void guc_exec_queue_fini_async(struct xe_exec_queue *q) > { > - bool kernel = e->flags & ENGINE_FLAG_KERNEL; > + bool kernel = q->flags & EXEC_QUEUE_FLAG_KERNEL; > > - INIT_WORK(&e->guc->fini_async, __guc_engine_fini_async); > - queue_work(system_wq, &e->guc->fini_async); > + INIT_WORK(&q->guc->fini_async, __guc_exec_queue_fini_async); > + queue_work(system_wq, &q->guc->fini_async); > > /* We must block on kernel engines so slabs are empty on driver unload */ > if (kernel) { > - struct xe_guc_engine *ge = e->guc; > + struct xe_guc_exec_queue *ge = q->guc; > > flush_work(&ge->fini_async); > kfree(ge); > - xe_engine_fini(e); > + xe_exec_queue_fini(q); > } > } > > -static void __guc_engine_fini(struct xe_guc *guc, struct xe_engine *e) > +static void __guc_exec_queue_fini(struct xe_guc *guc, struct xe_exec_queue *q) > { > /* > * Might be done from within the GPU scheduler, need to do async as we > @@ -976,104 +976,104 @@ static void __guc_engine_fini(struct xe_guc *guc, struct xe_engine *e) > * this we and don't really care when everything is fini'd, just that it > * is. > */ > - guc_engine_fini_async(e); > + guc_exec_queue_fini_async(q); > } > > -static void __guc_engine_process_msg_cleanup(struct drm_sched_msg *msg) > +static void __guc_exec_queue_process_msg_cleanup(struct drm_sched_msg *msg) > { > - struct xe_engine *e = msg->private_data; > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_exec_queue *q = msg->private_data; > + struct xe_guc *guc = exec_queue_to_guc(q); > > - XE_WARN_ON(e->flags & ENGINE_FLAG_KERNEL); > - trace_xe_engine_cleanup_entity(e); > + XE_WARN_ON(q->flags & EXEC_QUEUE_FLAG_KERNEL); > + trace_xe_exec_queue_cleanup_entity(q); > > - if (engine_registered(e)) > - disable_scheduling_deregister(guc, e); > + if (exec_queue_registered(q)) > + disable_scheduling_deregister(guc, q); > else > - __guc_engine_fini(guc, e); > + __guc_exec_queue_fini(guc, q); > } > > -static bool guc_engine_allowed_to_change_state(struct xe_engine *e) > +static bool guc_exec_queue_allowed_to_change_state(struct xe_exec_queue *q) > { > - return !engine_killed_or_banned(e) && engine_registered(e); > + return !exec_queue_killed_or_banned(q) && exec_queue_registered(q); > } > > -static void __guc_engine_process_msg_set_sched_props(struct drm_sched_msg *msg) > +static void __guc_exec_queue_process_msg_set_sched_props(struct drm_sched_msg *msg) > { > - struct xe_engine *e = msg->private_data; > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_exec_queue *q = msg->private_data; > + struct xe_guc *guc = exec_queue_to_guc(q); > > - if (guc_engine_allowed_to_change_state(e)) > - init_policies(guc, e); > + if (guc_exec_queue_allowed_to_change_state(q)) > + init_policies(guc, q); > kfree(msg); > } > > -static void suspend_fence_signal(struct xe_engine *e) > +static void suspend_fence_signal(struct xe_exec_queue *q) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > > - XE_WARN_ON(!engine_suspended(e) && !engine_killed(e) && > + XE_WARN_ON(!exec_queue_suspended(q) && !exec_queue_killed(q) && > !guc_read_stopped(guc)); > - XE_WARN_ON(!e->guc->suspend_pending); > + XE_WARN_ON(!q->guc->suspend_pending); > > - e->guc->suspend_pending = false; > + q->guc->suspend_pending = false; > smp_wmb(); > - wake_up(&e->guc->suspend_wait); > + wake_up(&q->guc->suspend_wait); > } > > -static void __guc_engine_process_msg_suspend(struct drm_sched_msg *msg) > +static void __guc_exec_queue_process_msg_suspend(struct drm_sched_msg *msg) > { > - struct xe_engine *e = msg->private_data; > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_exec_queue *q = msg->private_data; > + struct xe_guc *guc = exec_queue_to_guc(q); > > - if (guc_engine_allowed_to_change_state(e) && !engine_suspended(e) && > - engine_enabled(e)) { > - wait_event(guc->ct.wq, e->guc->resume_time != RESUME_PENDING || > + if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) && > + exec_queue_enabled(q)) { > + wait_event(guc->ct.wq, q->guc->resume_time != RESUME_PENDING || > guc_read_stopped(guc)); > > if (!guc_read_stopped(guc)) { > - MAKE_SCHED_CONTEXT_ACTION(e, DISABLE); > + MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); > s64 since_resume_ms = > ktime_ms_delta(ktime_get(), > - e->guc->resume_time); > - s64 wait_ms = e->vm->preempt.min_run_period_ms - > + q->guc->resume_time); > + s64 wait_ms = q->vm->preempt.min_run_period_ms - > since_resume_ms; > > - if (wait_ms > 0 && e->guc->resume_time) > + if (wait_ms > 0 && q->guc->resume_time) > msleep(wait_ms); > > - set_engine_suspended(e); > - clear_engine_enabled(e); > - set_engine_pending_disable(e); > - trace_xe_engine_scheduling_disable(e); > + set_exec_queue_suspended(q); > + clear_exec_queue_enabled(q); > + set_exec_queue_pending_disable(q); > + trace_xe_exec_queue_scheduling_disable(q); > > xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), > G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); > } > - } else if (e->guc->suspend_pending) { > - set_engine_suspended(e); > - suspend_fence_signal(e); > + } else if (q->guc->suspend_pending) { > + set_exec_queue_suspended(q); > + suspend_fence_signal(q); > } > } > > -static void __guc_engine_process_msg_resume(struct drm_sched_msg *msg) > +static void __guc_exec_queue_process_msg_resume(struct drm_sched_msg *msg) > { > - struct xe_engine *e = msg->private_data; > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_exec_queue *q = msg->private_data; > + struct xe_guc *guc = exec_queue_to_guc(q); > > - if (guc_engine_allowed_to_change_state(e)) { > - MAKE_SCHED_CONTEXT_ACTION(e, ENABLE); > + if (guc_exec_queue_allowed_to_change_state(q)) { > + MAKE_SCHED_CONTEXT_ACTION(q, ENABLE); > > - e->guc->resume_time = RESUME_PENDING; > - clear_engine_suspended(e); > - set_engine_pending_enable(e); > - set_engine_enabled(e); > - trace_xe_engine_scheduling_enable(e); > + q->guc->resume_time = RESUME_PENDING; > + clear_exec_queue_suspended(q); > + set_exec_queue_pending_enable(q); > + set_exec_queue_enabled(q); > + trace_xe_exec_queue_scheduling_enable(q); > > xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), > G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); > } else { > - clear_engine_suspended(e); > + clear_exec_queue_suspended(q); > } > } > > @@ -1082,22 +1082,22 @@ static void __guc_engine_process_msg_resume(struct drm_sched_msg *msg) > #define SUSPEND 3 > #define RESUME 4 > > -static void guc_engine_process_msg(struct drm_sched_msg *msg) > +static void guc_exec_queue_process_msg(struct drm_sched_msg *msg) > { > trace_drm_sched_msg_recv(msg); > > switch (msg->opcode) { > case CLEANUP: > - __guc_engine_process_msg_cleanup(msg); > + __guc_exec_queue_process_msg_cleanup(msg); > break; > case SET_SCHED_PROPS: > - __guc_engine_process_msg_set_sched_props(msg); > + __guc_exec_queue_process_msg_set_sched_props(msg); > break; > case SUSPEND: > - __guc_engine_process_msg_suspend(msg); > + __guc_exec_queue_process_msg_suspend(msg); > break; > case RESUME: > - __guc_engine_process_msg_resume(msg); > + __guc_exec_queue_process_msg_resume(msg); > break; > default: > XE_WARN_ON("Unknown message type"); > @@ -1105,17 +1105,17 @@ static void guc_engine_process_msg(struct drm_sched_msg *msg) > } > > static const struct drm_sched_backend_ops drm_sched_ops = { > - .run_job = guc_engine_run_job, > - .free_job = guc_engine_free_job, > - .timedout_job = guc_engine_timedout_job, > - .process_msg = guc_engine_process_msg, > + .run_job = guc_exec_queue_run_job, > + .free_job = guc_exec_queue_free_job, > + .timedout_job = guc_exec_queue_timedout_job, > + .process_msg = guc_exec_queue_process_msg, > }; > > -static int guc_engine_init(struct xe_engine *e) > +static int guc_exec_queue_init(struct xe_exec_queue *q) > { > struct drm_gpu_scheduler *sched; > - struct xe_guc *guc = engine_to_guc(e); > - struct xe_guc_engine *ge; > + struct xe_guc *guc = exec_queue_to_guc(q); > + struct xe_guc_exec_queue *ge; > long timeout; > int err; > > @@ -1125,16 +1125,16 @@ static int guc_engine_init(struct xe_engine *e) > if (!ge) > return -ENOMEM; > > - e->guc = ge; > - ge->engine = e; > + q->guc = ge; > + ge->q = q; > init_waitqueue_head(&ge->suspend_wait); > > - timeout = xe_vm_no_dma_fences(e->vm) ? MAX_SCHEDULE_TIMEOUT : HZ * 5; > + timeout = xe_vm_no_dma_fences(q->vm) ? MAX_SCHEDULE_TIMEOUT : HZ * 5; > err = drm_sched_init(&ge->sched, &drm_sched_ops, NULL, > - e->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, > + q->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, > 64, timeout, guc_to_gt(guc)->ordered_wq, NULL, > - e->name, DRM_SCHED_POLICY_SINGLE_ENTITY, > - gt_to_xe(e->gt)->drm.dev); > + q->name, DRM_SCHED_POLICY_SINGLE_ENTITY, > + gt_to_xe(q->gt)->drm.dev); > if (err) > goto err_free; > > @@ -1144,43 +1144,43 @@ static int guc_engine_init(struct xe_engine *e) > if (err) > goto err_sched; > > - if (xe_engine_is_lr(e)) > - INIT_WORK(&e->guc->lr_tdr, xe_guc_engine_lr_cleanup); > + if (xe_exec_queue_is_lr(q)) > + INIT_WORK(&q->guc->lr_tdr, xe_guc_exec_queue_lr_cleanup); > > mutex_lock(&guc->submission_state.lock); > > - err = alloc_guc_id(guc, e); > + err = alloc_guc_id(guc, q); > if (err) > goto err_entity; > > - e->entity = &ge->entity; > + q->entity = &ge->entity; > > if (guc_read_stopped(guc)) > drm_sched_stop(sched, NULL); > > mutex_unlock(&guc->submission_state.lock); > > - switch (e->class) { > + switch (q->class) { > case XE_ENGINE_CLASS_RENDER: > - sprintf(e->name, "rcs%d", e->guc->id); > + sprintf(q->name, "rcs%d", q->guc->id); > break; > case XE_ENGINE_CLASS_VIDEO_DECODE: > - sprintf(e->name, "vcs%d", e->guc->id); > + sprintf(q->name, "vcs%d", q->guc->id); > break; > case XE_ENGINE_CLASS_VIDEO_ENHANCE: > - sprintf(e->name, "vecs%d", e->guc->id); > + sprintf(q->name, "vecs%d", q->guc->id); > break; > case XE_ENGINE_CLASS_COPY: > - sprintf(e->name, "bcs%d", e->guc->id); > + sprintf(q->name, "bcs%d", q->guc->id); > break; > case XE_ENGINE_CLASS_COMPUTE: > - sprintf(e->name, "ccs%d", e->guc->id); > + sprintf(q->name, "ccs%d", q->guc->id); > break; > default: > - XE_WARN_ON(e->class); > + XE_WARN_ON(q->class); > } > > - trace_xe_engine_create(e); > + trace_xe_exec_queue_create(q); > > return 0; > > @@ -1194,132 +1194,132 @@ static int guc_engine_init(struct xe_engine *e) > return err; > } > > -static void guc_engine_kill(struct xe_engine *e) > +static void guc_exec_queue_kill(struct xe_exec_queue *q) > { > - trace_xe_engine_kill(e); > - set_engine_killed(e); > - xe_guc_engine_trigger_cleanup(e); > + trace_xe_exec_queue_kill(q); > + set_exec_queue_killed(q); > + xe_guc_exec_queue_trigger_cleanup(q); > } > > -static void guc_engine_add_msg(struct xe_engine *e, struct drm_sched_msg *msg, > - u32 opcode) > +static void guc_exec_queue_add_msg(struct xe_exec_queue *q, struct drm_sched_msg *msg, > + u32 opcode) > { > INIT_LIST_HEAD(&msg->link); > msg->opcode = opcode; > - msg->private_data = e; > + msg->private_data = q; > > trace_drm_sched_msg_add(msg); > - drm_sched_add_msg(&e->guc->sched, msg); > + drm_sched_add_msg(&q->guc->sched, msg); > } > > #define STATIC_MSG_CLEANUP 0 > #define STATIC_MSG_SUSPEND 1 > #define STATIC_MSG_RESUME 2 > -static void guc_engine_fini(struct xe_engine *e) > +static void guc_exec_queue_fini(struct xe_exec_queue *q) > { > - struct drm_sched_msg *msg = e->guc->static_msgs + STATIC_MSG_CLEANUP; > + struct drm_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP; > > - if (!(e->flags & ENGINE_FLAG_KERNEL)) > - guc_engine_add_msg(e, msg, CLEANUP); > + if (!(q->flags & EXEC_QUEUE_FLAG_KERNEL)) > + guc_exec_queue_add_msg(q, msg, CLEANUP); > else > - __guc_engine_fini(engine_to_guc(e), e); > + __guc_exec_queue_fini(exec_queue_to_guc(q), q); > } > > -static int guc_engine_set_priority(struct xe_engine *e, > - enum drm_sched_priority priority) > +static int guc_exec_queue_set_priority(struct xe_exec_queue *q, > + enum drm_sched_priority priority) > { > struct drm_sched_msg *msg; > > - if (e->entity->priority == priority || engine_killed_or_banned(e)) > + if (q->entity->priority == priority || exec_queue_killed_or_banned(q)) > return 0; > > msg = kmalloc(sizeof(*msg), GFP_KERNEL); > if (!msg) > return -ENOMEM; > > - guc_engine_add_msg(e, msg, SET_SCHED_PROPS); > + guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); > > return 0; > } > > -static int guc_engine_set_timeslice(struct xe_engine *e, u32 timeslice_us) > +static int guc_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us) > { > struct drm_sched_msg *msg; > > - if (e->sched_props.timeslice_us == timeslice_us || > - engine_killed_or_banned(e)) > + if (q->sched_props.timeslice_us == timeslice_us || > + exec_queue_killed_or_banned(q)) > return 0; > > msg = kmalloc(sizeof(*msg), GFP_KERNEL); > if (!msg) > return -ENOMEM; > > - e->sched_props.timeslice_us = timeslice_us; > - guc_engine_add_msg(e, msg, SET_SCHED_PROPS); > + q->sched_props.timeslice_us = timeslice_us; > + guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); > > return 0; > } > > -static int guc_engine_set_preempt_timeout(struct xe_engine *e, > - u32 preempt_timeout_us) > +static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q, > + u32 preempt_timeout_us) > { > struct drm_sched_msg *msg; > > - if (e->sched_props.preempt_timeout_us == preempt_timeout_us || > - engine_killed_or_banned(e)) > + if (q->sched_props.preempt_timeout_us == preempt_timeout_us || > + exec_queue_killed_or_banned(q)) > return 0; > > msg = kmalloc(sizeof(*msg), GFP_KERNEL); > if (!msg) > return -ENOMEM; > > - e->sched_props.preempt_timeout_us = preempt_timeout_us; > - guc_engine_add_msg(e, msg, SET_SCHED_PROPS); > + q->sched_props.preempt_timeout_us = preempt_timeout_us; > + guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); > > return 0; > } > > -static int guc_engine_set_job_timeout(struct xe_engine *e, u32 job_timeout_ms) > +static int guc_exec_queue_set_job_timeout(struct xe_exec_queue *q, u32 job_timeout_ms) > { > - struct drm_gpu_scheduler *sched = &e->guc->sched; > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > - XE_WARN_ON(engine_registered(e)); > - XE_WARN_ON(engine_banned(e)); > - XE_WARN_ON(engine_killed(e)); > + XE_WARN_ON(exec_queue_registered(q)); > + XE_WARN_ON(exec_queue_banned(q)); > + XE_WARN_ON(exec_queue_killed(q)); > > sched->timeout = job_timeout_ms; > > return 0; > } > > -static int guc_engine_suspend(struct xe_engine *e) > +static int guc_exec_queue_suspend(struct xe_exec_queue *q) > { > - struct drm_sched_msg *msg = e->guc->static_msgs + STATIC_MSG_SUSPEND; > + struct drm_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_SUSPEND; > > - if (engine_killed_or_banned(e) || e->guc->suspend_pending) > + if (exec_queue_killed_or_banned(q) || q->guc->suspend_pending) > return -EINVAL; > > - e->guc->suspend_pending = true; > - guc_engine_add_msg(e, msg, SUSPEND); > + q->guc->suspend_pending = true; > + guc_exec_queue_add_msg(q, msg, SUSPEND); > > return 0; > } > > -static void guc_engine_suspend_wait(struct xe_engine *e) > +static void guc_exec_queue_suspend_wait(struct xe_exec_queue *q) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > > - wait_event(e->guc->suspend_wait, !e->guc->suspend_pending || > + wait_event(q->guc->suspend_wait, !q->guc->suspend_pending || > guc_read_stopped(guc)); > } > > -static void guc_engine_resume(struct xe_engine *e) > +static void guc_exec_queue_resume(struct xe_exec_queue *q) > { > - struct drm_sched_msg *msg = e->guc->static_msgs + STATIC_MSG_RESUME; > + struct drm_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_RESUME; > > - XE_WARN_ON(e->guc->suspend_pending); > + XE_WARN_ON(q->guc->suspend_pending); > > - guc_engine_add_msg(e, msg, RESUME); > + guc_exec_queue_add_msg(q, msg, RESUME); > } > > /* > @@ -1328,49 +1328,49 @@ static void guc_engine_resume(struct xe_engine *e) > * really shouldn't do much other than trap into the DRM scheduler which > * synchronizes these operations. > */ > -static const struct xe_engine_ops guc_engine_ops = { > - .init = guc_engine_init, > - .kill = guc_engine_kill, > - .fini = guc_engine_fini, > - .set_priority = guc_engine_set_priority, > - .set_timeslice = guc_engine_set_timeslice, > - .set_preempt_timeout = guc_engine_set_preempt_timeout, > - .set_job_timeout = guc_engine_set_job_timeout, > - .suspend = guc_engine_suspend, > - .suspend_wait = guc_engine_suspend_wait, > - .resume = guc_engine_resume, > +static const struct xe_exec_queue_ops guc_exec_queue_ops = { > + .init = guc_exec_queue_init, > + .kill = guc_exec_queue_kill, > + .fini = guc_exec_queue_fini, > + .set_priority = guc_exec_queue_set_priority, > + .set_timeslice = guc_exec_queue_set_timeslice, > + .set_preempt_timeout = guc_exec_queue_set_preempt_timeout, > + .set_job_timeout = guc_exec_queue_set_job_timeout, > + .suspend = guc_exec_queue_suspend, > + .suspend_wait = guc_exec_queue_suspend_wait, > + .resume = guc_exec_queue_resume, > }; > > -static void guc_engine_stop(struct xe_guc *guc, struct xe_engine *e) > +static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q) > { > - struct drm_gpu_scheduler *sched = &e->guc->sched; > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > /* Stop scheduling + flush any DRM scheduler operations */ > drm_sched_run_wq_stop(sched); > > /* Clean up lost G2H + reset engine state */ > - if (engine_registered(e)) { > - if ((engine_banned(e) && engine_destroyed(e)) || > - xe_engine_is_lr(e)) > - xe_engine_put(e); > - else if (engine_destroyed(e)) > - __guc_engine_fini(guc, e); > + if (exec_queue_registered(q)) { > + if ((exec_queue_banned(q) && exec_queue_destroyed(q)) || > + xe_exec_queue_is_lr(q)) > + xe_exec_queue_put(q); > + else if (exec_queue_destroyed(q)) > + __guc_exec_queue_fini(guc, q); > } > - if (e->guc->suspend_pending) { > - set_engine_suspended(e); > - suspend_fence_signal(e); > + if (q->guc->suspend_pending) { > + set_exec_queue_suspended(q); > + suspend_fence_signal(q); > } > - atomic_and(ENGINE_STATE_DESTROYED | ENGINE_STATE_SUSPENDED, > - &e->guc->state); > - e->guc->resume_time = 0; > - trace_xe_engine_stop(e); > + atomic_and(EXEC_QUEUE_STATE_DESTROYED | ENGINE_STATE_SUSPENDED, > + &q->guc->state); > + q->guc->resume_time = 0; > + trace_xe_exec_queue_stop(q); > > /* > * Ban any engine (aside from kernel and engines used for VM ops) with a > * started but not complete job or if a job has gone through a GT reset > * more than twice. > */ > - if (!(e->flags & (ENGINE_FLAG_KERNEL | ENGINE_FLAG_VM))) { > + if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) { > struct drm_sched_job *drm_job = > list_first_entry_or_null(&sched->pending_list, > struct drm_sched_job, list); > @@ -1383,7 +1383,7 @@ static void guc_engine_stop(struct xe_guc *guc, struct xe_engine *e) > drm_sched_invalidate_job(drm_job, 2)) { > trace_xe_sched_job_ban(job); > sched->timeout = MIN_SCHED_TIMEOUT; > - set_engine_banned(e); > + set_exec_queue_banned(q); > } > } > } > @@ -1414,15 +1414,15 @@ void xe_guc_submit_reset_wait(struct xe_guc *guc) > > int xe_guc_submit_stop(struct xe_guc *guc) > { > - struct xe_engine *e; > + struct xe_exec_queue *q; > unsigned long index; > > XE_WARN_ON(guc_read_stopped(guc) != 1); > > mutex_lock(&guc->submission_state.lock); > > - xa_for_each(&guc->submission_state.engine_lookup, index, e) > - guc_engine_stop(guc, e); > + xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) > + guc_exec_queue_stop(guc, q); > > mutex_unlock(&guc->submission_state.lock); > > @@ -1434,16 +1434,16 @@ int xe_guc_submit_stop(struct xe_guc *guc) > return 0; > } > > -static void guc_engine_start(struct xe_engine *e) > +static void guc_exec_queue_start(struct xe_exec_queue *q) > { > - struct drm_gpu_scheduler *sched = &e->guc->sched; > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > - if (!engine_killed_or_banned(e)) { > + if (!exec_queue_killed_or_banned(q)) { > int i; > > - trace_xe_engine_resubmit(e); > - for (i = 0; i < e->width; ++i) > - xe_lrc_set_ring_head(e->lrc + i, e->lrc[i].ring.tail); > + trace_xe_exec_queue_resubmit(q); > + for (i = 0; i < q->width; ++i) > + xe_lrc_set_ring_head(q->lrc + i, q->lrc[i].ring.tail); > drm_sched_resubmit_jobs(sched); > } > > @@ -1453,15 +1453,15 @@ static void guc_engine_start(struct xe_engine *e) > > int xe_guc_submit_start(struct xe_guc *guc) > { > - struct xe_engine *e; > + struct xe_exec_queue *q; > unsigned long index; > > XE_WARN_ON(guc_read_stopped(guc) != 1); > > mutex_lock(&guc->submission_state.lock); > atomic_dec(&guc->submission_state.stopped); > - xa_for_each(&guc->submission_state.engine_lookup, index, e) > - guc_engine_start(e); > + xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) > + guc_exec_queue_start(q); > mutex_unlock(&guc->submission_state.lock); > > wake_up_all(&guc->ct.wq); > @@ -1469,36 +1469,36 @@ int xe_guc_submit_start(struct xe_guc *guc) > return 0; > } > > -static struct xe_engine * > -g2h_engine_lookup(struct xe_guc *guc, u32 guc_id) > +static struct xe_exec_queue * > +g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id) > { > struct xe_device *xe = guc_to_xe(guc); > - struct xe_engine *e; > + struct xe_exec_queue *q; > > if (unlikely(guc_id >= GUC_ID_MAX)) { > drm_err(&xe->drm, "Invalid guc_id %u", guc_id); > return NULL; > } > > - e = xa_load(&guc->submission_state.engine_lookup, guc_id); > - if (unlikely(!e)) { > + q = xa_load(&guc->submission_state.exec_queue_lookup, guc_id); > + if (unlikely(!q)) { > drm_err(&xe->drm, "Not engine present for guc_id %u", guc_id); > return NULL; > } > > - XE_WARN_ON(e->guc->id != guc_id); > + XE_WARN_ON(q->guc->id != guc_id); > > - return e; > + return q; > } > > -static void deregister_engine(struct xe_guc *guc, struct xe_engine *e) > +static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q) > { > u32 action[] = { > XE_GUC_ACTION_DEREGISTER_CONTEXT, > - e->guc->id, > + q->guc->id, > }; > > - trace_xe_engine_deregister(e); > + trace_xe_exec_queue_deregister(q); > > xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action)); > } > @@ -1506,7 +1506,7 @@ static void deregister_engine(struct xe_guc *guc, struct xe_engine *e) > int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > { > struct xe_device *xe = guc_to_xe(guc); > - struct xe_engine *e; > + struct xe_exec_queue *q; > u32 guc_id = msg[0]; > > if (unlikely(len < 2)) { > @@ -1514,34 +1514,34 @@ int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > return -EPROTO; > } > > - e = g2h_engine_lookup(guc, guc_id); > - if (unlikely(!e)) > + q = g2h_exec_queue_lookup(guc, guc_id); > + if (unlikely(!q)) > return -EPROTO; > > - if (unlikely(!engine_pending_enable(e) && > - !engine_pending_disable(e))) { > + if (unlikely(!exec_queue_pending_enable(q) && > + !exec_queue_pending_disable(q))) { > drm_err(&xe->drm, "Unexpected engine state 0x%04x", > - atomic_read(&e->guc->state)); > + atomic_read(&q->guc->state)); > return -EPROTO; > } > > - trace_xe_engine_scheduling_done(e); > + trace_xe_exec_queue_scheduling_done(q); > > - if (engine_pending_enable(e)) { > - e->guc->resume_time = ktime_get(); > - clear_engine_pending_enable(e); > + if (exec_queue_pending_enable(q)) { > + q->guc->resume_time = ktime_get(); > + clear_exec_queue_pending_enable(q); > smp_wmb(); > wake_up_all(&guc->ct.wq); > } else { > - clear_engine_pending_disable(e); > - if (e->guc->suspend_pending) { > - suspend_fence_signal(e); > + clear_exec_queue_pending_disable(q); > + if (q->guc->suspend_pending) { > + suspend_fence_signal(q); > } else { > - if (engine_banned(e)) { > + if (exec_queue_banned(q)) { > smp_wmb(); > wake_up_all(&guc->ct.wq); > } > - deregister_engine(guc, e); > + deregister_exec_queue(guc, q); > } > } > > @@ -1551,7 +1551,7 @@ int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > { > struct xe_device *xe = guc_to_xe(guc); > - struct xe_engine *e; > + struct xe_exec_queue *q; > u32 guc_id = msg[0]; > > if (unlikely(len < 1)) { > @@ -1559,33 +1559,33 @@ int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > return -EPROTO; > } > > - e = g2h_engine_lookup(guc, guc_id); > - if (unlikely(!e)) > + q = g2h_exec_queue_lookup(guc, guc_id); > + if (unlikely(!q)) > return -EPROTO; > > - if (!engine_destroyed(e) || engine_pending_disable(e) || > - engine_pending_enable(e) || engine_enabled(e)) { > + if (!exec_queue_destroyed(q) || exec_queue_pending_disable(q) || > + exec_queue_pending_enable(q) || exec_queue_enabled(q)) { > drm_err(&xe->drm, "Unexpected engine state 0x%04x", > - atomic_read(&e->guc->state)); > + atomic_read(&q->guc->state)); > return -EPROTO; > } > > - trace_xe_engine_deregister_done(e); > + trace_xe_exec_queue_deregister_done(q); > > - clear_engine_registered(e); > + clear_exec_queue_registered(q); > > - if (engine_banned(e) || xe_engine_is_lr(e)) > - xe_engine_put(e); > + if (exec_queue_banned(q) || xe_exec_queue_is_lr(q)) > + xe_exec_queue_put(q); > else > - __guc_engine_fini(guc, e); > + __guc_exec_queue_fini(guc, q); > > return 0; > } > > -int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) > +int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) > { > struct xe_device *xe = guc_to_xe(guc); > - struct xe_engine *e; > + struct xe_exec_queue *q; > u32 guc_id = msg[0]; > > if (unlikely(len < 1)) { > @@ -1593,34 +1593,34 @@ int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) > return -EPROTO; > } > > - e = g2h_engine_lookup(guc, guc_id); > - if (unlikely(!e)) > + q = g2h_exec_queue_lookup(guc, guc_id); > + if (unlikely(!q)) > return -EPROTO; > > drm_warn(&xe->drm, "Engine reset: guc_id=%d", guc_id); > > /* FIXME: Do error capture, most likely async */ > > - trace_xe_engine_reset(e); > + trace_xe_exec_queue_reset(q); > > /* > * A banned engine is a NOP at this point (came from > - * guc_engine_timedout_job). Otherwise, kick drm scheduler to cancel > + * guc_exec_queue_timedout_job). Otherwise, kick drm scheduler to cancel > * jobs by setting timeout of the job to the minimum value kicking > - * guc_engine_timedout_job. > + * guc_exec_queue_timedout_job. > */ > - set_engine_reset(e); > - if (!engine_banned(e)) > - xe_guc_engine_trigger_cleanup(e); > + set_exec_queue_reset(q); > + if (!exec_queue_banned(q)) > + xe_guc_exec_queue_trigger_cleanup(q); > > return 0; > } > > -int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > - u32 len) > +int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > + u32 len) > { > struct xe_device *xe = guc_to_xe(guc); > - struct xe_engine *e; > + struct xe_exec_queue *q; > u32 guc_id = msg[0]; > > if (unlikely(len < 1)) { > @@ -1628,22 +1628,22 @@ int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > return -EPROTO; > } > > - e = g2h_engine_lookup(guc, guc_id); > - if (unlikely(!e)) > + q = g2h_exec_queue_lookup(guc, guc_id); > + if (unlikely(!q)) > return -EPROTO; > > drm_warn(&xe->drm, "Engine memory cat error: guc_id=%d", guc_id); > - trace_xe_engine_memory_cat_error(e); > + trace_xe_exec_queue_memory_cat_error(q); > > /* Treat the same as engine reset */ > - set_engine_reset(e); > - if (!engine_banned(e)) > - xe_guc_engine_trigger_cleanup(e); > + set_exec_queue_reset(q); > + if (!exec_queue_banned(q)) > + xe_guc_exec_queue_trigger_cleanup(q); > > return 0; > } > > -int xe_guc_engine_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) > +int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) > { > struct xe_device *xe = guc_to_xe(guc); > u8 guc_class, instance; > @@ -1668,16 +1668,16 @@ int xe_guc_engine_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) > } > > static void > -guc_engine_wq_snapshot_capture(struct xe_engine *e, > - struct xe_guc_submit_engine_snapshot *snapshot) > +guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q, > + struct xe_guc_submit_exec_queue_snapshot *snapshot) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > struct xe_device *xe = guc_to_xe(guc); > - struct iosys_map map = xe_lrc_parallel_map(e->lrc); > + struct iosys_map map = xe_lrc_parallel_map(q->lrc); > int i; > > - snapshot->guc.wqi_head = e->guc->wqi_head; > - snapshot->guc.wqi_tail = e->guc->wqi_tail; > + snapshot->guc.wqi_head = q->guc->wqi_head; > + snapshot->guc.wqi_tail = q->guc->wqi_tail; > snapshot->parallel.wq_desc.head = parallel_read(xe, map, wq_desc.head); > snapshot->parallel.wq_desc.tail = parallel_read(xe, map, wq_desc.tail); > snapshot->parallel.wq_desc.status = parallel_read(xe, map, > @@ -1694,8 +1694,8 @@ guc_engine_wq_snapshot_capture(struct xe_engine *e, > } > > static void > -guc_engine_wq_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > - struct drm_printer *p) > +guc_exec_queue_wq_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, > + struct drm_printer *p) > { > int i; > > @@ -1716,23 +1716,23 @@ guc_engine_wq_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > } > > /** > - * xe_guc_engine_snapshot_capture - Take a quick snapshot of the GuC Engine. > + * xe_guc_exec_queue_snapshot_capture - Take a quick snapshot of the GuC Engine. > * @e: Xe Engine. > * > * This can be printed out in a later stage like during dev_coredump > * analysis. > * > * Returns: a GuC Submit Engine snapshot object that must be freed by the > - * caller, using `xe_guc_engine_snapshot_free`. > + * caller, using `xe_guc_exec_queue_snapshot_free`. > */ > -struct xe_guc_submit_engine_snapshot * > -xe_guc_engine_snapshot_capture(struct xe_engine *e) > +struct xe_guc_submit_exec_queue_snapshot * > +xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q) > { > - struct xe_guc *guc = engine_to_guc(e); > + struct xe_guc *guc = exec_queue_to_guc(q); > struct xe_device *xe = guc_to_xe(guc); > - struct drm_gpu_scheduler *sched = &e->guc->sched; > + struct drm_gpu_scheduler *sched = &q->guc->sched; > struct xe_sched_job *job; > - struct xe_guc_submit_engine_snapshot *snapshot; > + struct xe_guc_submit_exec_queue_snapshot *snapshot; > int i; > > snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); > @@ -1742,25 +1742,25 @@ xe_guc_engine_snapshot_capture(struct xe_engine *e) > return NULL; > } > > - snapshot->guc.id = e->guc->id; > - memcpy(&snapshot->name, &e->name, sizeof(snapshot->name)); > - snapshot->class = e->class; > - snapshot->logical_mask = e->logical_mask; > - snapshot->width = e->width; > - snapshot->refcount = kref_read(&e->refcount); > + snapshot->guc.id = q->guc->id; > + memcpy(&snapshot->name, &q->name, sizeof(snapshot->name)); > + snapshot->class = q->class; > + snapshot->logical_mask = q->logical_mask; > + snapshot->width = q->width; > + snapshot->refcount = kref_read(&q->refcount); > snapshot->sched_timeout = sched->timeout; > - snapshot->sched_props.timeslice_us = e->sched_props.timeslice_us; > + snapshot->sched_props.timeslice_us = q->sched_props.timeslice_us; > snapshot->sched_props.preempt_timeout_us = > - e->sched_props.preempt_timeout_us; > + q->sched_props.preempt_timeout_us; > > - snapshot->lrc = kmalloc_array(e->width, sizeof(struct lrc_snapshot), > + snapshot->lrc = kmalloc_array(q->width, sizeof(struct lrc_snapshot), > GFP_ATOMIC); > > if (!snapshot->lrc) { > drm_err(&xe->drm, "Skipping GuC Engine LRC snapshot.\n"); > } else { > - for (i = 0; i < e->width; ++i) { > - struct xe_lrc *lrc = e->lrc + i; > + for (i = 0; i < q->width; ++i) { > + struct xe_lrc *lrc = q->lrc + i; > > snapshot->lrc[i].context_desc = > lower_32_bits(xe_lrc_ggtt_addr(lrc)); > @@ -1773,12 +1773,12 @@ xe_guc_engine_snapshot_capture(struct xe_engine *e) > } > } > > - snapshot->schedule_state = atomic_read(&e->guc->state); > - snapshot->engine_flags = e->flags; > + snapshot->schedule_state = atomic_read(&q->guc->state); > + snapshot->exec_queue_flags = q->flags; > > - snapshot->parallel_execution = xe_engine_is_parallel(e); > + snapshot->parallel_execution = xe_exec_queue_is_parallel(q); > if (snapshot->parallel_execution) > - guc_engine_wq_snapshot_capture(e, snapshot); > + guc_exec_queue_wq_snapshot_capture(q, snapshot); > > spin_lock(&sched->job_list_lock); > snapshot->pending_list_size = list_count_nodes(&sched->pending_list); > @@ -1808,15 +1808,15 @@ xe_guc_engine_snapshot_capture(struct xe_engine *e) > } > > /** > - * xe_guc_engine_snapshot_print - Print out a given GuC Engine snapshot. > + * xe_guc_exec_queue_snapshot_print - Print out a given GuC Engine snapshot. > * @snapshot: GuC Submit Engine snapshot object. > * @p: drm_printer where it will be printed out. > * > * This function prints out a given GuC Submit Engine snapshot object. > */ > void > -xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > - struct drm_printer *p) > +xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, > + struct drm_printer *p) > { > int i; > > @@ -1848,10 +1848,10 @@ xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > drm_printf(p, "\tSeqno: (memory) %d\n", snapshot->lrc[i].seqno); > } > drm_printf(p, "\tSchedule State: 0x%x\n", snapshot->schedule_state); > - drm_printf(p, "\tFlags: 0x%lx\n", snapshot->engine_flags); > + drm_printf(p, "\tFlags: 0x%lx\n", snapshot->exec_queue_flags); > > if (snapshot->parallel_execution) > - guc_engine_wq_snapshot_print(snapshot, p); > + guc_exec_queue_wq_snapshot_print(snapshot, p); > > for (i = 0; snapshot->pending_list && i < snapshot->pending_list_size; > i++) > @@ -1862,14 +1862,14 @@ xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > } > > /** > - * xe_guc_engine_snapshot_free - Free all allocated objects for a given > + * xe_guc_exec_queue_snapshot_free - Free all allocated objects for a given > * snapshot. > * @snapshot: GuC Submit Engine snapshot object. > * > * This function free all the memory that needed to be allocated at capture > * time. > */ > -void xe_guc_engine_snapshot_free(struct xe_guc_submit_engine_snapshot *snapshot) > +void xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot) > { > if (!snapshot) > return; > @@ -1879,13 +1879,13 @@ void xe_guc_engine_snapshot_free(struct xe_guc_submit_engine_snapshot *snapshot) > kfree(snapshot); > } > > -static void guc_engine_print(struct xe_engine *e, struct drm_printer *p) > +static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p) > { > - struct xe_guc_submit_engine_snapshot *snapshot; > + struct xe_guc_submit_exec_queue_snapshot *snapshot; > > - snapshot = xe_guc_engine_snapshot_capture(e); > - xe_guc_engine_snapshot_print(snapshot, p); > - xe_guc_engine_snapshot_free(snapshot); > + snapshot = xe_guc_exec_queue_snapshot_capture(q); > + xe_guc_exec_queue_snapshot_print(snapshot, p); > + xe_guc_exec_queue_snapshot_free(snapshot); > } > > /** > @@ -1897,14 +1897,14 @@ static void guc_engine_print(struct xe_engine *e, struct drm_printer *p) > */ > void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p) > { > - struct xe_engine *e; > + struct xe_exec_queue *q; > unsigned long index; > > if (!xe_device_guc_submission_enabled(guc_to_xe(guc))) > return; > > mutex_lock(&guc->submission_state.lock); > - xa_for_each(&guc->submission_state.engine_lookup, index, e) > - guc_engine_print(e, p); > + xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) > + guc_exec_queue_print(q, p); > mutex_unlock(&guc->submission_state.lock); > } > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h > index 4153c2d22013..fc97869c5b86 100644 > --- a/drivers/gpu/drm/xe/xe_guc_submit.h > +++ b/drivers/gpu/drm/xe/xe_guc_submit.h > @@ -9,7 +9,7 @@ > #include <linux/types.h> > > struct drm_printer; > -struct xe_engine; > +struct xe_exec_queue; > struct xe_guc; > > int xe_guc_submit_init(struct xe_guc *guc); > @@ -21,18 +21,18 @@ int xe_guc_submit_start(struct xe_guc *guc); > > int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len); > int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len); > -int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len); > -int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > - u32 len); > -int xe_guc_engine_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len); > +int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len); > +int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > + u32 len); > +int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len); > > -struct xe_guc_submit_engine_snapshot * > -xe_guc_engine_snapshot_capture(struct xe_engine *e); > +struct xe_guc_submit_exec_queue_snapshot * > +xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q); > void > -xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > - struct drm_printer *p); > +xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, > + struct drm_printer *p); > void > -xe_guc_engine_snapshot_free(struct xe_guc_submit_engine_snapshot *snapshot); > +xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot); > void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p); > > #endif > diff --git a/drivers/gpu/drm/xe/xe_guc_submit_types.h b/drivers/gpu/drm/xe/xe_guc_submit_types.h > index 6765b2c6eab1..649b0a852692 100644 > --- a/drivers/gpu/drm/xe/xe_guc_submit_types.h > +++ b/drivers/gpu/drm/xe/xe_guc_submit_types.h > @@ -79,20 +79,20 @@ struct pending_list_snapshot { > }; > > /** > - * struct xe_guc_submit_engine_snapshot - Snapshot for devcoredump > + * struct xe_guc_submit_exec_queue_snapshot - Snapshot for devcoredump > */ > -struct xe_guc_submit_engine_snapshot { > - /** @name: name of this engine */ > +struct xe_guc_submit_exec_queue_snapshot { > + /** @name: name of this exec queue */ > char name[MAX_FENCE_NAME_LEN]; > - /** @class: class of this engine */ > + /** @class: class of this exec queue */ > enum xe_engine_class class; > /** > - * @logical_mask: logical mask of where job submitted to engine can run > + * @logical_mask: logical mask of where job submitted to exec queue can run > */ > u32 logical_mask; > - /** @width: width (number BB submitted per exec) of this engine */ > + /** @width: width (number BB submitted per exec) of this exec queue */ > u16 width; > - /** @refcount: ref count of this engine */ > + /** @refcount: ref count of this exec queue */ > u32 refcount; > /** > * @sched_timeout: the time after which a job is removed from the > @@ -113,8 +113,8 @@ struct xe_guc_submit_engine_snapshot { > > /** @schedule_state: Schedule State at the moment of Crash */ > u32 schedule_state; > - /** @engine_flags: Flags of the faulty engine */ > - unsigned long engine_flags; > + /** @exec_queue_flags: Flags of the faulty exec_queue */ > + unsigned long exec_queue_flags; > > /** @guc: GuC Engine Snapshot */ > struct { > @@ -122,7 +122,7 @@ struct xe_guc_submit_engine_snapshot { > u32 wqi_head; > /** @wqi_tail: work queue item tail */ > u32 wqi_tail; > - /** @id: GuC id for this xe_engine */ > + /** @id: GuC id for this exec_queue */ > u16 id; > } guc; > > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h > index a304dce4e9f4..a5e58917a499 100644 > --- a/drivers/gpu/drm/xe/xe_guc_types.h > +++ b/drivers/gpu/drm/xe/xe_guc_types.h > @@ -33,8 +33,8 @@ struct xe_guc { > struct xe_guc_pc pc; > /** @submission_state: GuC submission state */ > struct { > - /** @engine_lookup: Lookup an xe_engine from guc_id */ > - struct xarray engine_lookup; > + /** @exec_queue_lookup: Lookup an xe_engine from guc_id */ > + struct xarray exec_queue_lookup; > /** @guc_ids: used to allocate new guc_ids, single-lrc */ > struct ida guc_ids; > /** @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc */ > diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c > index 05f3d8d68379..09db8da261a3 100644 > --- a/drivers/gpu/drm/xe/xe_lrc.c > +++ b/drivers/gpu/drm/xe/xe_lrc.c > @@ -12,7 +12,7 @@ > #include "regs/xe_regs.h" > #include "xe_bo.h" > #include "xe_device.h" > -#include "xe_engine_types.h" > +#include "xe_exec_queue_types.h" > #include "xe_gt.h" > #include "xe_hw_fence.h" > #include "xe_map.h" > @@ -604,7 +604,7 @@ static void xe_lrc_set_ppgtt(struct xe_lrc *lrc, struct xe_vm *vm) > #define ACC_NOTIFY_S 16 > > int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, > - struct xe_engine *e, struct xe_vm *vm, u32 ring_size) > + struct xe_exec_queue *q, struct xe_vm *vm, u32 ring_size) > { > struct xe_gt *gt = hwe->gt; > struct xe_tile *tile = gt_to_tile(gt); > @@ -669,12 +669,12 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, > RING_CTL_SIZE(lrc->ring.size) | RING_VALID); > if (xe->info.has_asid && vm) > xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID, > - (e->usm.acc_granularity << > + (q->usm.acc_granularity << > ACC_GRANULARITY_S) | vm->usm.asid); > if (xe->info.supports_usm && vm) > xe_lrc_write_ctx_reg(lrc, PVC_CTX_ACC_CTR_THOLD, > - (e->usm.acc_notify << ACC_NOTIFY_S) | > - e->usm.acc_trigger); > + (q->usm.acc_notify << ACC_NOTIFY_S) | > + q->usm.acc_trigger); > > lrc->desc = GEN8_CTX_VALID; > lrc->desc |= INTEL_LEGACY_64B_CONTEXT << GEN8_CTX_ADDRESSING_MODE_SHIFT; > diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h > index e37f89e75ef8..3a6e8fc5a837 100644 > --- a/drivers/gpu/drm/xe/xe_lrc.h > +++ b/drivers/gpu/drm/xe/xe_lrc.h > @@ -8,7 +8,7 @@ > #include "xe_lrc_types.h" > > struct xe_device; > -struct xe_engine; > +struct xe_exec_queue; > enum xe_engine_class; > struct xe_hw_engine; > struct xe_vm; > @@ -16,7 +16,7 @@ struct xe_vm; > #define LRC_PPHWSP_SCRATCH_ADDR (0x34 * 4) > > int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, > - struct xe_engine *e, struct xe_vm *vm, u32 ring_size); > + struct xe_exec_queue *q, struct xe_vm *vm, u32 ring_size); > void xe_lrc_finish(struct xe_lrc *lrc); > > size_t xe_lrc_size(struct xe_device *xe, enum xe_engine_class class); > diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c > index 414f93cddb28..7af2d74833c0 100644 > --- a/drivers/gpu/drm/xe/xe_migrate.c > +++ b/drivers/gpu/drm/xe/xe_migrate.c > @@ -16,7 +16,7 @@ > #include "tests/xe_test.h" > #include "xe_bb.h" > #include "xe_bo.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_ggtt.h" > #include "xe_gt.h" > #include "xe_hw_engine.h" > @@ -35,7 +35,7 @@ > */ > struct xe_migrate { > /** @eng: Default engine used for migration */ > - struct xe_engine *eng; > + struct xe_exec_queue *q; > /** @tile: Backpointer to the tile this struct xe_migrate belongs to. */ > struct xe_tile *tile; > /** @job_mutex: Timeline mutex for @eng. */ > @@ -78,9 +78,9 @@ struct xe_migrate { > * > * Return: The default migrate engine > */ > -struct xe_engine *xe_tile_migrate_engine(struct xe_tile *tile) > +struct xe_exec_queue *xe_tile_migrate_engine(struct xe_tile *tile) > { > - return tile->migrate->eng; > + return tile->migrate->q; > } > > static void xe_migrate_fini(struct drm_device *dev, void *arg) > @@ -88,11 +88,11 @@ static void xe_migrate_fini(struct drm_device *dev, void *arg) > struct xe_migrate *m = arg; > struct ww_acquire_ctx ww; > > - xe_vm_lock(m->eng->vm, &ww, 0, false); > + xe_vm_lock(m->q->vm, &ww, 0, false); > xe_bo_unpin(m->pt_bo); > if (m->cleared_bo) > xe_bo_unpin(m->cleared_bo); > - xe_vm_unlock(m->eng->vm, &ww); > + xe_vm_unlock(m->q->vm, &ww); > > dma_fence_put(m->fence); > if (m->cleared_bo) > @@ -100,8 +100,8 @@ static void xe_migrate_fini(struct drm_device *dev, void *arg) > xe_bo_put(m->pt_bo); > drm_suballoc_manager_fini(&m->vm_update_sa); > mutex_destroy(&m->job_mutex); > - xe_vm_close_and_put(m->eng->vm); > - xe_engine_put(m->eng); > + xe_vm_close_and_put(m->q->vm); > + xe_exec_queue_put(m->q); > } > > static u64 xe_migrate_vm_addr(u64 slot, u32 level) > @@ -341,20 +341,20 @@ struct xe_migrate *xe_migrate_init(struct xe_tile *tile) > if (!hwe) > return ERR_PTR(-EINVAL); > > - m->eng = xe_engine_create(xe, vm, > - BIT(hwe->logical_instance), 1, > - hwe, ENGINE_FLAG_KERNEL); > + m->q = xe_exec_queue_create(xe, vm, > + BIT(hwe->logical_instance), 1, > + hwe, EXEC_QUEUE_FLAG_KERNEL); > } else { > - m->eng = xe_engine_create_class(xe, primary_gt, vm, > - XE_ENGINE_CLASS_COPY, > - ENGINE_FLAG_KERNEL); > + m->q = xe_exec_queue_create_class(xe, primary_gt, vm, > + XE_ENGINE_CLASS_COPY, > + EXEC_QUEUE_FLAG_KERNEL); > } > - if (IS_ERR(m->eng)) { > + if (IS_ERR(m->q)) { > xe_vm_close_and_put(vm); > - return ERR_CAST(m->eng); > + return ERR_CAST(m->q); > } > if (xe->info.supports_usm) > - m->eng->entity->priority = DRM_SCHED_PRIORITY_KERNEL; > + m->q->entity->priority = DRM_SCHED_PRIORITY_KERNEL; > > mutex_init(&m->job_mutex); > > @@ -456,7 +456,7 @@ static void emit_pte(struct xe_migrate *m, > addr = xe_res_dma(cur) & PAGE_MASK; > if (is_vram) { > /* Is this a 64K PTE entry? */ > - if ((m->eng->vm->flags & XE_VM_FLAG_64K) && > + if ((m->q->vm->flags & XE_VM_FLAG_64K) && > !(cur_ofs & (16 * 8 - 1))) { > XE_WARN_ON(!IS_ALIGNED(addr, SZ_64K)); > addr |= XE_PTE_PS64; > @@ -714,7 +714,7 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m, > src_L0, ccs_ofs, copy_ccs); > > mutex_lock(&m->job_mutex); > - job = xe_bb_create_migration_job(m->eng, bb, > + job = xe_bb_create_migration_job(m->q, bb, > xe_migrate_batch_base(m, usm), > update_idx); > if (IS_ERR(job)) { > @@ -938,7 +938,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m, > } > > mutex_lock(&m->job_mutex); > - job = xe_bb_create_migration_job(m->eng, bb, > + job = xe_bb_create_migration_job(m->q, bb, > xe_migrate_batch_base(m, usm), > update_idx); > if (IS_ERR(job)) { > @@ -1024,7 +1024,7 @@ static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs, > > struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m) > { > - return xe_vm_get(m->eng->vm); > + return xe_vm_get(m->q->vm); > } > > #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) > @@ -1132,7 +1132,7 @@ struct dma_fence * > xe_migrate_update_pgtables(struct xe_migrate *m, > struct xe_vm *vm, > struct xe_bo *bo, > - struct xe_engine *eng, > + struct xe_exec_queue *q, > const struct xe_vm_pgtable_update *updates, > u32 num_updates, > struct xe_sync_entry *syncs, u32 num_syncs, > @@ -1150,13 +1150,13 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > u32 i, batch_size, ppgtt_ofs, update_idx, page_ofs = 0; > u64 addr; > int err = 0; > - bool usm = !eng && xe->info.supports_usm; > + bool usm = !q && xe->info.supports_usm; > bool first_munmap_rebind = vma && > vma->gpuva.flags & XE_VMA_FIRST_REBIND; > - struct xe_engine *eng_override = !eng ? m->eng : eng; > + struct xe_exec_queue *q_override = !q ? m->q : q; > > /* Use the CPU if no in syncs and engine is idle */ > - if (no_in_syncs(syncs, num_syncs) && xe_engine_is_idle(eng_override)) { > + if (no_in_syncs(syncs, num_syncs) && xe_exec_queue_is_idle(q_override)) { > fence = xe_migrate_update_pgtables_cpu(m, vm, bo, updates, > num_updates, > first_munmap_rebind, > @@ -1186,14 +1186,14 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > */ > XE_WARN_ON(batch_size >= SZ_128K); > > - bb = xe_bb_new(gt, batch_size, !eng && xe->info.supports_usm); > + bb = xe_bb_new(gt, batch_size, !q && xe->info.supports_usm); > if (IS_ERR(bb)) > return ERR_CAST(bb); > > /* For sysmem PTE's, need to map them in our hole.. */ > if (!IS_DGFX(xe)) { > ppgtt_ofs = NUM_KERNEL_PDE - 1; > - if (eng) { > + if (q) { > XE_WARN_ON(num_updates > NUM_VMUSA_WRITES_PER_UNIT); > > sa_bo = drm_suballoc_new(&m->vm_update_sa, 1, > @@ -1249,10 +1249,10 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > write_pgtable(tile, bb, 0, &updates[i], pt_update); > } > > - if (!eng) > + if (!q) > mutex_lock(&m->job_mutex); > > - job = xe_bb_create_migration_job(eng ?: m->eng, bb, > + job = xe_bb_create_migration_job(q ?: m->q, bb, > xe_migrate_batch_base(m, usm), > update_idx); > if (IS_ERR(job)) { > @@ -1295,7 +1295,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > fence = dma_fence_get(&job->drm.s_fence->finished); > xe_sched_job_push(job); > > - if (!eng) > + if (!q) > mutex_unlock(&m->job_mutex); > > xe_bb_free(bb, fence); > @@ -1306,7 +1306,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > err_job: > xe_sched_job_put(job); > err_bb: > - if (!eng) > + if (!q) > mutex_unlock(&m->job_mutex); > xe_bb_free(bb, NULL); > err: > diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h > index 0d62aff6421c..c729241776ad 100644 > --- a/drivers/gpu/drm/xe/xe_migrate.h > +++ b/drivers/gpu/drm/xe/xe_migrate.h > @@ -14,7 +14,7 @@ struct ttm_resource; > > struct xe_bo; > struct xe_gt; > -struct xe_engine; > +struct xe_exec_queue; > struct xe_migrate; > struct xe_migrate_pt_update; > struct xe_sync_entry; > @@ -97,7 +97,7 @@ struct dma_fence * > xe_migrate_update_pgtables(struct xe_migrate *m, > struct xe_vm *vm, > struct xe_bo *bo, > - struct xe_engine *eng, > + struct xe_exec_queue *q, > const struct xe_vm_pgtable_update *updates, > u32 num_updates, > struct xe_sync_entry *syncs, u32 num_syncs, > @@ -105,5 +105,5 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > > void xe_migrate_wait(struct xe_migrate *m); > > -struct xe_engine *xe_tile_migrate_engine(struct xe_tile *tile); > +struct xe_exec_queue *xe_tile_migrate_engine(struct xe_tile *tile); > #endif > diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c > index ccc852500eda..c9653978fc9f 100644 > --- a/drivers/gpu/drm/xe/xe_mocs.c > +++ b/drivers/gpu/drm/xe/xe_mocs.c > @@ -8,7 +8,7 @@ > #include "regs/xe_gt_regs.h" > #include "xe_bo.h" > #include "xe_device.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_gt.h" > #include "xe_mmio.h" > #include "xe_platform_types.h" > diff --git a/drivers/gpu/drm/xe/xe_mocs.h b/drivers/gpu/drm/xe/xe_mocs.h > index 25f7b35a76da..d0f1ec4b0336 100644 > --- a/drivers/gpu/drm/xe/xe_mocs.h > +++ b/drivers/gpu/drm/xe/xe_mocs.h > @@ -8,7 +8,7 @@ > > #include <linux/types.h> > > -struct xe_engine; > +struct xe_exec_queue; > struct xe_gt; > > void xe_mocs_init_early(struct xe_gt *gt); > diff --git a/drivers/gpu/drm/xe/xe_preempt_fence.c b/drivers/gpu/drm/xe/xe_preempt_fence.c > index 219eefeb90ff..e0ce1588a734 100644 > --- a/drivers/gpu/drm/xe/xe_preempt_fence.c > +++ b/drivers/gpu/drm/xe/xe_preempt_fence.c > @@ -7,7 +7,7 @@ > > #include <linux/slab.h> > > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_vm.h" > > static void preempt_fence_work_func(struct work_struct *w) > @@ -15,19 +15,19 @@ static void preempt_fence_work_func(struct work_struct *w) > bool cookie = dma_fence_begin_signalling(); > struct xe_preempt_fence *pfence = > container_of(w, typeof(*pfence), preempt_work); > - struct xe_engine *e = pfence->engine; > + struct xe_exec_queue *q = pfence->q; > > if (pfence->error) > dma_fence_set_error(&pfence->base, pfence->error); > else > - e->ops->suspend_wait(e); > + q->ops->suspend_wait(q); > > dma_fence_signal(&pfence->base); > dma_fence_end_signalling(cookie); > > - xe_vm_queue_rebind_worker(e->vm); > + xe_vm_queue_rebind_worker(q->vm); > > - xe_engine_put(e); > + xe_exec_queue_put(q); > } > > static const char * > @@ -46,9 +46,9 @@ static bool preempt_fence_enable_signaling(struct dma_fence *fence) > { > struct xe_preempt_fence *pfence = > container_of(fence, typeof(*pfence), base); > - struct xe_engine *e = pfence->engine; > + struct xe_exec_queue *q = pfence->q; > > - pfence->error = e->ops->suspend(e); > + pfence->error = q->ops->suspend(q); > queue_work(system_unbound_wq, &pfence->preempt_work); > return true; > } > @@ -104,43 +104,43 @@ void xe_preempt_fence_free(struct xe_preempt_fence *pfence) > * xe_preempt_fence_alloc(). > * @pfence: The struct xe_preempt_fence pointer returned from > * xe_preempt_fence_alloc(). > - * @e: The struct xe_engine used for arming. > + * @e: The struct xe_exec_queue used for arming. > * @context: The dma-fence context used for arming. > * @seqno: The dma-fence seqno used for arming. > * > * Inserts the preempt fence into @context's timeline, takes @link off any > - * list, and registers the struct xe_engine as the xe_engine to be preempted. > + * list, and registers the struct xe_exec_queue as the xe_engine to be preempted. > * > * Return: A pointer to a struct dma_fence embedded into the preempt fence. > * This function doesn't error. > */ > struct dma_fence * > -xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_engine *e, > +xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_exec_queue *q, > u64 context, u32 seqno) > { > list_del_init(&pfence->link); > - pfence->engine = xe_engine_get(e); > + pfence->q = xe_exec_queue_get(q); > dma_fence_init(&pfence->base, &preempt_fence_ops, > - &e->compute.lock, context, seqno); > + &q->compute.lock, context, seqno); > > return &pfence->base; > } > > /** > * xe_preempt_fence_create() - Helper to create and arm a preempt fence. > - * @e: The struct xe_engine used for arming. > + * @e: The struct xe_exec_queue used for arming. > * @context: The dma-fence context used for arming. > * @seqno: The dma-fence seqno used for arming. > * > * Allocates and inserts the preempt fence into @context's timeline, > - * and registers @e as the struct xe_engine to be preempted. > + * and registers @e as the struct xe_exec_queue to be preempted. > * > * Return: A pointer to the resulting struct dma_fence on success. An error > * pointer on error. In particular if allocation fails it returns > * ERR_PTR(-ENOMEM); > */ > struct dma_fence * > -xe_preempt_fence_create(struct xe_engine *e, > +xe_preempt_fence_create(struct xe_exec_queue *q, > u64 context, u32 seqno) > { > struct xe_preempt_fence *pfence; > @@ -149,7 +149,7 @@ xe_preempt_fence_create(struct xe_engine *e, > if (IS_ERR(pfence)) > return ERR_CAST(pfence); > > - return xe_preempt_fence_arm(pfence, e, context, seqno); > + return xe_preempt_fence_arm(pfence, q, context, seqno); > } > > bool xe_fence_is_xe_preempt(const struct dma_fence *fence) > diff --git a/drivers/gpu/drm/xe/xe_preempt_fence.h b/drivers/gpu/drm/xe/xe_preempt_fence.h > index 4f3966103203..9406c6fea525 100644 > --- a/drivers/gpu/drm/xe/xe_preempt_fence.h > +++ b/drivers/gpu/drm/xe/xe_preempt_fence.h > @@ -11,7 +11,7 @@ > struct list_head; > > struct dma_fence * > -xe_preempt_fence_create(struct xe_engine *e, > +xe_preempt_fence_create(struct xe_exec_queue *q, > u64 context, u32 seqno); > > struct xe_preempt_fence *xe_preempt_fence_alloc(void); > @@ -19,7 +19,7 @@ struct xe_preempt_fence *xe_preempt_fence_alloc(void); > void xe_preempt_fence_free(struct xe_preempt_fence *pfence); > > struct dma_fence * > -xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_engine *e, > +xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_exec_queue *q, > u64 context, u32 seqno); > > static inline struct xe_preempt_fence * > diff --git a/drivers/gpu/drm/xe/xe_preempt_fence_types.h b/drivers/gpu/drm/xe/xe_preempt_fence_types.h > index 9d9efd8ff0ed..176ea1e9e204 100644 > --- a/drivers/gpu/drm/xe/xe_preempt_fence_types.h > +++ b/drivers/gpu/drm/xe/xe_preempt_fence_types.h > @@ -9,12 +9,11 @@ > #include <linux/dma-fence.h> > #include <linux/workqueue.h> > > -struct xe_engine; > +struct xe_exec_queue; > > /** > * struct xe_preempt_fence - XE preempt fence > * > - * A preemption fence which suspends the execution of an xe_engine on the > * hardware and triggers a callback once the xe_engine is complete. > */ > struct xe_preempt_fence { > @@ -23,7 +22,7 @@ struct xe_preempt_fence { > /** @link: link into list of pending preempt fences */ > struct list_head link; > /** @engine: xe engine for this preempt fence */ > - struct xe_engine *engine; > + struct xe_exec_queue *q; > /** @preempt_work: work struct which issues preemption */ > struct work_struct preempt_work; > /** @error: preempt fence is in error state */ > diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c > index 9b034272d82f..5709518e314b 100644 > --- a/drivers/gpu/drm/xe/xe_pt.c > +++ b/drivers/gpu/drm/xe/xe_pt.c > @@ -1307,7 +1307,7 @@ static void xe_pt_calc_rfence_interval(struct xe_vma *vma, > * address range. > * @tile: The tile to bind for. > * @vma: The vma to bind. > - * @e: The engine with which to do pipelined page-table updates. > + * @q: The exec_queue with which to do pipelined page-table updates. > * @syncs: Entries to sync on before binding the built tree to the live vm tree. > * @num_syncs: Number of @sync entries. > * @rebind: Whether we're rebinding this vma to the same address range without > @@ -1325,7 +1325,7 @@ static void xe_pt_calc_rfence_interval(struct xe_vma *vma, > * on success, an error pointer on error. > */ > struct dma_fence * > -__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > +__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, > struct xe_sync_entry *syncs, u32 num_syncs, > bool rebind) > { > @@ -1351,7 +1351,7 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > > vm_dbg(&xe_vma_vm(vma)->xe->drm, > "Preparing bind, with range [%llx...%llx) engine %p.\n", > - xe_vma_start(vma), xe_vma_end(vma) - 1, e); > + xe_vma_start(vma), xe_vma_end(vma) - 1, q); > > err = xe_pt_prepare_bind(tile, vma, entries, &num_entries, rebind); > if (err) > @@ -1388,7 +1388,7 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > } > > fence = xe_migrate_update_pgtables(tile->migrate, > - vm, xe_vma_bo(vma), e, > + vm, xe_vma_bo(vma), q, > entries, num_entries, > syncs, num_syncs, > &bind_pt_update.base); > @@ -1663,7 +1663,7 @@ static const struct xe_migrate_pt_update_ops userptr_unbind_ops = { > * address range. > * @tile: The tile to unbind for. > * @vma: The vma to unbind. > - * @e: The engine with which to do pipelined page-table updates. > + * @q: The exec_queue with which to do pipelined page-table updates. > * @syncs: Entries to sync on before disconnecting the tree to be destroyed. > * @num_syncs: Number of @sync entries. > * > @@ -1679,7 +1679,7 @@ static const struct xe_migrate_pt_update_ops userptr_unbind_ops = { > * on success, an error pointer on error. > */ > struct dma_fence * > -__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > +__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, > struct xe_sync_entry *syncs, u32 num_syncs) > { > struct xe_vm_pgtable_update entries[XE_VM_MAX_LEVEL * 2 + 1]; > @@ -1704,7 +1704,7 @@ __xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e > > vm_dbg(&xe_vma_vm(vma)->xe->drm, > "Preparing unbind, with range [%llx...%llx) engine %p.\n", > - xe_vma_start(vma), xe_vma_end(vma) - 1, e); > + xe_vma_start(vma), xe_vma_end(vma) - 1, q); > > num_entries = xe_pt_stage_unbind(tile, vma, entries); > XE_WARN_ON(num_entries > ARRAY_SIZE(entries)); > @@ -1729,8 +1729,8 @@ __xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e > * lower level, because it needs to be more conservative. > */ > fence = xe_migrate_update_pgtables(tile->migrate, > - vm, NULL, e ? e : > - vm->eng[tile->id], > + vm, NULL, q ? q : > + vm->q[tile->id], > entries, num_entries, > syncs, num_syncs, > &unbind_pt_update.base); > diff --git a/drivers/gpu/drm/xe/xe_pt.h b/drivers/gpu/drm/xe/xe_pt.h > index bbb00d6461ff..01be7ab08f87 100644 > --- a/drivers/gpu/drm/xe/xe_pt.h > +++ b/drivers/gpu/drm/xe/xe_pt.h > @@ -12,7 +12,7 @@ > struct dma_fence; > struct xe_bo; > struct xe_device; > -struct xe_engine; > +struct xe_exec_queue; > struct xe_sync_entry; > struct xe_tile; > struct xe_vm; > @@ -35,12 +35,12 @@ void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm, > void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred); > > struct dma_fence * > -__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > +__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, > struct xe_sync_entry *syncs, u32 num_syncs, > bool rebind); > > struct dma_fence * > -__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > +__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, > struct xe_sync_entry *syncs, u32 num_syncs); > > bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma); > diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c > index 6ba7baf7c777..7ea235c71385 100644 > --- a/drivers/gpu/drm/xe/xe_query.c > +++ b/drivers/gpu/drm/xe/xe_query.c > @@ -12,7 +12,7 @@ > > #include "xe_bo.h" > #include "xe_device.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_ggtt.h" > #include "xe_gt.h" > #include "xe_guc_hwconfig.h" > @@ -203,7 +203,7 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query) > config->info[XE_QUERY_CONFIG_MEM_REGION_COUNT] = > hweight_long(xe->info.mem_region_mask); > config->info[XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY] = > - xe_engine_device_get_max_priority(xe); > + xe_exec_queue_device_get_max_priority(xe); > > if (copy_to_user(query_ptr, config, size)) { > kfree(config); > diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c > index c9ef44e63772..4a474ab04f96 100644 > --- a/drivers/gpu/drm/xe/xe_ring_ops.c > +++ b/drivers/gpu/drm/xe/xe_ring_ops.c > @@ -10,7 +10,7 @@ > #include "regs/xe_gt_regs.h" > #include "regs/xe_lrc_layout.h" > #include "regs/xe_regs.h" > -#include "xe_engine_types.h" > +#include "xe_exec_queue_types.h" > #include "xe_gt.h" > #include "xe_lrc.h" > #include "xe_macros.h" > @@ -156,7 +156,7 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value, > > static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i) > { > - struct xe_gt *gt = job->engine->gt; > + struct xe_gt *gt = job->q->gt; > bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); > u32 flags; > > @@ -172,7 +172,7 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i) > > if (lacks_render) > flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > - else if (job->engine->class == XE_ENGINE_CLASS_COMPUTE) > + else if (job->q->class == XE_ENGINE_CLASS_COMPUTE) > flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > dw[i++] = GFX_OP_PIPE_CONTROL(6) | PIPE_CONTROL0_HDC_PIPELINE_FLUSH; > @@ -202,7 +202,7 @@ static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw, > > static u32 get_ppgtt_flag(struct xe_sched_job *job) > { > - return !(job->engine->flags & ENGINE_FLAG_WA) ? BIT(8) : 0; > + return !(job->q->flags & EXEC_QUEUE_FLAG_WA) ? BIT(8) : 0; > } > > static void __emit_job_gen12_copy(struct xe_sched_job *job, struct xe_lrc *lrc, > @@ -210,7 +210,7 @@ static void __emit_job_gen12_copy(struct xe_sched_job *job, struct xe_lrc *lrc, > { > u32 dw[MAX_JOB_SIZE_DW], i = 0; > u32 ppgtt_flag = get_ppgtt_flag(job); > - struct xe_vm *vm = job->engine->vm; > + struct xe_vm *vm = job->q->vm; > > if (vm->batch_invalidate_tlb) { > dw[i++] = preparser_disable(true); > @@ -255,10 +255,10 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc, > { > u32 dw[MAX_JOB_SIZE_DW], i = 0; > u32 ppgtt_flag = get_ppgtt_flag(job); > - struct xe_gt *gt = job->engine->gt; > + struct xe_gt *gt = job->q->gt; > struct xe_device *xe = gt_to_xe(gt); > - bool decode = job->engine->class == XE_ENGINE_CLASS_VIDEO_DECODE; > - struct xe_vm *vm = job->engine->vm; > + bool decode = job->q->class == XE_ENGINE_CLASS_VIDEO_DECODE; > + struct xe_vm *vm = job->q->vm; > > dw[i++] = preparser_disable(true); > > @@ -302,16 +302,16 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job, > { > u32 dw[MAX_JOB_SIZE_DW], i = 0; > u32 ppgtt_flag = get_ppgtt_flag(job); > - struct xe_gt *gt = job->engine->gt; > + struct xe_gt *gt = job->q->gt; > struct xe_device *xe = gt_to_xe(gt); > bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); > - struct xe_vm *vm = job->engine->vm; > + struct xe_vm *vm = job->q->vm; > u32 mask_flags = 0; > > dw[i++] = preparser_disable(true); > if (lacks_render) > mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS; > - else if (job->engine->class == XE_ENGINE_CLASS_COMPUTE) > + else if (job->q->class == XE_ENGINE_CLASS_COMPUTE) > mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS; > > /* See __xe_pt_bind_vma() for a discussion on TLB invalidations. */ > @@ -378,14 +378,14 @@ static void emit_job_gen12_copy(struct xe_sched_job *job) > { > int i; > > - if (xe_sched_job_is_migration(job->engine)) { > - emit_migration_job_gen12(job, job->engine->lrc, > + if (xe_sched_job_is_migration(job->q)) { > + emit_migration_job_gen12(job, job->q->lrc, > xe_sched_job_seqno(job)); > return; > } > > - for (i = 0; i < job->engine->width; ++i) > - __emit_job_gen12_copy(job, job->engine->lrc + i, > + for (i = 0; i < job->q->width; ++i) > + __emit_job_gen12_copy(job, job->q->lrc + i, > job->batch_addr[i], > xe_sched_job_seqno(job)); > } > @@ -395,8 +395,8 @@ static void emit_job_gen12_video(struct xe_sched_job *job) > int i; > > /* FIXME: Not doing parallel handshake for now */ > - for (i = 0; i < job->engine->width; ++i) > - __emit_job_gen12_video(job, job->engine->lrc + i, > + for (i = 0; i < job->q->width; ++i) > + __emit_job_gen12_video(job, job->q->lrc + i, > job->batch_addr[i], > xe_sched_job_seqno(job)); > } > @@ -405,8 +405,8 @@ static void emit_job_gen12_render_compute(struct xe_sched_job *job) > { > int i; > > - for (i = 0; i < job->engine->width; ++i) > - __emit_job_gen12_render_compute(job, job->engine->lrc + i, > + for (i = 0; i < job->q->width; ++i) > + __emit_job_gen12_render_compute(job, job->q->lrc + i, > job->batch_addr[i], > xe_sched_job_seqno(job)); > } > diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c > index b5bf14b828f9..753aab0cc6f4 100644 > --- a/drivers/gpu/drm/xe/xe_sched_job.c > +++ b/drivers/gpu/drm/xe/xe_sched_job.c > @@ -9,7 +9,7 @@ > #include <linux/slab.h> > > #include "xe_device.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_gt.h" > #include "xe_hw_engine_types.h" > #include "xe_hw_fence.h" > @@ -57,58 +57,58 @@ static struct xe_sched_job *job_alloc(bool parallel) > xe_sched_job_slab, GFP_KERNEL); > } > > -bool xe_sched_job_is_migration(struct xe_engine *e) > +bool xe_sched_job_is_migration(struct xe_exec_queue *q) > { > - return e->vm && (e->vm->flags & XE_VM_FLAG_MIGRATION) && > - !(e->flags & ENGINE_FLAG_WA); > + return q->vm && (q->vm->flags & XE_VM_FLAG_MIGRATION) && > + !(q->flags & EXEC_QUEUE_FLAG_WA); > } > > static void job_free(struct xe_sched_job *job) > { > - struct xe_engine *e = job->engine; > - bool is_migration = xe_sched_job_is_migration(e); > + struct xe_exec_queue *q = job->q; > + bool is_migration = xe_sched_job_is_migration(q); > > - kmem_cache_free(xe_engine_is_parallel(job->engine) || is_migration ? > + kmem_cache_free(xe_exec_queue_is_parallel(job->q) || is_migration ? > xe_sched_job_parallel_slab : xe_sched_job_slab, job); > } > > static struct xe_device *job_to_xe(struct xe_sched_job *job) > { > - return gt_to_xe(job->engine->gt); > + return gt_to_xe(job->q->gt); > } > > -struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > +struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q, > u64 *batch_addr) > { > struct xe_sched_job *job; > struct dma_fence **fences; > - bool is_migration = xe_sched_job_is_migration(e); > + bool is_migration = xe_sched_job_is_migration(q); > int err; > int i, j; > u32 width; > > /* Migration and kernel engines have their own locking */ > - if (!(e->flags & (ENGINE_FLAG_KERNEL | ENGINE_FLAG_VM | > - ENGINE_FLAG_WA))) { > - lockdep_assert_held(&e->vm->lock); > - if (!xe_vm_no_dma_fences(e->vm)) > - xe_vm_assert_held(e->vm); > + if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM | > + EXEC_QUEUE_FLAG_WA))) { > + lockdep_assert_held(&q->vm->lock); > + if (!xe_vm_no_dma_fences(q->vm)) > + xe_vm_assert_held(q->vm); > } > > - job = job_alloc(xe_engine_is_parallel(e) || is_migration); > + job = job_alloc(xe_exec_queue_is_parallel(q) || is_migration); > if (!job) > return ERR_PTR(-ENOMEM); > > - job->engine = e; > + job->q = q; > kref_init(&job->refcount); > - xe_engine_get(job->engine); > + xe_exec_queue_get(job->q); > > - err = drm_sched_job_init(&job->drm, e->entity, NULL); > + err = drm_sched_job_init(&job->drm, q->entity, NULL); > if (err) > goto err_free; > > - if (!xe_engine_is_parallel(e)) { > - job->fence = xe_lrc_create_seqno_fence(e->lrc); > + if (!xe_exec_queue_is_parallel(q)) { > + job->fence = xe_lrc_create_seqno_fence(q->lrc); > if (IS_ERR(job->fence)) { > err = PTR_ERR(job->fence); > goto err_sched_job; > @@ -116,38 +116,38 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > } else { > struct dma_fence_array *cf; > > - fences = kmalloc_array(e->width, sizeof(*fences), GFP_KERNEL); > + fences = kmalloc_array(q->width, sizeof(*fences), GFP_KERNEL); > if (!fences) { > err = -ENOMEM; > goto err_sched_job; > } > > - for (j = 0; j < e->width; ++j) { > - fences[j] = xe_lrc_create_seqno_fence(e->lrc + j); > + for (j = 0; j < q->width; ++j) { > + fences[j] = xe_lrc_create_seqno_fence(q->lrc + j); > if (IS_ERR(fences[j])) { > err = PTR_ERR(fences[j]); > goto err_fences; > } > } > > - cf = dma_fence_array_create(e->width, fences, > - e->parallel.composite_fence_ctx, > - e->parallel.composite_fence_seqno++, > + cf = dma_fence_array_create(q->width, fences, > + q->parallel.composite_fence_ctx, > + q->parallel.composite_fence_seqno++, > false); > if (!cf) { > - --e->parallel.composite_fence_seqno; > + --q->parallel.composite_fence_seqno; > err = -ENOMEM; > goto err_fences; > } > > /* Sanity check */ > - for (j = 0; j < e->width; ++j) > + for (j = 0; j < q->width; ++j) > XE_WARN_ON(cf->base.seqno != fences[j]->seqno); > > job->fence = &cf->base; > } > > - width = e->width; > + width = q->width; > if (is_migration) > width = 2; > > @@ -155,7 +155,7 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > job->batch_addr[i] = batch_addr[i]; > > /* All other jobs require a VM to be open which has a ref */ > - if (unlikely(e->flags & ENGINE_FLAG_KERNEL)) > + if (unlikely(q->flags & EXEC_QUEUE_FLAG_KERNEL)) > xe_device_mem_access_get(job_to_xe(job)); > xe_device_assert_mem_access(job_to_xe(job)); > > @@ -164,14 +164,14 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > > err_fences: > for (j = j - 1; j >= 0; --j) { > - --e->lrc[j].fence_ctx.next_seqno; > + --q->lrc[j].fence_ctx.next_seqno; > dma_fence_put(fences[j]); > } > kfree(fences); > err_sched_job: > drm_sched_job_cleanup(&job->drm); > err_free: > - xe_engine_put(e); > + xe_exec_queue_put(q); > job_free(job); > return ERR_PTR(err); > } > @@ -188,9 +188,9 @@ void xe_sched_job_destroy(struct kref *ref) > struct xe_sched_job *job = > container_of(ref, struct xe_sched_job, refcount); > > - if (unlikely(job->engine->flags & ENGINE_FLAG_KERNEL)) > + if (unlikely(job->q->flags & EXEC_QUEUE_FLAG_KERNEL)) > xe_device_mem_access_put(job_to_xe(job)); > - xe_engine_put(job->engine); > + xe_exec_queue_put(job->q); > dma_fence_put(job->fence); > drm_sched_job_cleanup(&job->drm); > job_free(job); > @@ -222,12 +222,12 @@ void xe_sched_job_set_error(struct xe_sched_job *job, int error) > trace_xe_sched_job_set_error(job); > > dma_fence_enable_sw_signaling(job->fence); > - xe_hw_fence_irq_run(job->engine->fence_irq); > + xe_hw_fence_irq_run(job->q->fence_irq); > } > > bool xe_sched_job_started(struct xe_sched_job *job) > { > - struct xe_lrc *lrc = job->engine->lrc; > + struct xe_lrc *lrc = job->q->lrc; > > return !__dma_fence_is_later(xe_sched_job_seqno(job), > xe_lrc_start_seqno(lrc), > @@ -236,7 +236,7 @@ bool xe_sched_job_started(struct xe_sched_job *job) > > bool xe_sched_job_completed(struct xe_sched_job *job) > { > - struct xe_lrc *lrc = job->engine->lrc; > + struct xe_lrc *lrc = job->q->lrc; > > /* > * Can safely check just LRC[0] seqno as that is last seqno written when > diff --git a/drivers/gpu/drm/xe/xe_sched_job.h b/drivers/gpu/drm/xe/xe_sched_job.h > index 5315ad8656c2..6ca1d426c036 100644 > --- a/drivers/gpu/drm/xe/xe_sched_job.h > +++ b/drivers/gpu/drm/xe/xe_sched_job.h > @@ -14,7 +14,7 @@ > int xe_sched_job_module_init(void); > void xe_sched_job_module_exit(void); > > -struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > +struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q, > u64 *batch_addr); > void xe_sched_job_destroy(struct kref *ref); > > @@ -71,6 +71,6 @@ xe_sched_job_add_migrate_flush(struct xe_sched_job *job, u32 flags) > job->migrate_flush_flags = flags; > } > > -bool xe_sched_job_is_migration(struct xe_engine *e); > +bool xe_sched_job_is_migration(struct xe_exec_queue *q); > > #endif > diff --git a/drivers/gpu/drm/xe/xe_sched_job_types.h b/drivers/gpu/drm/xe/xe_sched_job_types.h > index 5534bfacaa16..08db0db7814b 100644 > --- a/drivers/gpu/drm/xe/xe_sched_job_types.h > +++ b/drivers/gpu/drm/xe/xe_sched_job_types.h > @@ -10,7 +10,7 @@ > > #include <drm/gpu_scheduler.h> > > -struct xe_engine; > +struct xe_exec_queue; > > /** > * struct xe_sched_job - XE schedule job (batch buffer tracking) > @@ -18,8 +18,8 @@ struct xe_engine; > struct xe_sched_job { > /** @drm: base DRM scheduler job */ > struct drm_sched_job drm; > - /** @engine: XE submission engine */ > - struct xe_engine *engine; > + /** @exec_queue: Exec queue */ > + struct xe_exec_queue *q; > /** @refcount: ref count of this job */ > struct kref refcount; > /** > diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h > index 463152528281..e32f1cad51d9 100644 > --- a/drivers/gpu/drm/xe/xe_trace.h > +++ b/drivers/gpu/drm/xe/xe_trace.h > @@ -13,10 +13,10 @@ > #include <linux/types.h> > > #include "xe_bo_types.h" > -#include "xe_engine_types.h" > +#include "xe_exec_queue_types.h" > #include "xe_gt_tlb_invalidation_types.h" > #include "xe_gt_types.h" > -#include "xe_guc_engine_types.h" > +#include "xe_guc_exec_queue_types.h" > #include "xe_sched_job.h" > #include "xe_vm.h" > > @@ -104,9 +104,9 @@ DEFINE_EVENT(xe_bo, xe_bo_move, > TP_ARGS(bo) > ); > > -DECLARE_EVENT_CLASS(xe_engine, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e), > +DECLARE_EVENT_CLASS(xe_exec_queue, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q), > > TP_STRUCT__entry( > __field(enum xe_engine_class, class) > @@ -119,13 +119,13 @@ DECLARE_EVENT_CLASS(xe_engine, > ), > > TP_fast_assign( > - __entry->class = e->class; > - __entry->logical_mask = e->logical_mask; > - __entry->gt_id = e->gt->info.id; > - __entry->width = e->width; > - __entry->guc_id = e->guc->id; > - __entry->guc_state = atomic_read(&e->guc->state); > - __entry->flags = e->flags; > + __entry->class = q->class; > + __entry->logical_mask = q->logical_mask; > + __entry->gt_id = q->gt->info.id; > + __entry->width = q->width; > + __entry->guc_id = q->guc->id; > + __entry->guc_state = atomic_read(&q->guc->state); > + __entry->flags = q->flags; > ), > > TP_printk("%d:0x%x, gt=%d, width=%d, guc_id=%d, guc_state=0x%x, flags=0x%x", > @@ -134,94 +134,94 @@ DECLARE_EVENT_CLASS(xe_engine, > __entry->guc_state, __entry->flags) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_create, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_create, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_supress_resume, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_supress_resume, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_submit, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_submit, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_scheduling_enable, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_enable, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_scheduling_disable, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_disable, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_scheduling_done, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_done, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_register, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_register, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_deregister, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_deregister, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_deregister_done, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_deregister_done, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_close, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_close, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_kill, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_kill, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_cleanup_entity, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_cleanup_entity, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_destroy, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_destroy, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_reset, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_reset, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_memory_cat_error, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_memory_cat_error, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_stop, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_stop, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_resubmit, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_resubmit, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > -DEFINE_EVENT(xe_engine, xe_engine_lr_cleanup, > - TP_PROTO(struct xe_engine *e), > - TP_ARGS(e) > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_lr_cleanup, > + TP_PROTO(struct xe_exec_queue *q), > + TP_ARGS(q) > ); > > DECLARE_EVENT_CLASS(xe_sched_job, > @@ -240,10 +240,10 @@ DECLARE_EVENT_CLASS(xe_sched_job, > > TP_fast_assign( > __entry->seqno = xe_sched_job_seqno(job); > - __entry->guc_id = job->engine->guc->id; > + __entry->guc_id = job->q->guc->id; > __entry->guc_state = > - atomic_read(&job->engine->guc->state); > - __entry->flags = job->engine->flags; > + atomic_read(&job->q->guc->state); > + __entry->flags = job->q->flags; > __entry->error = job->fence->error; > __entry->fence = (unsigned long)job->fence; > __entry->batch_addr = (u64)job->batch_addr[0]; > @@ -302,7 +302,7 @@ DECLARE_EVENT_CLASS(drm_sched_msg, > TP_fast_assign( > __entry->opcode = msg->opcode; > __entry->guc_id = > - ((struct xe_engine *)msg->private_data)->guc->id; > + ((struct xe_exec_queue *)msg->private_data)->guc->id; > ), > > TP_printk("guc_id=%d, opcode=%u", __entry->guc_id, > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c > index 44df7b9d801e..cb28dbc2bdbb 100644 > --- a/drivers/gpu/drm/xe/xe_vm.c > +++ b/drivers/gpu/drm/xe/xe_vm.c > @@ -18,7 +18,7 @@ > > #include "xe_bo.h" > #include "xe_device.h" > -#include "xe_engine.h" > +#include "xe_exec_queue.h" > #include "xe_gt.h" > #include "xe_gt_pagefault.h" > #include "xe_gt_tlb_invalidation.h" > @@ -165,15 +165,15 @@ int xe_vma_userptr_pin_pages(struct xe_vma *vma) > > static bool preempt_fences_waiting(struct xe_vm *vm) > { > - struct xe_engine *e; > + struct xe_exec_queue *q; > > lockdep_assert_held(&vm->lock); > xe_vm_assert_held(vm); > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > - if (!e->compute.pfence || (e->compute.pfence && > - test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, > - &e->compute.pfence->flags))) { > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > + if (!q->compute.pfence || > + (q->compute.pfence && test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, > + &q->compute.pfence->flags))) { > return true; > } > } > @@ -212,18 +212,18 @@ static int alloc_preempt_fences(struct xe_vm *vm, struct list_head *list, > > static int wait_for_existing_preempt_fences(struct xe_vm *vm) > { > - struct xe_engine *e; > + struct xe_exec_queue *q; > > xe_vm_assert_held(vm); > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > - if (e->compute.pfence) { > - long timeout = dma_fence_wait(e->compute.pfence, false); > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > + if (q->compute.pfence) { > + long timeout = dma_fence_wait(q->compute.pfence, false); > > if (timeout < 0) > return -ETIME; > - dma_fence_put(e->compute.pfence); > - e->compute.pfence = NULL; > + dma_fence_put(q->compute.pfence); > + q->compute.pfence = NULL; > } > } > > @@ -232,11 +232,11 @@ static int wait_for_existing_preempt_fences(struct xe_vm *vm) > > static bool xe_vm_is_idle(struct xe_vm *vm) > { > - struct xe_engine *e; > + struct xe_exec_queue *q; > > xe_vm_assert_held(vm); > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > - if (!xe_engine_is_idle(e)) > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > + if (!xe_exec_queue_is_idle(q)) > return false; > } > > @@ -246,25 +246,25 @@ static bool xe_vm_is_idle(struct xe_vm *vm) > static void arm_preempt_fences(struct xe_vm *vm, struct list_head *list) > { > struct list_head *link; > - struct xe_engine *e; > + struct xe_exec_queue *q; > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > struct dma_fence *fence; > > link = list->next; > XE_WARN_ON(link == list); > > fence = xe_preempt_fence_arm(to_preempt_fence_from_link(link), > - e, e->compute.context, > - ++e->compute.seqno); > - dma_fence_put(e->compute.pfence); > - e->compute.pfence = fence; > + q, q->compute.context, > + ++q->compute.seqno); > + dma_fence_put(q->compute.pfence); > + q->compute.pfence = fence; > } > } > > static int add_preempt_fences(struct xe_vm *vm, struct xe_bo *bo) > { > - struct xe_engine *e; > + struct xe_exec_queue *q; > struct ww_acquire_ctx ww; > int err; > > @@ -272,10 +272,10 @@ static int add_preempt_fences(struct xe_vm *vm, struct xe_bo *bo) > if (err) > return err; > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) > - if (e->compute.pfence) { > + list_for_each_entry(q, &vm->preempt.engines, compute.link) > + if (q->compute.pfence) { > dma_resv_add_fence(bo->ttm.base.resv, > - e->compute.pfence, > + q->compute.pfence, > DMA_RESV_USAGE_BOOKKEEP); > } > > @@ -304,22 +304,22 @@ void xe_vm_fence_all_extobjs(struct xe_vm *vm, struct dma_fence *fence, > > static void resume_and_reinstall_preempt_fences(struct xe_vm *vm) > { > - struct xe_engine *e; > + struct xe_exec_queue *q; > > lockdep_assert_held(&vm->lock); > xe_vm_assert_held(vm); > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > - e->ops->resume(e); > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > + q->ops->resume(q); > > - dma_resv_add_fence(&vm->resv, e->compute.pfence, > + dma_resv_add_fence(&vm->resv, q->compute.pfence, > DMA_RESV_USAGE_BOOKKEEP); > - xe_vm_fence_all_extobjs(vm, e->compute.pfence, > + xe_vm_fence_all_extobjs(vm, q->compute.pfence, > DMA_RESV_USAGE_BOOKKEEP); > } > } > > -int xe_vm_add_compute_engine(struct xe_vm *vm, struct xe_engine *e) > +int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q) > { > struct ttm_validate_buffer tv_onstack[XE_ONSTACK_TV]; > struct ttm_validate_buffer *tv; > @@ -337,16 +337,16 @@ int xe_vm_add_compute_engine(struct xe_vm *vm, struct xe_engine *e) > if (err) > goto out_unlock_outer; > > - pfence = xe_preempt_fence_create(e, e->compute.context, > - ++e->compute.seqno); > + pfence = xe_preempt_fence_create(q, q->compute.context, > + ++q->compute.seqno); > if (!pfence) { > err = -ENOMEM; > goto out_unlock; > } > > - list_add(&e->compute.link, &vm->preempt.engines); > + list_add(&q->compute.link, &vm->preempt.engines); > ++vm->preempt.num_engines; > - e->compute.pfence = pfence; > + q->compute.pfence = pfence; > > down_read(&vm->userptr.notifier_lock); > > @@ -518,7 +518,7 @@ void xe_vm_unlock_dma_resv(struct xe_vm *vm, > static void xe_vm_kill(struct xe_vm *vm) > { > struct ww_acquire_ctx ww; > - struct xe_engine *e; > + struct xe_exec_queue *q; > > lockdep_assert_held(&vm->lock); > > @@ -526,8 +526,8 @@ static void xe_vm_kill(struct xe_vm *vm) > vm->flags |= XE_VM_FLAG_BANNED; > trace_xe_vm_kill(vm); > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) > - e->ops->kill(e); > + list_for_each_entry(q, &vm->preempt.engines, compute.link) > + q->ops->kill(q); > xe_vm_unlock(vm, &ww); > > /* TODO: Inform user the VM is banned */ > @@ -833,7 +833,7 @@ int xe_vm_userptr_check_repin(struct xe_vm *vm) > } > > static struct dma_fence * > -xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, > +xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q, > struct xe_sync_entry *syncs, u32 num_syncs, > bool first_op, bool last_op); > > @@ -1297,21 +1297,21 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags) > for_each_tile(tile, xe, id) { > struct xe_gt *gt = tile->primary_gt; > struct xe_vm *migrate_vm; > - struct xe_engine *eng; > + struct xe_exec_queue *q; > > if (!vm->pt_root[id]) > continue; > > migrate_vm = xe_migrate_get_vm(tile->migrate); > - eng = xe_engine_create_class(xe, gt, migrate_vm, > - XE_ENGINE_CLASS_COPY, > - ENGINE_FLAG_VM); > + q = xe_exec_queue_create_class(xe, gt, migrate_vm, > + XE_ENGINE_CLASS_COPY, > + EXEC_QUEUE_FLAG_VM); > xe_vm_put(migrate_vm); > - if (IS_ERR(eng)) { > + if (IS_ERR(q)) { > xe_vm_close_and_put(vm); > - return ERR_CAST(eng); > + return ERR_CAST(q); > } > - vm->eng[id] = eng; > + vm->q[id] = q; > number_tiles++; > } > } > @@ -1422,10 +1422,10 @@ void xe_vm_close_and_put(struct xe_vm *vm) > flush_work(&vm->preempt.rebind_work); > > for_each_tile(tile, xe, id) { > - if (vm->eng[id]) { > - xe_engine_kill(vm->eng[id]); > - xe_engine_put(vm->eng[id]); > - vm->eng[id] = NULL; > + if (vm->q[id]) { > + xe_exec_queue_kill(vm->q[id]); > + xe_exec_queue_put(vm->q[id]); > + vm->q[id] = NULL; > } > } > > @@ -1576,7 +1576,7 @@ u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile) > } > > static struct dma_fence * > -xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, > +xe_vm_unbind_vma(struct xe_vma *vma, struct xe_exec_queue *q, > struct xe_sync_entry *syncs, u32 num_syncs, > bool first_op, bool last_op) > { > @@ -1603,7 +1603,7 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, > if (!(vma->tile_present & BIT(id))) > goto next; > > - fence = __xe_pt_unbind_vma(tile, vma, e, first_op ? syncs : NULL, > + fence = __xe_pt_unbind_vma(tile, vma, q, first_op ? syncs : NULL, > first_op ? num_syncs : 0); > if (IS_ERR(fence)) { > err = PTR_ERR(fence); > @@ -1614,8 +1614,8 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, > fences[cur_fence++] = fence; > > next: > - if (e && vm->pt_root[id] && !list_empty(&e->multi_gt_list)) > - e = list_next_entry(e, multi_gt_list); > + if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list)) > + q = list_next_entry(q, multi_gt_list); > } > > if (fences) { > @@ -1651,7 +1651,7 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, > } > > static struct dma_fence * > -xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, > +xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q, > struct xe_sync_entry *syncs, u32 num_syncs, > bool first_op, bool last_op) > { > @@ -1678,7 +1678,7 @@ xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, > if (!(vma->tile_mask & BIT(id))) > goto next; > > - fence = __xe_pt_bind_vma(tile, vma, e ? e : vm->eng[id], > + fence = __xe_pt_bind_vma(tile, vma, q ? q : vm->q[id], > first_op ? syncs : NULL, > first_op ? num_syncs : 0, > vma->tile_present & BIT(id)); > @@ -1691,8 +1691,8 @@ xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, > fences[cur_fence++] = fence; > > next: > - if (e && vm->pt_root[id] && !list_empty(&e->multi_gt_list)) > - e = list_next_entry(e, multi_gt_list); > + if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list)) > + q = list_next_entry(q, multi_gt_list); > } > > if (fences) { > @@ -1808,7 +1808,7 @@ int xe_vm_async_fence_wait_start(struct dma_fence *fence) > } > > static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, > - struct xe_engine *e, struct xe_sync_entry *syncs, > + struct xe_exec_queue *q, struct xe_sync_entry *syncs, > u32 num_syncs, struct async_op_fence *afence, > bool immediate, bool first_op, bool last_op) > { > @@ -1817,7 +1817,7 @@ static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, > xe_vm_assert_held(vm); > > if (immediate) { > - fence = xe_vm_bind_vma(vma, e, syncs, num_syncs, first_op, > + fence = xe_vm_bind_vma(vma, q, syncs, num_syncs, first_op, > last_op); > if (IS_ERR(fence)) > return PTR_ERR(fence); > @@ -1839,7 +1839,7 @@ static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, > return 0; > } > > -static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_engine *e, > +static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_exec_queue *q, > struct xe_bo *bo, struct xe_sync_entry *syncs, > u32 num_syncs, struct async_op_fence *afence, > bool immediate, bool first_op, bool last_op) > @@ -1855,12 +1855,12 @@ static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_engine *e, > return err; > } > > - return __xe_vm_bind(vm, vma, e, syncs, num_syncs, afence, immediate, > + return __xe_vm_bind(vm, vma, q, syncs, num_syncs, afence, immediate, > first_op, last_op); > } > > static int xe_vm_unbind(struct xe_vm *vm, struct xe_vma *vma, > - struct xe_engine *e, struct xe_sync_entry *syncs, > + struct xe_exec_queue *q, struct xe_sync_entry *syncs, > u32 num_syncs, struct async_op_fence *afence, > bool first_op, bool last_op) > { > @@ -1869,7 +1869,7 @@ static int xe_vm_unbind(struct xe_vm *vm, struct xe_vma *vma, > xe_vm_assert_held(vm); > xe_bo_assert_held(xe_vma_bo(vma)); > > - fence = xe_vm_unbind_vma(vma, e, syncs, num_syncs, first_op, last_op); > + fence = xe_vm_unbind_vma(vma, q, syncs, num_syncs, first_op, last_op); > if (IS_ERR(fence)) > return PTR_ERR(fence); > if (afence) > @@ -2096,7 +2096,7 @@ static const u32 region_to_mem_type[] = { > }; > > static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma, > - struct xe_engine *e, u32 region, > + struct xe_exec_queue *q, u32 region, > struct xe_sync_entry *syncs, u32 num_syncs, > struct async_op_fence *afence, bool first_op, > bool last_op) > @@ -2112,7 +2112,7 @@ static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma, > } > > if (vma->tile_mask != (vma->tile_present & ~vma->usm.tile_invalidated)) { > - return xe_vm_bind(vm, vma, e, xe_vma_bo(vma), syncs, num_syncs, > + return xe_vm_bind(vm, vma, q, xe_vma_bo(vma), syncs, num_syncs, > afence, true, first_op, last_op); > } else { > int i; > @@ -2410,7 +2410,7 @@ static u64 xe_vma_max_pte_size(struct xe_vma *vma) > * Parse operations list and create any resources needed for the operations > * prior to fully committing to the operations. This setup can fail. > */ > -static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_engine *e, > +static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_exec_queue *q, > struct drm_gpuva_ops **ops, int num_ops_list, > struct xe_sync_entry *syncs, u32 num_syncs, > struct list_head *ops_list, bool async) > @@ -2430,9 +2430,9 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_engine *e, > if (!fence) > return -ENOMEM; > > - seqno = e ? ++e->bind.fence_seqno : ++vm->async_ops.fence.seqno; > + seqno = q ? ++q->bind.fence_seqno : ++vm->async_ops.fence.seqno; > dma_fence_init(&fence->fence, &async_op_fence_ops, > - &vm->async_ops.lock, e ? e->bind.fence_ctx : > + &vm->async_ops.lock, q ? q->bind.fence_ctx : > vm->async_ops.fence.context, seqno); > > if (!xe_vm_no_dma_fences(vm)) { > @@ -2463,7 +2463,7 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_engine *e, > op->syncs = syncs; > } > > - op->engine = e; > + op->q = q; > > switch (op->base.op) { > case DRM_GPUVA_OP_MAP: > @@ -2673,7 +2673,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > > switch (op->base.op) { > case DRM_GPUVA_OP_MAP: > - err = xe_vm_bind(vm, vma, op->engine, xe_vma_bo(vma), > + err = xe_vm_bind(vm, vma, op->q, xe_vma_bo(vma), > op->syncs, op->num_syncs, op->fence, > op->map.immediate || !xe_vm_in_fault_mode(vm), > op->flags & XE_VMA_OP_FIRST, > @@ -2689,7 +2689,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > vm->async_ops.munmap_rebind_inflight = true; > vma->gpuva.flags |= XE_VMA_FIRST_REBIND; > } > - err = xe_vm_unbind(vm, vma, op->engine, op->syncs, > + err = xe_vm_unbind(vm, vma, op->q, op->syncs, > op->num_syncs, > !prev && !next ? op->fence : NULL, > op->flags & XE_VMA_OP_FIRST, > @@ -2702,7 +2702,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > > if (prev) { > op->remap.prev->gpuva.flags |= XE_VMA_LAST_REBIND; > - err = xe_vm_bind(vm, op->remap.prev, op->engine, > + err = xe_vm_bind(vm, op->remap.prev, op->q, > xe_vma_bo(op->remap.prev), op->syncs, > op->num_syncs, > !next ? op->fence : NULL, true, false, > @@ -2715,7 +2715,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > > if (next) { > op->remap.next->gpuva.flags |= XE_VMA_LAST_REBIND; > - err = xe_vm_bind(vm, op->remap.next, op->engine, > + err = xe_vm_bind(vm, op->remap.next, op->q, > xe_vma_bo(op->remap.next), > op->syncs, op->num_syncs, > op->fence, true, false, > @@ -2730,13 +2730,13 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > break; > } > case DRM_GPUVA_OP_UNMAP: > - err = xe_vm_unbind(vm, vma, op->engine, op->syncs, > + err = xe_vm_unbind(vm, vma, op->q, op->syncs, > op->num_syncs, op->fence, > op->flags & XE_VMA_OP_FIRST, > op->flags & XE_VMA_OP_LAST); > break; > case DRM_GPUVA_OP_PREFETCH: > - err = xe_vm_prefetch(vm, vma, op->engine, op->prefetch.region, > + err = xe_vm_prefetch(vm, vma, op->q, op->prefetch.region, > op->syncs, op->num_syncs, op->fence, > op->flags & XE_VMA_OP_FIRST, > op->flags & XE_VMA_OP_LAST); > @@ -2815,8 +2815,8 @@ static void xe_vma_op_cleanup(struct xe_vm *vm, struct xe_vma_op *op) > while (op->num_syncs--) > xe_sync_entry_cleanup(&op->syncs[op->num_syncs]); > kfree(op->syncs); > - if (op->engine) > - xe_engine_put(op->engine); > + if (op->q) > + xe_exec_queue_put(op->q); > if (op->fence) > dma_fence_put(&op->fence->fence); > } > @@ -3170,7 +3170,7 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > struct xe_bo **bos = NULL; > struct drm_gpuva_ops **ops = NULL; > struct xe_vm *vm; > - struct xe_engine *e = NULL; > + struct xe_exec_queue *q = NULL; > u32 num_syncs; > struct xe_sync_entry *syncs = NULL; > struct drm_xe_vm_bind_op *bind_ops; > @@ -3183,23 +3183,23 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > if (err) > return err; > > - if (args->engine_id) { > - e = xe_engine_lookup(xef, args->engine_id); > - if (XE_IOCTL_DBG(xe, !e)) { > + if (args->exec_queue_id) { > + q = xe_exec_queue_lookup(xef, args->exec_queue_id); > + if (XE_IOCTL_DBG(xe, !q)) { > err = -ENOENT; > goto free_objs; > } > > - if (XE_IOCTL_DBG(xe, !(e->flags & ENGINE_FLAG_VM))) { > + if (XE_IOCTL_DBG(xe, !(q->flags & EXEC_QUEUE_FLAG_VM))) { > err = -EINVAL; > - goto put_engine; > + goto put_exec_queue; > } > } > > vm = xe_vm_lookup(xef, args->vm_id); > if (XE_IOCTL_DBG(xe, !vm)) { > err = -EINVAL; > - goto put_engine; > + goto put_exec_queue; > } > > err = down_write_killable(&vm->lock); > @@ -3353,7 +3353,7 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > } > } > > - err = vm_bind_ioctl_ops_parse(vm, e, ops, args->num_binds, > + err = vm_bind_ioctl_ops_parse(vm, q, ops, args->num_binds, > syncs, num_syncs, &ops_list, async); > if (err) > goto unwind_ops; > @@ -3387,9 +3387,9 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > up_write(&vm->lock); > put_vm: > xe_vm_put(vm); > -put_engine: > - if (e) > - xe_engine_put(e); > +put_exec_queue: > + if (q) > + xe_exec_queue_put(q); > free_objs: > kfree(bos); > kfree(ops); > diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h > index 4db777d7e375..6de6e3edb24a 100644 > --- a/drivers/gpu/drm/xe/xe_vm.h > +++ b/drivers/gpu/drm/xe/xe_vm.h > @@ -18,7 +18,7 @@ struct drm_file; > struct ttm_buffer_object; > struct ttm_validate_buffer; > > -struct xe_engine; > +struct xe_exec_queue; > struct xe_file; > struct xe_sync_entry; > > @@ -167,7 +167,7 @@ static inline bool xe_vm_no_dma_fences(struct xe_vm *vm) > return xe_vm_in_compute_mode(vm) || xe_vm_in_fault_mode(vm); > } > > -int xe_vm_add_compute_engine(struct xe_vm *vm, struct xe_engine *e); > +int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q); > > int xe_vm_userptr_pin(struct xe_vm *vm); > > diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h > index 261a4b0e8570..3681a5ff588b 100644 > --- a/drivers/gpu/drm/xe/xe_vm_types.h > +++ b/drivers/gpu/drm/xe/xe_vm_types.h > @@ -142,8 +142,8 @@ struct xe_vm { > > struct kref refcount; > > - /* engine used for (un)binding vma's */ > - struct xe_engine *eng[XE_MAX_TILES_PER_DEVICE]; > + /* exec queue used for (un)binding vma's */ > + struct xe_exec_queue *q[XE_MAX_TILES_PER_DEVICE]; > > /** Protects @rebind_list and the page-table structures */ > struct dma_resv resv; > @@ -394,7 +394,7 @@ struct xe_vma_op { > */ > struct drm_gpuva_ops *ops; > /** @engine: engine for this operation */ > - struct xe_engine *engine; > + struct xe_exec_queue *q; > /** > * @syncs: syncs for this operation, only used on first and last > * operation > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h > index 3d09e9e9267b..86f16d50e9cc 100644 > --- a/include/uapi/drm/xe_drm.h > +++ b/include/uapi/drm/xe_drm.h > @@ -103,14 +103,14 @@ struct xe_user_extension { > #define DRM_XE_VM_CREATE 0x03 > #define DRM_XE_VM_DESTROY 0x04 > #define DRM_XE_VM_BIND 0x05 > -#define DRM_XE_ENGINE_CREATE 0x06 > -#define DRM_XE_ENGINE_DESTROY 0x07 > +#define DRM_XE_EXEC_QUEUE_CREATE 0x06 > +#define DRM_XE_EXEC_QUEUE_DESTROY 0x07 > #define DRM_XE_EXEC 0x08 > #define DRM_XE_MMIO 0x09 > -#define DRM_XE_ENGINE_SET_PROPERTY 0x0a > +#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0a > #define DRM_XE_WAIT_USER_FENCE 0x0b > #define DRM_XE_VM_MADVISE 0x0c > -#define DRM_XE_ENGINE_GET_PROPERTY 0x0d > +#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x0d > > /* Must be kept compact -- no holes */ > #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) > @@ -119,12 +119,12 @@ struct xe_user_extension { > #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) > #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) > #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) > -#define DRM_IOCTL_XE_ENGINE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_CREATE, struct drm_xe_engine_create) > -#define DRM_IOCTL_XE_ENGINE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_GET_PROPERTY, struct drm_xe_engine_get_property) > -#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy) > +#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) > +#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) > +#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) > #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) > #define DRM_IOCTL_XE_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_MMIO, struct drm_xe_mmio) > -#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property) > +#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property) > #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) > #define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise) > > @@ -649,11 +649,11 @@ struct drm_xe_vm_bind { > __u32 vm_id; > > /** > - * @engine_id: engine_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND > - * and engine must have same vm_id. If zero, the default VM bind engine > + * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND > + * and exec queue must have same vm_id. If zero, the default VM bind engine > * is used. > */ > - __u32 engine_id; > + __u32 exec_queue_id; > > /** @num_binds: number of binds in this IOCTL */ > __u32 num_binds; > @@ -685,8 +685,8 @@ struct drm_xe_vm_bind { > __u64 reserved[2]; > }; > > -/** struct drm_xe_ext_engine_set_property - engine set property extension */ > -struct drm_xe_ext_engine_set_property { > +/** struct drm_xe_ext_exec_queue_set_property - exec queue set property extension */ > +struct drm_xe_ext_exec_queue_set_property { > /** @base: base user extension */ > struct xe_user_extension base; > > @@ -701,32 +701,32 @@ struct drm_xe_ext_engine_set_property { > }; > > /** > - * struct drm_xe_engine_set_property - engine set property > + * struct drm_xe_exec_queue_set_property - exec queue set property > * > - * Same namespace for extensions as drm_xe_engine_create > + * Same namespace for extensions as drm_xe_exec_queue_create > */ > -struct drm_xe_engine_set_property { > +struct drm_xe_exec_queue_set_property { > /** @extensions: Pointer to the first extension struct, if any */ > __u64 extensions; > > - /** @engine_id: Engine ID */ > - __u32 engine_id; > + /** @exec_queue_id: Exec queue ID */ > + __u32 exec_queue_id; > > -#define XE_ENGINE_SET_PROPERTY_PRIORITY 0 > -#define XE_ENGINE_SET_PROPERTY_TIMESLICE 1 > -#define XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT 2 > +#define XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 > +#define XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 > +#define XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2 > /* > * Long running or ULLS engine mode. DMA fences not allowed in this > * mode. Must match the value of DRM_XE_VM_CREATE_COMPUTE_MODE, serves > * as a sanity check the UMD knows what it is doing. Can only be set at > * engine create time. > */ > -#define XE_ENGINE_SET_PROPERTY_COMPUTE_MODE 3 > -#define XE_ENGINE_SET_PROPERTY_PERSISTENCE 4 > -#define XE_ENGINE_SET_PROPERTY_JOB_TIMEOUT 5 > -#define XE_ENGINE_SET_PROPERTY_ACC_TRIGGER 6 > -#define XE_ENGINE_SET_PROPERTY_ACC_NOTIFY 7 > -#define XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY 8 > +#define XE_EXEC_QUEUE_SET_PROPERTY_COMPUTE_MODE 3 > +#define XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 4 > +#define XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 5 > +#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 6 > +#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 7 > +#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 8 > /** @property: property to set */ > __u32 property; > > @@ -755,25 +755,25 @@ struct drm_xe_engine_class_instance { > __u16 gt_id; > }; > > -struct drm_xe_engine_create { > -#define XE_ENGINE_EXTENSION_SET_PROPERTY 0 > +struct drm_xe_exec_queue_create { > +#define XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 > /** @extensions: Pointer to the first extension struct, if any */ > __u64 extensions; > > - /** @width: submission width (number BB per exec) for this engine */ > + /** @width: submission width (number BB per exec) for this exec queue */ > __u16 width; > > - /** @num_placements: number of valid placements for this engine */ > + /** @num_placements: number of valid placements for this exec queue */ > __u16 num_placements; > > - /** @vm_id: VM to use for this engine */ > + /** @vm_id: VM to use for this exec queue */ > __u32 vm_id; > > /** @flags: MBZ */ > __u32 flags; > > - /** @engine_id: Returned engine ID */ > - __u32 engine_id; > + /** @exec_queue_id: Returned exec queue ID */ > + __u32 exec_queue_id; > > /** > * @instances: user pointer to a 2-d array of struct > @@ -788,14 +788,14 @@ struct drm_xe_engine_create { > __u64 reserved[2]; > }; > > -struct drm_xe_engine_get_property { > +struct drm_xe_exec_queue_get_property { > /** @extensions: Pointer to the first extension struct, if any */ > __u64 extensions; > > - /** @engine_id: Engine ID */ > - __u32 engine_id; > + /** @exec_queue_id: Exec queue ID */ > + __u32 exec_queue_id; > > -#define XE_ENGINE_GET_PROPERTY_BAN 0 > +#define XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 > /** @property: property to get */ > __u32 property; > > @@ -806,9 +806,9 @@ struct drm_xe_engine_get_property { > __u64 reserved[2]; > }; > > -struct drm_xe_engine_destroy { > - /** @engine_id: Engine ID */ > - __u32 engine_id; > +struct drm_xe_exec_queue_destroy { > + /** @exec_queue_id: Exec queue ID */ > + __u32 exec_queue_id; > > /** @pad: MBZ */ > __u32 pad; > @@ -855,8 +855,8 @@ struct drm_xe_exec { > /** @extensions: Pointer to the first extension struct, if any */ > __u64 extensions; > > - /** @engine_id: Engine ID for the batch buffer */ > - __u32 engine_id; > + /** @exec_queue_id: Exec queue ID for the batch buffer */ > + __u32 exec_queue_id; > > /** @num_syncs: Amount of struct drm_xe_sync in array. */ > __u32 num_syncs; > -- > 2.34.1 > ^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-xe] [RFC PATCH 1/1] drm/xe: Rename engine to exec_queue 2023-07-31 18:03 ` Rodrigo Vivi @ 2023-07-31 19:19 ` Francois Dugast 0 siblings, 0 replies; 9+ messages in thread From: Francois Dugast @ 2023-07-31 19:19 UTC (permalink / raw) To: Rodrigo Vivi; +Cc: intel-xe On Mon, Jul 31, 2023 at 02:03:43PM -0400, Rodrigo Vivi wrote: > On Mon, Jul 31, 2023 at 04:08:49PM +0000, Francois Dugast wrote: > > Engine was inappropriately used to refer to execution queues and > > exec_queue is much better than engine here indeed. Thanks for the fast feedback. > > > it also created some confusion with hardware engines. Where it applies > > the exec_queue variable name is changed to q and comments are also > > updated. > > my only bikeshed on this is on the 'q'... could we make that 'eq' > instead? That would be fine with me but I based this choice on the discussion in the Gitlab issue, where it seemed we had a consensus on going with 'q'. > > it will be very hard to run a detailed review, but based on what > I saw so far everything looks correct. So, we should probably > move fast with this after passing CI. Anyone else conflicting > with this would have to rebase and resubmit. > > Acked-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Great, I would like at least another pair of eyes to take a look and also I already found some minor fixes so I will have to sent a new version anyway. > > > > > Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/162 > > Signed-off-by: Francois Dugast <francois.dugast@intel.com> > > --- > > drivers/gpu/drm/xe/Makefile | 2 +- > > drivers/gpu/drm/xe/tests/xe_migrate.c | 18 +- > > drivers/gpu/drm/xe/xe_bb.c | 26 +- > > drivers/gpu/drm/xe/xe_bb.h | 8 +- > > drivers/gpu/drm/xe/xe_devcoredump.c | 40 +- > > drivers/gpu/drm/xe/xe_devcoredump.h | 6 +- > > drivers/gpu/drm/xe/xe_devcoredump_types.h | 2 +- > > drivers/gpu/drm/xe/xe_device.c | 62 +- > > drivers/gpu/drm/xe/xe_device.h | 8 +- > > drivers/gpu/drm/xe/xe_device_types.h | 2 +- > > drivers/gpu/drm/xe/xe_engine.c | 850 ------------- > > drivers/gpu/drm/xe/xe_engine.h | 63 - > > drivers/gpu/drm/xe/xe_exec.c | 62 +- > > drivers/gpu/drm/xe/xe_exec_queue.c | 850 +++++++++++++ > > drivers/gpu/drm/xe/xe_exec_queue.h | 63 + > > ...e_engine_types.h => xe_exec_queue_types.h} | 110 +- > > drivers/gpu/drm/xe/xe_execlist.c | 126 +- > > drivers/gpu/drm/xe/xe_execlist_types.h | 8 +- > > drivers/gpu/drm/xe/xe_gt.c | 72 +- > > drivers/gpu/drm/xe/xe_gt_types.h | 6 +- > > drivers/gpu/drm/xe/xe_guc_ads.c | 2 +- > > drivers/gpu/drm/xe/xe_guc_ct.c | 10 +- > > ...gine_types.h => xe_guc_exec_queue_types.h} | 10 +- > > drivers/gpu/drm/xe/xe_guc_fwif.h | 6 +- > > drivers/gpu/drm/xe/xe_guc_submit.c | 1074 ++++++++--------- > > drivers/gpu/drm/xe/xe_guc_submit.h | 20 +- > > drivers/gpu/drm/xe/xe_guc_submit_types.h | 20 +- > > drivers/gpu/drm/xe/xe_guc_types.h | 4 +- > > drivers/gpu/drm/xe/xe_lrc.c | 10 +- > > drivers/gpu/drm/xe/xe_lrc.h | 4 +- > > drivers/gpu/drm/xe/xe_migrate.c | 62 +- > > drivers/gpu/drm/xe/xe_migrate.h | 6 +- > > drivers/gpu/drm/xe/xe_mocs.c | 2 +- > > drivers/gpu/drm/xe/xe_mocs.h | 2 +- > > drivers/gpu/drm/xe/xe_preempt_fence.c | 32 +- > > drivers/gpu/drm/xe/xe_preempt_fence.h | 4 +- > > drivers/gpu/drm/xe/xe_preempt_fence_types.h | 5 +- > > drivers/gpu/drm/xe/xe_pt.c | 18 +- > > drivers/gpu/drm/xe/xe_pt.h | 6 +- > > drivers/gpu/drm/xe/xe_query.c | 4 +- > > drivers/gpu/drm/xe/xe_ring_ops.c | 38 +- > > drivers/gpu/drm/xe/xe_sched_job.c | 76 +- > > drivers/gpu/drm/xe/xe_sched_job.h | 4 +- > > drivers/gpu/drm/xe/xe_sched_job_types.h | 6 +- > > drivers/gpu/drm/xe/xe_trace.h | 140 +-- > > drivers/gpu/drm/xe/xe_vm.c | 178 +-- > > drivers/gpu/drm/xe/xe_vm.h | 4 +- > > drivers/gpu/drm/xe/xe_vm_types.h | 6 +- > > include/uapi/drm/xe_drm.h | 86 +- > > 49 files changed, 2111 insertions(+), 2112 deletions(-) > > delete mode 100644 drivers/gpu/drm/xe/xe_engine.c > > delete mode 100644 drivers/gpu/drm/xe/xe_engine.h > > create mode 100644 drivers/gpu/drm/xe/xe_exec_queue.c > > create mode 100644 drivers/gpu/drm/xe/xe_exec_queue.h > > rename drivers/gpu/drm/xe/{xe_engine_types.h => xe_exec_queue_types.h} (52%) > > rename drivers/gpu/drm/xe/{xe_guc_engine_types.h => xe_guc_exec_queue_types.h} (88%) > > > > diff --git a/drivers/gpu/drm/xe/Makefile b/drivers/gpu/drm/xe/Makefile > > index 4ea9e3150c20..e79624ab2cb3 100644 > > --- a/drivers/gpu/drm/xe/Makefile > > +++ b/drivers/gpu/drm/xe/Makefile > > @@ -51,9 +51,9 @@ xe-y += xe_bb.o \ > > xe_device.o \ > > xe_device_sysfs.o \ > > xe_dma_buf.o \ > > - xe_engine.o \ > > xe_exec.o \ > > xe_execlist.o \ > > + xe_exec_queue.o \ > > xe_force_wake.o \ > > xe_ggtt.o \ > > xe_gt.o \ > > diff --git a/drivers/gpu/drm/xe/tests/xe_migrate.c b/drivers/gpu/drm/xe/tests/xe_migrate.c > > index 9e9b228fe315..5c8d5e78d9bc 100644 > > --- a/drivers/gpu/drm/xe/tests/xe_migrate.c > > +++ b/drivers/gpu/drm/xe/tests/xe_migrate.c > > @@ -38,7 +38,7 @@ static int run_sanity_job(struct xe_migrate *m, struct xe_device *xe, > > struct kunit *test) > > { > > u64 batch_base = xe_migrate_batch_base(m, xe->info.supports_usm); > > - struct xe_sched_job *job = xe_bb_create_migration_job(m->eng, bb, > > + struct xe_sched_job *job = xe_bb_create_migration_job(m->q, bb, > > batch_base, > > second_idx); > > struct dma_fence *fence; > > @@ -215,7 +215,7 @@ static void test_pt_update(struct xe_migrate *m, struct xe_bo *pt, > > xe_map_memset(xe, &pt->vmap, 0, (u8)expected, pt->size); > > > > then = ktime_get(); > > - fence = xe_migrate_update_pgtables(m, NULL, NULL, m->eng, &update, 1, > > + fence = xe_migrate_update_pgtables(m, NULL, NULL, m->q, &update, 1, > > NULL, 0, &pt_update); > > now = ktime_get(); > > if (sanity_fence_failed(xe, fence, "Migration pagetable update", test)) > > @@ -257,7 +257,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) > > return; > > } > > > > - big = xe_bo_create_pin_map(xe, tile, m->eng->vm, SZ_4M, > > + big = xe_bo_create_pin_map(xe, tile, m->q->vm, SZ_4M, > > ttm_bo_type_kernel, > > XE_BO_CREATE_VRAM_IF_DGFX(tile) | > > XE_BO_CREATE_PINNED_BIT); > > @@ -266,7 +266,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) > > goto vunmap; > > } > > > > - pt = xe_bo_create_pin_map(xe, tile, m->eng->vm, XE_PAGE_SIZE, > > + pt = xe_bo_create_pin_map(xe, tile, m->q->vm, XE_PAGE_SIZE, > > ttm_bo_type_kernel, > > XE_BO_CREATE_VRAM_IF_DGFX(tile) | > > XE_BO_CREATE_PINNED_BIT); > > @@ -276,7 +276,7 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) > > goto free_big; > > } > > > > - tiny = xe_bo_create_pin_map(xe, tile, m->eng->vm, > > + tiny = xe_bo_create_pin_map(xe, tile, m->q->vm, > > 2 * SZ_4K, > > ttm_bo_type_kernel, > > XE_BO_CREATE_VRAM_IF_DGFX(tile) | > > @@ -295,14 +295,14 @@ static void xe_migrate_sanity_test(struct xe_migrate *m, struct kunit *test) > > } > > > > kunit_info(test, "Starting tests, top level PT addr: %lx, special pagetable base addr: %lx\n", > > - (unsigned long)xe_bo_main_addr(m->eng->vm->pt_root[id]->bo, XE_PAGE_SIZE), > > + (unsigned long)xe_bo_main_addr(m->q->vm->pt_root[id]->bo, XE_PAGE_SIZE), > > (unsigned long)xe_bo_main_addr(m->pt_bo, XE_PAGE_SIZE)); > > > > /* First part of the test, are we updating our pagetable bo with a new entry? */ > > xe_map_wr(xe, &bo->vmap, XE_PAGE_SIZE * (NUM_KERNEL_PDE - 1), u64, > > 0xdeaddeadbeefbeef); > > expected = xe_pte_encode(pt, 0, XE_CACHE_WB, 0); > > - if (m->eng->vm->flags & XE_VM_FLAG_64K) > > + if (m->q->vm->flags & XE_VM_FLAG_64K) > > expected |= XE_PTE_PS64; > > if (xe_bo_is_vram(pt)) > > xe_res_first(pt->ttm.resource, 0, pt->size, &src_it); > > @@ -399,11 +399,11 @@ static int migrate_test_run_device(struct xe_device *xe) > > struct ww_acquire_ctx ww; > > > > kunit_info(test, "Testing tile id %d.\n", id); > > - xe_vm_lock(m->eng->vm, &ww, 0, true); > > + xe_vm_lock(m->q->vm, &ww, 0, true); > > xe_device_mem_access_get(xe); > > xe_migrate_sanity_test(m, test); > > xe_device_mem_access_put(xe); > > - xe_vm_unlock(m->eng->vm, &ww); > > + xe_vm_unlock(m->q->vm, &ww); > > } > > > > return 0; > > diff --git a/drivers/gpu/drm/xe/xe_bb.c b/drivers/gpu/drm/xe/xe_bb.c > > index b15a7cb7db4c..38f4ce83a207 100644 > > --- a/drivers/gpu/drm/xe/xe_bb.c > > +++ b/drivers/gpu/drm/xe/xe_bb.c > > @@ -7,7 +7,7 @@ > > > > #include "regs/xe_gpu_commands.h" > > #include "xe_device.h" > > -#include "xe_engine_types.h" > > +#include "xe_exec_queue_types.h" > > #include "xe_gt.h" > > #include "xe_hw_fence.h" > > #include "xe_sa.h" > > @@ -60,30 +60,30 @@ struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 dwords, bool usm) > > } > > > > static struct xe_sched_job * > > -__xe_bb_create_job(struct xe_engine *kernel_eng, struct xe_bb *bb, u64 *addr) > > +__xe_bb_create_job(struct xe_exec_queue *q, struct xe_bb *bb, u64 *addr) > > { > > u32 size = drm_suballoc_size(bb->bo); > > > > bb->cs[bb->len++] = MI_BATCH_BUFFER_END; > > > > - WARN_ON(bb->len * 4 + bb_prefetch(kernel_eng->gt) > size); > > + WARN_ON(bb->len * 4 + bb_prefetch(q->gt) > size); > > > > xe_sa_bo_flush_write(bb->bo); > > > > - return xe_sched_job_create(kernel_eng, addr); > > + return xe_sched_job_create(q, addr); > > } > > > > -struct xe_sched_job *xe_bb_create_wa_job(struct xe_engine *wa_eng, > > +struct xe_sched_job *xe_bb_create_wa_job(struct xe_exec_queue *q, > > struct xe_bb *bb, u64 batch_base_ofs) > > { > > u64 addr = batch_base_ofs + drm_suballoc_soffset(bb->bo); > > > > - XE_WARN_ON(!(wa_eng->vm->flags & XE_VM_FLAG_MIGRATION)); > > + XE_WARN_ON(!(q->vm->flags & XE_VM_FLAG_MIGRATION)); > > > > - return __xe_bb_create_job(wa_eng, bb, &addr); > > + return __xe_bb_create_job(q, bb, &addr); > > } > > > > -struct xe_sched_job *xe_bb_create_migration_job(struct xe_engine *kernel_eng, > > +struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q, > > struct xe_bb *bb, > > u64 batch_base_ofs, > > u32 second_idx) > > @@ -95,18 +95,18 @@ struct xe_sched_job *xe_bb_create_migration_job(struct xe_engine *kernel_eng, > > }; > > > > XE_WARN_ON(second_idx > bb->len); > > - XE_WARN_ON(!(kernel_eng->vm->flags & XE_VM_FLAG_MIGRATION)); > > + XE_WARN_ON(!(q->vm->flags & XE_VM_FLAG_MIGRATION)); > > > > - return __xe_bb_create_job(kernel_eng, bb, addr); > > + return __xe_bb_create_job(q, bb, addr); > > } > > > > -struct xe_sched_job *xe_bb_create_job(struct xe_engine *kernel_eng, > > +struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q, > > struct xe_bb *bb) > > { > > u64 addr = xe_sa_bo_gpu_addr(bb->bo); > > > > - XE_WARN_ON(kernel_eng->vm && kernel_eng->vm->flags & XE_VM_FLAG_MIGRATION); > > - return __xe_bb_create_job(kernel_eng, bb, &addr); > > + XE_WARN_ON(q->vm && q->vm->flags & XE_VM_FLAG_MIGRATION); > > + return __xe_bb_create_job(q, bb, &addr); > > } > > > > void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence) > > diff --git a/drivers/gpu/drm/xe/xe_bb.h b/drivers/gpu/drm/xe/xe_bb.h > > index 0cc9260c9634..c5ae0770bab5 100644 > > --- a/drivers/gpu/drm/xe/xe_bb.h > > +++ b/drivers/gpu/drm/xe/xe_bb.h > > @@ -11,16 +11,16 @@ > > struct dma_fence; > > > > struct xe_gt; > > -struct xe_engine; > > +struct xe_exec_queue; > > struct xe_sched_job; > > > > struct xe_bb *xe_bb_new(struct xe_gt *gt, u32 size, bool usm); > > -struct xe_sched_job *xe_bb_create_job(struct xe_engine *kernel_eng, > > +struct xe_sched_job *xe_bb_create_job(struct xe_exec_queue *q, > > struct xe_bb *bb); > > -struct xe_sched_job *xe_bb_create_migration_job(struct xe_engine *kernel_eng, > > +struct xe_sched_job *xe_bb_create_migration_job(struct xe_exec_queue *q, > > struct xe_bb *bb, u64 batch_ofs, > > u32 second_idx); > > -struct xe_sched_job *xe_bb_create_wa_job(struct xe_engine *wa_eng, > > +struct xe_sched_job *xe_bb_create_wa_job(struct xe_exec_queue *q, > > struct xe_bb *bb, u64 batch_ofs); > > void xe_bb_free(struct xe_bb *bb, struct dma_fence *fence); > > > > diff --git a/drivers/gpu/drm/xe/xe_devcoredump.c b/drivers/gpu/drm/xe/xe_devcoredump.c > > index f53f4b51233a..68abc0b195be 100644 > > --- a/drivers/gpu/drm/xe/xe_devcoredump.c > > +++ b/drivers/gpu/drm/xe/xe_devcoredump.c > > @@ -10,7 +10,7 @@ > > #include <generated/utsrelease.h> > > > > #include "xe_device.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_force_wake.h" > > #include "xe_gt.h" > > #include "xe_guc_ct.h" > > @@ -53,9 +53,9 @@ static struct xe_device *coredump_to_xe(const struct xe_devcoredump *coredump) > > return container_of(coredump, struct xe_device, devcoredump); > > } > > > > -static struct xe_guc *engine_to_guc(struct xe_engine *e) > > +static struct xe_guc *exec_queue_to_guc(struct xe_exec_queue *q) > > { > > - return &e->gt->uc.guc; > > + return &q->gt->uc.guc; > > } > > > > static ssize_t xe_devcoredump_read(char *buffer, loff_t offset, > > @@ -91,7 +91,7 @@ static ssize_t xe_devcoredump_read(char *buffer, loff_t offset, > > > > drm_printf(&p, "\n**** GuC CT ****\n"); > > xe_guc_ct_snapshot_print(coredump->snapshot.ct, &p); > > - xe_guc_engine_snapshot_print(coredump->snapshot.ge, &p); > > + xe_guc_exec_queue_snapshot_print(coredump->snapshot.ge, &p); > > > > drm_printf(&p, "\n**** HW Engines ****\n"); > > for (i = 0; i < XE_NUM_HW_ENGINES; i++) > > @@ -112,7 +112,7 @@ static void xe_devcoredump_free(void *data) > > return; > > > > xe_guc_ct_snapshot_free(coredump->snapshot.ct); > > - xe_guc_engine_snapshot_free(coredump->snapshot.ge); > > + xe_guc_exec_queue_snapshot_free(coredump->snapshot.ge); > > for (i = 0; i < XE_NUM_HW_ENGINES; i++) > > if (coredump->snapshot.hwe[i]) > > xe_hw_engine_snapshot_free(coredump->snapshot.hwe[i]); > > @@ -123,14 +123,14 @@ static void xe_devcoredump_free(void *data) > > } > > > > static void devcoredump_snapshot(struct xe_devcoredump *coredump, > > - struct xe_engine *e) > > + struct xe_exec_queue *q) > > { > > struct xe_devcoredump_snapshot *ss = &coredump->snapshot; > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > struct xe_hw_engine *hwe; > > enum xe_hw_engine_id id; > > - u32 adj_logical_mask = e->logical_mask; > > - u32 width_mask = (0x1 << e->width) - 1; > > + u32 adj_logical_mask = q->logical_mask; > > + u32 width_mask = (0x1 << q->width) - 1; > > int i; > > bool cookie; > > > > @@ -138,22 +138,22 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump, > > ss->boot_time = ktime_get_boottime(); > > > > cookie = dma_fence_begin_signalling(); > > - for (i = 0; e->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { > > + for (i = 0; q->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { > > if (adj_logical_mask & BIT(i)) { > > adj_logical_mask |= width_mask << i; > > - i += e->width; > > + i += q->width; > > } else { > > ++i; > > } > > } > > > > - xe_force_wake_get(gt_to_fw(e->gt), XE_FORCEWAKE_ALL); > > + xe_force_wake_get(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); > > > > coredump->snapshot.ct = xe_guc_ct_snapshot_capture(&guc->ct, true); > > - coredump->snapshot.ge = xe_guc_engine_snapshot_capture(e); > > + coredump->snapshot.ge = xe_guc_exec_queue_snapshot_capture(q); > > > > - for_each_hw_engine(hwe, e->gt, id) { > > - if (hwe->class != e->hwe->class || > > + for_each_hw_engine(hwe, q->gt, id) { > > + if (hwe->class != q->hwe->class || > > !(BIT(hwe->logical_instance) & adj_logical_mask)) { > > coredump->snapshot.hwe[id] = NULL; > > continue; > > @@ -161,21 +161,21 @@ static void devcoredump_snapshot(struct xe_devcoredump *coredump, > > coredump->snapshot.hwe[id] = xe_hw_engine_snapshot_capture(hwe); > > } > > > > - xe_force_wake_put(gt_to_fw(e->gt), XE_FORCEWAKE_ALL); > > + xe_force_wake_put(gt_to_fw(q->gt), XE_FORCEWAKE_ALL); > > dma_fence_end_signalling(cookie); > > } > > > > /** > > * xe_devcoredump - Take the required snapshots and initialize coredump device. > > - * @e: The faulty xe_engine, where the issue was detected. > > + * @q: The faulty xe_exec_queue, where the issue was detected. > > * > > * This function should be called at the crash time within the serialized > > * gt_reset. It is skipped if we still have the core dump device available > > * with the information of the 'first' snapshot. > > */ > > -void xe_devcoredump(struct xe_engine *e) > > +void xe_devcoredump(struct xe_exec_queue *q) > > { > > - struct xe_device *xe = gt_to_xe(e->gt); > > + struct xe_device *xe = gt_to_xe(q->gt); > > struct xe_devcoredump *coredump = &xe->devcoredump; > > > > if (coredump->captured) { > > @@ -184,7 +184,7 @@ void xe_devcoredump(struct xe_engine *e) > > } > > > > coredump->captured = true; > > - devcoredump_snapshot(coredump, e); > > + devcoredump_snapshot(coredump, q); > > > > drm_info(&xe->drm, "Xe device coredump has been created\n"); > > drm_info(&xe->drm, "Check your /sys/class/drm/card%d/device/devcoredump/data\n", > > diff --git a/drivers/gpu/drm/xe/xe_devcoredump.h b/drivers/gpu/drm/xe/xe_devcoredump.h > > index 854882129227..6ac218a5c194 100644 > > --- a/drivers/gpu/drm/xe/xe_devcoredump.h > > +++ b/drivers/gpu/drm/xe/xe_devcoredump.h > > @@ -7,12 +7,12 @@ > > #define _XE_DEVCOREDUMP_H_ > > > > struct xe_device; > > -struct xe_engine; > > +struct xe_exec_queue; > > > > #ifdef CONFIG_DEV_COREDUMP > > -void xe_devcoredump(struct xe_engine *e); > > +void xe_devcoredump(struct xe_exec_queue *q); > > #else > > -static inline void xe_devcoredump(struct xe_engine *e) > > +static inline void xe_devcoredump(struct xe_exec_queue *q) > > { > > } > > #endif > > diff --git a/drivers/gpu/drm/xe/xe_devcoredump_types.h b/drivers/gpu/drm/xe/xe_devcoredump_types.h > > index c0d711eb6ab3..7fdad9c3d3dd 100644 > > --- a/drivers/gpu/drm/xe/xe_devcoredump_types.h > > +++ b/drivers/gpu/drm/xe/xe_devcoredump_types.h > > @@ -30,7 +30,7 @@ struct xe_devcoredump_snapshot { > > /** @ct: GuC CT snapshot */ > > struct xe_guc_ct_snapshot *ct; > > /** @ge: Guc Engine snapshot */ > > - struct xe_guc_submit_engine_snapshot *ge; > > + struct xe_guc_submit_exec_queue_snapshot *ge; > > /** @hwe: HW Engine snapshot array */ > > struct xe_hw_engine_snapshot *hwe[XE_NUM_HW_ENGINES]; > > }; > > diff --git a/drivers/gpu/drm/xe/xe_device.c b/drivers/gpu/drm/xe/xe_device.c > > index 5409cf7895d3..766df07de979 100644 > > --- a/drivers/gpu/drm/xe/xe_device.c > > +++ b/drivers/gpu/drm/xe/xe_device.c > > @@ -19,7 +19,7 @@ > > #include "xe_display.h" > > #include "xe_dma_buf.h" > > #include "xe_drv.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_exec.h" > > #include "xe_gt.h" > > #include "xe_irq.h" > > @@ -54,33 +54,33 @@ static int xe_file_open(struct drm_device *dev, struct drm_file *file) > > mutex_init(&xef->vm.lock); > > xa_init_flags(&xef->vm.xa, XA_FLAGS_ALLOC1); > > > > - mutex_init(&xef->engine.lock); > > - xa_init_flags(&xef->engine.xa, XA_FLAGS_ALLOC1); > > + mutex_init(&xef->exec_queue.lock); > > + xa_init_flags(&xef->exec_queue.xa, XA_FLAGS_ALLOC1); > > > > file->driver_priv = xef; > > return 0; > > } > > > > -static void device_kill_persistent_engines(struct xe_device *xe, > > - struct xe_file *xef); > > +static void device_kill_persistent_exec_queues(struct xe_device *xe, > > + struct xe_file *xef); > > > > static void xe_file_close(struct drm_device *dev, struct drm_file *file) > > { > > struct xe_device *xe = to_xe_device(dev); > > struct xe_file *xef = file->driver_priv; > > struct xe_vm *vm; > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > unsigned long idx; > > > > - mutex_lock(&xef->engine.lock); > > - xa_for_each(&xef->engine.xa, idx, e) { > > - xe_engine_kill(e); > > - xe_engine_put(e); > > + mutex_lock(&xef->exec_queue.lock); > > + xa_for_each(&xef->exec_queue.xa, idx, q) { > > + xe_exec_queue_kill(q); > > + xe_exec_queue_put(q); > > } > > - mutex_unlock(&xef->engine.lock); > > - xa_destroy(&xef->engine.xa); > > - mutex_destroy(&xef->engine.lock); > > - device_kill_persistent_engines(xe, xef); > > + mutex_unlock(&xef->exec_queue.lock); > > + xa_destroy(&xef->exec_queue.xa); > > + mutex_destroy(&xef->exec_queue.lock); > > + device_kill_persistent_exec_queues(xe, xef); > > > > mutex_lock(&xef->vm.lock); > > xa_for_each(&xef->vm.xa, idx, vm) > > @@ -100,15 +100,15 @@ static const struct drm_ioctl_desc xe_ioctls[] = { > > DRM_IOCTL_DEF_DRV(XE_VM_CREATE, xe_vm_create_ioctl, DRM_RENDER_ALLOW), > > DRM_IOCTL_DEF_DRV(XE_VM_DESTROY, xe_vm_destroy_ioctl, DRM_RENDER_ALLOW), > > DRM_IOCTL_DEF_DRV(XE_VM_BIND, xe_vm_bind_ioctl, DRM_RENDER_ALLOW), > > - DRM_IOCTL_DEF_DRV(XE_ENGINE_CREATE, xe_engine_create_ioctl, > > + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_CREATE, xe_exec_queue_create_ioctl, > > DRM_RENDER_ALLOW), > > - DRM_IOCTL_DEF_DRV(XE_ENGINE_GET_PROPERTY, xe_engine_get_property_ioctl, > > + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_GET_PROPERTY, xe_exec_queue_get_property_ioctl, > > DRM_RENDER_ALLOW), > > - DRM_IOCTL_DEF_DRV(XE_ENGINE_DESTROY, xe_engine_destroy_ioctl, > > + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_DESTROY, xe_exec_queue_destroy_ioctl, > > DRM_RENDER_ALLOW), > > DRM_IOCTL_DEF_DRV(XE_EXEC, xe_exec_ioctl, DRM_RENDER_ALLOW), > > DRM_IOCTL_DEF_DRV(XE_MMIO, xe_mmio_ioctl, DRM_RENDER_ALLOW), > > - DRM_IOCTL_DEF_DRV(XE_ENGINE_SET_PROPERTY, xe_engine_set_property_ioctl, > > + DRM_IOCTL_DEF_DRV(XE_EXEC_QUEUE_SET_PROPERTY, xe_exec_queue_set_property_ioctl, > > DRM_RENDER_ALLOW), > > DRM_IOCTL_DEF_DRV(XE_WAIT_USER_FENCE, xe_wait_user_fence_ioctl, > > DRM_RENDER_ALLOW), > > @@ -372,33 +372,33 @@ void xe_device_shutdown(struct xe_device *xe) > > { > > } > > > > -void xe_device_add_persistent_engines(struct xe_device *xe, struct xe_engine *e) > > +void xe_device_add_persistent_exec_queues(struct xe_device *xe, struct xe_exec_queue *q) > > { > > mutex_lock(&xe->persistent_engines.lock); > > - list_add_tail(&e->persistent.link, &xe->persistent_engines.list); > > + list_add_tail(&q->persistent.link, &xe->persistent_engines.list); > > mutex_unlock(&xe->persistent_engines.lock); > > } > > > > -void xe_device_remove_persistent_engines(struct xe_device *xe, > > - struct xe_engine *e) > > +void xe_device_remove_persistent_exec_queues(struct xe_device *xe, > > + struct xe_exec_queue *q) > > { > > mutex_lock(&xe->persistent_engines.lock); > > - if (!list_empty(&e->persistent.link)) > > - list_del(&e->persistent.link); > > + if (!list_empty(&q->persistent.link)) > > + list_del(&q->persistent.link); > > mutex_unlock(&xe->persistent_engines.lock); > > } > > > > -static void device_kill_persistent_engines(struct xe_device *xe, > > - struct xe_file *xef) > > +static void device_kill_persistent_exec_queues(struct xe_device *xe, > > + struct xe_file *xef) > > { > > - struct xe_engine *e, *next; > > + struct xe_exec_queue *q, *next; > > > > mutex_lock(&xe->persistent_engines.lock); > > - list_for_each_entry_safe(e, next, &xe->persistent_engines.list, > > + list_for_each_entry_safe(q, next, &xe->persistent_engines.list, > > persistent.link) > > - if (e->persistent.xef == xef) { > > - xe_engine_kill(e); > > - list_del_init(&e->persistent.link); > > + if (q->persistent.xef == xef) { > > + xe_exec_queue_kill(q); > > + list_del_init(&q->persistent.link); > > } > > mutex_unlock(&xe->persistent_engines.lock); > > } > > diff --git a/drivers/gpu/drm/xe/xe_device.h b/drivers/gpu/drm/xe/xe_device.h > > index 61a5cf1f7300..71582094834c 100644 > > --- a/drivers/gpu/drm/xe/xe_device.h > > +++ b/drivers/gpu/drm/xe/xe_device.h > > @@ -6,7 +6,7 @@ > > #ifndef _XE_DEVICE_H_ > > #define _XE_DEVICE_H_ > > > > -struct xe_engine; > > +struct xe_exec_queue; > > struct xe_file; > > > > #include <drm/drm_util.h> > > @@ -41,9 +41,9 @@ int xe_device_probe(struct xe_device *xe); > > void xe_device_remove(struct xe_device *xe); > > void xe_device_shutdown(struct xe_device *xe); > > > > -void xe_device_add_persistent_engines(struct xe_device *xe, struct xe_engine *e); > > -void xe_device_remove_persistent_engines(struct xe_device *xe, > > - struct xe_engine *e); > > +void xe_device_add_persistent_exec_queues(struct xe_device *xe, struct xe_exec_queue *q); > > +void xe_device_remove_persistent_exec_queues(struct xe_device *xe, > > + struct xe_exec_queue *q); > > > > void xe_device_wmb(struct xe_device *xe); > > > > diff --git a/drivers/gpu/drm/xe/xe_device_types.h b/drivers/gpu/drm/xe/xe_device_types.h > > index b156f69d7320..f6665cd16a66 100644 > > --- a/drivers/gpu/drm/xe/xe_device_types.h > > +++ b/drivers/gpu/drm/xe/xe_device_types.h > > @@ -494,7 +494,7 @@ struct xe_file { > > struct xarray xa; > > /** @lock: protects file engine state */ > > struct mutex lock; > > - } engine; > > + } exec_queue; > > }; > > > > #endif > > diff --git a/drivers/gpu/drm/xe/xe_engine.c b/drivers/gpu/drm/xe/xe_engine.c > > deleted file mode 100644 > > index c30810a687b1..000000000000 > > --- a/drivers/gpu/drm/xe/xe_engine.c > > +++ /dev/null > > @@ -1,850 +0,0 @@ > > -// SPDX-License-Identifier: MIT > > -/* > > - * Copyright © 2021 Intel Corporation > > - */ > > - > > -#include "xe_engine.h" > > - > > -#include <linux/nospec.h> > > - > > -#include <drm/drm_device.h> > > -#include <drm/drm_file.h> > > -#include <drm/xe_drm.h> > > - > > -#include "xe_device.h" > > -#include "xe_gt.h" > > -#include "xe_hw_fence.h" > > -#include "xe_lrc.h" > > -#include "xe_macros.h" > > -#include "xe_migrate.h" > > -#include "xe_pm.h" > > -#include "xe_ring_ops_types.h" > > -#include "xe_trace.h" > > -#include "xe_vm.h" > > - > > -static struct xe_engine *__xe_engine_create(struct xe_device *xe, > > - struct xe_vm *vm, > > - u32 logical_mask, > > - u16 width, struct xe_hw_engine *hwe, > > - u32 flags) > > -{ > > - struct xe_engine *e; > > - struct xe_gt *gt = hwe->gt; > > - int err; > > - int i; > > - > > - e = kzalloc(sizeof(*e) + sizeof(struct xe_lrc) * width, GFP_KERNEL); > > - if (!e) > > - return ERR_PTR(-ENOMEM); > > - > > - kref_init(&e->refcount); > > - e->flags = flags; > > - e->hwe = hwe; > > - e->gt = gt; > > - if (vm) > > - e->vm = xe_vm_get(vm); > > - e->class = hwe->class; > > - e->width = width; > > - e->logical_mask = logical_mask; > > - e->fence_irq = >->fence_irq[hwe->class]; > > - e->ring_ops = gt->ring_ops[hwe->class]; > > - e->ops = gt->engine_ops; > > - INIT_LIST_HEAD(&e->persistent.link); > > - INIT_LIST_HEAD(&e->compute.link); > > - INIT_LIST_HEAD(&e->multi_gt_link); > > - > > - /* FIXME: Wire up to configurable default value */ > > - e->sched_props.timeslice_us = 1 * 1000; > > - e->sched_props.preempt_timeout_us = 640 * 1000; > > - > > - if (xe_engine_is_parallel(e)) { > > - e->parallel.composite_fence_ctx = dma_fence_context_alloc(1); > > - e->parallel.composite_fence_seqno = XE_FENCE_INITIAL_SEQNO; > > - } > > - if (e->flags & ENGINE_FLAG_VM) { > > - e->bind.fence_ctx = dma_fence_context_alloc(1); > > - e->bind.fence_seqno = XE_FENCE_INITIAL_SEQNO; > > - } > > - > > - for (i = 0; i < width; ++i) { > > - err = xe_lrc_init(e->lrc + i, hwe, e, vm, SZ_16K); > > - if (err) > > - goto err_lrc; > > - } > > - > > - err = e->ops->init(e); > > - if (err) > > - goto err_lrc; > > - > > - /* > > - * Normally the user vm holds an rpm ref to keep the device > > - * awake, and the context holds a ref for the vm, however for > > - * some engines we use the kernels migrate vm underneath which > > - * offers no such rpm ref. Make sure we keep a ref here, so we > > - * can perform GuC CT actions when needed. Caller is expected to > > - * have already grabbed the rpm ref outside any sensitive locks. > > - */ > > - if (e->flags & ENGINE_FLAG_VM) > > - drm_WARN_ON(&xe->drm, !xe_device_mem_access_get_if_ongoing(xe)); > > - > > - return e; > > - > > -err_lrc: > > - for (i = i - 1; i >= 0; --i) > > - xe_lrc_finish(e->lrc + i); > > - kfree(e); > > - return ERR_PTR(err); > > -} > > - > > -struct xe_engine *xe_engine_create(struct xe_device *xe, struct xe_vm *vm, > > - u32 logical_mask, u16 width, > > - struct xe_hw_engine *hwe, u32 flags) > > -{ > > - struct ww_acquire_ctx ww; > > - struct xe_engine *e; > > - int err; > > - > > - if (vm) { > > - err = xe_vm_lock(vm, &ww, 0, true); > > - if (err) > > - return ERR_PTR(err); > > - } > > - e = __xe_engine_create(xe, vm, logical_mask, width, hwe, flags); > > - if (vm) > > - xe_vm_unlock(vm, &ww); > > - > > - return e; > > -} > > - > > -struct xe_engine *xe_engine_create_class(struct xe_device *xe, struct xe_gt *gt, > > - struct xe_vm *vm, > > - enum xe_engine_class class, u32 flags) > > -{ > > - struct xe_hw_engine *hwe, *hwe0 = NULL; > > - enum xe_hw_engine_id id; > > - u32 logical_mask = 0; > > - > > - for_each_hw_engine(hwe, gt, id) { > > - if (xe_hw_engine_is_reserved(hwe)) > > - continue; > > - > > - if (hwe->class == class) { > > - logical_mask |= BIT(hwe->logical_instance); > > - if (!hwe0) > > - hwe0 = hwe; > > - } > > - } > > - > > - if (!logical_mask) > > - return ERR_PTR(-ENODEV); > > - > > - return xe_engine_create(xe, vm, logical_mask, 1, hwe0, flags); > > -} > > - > > -void xe_engine_destroy(struct kref *ref) > > -{ > > - struct xe_engine *e = container_of(ref, struct xe_engine, refcount); > > - struct xe_engine *engine, *next; > > - > > - if (!(e->flags & ENGINE_FLAG_BIND_ENGINE_CHILD)) { > > - list_for_each_entry_safe(engine, next, &e->multi_gt_list, > > - multi_gt_link) > > - xe_engine_put(engine); > > - } > > - > > - e->ops->fini(e); > > -} > > - > > -void xe_engine_fini(struct xe_engine *e) > > -{ > > - int i; > > - > > - for (i = 0; i < e->width; ++i) > > - xe_lrc_finish(e->lrc + i); > > - if (e->vm) > > - xe_vm_put(e->vm); > > - if (e->flags & ENGINE_FLAG_VM) > > - xe_device_mem_access_put(gt_to_xe(e->gt)); > > - > > - kfree(e); > > -} > > - > > -struct xe_engine *xe_engine_lookup(struct xe_file *xef, u32 id) > > -{ > > - struct xe_engine *e; > > - > > - mutex_lock(&xef->engine.lock); > > - e = xa_load(&xef->engine.xa, id); > > - if (e) > > - xe_engine_get(e); > > - mutex_unlock(&xef->engine.lock); > > - > > - return e; > > -} > > - > > -enum drm_sched_priority > > -xe_engine_device_get_max_priority(struct xe_device *xe) > > -{ > > - return capable(CAP_SYS_NICE) ? DRM_SCHED_PRIORITY_HIGH : > > - DRM_SCHED_PRIORITY_NORMAL; > > -} > > - > > -static int engine_set_priority(struct xe_device *xe, struct xe_engine *e, > > - u64 value, bool create) > > -{ > > - if (XE_IOCTL_DBG(xe, value > DRM_SCHED_PRIORITY_HIGH)) > > - return -EINVAL; > > - > > - if (XE_IOCTL_DBG(xe, value > xe_engine_device_get_max_priority(xe))) > > - return -EPERM; > > - > > - return e->ops->set_priority(e, value); > > -} > > - > > -static int engine_set_timeslice(struct xe_device *xe, struct xe_engine *e, > > - u64 value, bool create) > > -{ > > - if (!capable(CAP_SYS_NICE)) > > - return -EPERM; > > - > > - return e->ops->set_timeslice(e, value); > > -} > > - > > -static int engine_set_preemption_timeout(struct xe_device *xe, > > - struct xe_engine *e, u64 value, > > - bool create) > > -{ > > - if (!capable(CAP_SYS_NICE)) > > - return -EPERM; > > - > > - return e->ops->set_preempt_timeout(e, value); > > -} > > - > > -static int engine_set_compute_mode(struct xe_device *xe, struct xe_engine *e, > > - u64 value, bool create) > > -{ > > - if (XE_IOCTL_DBG(xe, !create)) > > - return -EINVAL; > > - > > - if (XE_IOCTL_DBG(xe, e->flags & ENGINE_FLAG_COMPUTE_MODE)) > > - return -EINVAL; > > - > > - if (XE_IOCTL_DBG(xe, e->flags & ENGINE_FLAG_VM)) > > - return -EINVAL; > > - > > - if (value) { > > - struct xe_vm *vm = e->vm; > > - int err; > > - > > - if (XE_IOCTL_DBG(xe, xe_vm_in_fault_mode(vm))) > > - return -EOPNOTSUPP; > > - > > - if (XE_IOCTL_DBG(xe, !xe_vm_in_compute_mode(vm))) > > - return -EOPNOTSUPP; > > - > > - if (XE_IOCTL_DBG(xe, e->width != 1)) > > - return -EINVAL; > > - > > - e->compute.context = dma_fence_context_alloc(1); > > - spin_lock_init(&e->compute.lock); > > - > > - err = xe_vm_add_compute_engine(vm, e); > > - if (XE_IOCTL_DBG(xe, err)) > > - return err; > > - > > - e->flags |= ENGINE_FLAG_COMPUTE_MODE; > > - e->flags &= ~ENGINE_FLAG_PERSISTENT; > > - } > > - > > - return 0; > > -} > > - > > -static int engine_set_persistence(struct xe_device *xe, struct xe_engine *e, > > - u64 value, bool create) > > -{ > > - if (XE_IOCTL_DBG(xe, !create)) > > - return -EINVAL; > > - > > - if (XE_IOCTL_DBG(xe, e->flags & ENGINE_FLAG_COMPUTE_MODE)) > > - return -EINVAL; > > - > > - if (value) > > - e->flags |= ENGINE_FLAG_PERSISTENT; > > - else > > - e->flags &= ~ENGINE_FLAG_PERSISTENT; > > - > > - return 0; > > -} > > - > > -static int engine_set_job_timeout(struct xe_device *xe, struct xe_engine *e, > > - u64 value, bool create) > > -{ > > - if (XE_IOCTL_DBG(xe, !create)) > > - return -EINVAL; > > - > > - if (!capable(CAP_SYS_NICE)) > > - return -EPERM; > > - > > - return e->ops->set_job_timeout(e, value); > > -} > > - > > -static int engine_set_acc_trigger(struct xe_device *xe, struct xe_engine *e, > > - u64 value, bool create) > > -{ > > - if (XE_IOCTL_DBG(xe, !create)) > > - return -EINVAL; > > - > > - if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > > - return -EINVAL; > > - > > - e->usm.acc_trigger = value; > > - > > - return 0; > > -} > > - > > -static int engine_set_acc_notify(struct xe_device *xe, struct xe_engine *e, > > - u64 value, bool create) > > -{ > > - if (XE_IOCTL_DBG(xe, !create)) > > - return -EINVAL; > > - > > - if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > > - return -EINVAL; > > - > > - e->usm.acc_notify = value; > > - > > - return 0; > > -} > > - > > -static int engine_set_acc_granularity(struct xe_device *xe, struct xe_engine *e, > > - u64 value, bool create) > > -{ > > - if (XE_IOCTL_DBG(xe, !create)) > > - return -EINVAL; > > - > > - if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > > - return -EINVAL; > > - > > - e->usm.acc_granularity = value; > > - > > - return 0; > > -} > > - > > -typedef int (*xe_engine_set_property_fn)(struct xe_device *xe, > > - struct xe_engine *e, > > - u64 value, bool create); > > - > > -static const xe_engine_set_property_fn engine_set_property_funcs[] = { > > - [XE_ENGINE_SET_PROPERTY_PRIORITY] = engine_set_priority, > > - [XE_ENGINE_SET_PROPERTY_TIMESLICE] = engine_set_timeslice, > > - [XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT] = engine_set_preemption_timeout, > > - [XE_ENGINE_SET_PROPERTY_COMPUTE_MODE] = engine_set_compute_mode, > > - [XE_ENGINE_SET_PROPERTY_PERSISTENCE] = engine_set_persistence, > > - [XE_ENGINE_SET_PROPERTY_JOB_TIMEOUT] = engine_set_job_timeout, > > - [XE_ENGINE_SET_PROPERTY_ACC_TRIGGER] = engine_set_acc_trigger, > > - [XE_ENGINE_SET_PROPERTY_ACC_NOTIFY] = engine_set_acc_notify, > > - [XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY] = engine_set_acc_granularity, > > -}; > > - > > -static int engine_user_ext_set_property(struct xe_device *xe, > > - struct xe_engine *e, > > - u64 extension, > > - bool create) > > -{ > > - u64 __user *address = u64_to_user_ptr(extension); > > - struct drm_xe_ext_engine_set_property ext; > > - int err; > > - u32 idx; > > - > > - err = __copy_from_user(&ext, address, sizeof(ext)); > > - if (XE_IOCTL_DBG(xe, err)) > > - return -EFAULT; > > - > > - if (XE_IOCTL_DBG(xe, ext.property >= > > - ARRAY_SIZE(engine_set_property_funcs)) || > > - XE_IOCTL_DBG(xe, ext.pad)) > > - return -EINVAL; > > - > > - idx = array_index_nospec(ext.property, ARRAY_SIZE(engine_set_property_funcs)); > > - return engine_set_property_funcs[idx](xe, e, ext.value, create); > > -} > > - > > -typedef int (*xe_engine_user_extension_fn)(struct xe_device *xe, > > - struct xe_engine *e, > > - u64 extension, > > - bool create); > > - > > -static const xe_engine_set_property_fn engine_user_extension_funcs[] = { > > - [XE_ENGINE_EXTENSION_SET_PROPERTY] = engine_user_ext_set_property, > > -}; > > - > > -#define MAX_USER_EXTENSIONS 16 > > -static int engine_user_extensions(struct xe_device *xe, struct xe_engine *e, > > - u64 extensions, int ext_number, bool create) > > -{ > > - u64 __user *address = u64_to_user_ptr(extensions); > > - struct xe_user_extension ext; > > - int err; > > - u32 idx; > > - > > - if (XE_IOCTL_DBG(xe, ext_number >= MAX_USER_EXTENSIONS)) > > - return -E2BIG; > > - > > - err = __copy_from_user(&ext, address, sizeof(ext)); > > - if (XE_IOCTL_DBG(xe, err)) > > - return -EFAULT; > > - > > - if (XE_IOCTL_DBG(xe, ext.pad) || > > - XE_IOCTL_DBG(xe, ext.name >= > > - ARRAY_SIZE(engine_user_extension_funcs))) > > - return -EINVAL; > > - > > - idx = array_index_nospec(ext.name, > > - ARRAY_SIZE(engine_user_extension_funcs)); > > - err = engine_user_extension_funcs[idx](xe, e, extensions, create); > > - if (XE_IOCTL_DBG(xe, err)) > > - return err; > > - > > - if (ext.next_extension) > > - return engine_user_extensions(xe, e, ext.next_extension, > > - ++ext_number, create); > > - > > - return 0; > > -} > > - > > -static const enum xe_engine_class user_to_xe_engine_class[] = { > > - [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, > > - [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, > > - [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, > > - [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, > > - [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, > > -}; > > - > > -static struct xe_hw_engine * > > -find_hw_engine(struct xe_device *xe, > > - struct drm_xe_engine_class_instance eci) > > -{ > > - u32 idx; > > - > > - if (eci.engine_class > ARRAY_SIZE(user_to_xe_engine_class)) > > - return NULL; > > - > > - if (eci.gt_id >= xe->info.gt_count) > > - return NULL; > > - > > - idx = array_index_nospec(eci.engine_class, > > - ARRAY_SIZE(user_to_xe_engine_class)); > > - > > - return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id), > > - user_to_xe_engine_class[idx], > > - eci.engine_instance, true); > > -} > > - > > -static u32 bind_engine_logical_mask(struct xe_device *xe, struct xe_gt *gt, > > - struct drm_xe_engine_class_instance *eci, > > - u16 width, u16 num_placements) > > -{ > > - struct xe_hw_engine *hwe; > > - enum xe_hw_engine_id id; > > - u32 logical_mask = 0; > > - > > - if (XE_IOCTL_DBG(xe, width != 1)) > > - return 0; > > - if (XE_IOCTL_DBG(xe, num_placements != 1)) > > - return 0; > > - if (XE_IOCTL_DBG(xe, eci[0].engine_instance != 0)) > > - return 0; > > - > > - eci[0].engine_class = DRM_XE_ENGINE_CLASS_COPY; > > - > > - for_each_hw_engine(hwe, gt, id) { > > - if (xe_hw_engine_is_reserved(hwe)) > > - continue; > > - > > - if (hwe->class == > > - user_to_xe_engine_class[DRM_XE_ENGINE_CLASS_COPY]) > > - logical_mask |= BIT(hwe->logical_instance); > > - } > > - > > - return logical_mask; > > -} > > - > > -static u32 calc_validate_logical_mask(struct xe_device *xe, struct xe_gt *gt, > > - struct drm_xe_engine_class_instance *eci, > > - u16 width, u16 num_placements) > > -{ > > - int len = width * num_placements; > > - int i, j, n; > > - u16 class; > > - u16 gt_id; > > - u32 return_mask = 0, prev_mask; > > - > > - if (XE_IOCTL_DBG(xe, !xe_device_guc_submission_enabled(xe) && > > - len > 1)) > > - return 0; > > - > > - for (i = 0; i < width; ++i) { > > - u32 current_mask = 0; > > - > > - for (j = 0; j < num_placements; ++j) { > > - struct xe_hw_engine *hwe; > > - > > - n = j * width + i; > > - > > - hwe = find_hw_engine(xe, eci[n]); > > - if (XE_IOCTL_DBG(xe, !hwe)) > > - return 0; > > - > > - if (XE_IOCTL_DBG(xe, xe_hw_engine_is_reserved(hwe))) > > - return 0; > > - > > - if (XE_IOCTL_DBG(xe, n && eci[n].gt_id != gt_id) || > > - XE_IOCTL_DBG(xe, n && eci[n].engine_class != class)) > > - return 0; > > - > > - class = eci[n].engine_class; > > - gt_id = eci[n].gt_id; > > - > > - if (width == 1 || !i) > > - return_mask |= BIT(eci[n].engine_instance); > > - current_mask |= BIT(eci[n].engine_instance); > > - } > > - > > - /* Parallel submissions must be logically contiguous */ > > - if (i && XE_IOCTL_DBG(xe, current_mask != prev_mask << 1)) > > - return 0; > > - > > - prev_mask = current_mask; > > - } > > - > > - return return_mask; > > -} > > - > > -int xe_engine_create_ioctl(struct drm_device *dev, void *data, > > - struct drm_file *file) > > -{ > > - struct xe_device *xe = to_xe_device(dev); > > - struct xe_file *xef = to_xe_file(file); > > - struct drm_xe_engine_create *args = data; > > - struct drm_xe_engine_class_instance eci[XE_HW_ENGINE_MAX_INSTANCE]; > > - struct drm_xe_engine_class_instance __user *user_eci = > > - u64_to_user_ptr(args->instances); > > - struct xe_hw_engine *hwe; > > - struct xe_vm *vm, *migrate_vm; > > - struct xe_gt *gt; > > - struct xe_engine *e = NULL; > > - u32 logical_mask; > > - u32 id; > > - u32 len; > > - int err; > > - > > - if (XE_IOCTL_DBG(xe, args->flags) || > > - XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > > - return -EINVAL; > > - > > - len = args->width * args->num_placements; > > - if (XE_IOCTL_DBG(xe, !len || len > XE_HW_ENGINE_MAX_INSTANCE)) > > - return -EINVAL; > > - > > - err = __copy_from_user(eci, user_eci, > > - sizeof(struct drm_xe_engine_class_instance) * > > - len); > > - if (XE_IOCTL_DBG(xe, err)) > > - return -EFAULT; > > - > > - if (XE_IOCTL_DBG(xe, eci[0].gt_id >= xe->info.gt_count)) > > - return -EINVAL; > > - > > - if (eci[0].engine_class == DRM_XE_ENGINE_CLASS_VM_BIND) { > > - for_each_gt(gt, xe, id) { > > - struct xe_engine *new; > > - > > - if (xe_gt_is_media_type(gt)) > > - continue; > > - > > - eci[0].gt_id = gt->info.id; > > - logical_mask = bind_engine_logical_mask(xe, gt, eci, > > - args->width, > > - args->num_placements); > > - if (XE_IOCTL_DBG(xe, !logical_mask)) > > - return -EINVAL; > > - > > - hwe = find_hw_engine(xe, eci[0]); > > - if (XE_IOCTL_DBG(xe, !hwe)) > > - return -EINVAL; > > - > > - /* The migration vm doesn't hold rpm ref */ > > - xe_device_mem_access_get(xe); > > - > > - migrate_vm = xe_migrate_get_vm(gt_to_tile(gt)->migrate); > > - new = xe_engine_create(xe, migrate_vm, logical_mask, > > - args->width, hwe, > > - ENGINE_FLAG_PERSISTENT | > > - ENGINE_FLAG_VM | > > - (id ? > > - ENGINE_FLAG_BIND_ENGINE_CHILD : > > - 0)); > > - > > - xe_device_mem_access_put(xe); /* now held by engine */ > > - > > - xe_vm_put(migrate_vm); > > - if (IS_ERR(new)) { > > - err = PTR_ERR(new); > > - if (e) > > - goto put_engine; > > - return err; > > - } > > - if (id == 0) > > - e = new; > > - else > > - list_add_tail(&new->multi_gt_list, > > - &e->multi_gt_link); > > - } > > - } else { > > - gt = xe_device_get_gt(xe, eci[0].gt_id); > > - logical_mask = calc_validate_logical_mask(xe, gt, eci, > > - args->width, > > - args->num_placements); > > - if (XE_IOCTL_DBG(xe, !logical_mask)) > > - return -EINVAL; > > - > > - hwe = find_hw_engine(xe, eci[0]); > > - if (XE_IOCTL_DBG(xe, !hwe)) > > - return -EINVAL; > > - > > - vm = xe_vm_lookup(xef, args->vm_id); > > - if (XE_IOCTL_DBG(xe, !vm)) > > - return -ENOENT; > > - > > - err = down_read_interruptible(&vm->lock); > > - if (err) { > > - xe_vm_put(vm); > > - return err; > > - } > > - > > - if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) { > > - up_read(&vm->lock); > > - xe_vm_put(vm); > > - return -ENOENT; > > - } > > - > > - e = xe_engine_create(xe, vm, logical_mask, > > - args->width, hwe, > > - xe_vm_no_dma_fences(vm) ? 0 : > > - ENGINE_FLAG_PERSISTENT); > > - up_read(&vm->lock); > > - xe_vm_put(vm); > > - if (IS_ERR(e)) > > - return PTR_ERR(e); > > - } > > - > > - if (args->extensions) { > > - err = engine_user_extensions(xe, e, args->extensions, 0, true); > > - if (XE_IOCTL_DBG(xe, err)) > > - goto put_engine; > > - } > > - > > - if (XE_IOCTL_DBG(xe, e->vm && xe_vm_in_compute_mode(e->vm) != > > - !!(e->flags & ENGINE_FLAG_COMPUTE_MODE))) { > > - err = -EOPNOTSUPP; > > - goto put_engine; > > - } > > - > > - e->persistent.xef = xef; > > - > > - mutex_lock(&xef->engine.lock); > > - err = xa_alloc(&xef->engine.xa, &id, e, xa_limit_32b, GFP_KERNEL); > > - mutex_unlock(&xef->engine.lock); > > - if (err) > > - goto put_engine; > > - > > - args->engine_id = id; > > - > > - return 0; > > - > > -put_engine: > > - xe_engine_kill(e); > > - xe_engine_put(e); > > - return err; > > -} > > - > > -int xe_engine_get_property_ioctl(struct drm_device *dev, void *data, > > - struct drm_file *file) > > -{ > > - struct xe_device *xe = to_xe_device(dev); > > - struct xe_file *xef = to_xe_file(file); > > - struct drm_xe_engine_get_property *args = data; > > - struct xe_engine *e; > > - int ret; > > - > > - if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > > - return -EINVAL; > > - > > - e = xe_engine_lookup(xef, args->engine_id); > > - if (XE_IOCTL_DBG(xe, !e)) > > - return -ENOENT; > > - > > - switch (args->property) { > > - case XE_ENGINE_GET_PROPERTY_BAN: > > - args->value = !!(e->flags & ENGINE_FLAG_BANNED); > > - ret = 0; > > - break; > > - default: > > - ret = -EINVAL; > > - } > > - > > - xe_engine_put(e); > > - > > - return ret; > > -} > > - > > -static void engine_kill_compute(struct xe_engine *e) > > -{ > > - if (!xe_vm_in_compute_mode(e->vm)) > > - return; > > - > > - down_write(&e->vm->lock); > > - list_del(&e->compute.link); > > - --e->vm->preempt.num_engines; > > - if (e->compute.pfence) { > > - dma_fence_enable_sw_signaling(e->compute.pfence); > > - dma_fence_put(e->compute.pfence); > > - e->compute.pfence = NULL; > > - } > > - up_write(&e->vm->lock); > > -} > > - > > -/** > > - * xe_engine_is_lr() - Whether an engine is long-running > > - * @e: The engine > > - * > > - * Return: True if the engine is long-running, false otherwise. > > - */ > > -bool xe_engine_is_lr(struct xe_engine *e) > > -{ > > - return e->vm && xe_vm_no_dma_fences(e->vm) && > > - !(e->flags & ENGINE_FLAG_VM); > > -} > > - > > -static s32 xe_engine_num_job_inflight(struct xe_engine *e) > > -{ > > - return e->lrc->fence_ctx.next_seqno - xe_lrc_seqno(e->lrc) - 1; > > -} > > - > > -/** > > - * xe_engine_ring_full() - Whether an engine's ring is full > > - * @e: The engine > > - * > > - * Return: True if the engine's ring is full, false otherwise. > > - */ > > -bool xe_engine_ring_full(struct xe_engine *e) > > -{ > > - struct xe_lrc *lrc = e->lrc; > > - s32 max_job = lrc->ring.size / MAX_JOB_SIZE_BYTES; > > - > > - return xe_engine_num_job_inflight(e) >= max_job; > > -} > > - > > -/** > > - * xe_engine_is_idle() - Whether an engine is idle. > > - * @engine: The engine > > - * > > - * FIXME: Need to determine what to use as the short-lived > > - * timeline lock for the engines, so that the return value > > - * of this function becomes more than just an advisory > > - * snapshot in time. The timeline lock must protect the > > - * seqno from racing submissions on the same engine. > > - * Typically vm->resv, but user-created timeline locks use the migrate vm > > - * and never grabs the migrate vm->resv so we have a race there. > > - * > > - * Return: True if the engine is idle, false otherwise. > > - */ > > -bool xe_engine_is_idle(struct xe_engine *engine) > > -{ > > - if (XE_WARN_ON(xe_engine_is_parallel(engine))) > > - return false; > > - > > - return xe_lrc_seqno(&engine->lrc[0]) == > > - engine->lrc[0].fence_ctx.next_seqno - 1; > > -} > > - > > -void xe_engine_kill(struct xe_engine *e) > > -{ > > - struct xe_engine *engine = e, *next; > > - > > - list_for_each_entry_safe(engine, next, &engine->multi_gt_list, > > - multi_gt_link) { > > - e->ops->kill(engine); > > - engine_kill_compute(engine); > > - } > > - > > - e->ops->kill(e); > > - engine_kill_compute(e); > > -} > > - > > -int xe_engine_destroy_ioctl(struct drm_device *dev, void *data, > > - struct drm_file *file) > > -{ > > - struct xe_device *xe = to_xe_device(dev); > > - struct xe_file *xef = to_xe_file(file); > > - struct drm_xe_engine_destroy *args = data; > > - struct xe_engine *e; > > - > > - if (XE_IOCTL_DBG(xe, args->pad) || > > - XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > > - return -EINVAL; > > - > > - mutex_lock(&xef->engine.lock); > > - e = xa_erase(&xef->engine.xa, args->engine_id); > > - mutex_unlock(&xef->engine.lock); > > - if (XE_IOCTL_DBG(xe, !e)) > > - return -ENOENT; > > - > > - if (!(e->flags & ENGINE_FLAG_PERSISTENT)) > > - xe_engine_kill(e); > > - else > > - xe_device_add_persistent_engines(xe, e); > > - > > - trace_xe_engine_close(e); > > - xe_engine_put(e); > > - > > - return 0; > > -} > > - > > -int xe_engine_set_property_ioctl(struct drm_device *dev, void *data, > > - struct drm_file *file) > > -{ > > - struct xe_device *xe = to_xe_device(dev); > > - struct xe_file *xef = to_xe_file(file); > > - struct drm_xe_engine_set_property *args = data; > > - struct xe_engine *e; > > - int ret; > > - u32 idx; > > - > > - if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > > - return -EINVAL; > > - > > - e = xe_engine_lookup(xef, args->engine_id); > > - if (XE_IOCTL_DBG(xe, !e)) > > - return -ENOENT; > > - > > - if (XE_IOCTL_DBG(xe, args->property >= > > - ARRAY_SIZE(engine_set_property_funcs))) { > > - ret = -EINVAL; > > - goto out; > > - } > > - > > - idx = array_index_nospec(args->property, > > - ARRAY_SIZE(engine_set_property_funcs)); > > - ret = engine_set_property_funcs[idx](xe, e, args->value, false); > > - if (XE_IOCTL_DBG(xe, ret)) > > - goto out; > > - > > - if (args->extensions) > > - ret = engine_user_extensions(xe, e, args->extensions, 0, > > - false); > > -out: > > - xe_engine_put(e); > > - > > - return ret; > > -} > > diff --git a/drivers/gpu/drm/xe/xe_engine.h b/drivers/gpu/drm/xe/xe_engine.h > > deleted file mode 100644 > > index 2e60f6d90226..000000000000 > > --- a/drivers/gpu/drm/xe/xe_engine.h > > +++ /dev/null > > @@ -1,63 +0,0 @@ > > -/* SPDX-License-Identifier: MIT */ > > -/* > > - * Copyright © 2021 Intel Corporation > > - */ > > - > > -#ifndef _XE_ENGINE_H_ > > -#define _XE_ENGINE_H_ > > - > > -#include "xe_engine_types.h" > > -#include "xe_vm_types.h" > > - > > -struct drm_device; > > -struct drm_file; > > -struct xe_device; > > -struct xe_file; > > - > > -struct xe_engine *xe_engine_create(struct xe_device *xe, struct xe_vm *vm, > > - u32 logical_mask, u16 width, > > - struct xe_hw_engine *hw_engine, u32 flags); > > -struct xe_engine *xe_engine_create_class(struct xe_device *xe, struct xe_gt *gt, > > - struct xe_vm *vm, > > - enum xe_engine_class class, u32 flags); > > - > > -void xe_engine_fini(struct xe_engine *e); > > -void xe_engine_destroy(struct kref *ref); > > - > > -struct xe_engine *xe_engine_lookup(struct xe_file *xef, u32 id); > > - > > -static inline struct xe_engine *xe_engine_get(struct xe_engine *engine) > > -{ > > - kref_get(&engine->refcount); > > - return engine; > > -} > > - > > -static inline void xe_engine_put(struct xe_engine *engine) > > -{ > > - kref_put(&engine->refcount, xe_engine_destroy); > > -} > > - > > -static inline bool xe_engine_is_parallel(struct xe_engine *engine) > > -{ > > - return engine->width > 1; > > -} > > - > > -bool xe_engine_is_lr(struct xe_engine *e); > > - > > -bool xe_engine_ring_full(struct xe_engine *e); > > - > > -bool xe_engine_is_idle(struct xe_engine *engine); > > - > > -void xe_engine_kill(struct xe_engine *e); > > - > > -int xe_engine_create_ioctl(struct drm_device *dev, void *data, > > - struct drm_file *file); > > -int xe_engine_destroy_ioctl(struct drm_device *dev, void *data, > > - struct drm_file *file); > > -int xe_engine_set_property_ioctl(struct drm_device *dev, void *data, > > - struct drm_file *file); > > -int xe_engine_get_property_ioctl(struct drm_device *dev, void *data, > > - struct drm_file *file); > > -enum drm_sched_priority xe_engine_device_get_max_priority(struct xe_device *xe); > > - > > -#endif > > diff --git a/drivers/gpu/drm/xe/xe_exec.c b/drivers/gpu/drm/xe/xe_exec.c > > index fff4a9d9d12a..8a5b614df090 100644 > > --- a/drivers/gpu/drm/xe/xe_exec.c > > +++ b/drivers/gpu/drm/xe/xe_exec.c > > @@ -12,7 +12,7 @@ > > > > #include "xe_bo.h" > > #include "xe_device.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_macros.h" > > #include "xe_ring_ops_types.h" > > #include "xe_sched_job.h" > > @@ -95,19 +95,19 @@ > > > > #define XE_EXEC_BIND_RETRY_TIMEOUT_MS 1000 > > > > -static int xe_exec_begin(struct xe_engine *e, struct ww_acquire_ctx *ww, > > +static int xe_exec_begin(struct xe_exec_queue *q, struct ww_acquire_ctx *ww, > > struct ttm_validate_buffer tv_onstack[], > > struct ttm_validate_buffer **tv, > > struct list_head *objs) > > { > > - struct xe_vm *vm = e->vm; > > + struct xe_vm *vm = q->vm; > > struct xe_vma *vma; > > LIST_HEAD(dups); > > ktime_t end = 0; > > int err = 0; > > > > *tv = NULL; > > - if (xe_vm_no_dma_fences(e->vm)) > > + if (xe_vm_no_dma_fences(q->vm)) > > return 0; > > > > retry: > > @@ -153,14 +153,14 @@ static int xe_exec_begin(struct xe_engine *e, struct ww_acquire_ctx *ww, > > return err; > > } > > > > -static void xe_exec_end(struct xe_engine *e, > > +static void xe_exec_end(struct xe_exec_queue *q, > > struct ttm_validate_buffer *tv_onstack, > > struct ttm_validate_buffer *tv, > > struct ww_acquire_ctx *ww, > > struct list_head *objs) > > { > > - if (!xe_vm_no_dma_fences(e->vm)) > > - xe_vm_unlock_dma_resv(e->vm, tv_onstack, tv, ww, objs); > > + if (!xe_vm_no_dma_fences(q->vm)) > > + xe_vm_unlock_dma_resv(q->vm, tv_onstack, tv, ww, objs); > > } > > > > int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > @@ -170,7 +170,7 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > struct drm_xe_exec *args = data; > > struct drm_xe_sync __user *syncs_user = u64_to_user_ptr(args->syncs); > > u64 __user *addresses_user = u64_to_user_ptr(args->address); > > - struct xe_engine *engine; > > + struct xe_exec_queue *q; > > struct xe_sync_entry *syncs = NULL; > > u64 addresses[XE_HW_ENGINE_MAX_INSTANCE]; > > struct ttm_validate_buffer tv_onstack[XE_ONSTACK_TV]; > > @@ -189,30 +189,30 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > > return -EINVAL; > > > > - engine = xe_engine_lookup(xef, args->engine_id); > > - if (XE_IOCTL_DBG(xe, !engine)) > > + q = xe_exec_queue_lookup(xef, args->exec_queue_id); > > + if (XE_IOCTL_DBG(xe, !q)) > > return -ENOENT; > > > > - if (XE_IOCTL_DBG(xe, engine->flags & ENGINE_FLAG_VM)) > > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_VM)) > > return -EINVAL; > > > > - if (XE_IOCTL_DBG(xe, engine->width != args->num_batch_buffer)) > > + if (XE_IOCTL_DBG(xe, q->width != args->num_batch_buffer)) > > return -EINVAL; > > > > - if (XE_IOCTL_DBG(xe, engine->flags & ENGINE_FLAG_BANNED)) { > > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_BANNED)) { > > err = -ECANCELED; > > - goto err_engine; > > + goto err_exec_queue; > > } > > > > if (args->num_syncs) { > > syncs = kcalloc(args->num_syncs, sizeof(*syncs), GFP_KERNEL); > > if (!syncs) { > > err = -ENOMEM; > > - goto err_engine; > > + goto err_exec_queue; > > } > > } > > > > - vm = engine->vm; > > + vm = q->vm; > > > > for (i = 0; i < args->num_syncs; i++) { > > err = xe_sync_entry_parse(xe, xef, &syncs[num_syncs++], > > @@ -222,9 +222,9 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > goto err_syncs; > > } > > > > - if (xe_engine_is_parallel(engine)) { > > + if (xe_exec_queue_is_parallel(q)) { > > err = __copy_from_user(addresses, addresses_user, sizeof(u64) * > > - engine->width); > > + q->width); > > if (err) { > > err = -EFAULT; > > goto err_syncs; > > @@ -294,26 +294,26 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > goto err_unlock_list; > > } > > > > - err = xe_exec_begin(engine, &ww, tv_onstack, &tv, &objs); > > + err = xe_exec_begin(q, &ww, tv_onstack, &tv, &objs); > > if (err) > > goto err_unlock_list; > > > > - if (xe_vm_is_closed_or_banned(engine->vm)) { > > + if (xe_vm_is_closed_or_banned(q->vm)) { > > drm_warn(&xe->drm, "Trying to schedule after vm is closed or banned\n"); > > err = -ECANCELED; > > - goto err_engine_end; > > + goto err_exec_queue_end; > > } > > > > - if (xe_engine_is_lr(engine) && xe_engine_ring_full(engine)) { > > + if (xe_exec_queue_is_lr(q) && xe_exec_queue_ring_full(q)) { > > err = -EWOULDBLOCK; > > - goto err_engine_end; > > + goto err_exec_queue_end; > > } > > > > - job = xe_sched_job_create(engine, xe_engine_is_parallel(engine) ? > > + job = xe_sched_job_create(q, xe_exec_queue_is_parallel(q) ? > > addresses : &args->address); > > if (IS_ERR(job)) { > > err = PTR_ERR(job); > > - goto err_engine_end; > > + goto err_exec_queue_end; > > } > > > > /* > > @@ -395,8 +395,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > xe_sync_entry_signal(&syncs[i], job, > > &job->drm.s_fence->finished); > > > > - if (xe_engine_is_lr(engine)) > > - engine->ring_ops->emit_job(job); > > + if (xe_exec_queue_is_lr(q)) > > + q->ring_ops->emit_job(job); > > xe_sched_job_push(job); > > xe_vm_reactivate_rebind(vm); > > > > @@ -412,8 +412,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > err_put_job: > > if (err) > > xe_sched_job_put(job); > > -err_engine_end: > > - xe_exec_end(engine, tv_onstack, tv, &ww, &objs); > > +err_exec_queue_end: > > + xe_exec_end(q, tv_onstack, tv, &ww, &objs); > > err_unlock_list: > > if (write_locked) > > up_write(&vm->lock); > > @@ -425,8 +425,8 @@ int xe_exec_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > for (i = 0; i < num_syncs; i++) > > xe_sync_entry_cleanup(&syncs[i]); > > kfree(syncs); > > -err_engine: > > - xe_engine_put(engine); > > +err_exec_queue: > > + xe_exec_queue_put(q); > > > > return err; > > } > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.c b/drivers/gpu/drm/xe/xe_exec_queue.c > > new file mode 100644 > > index 000000000000..49cff0dd2bc7 > > --- /dev/null > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.c > > @@ -0,0 +1,850 @@ > > +// SPDX-License-Identifier: MIT > > +/* > > + * Copyright © 2021 Intel Corporation > > + */ > > + > > +#include "xe_exec_queue.h" > > + > > +#include <linux/nospec.h> > > + > > +#include <drm/drm_device.h> > > +#include <drm/drm_file.h> > > +#include <drm/xe_drm.h> > > + > > +#include "xe_device.h" > > +#include "xe_gt.h" > > +#include "xe_hw_fence.h" > > +#include "xe_lrc.h" > > +#include "xe_macros.h" > > +#include "xe_migrate.h" > > +#include "xe_pm.h" > > +#include "xe_ring_ops_types.h" > > +#include "xe_trace.h" > > +#include "xe_vm.h" > > + > > +static struct xe_exec_queue *__xe_exec_queue_create(struct xe_device *xe, > > + struct xe_vm *vm, > > + u32 logical_mask, > > + u16 width, struct xe_hw_engine *hwe, > > + u32 flags) > > +{ > > + struct xe_exec_queue *q; > > + struct xe_gt *gt = hwe->gt; > > + int err; > > + int i; > > + > > + q = kzalloc(sizeof(*q) + sizeof(struct xe_lrc) * width, GFP_KERNEL); > > + if (!q) > > + return ERR_PTR(-ENOMEM); > > + > > + kref_init(&q->refcount); > > + q->flags = flags; > > + q->hwe = hwe; > > + q->gt = gt; > > + if (vm) > > + q->vm = xe_vm_get(vm); > > + q->class = hwe->class; > > + q->width = width; > > + q->logical_mask = logical_mask; > > + q->fence_irq = >->fence_irq[hwe->class]; > > + q->ring_ops = gt->ring_ops[hwe->class]; > > + q->ops = gt->exec_queue_ops; > > + INIT_LIST_HEAD(&q->persistent.link); > > + INIT_LIST_HEAD(&q->compute.link); > > + INIT_LIST_HEAD(&q->multi_gt_link); > > + > > + /* FIXME: Wire up to configurable default value */ > > + q->sched_props.timeslice_us = 1 * 1000; > > + q->sched_props.preempt_timeout_us = 640 * 1000; > > + > > + if (xe_exec_queue_is_parallel(q)) { > > + q->parallel.composite_fence_ctx = dma_fence_context_alloc(1); > > + q->parallel.composite_fence_seqno = XE_FENCE_INITIAL_SEQNO; > > + } > > + if (q->flags & EXEC_QUEUE_FLAG_VM) { > > + q->bind.fence_ctx = dma_fence_context_alloc(1); > > + q->bind.fence_seqno = XE_FENCE_INITIAL_SEQNO; > > + } > > + > > + for (i = 0; i < width; ++i) { > > + err = xe_lrc_init(q->lrc + i, hwe, q, vm, SZ_16K); > > + if (err) > > + goto err_lrc; > > + } > > + > > + err = q->ops->init(q); > > + if (err) > > + goto err_lrc; > > + > > + /* > > + * Normally the user vm holds an rpm ref to keep the device > > + * awake, and the context holds a ref for the vm, however for > > + * some engines we use the kernels migrate vm underneath which > > + * offers no such rpm ref. Make sure we keep a ref here, so we > > + * can perform GuC CT actions when needed. Caller is expected to > > + * have already grabbed the rpm ref outside any sensitive locks. > > + */ > > + if (q->flags & EXEC_QUEUE_FLAG_VM) > > + drm_WARN_ON(&xe->drm, !xe_device_mem_access_get_if_ongoing(xe)); > > + > > + return q; > > + > > +err_lrc: > > + for (i = i - 1; i >= 0; --i) > > + xe_lrc_finish(q->lrc + i); > > + kfree(q); > > + return ERR_PTR(err); > > +} > > + > > +struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm, > > + u32 logical_mask, u16 width, > > + struct xe_hw_engine *hwe, u32 flags) > > +{ > > + struct ww_acquire_ctx ww; > > + struct xe_exec_queue *q; > > + int err; > > + > > + if (vm) { > > + err = xe_vm_lock(vm, &ww, 0, true); > > + if (err) > > + return ERR_PTR(err); > > + } > > + q = __xe_exec_queue_create(xe, vm, logical_mask, width, hwe, flags); > > + if (vm) > > + xe_vm_unlock(vm, &ww); > > + > > + return q; > > +} > > + > > +struct xe_exec_queue *xe_exec_queue_create_class(struct xe_device *xe, struct xe_gt *gt, > > + struct xe_vm *vm, > > + enum xe_engine_class class, u32 flags) > > +{ > > + struct xe_hw_engine *hwe, *hwe0 = NULL; > > + enum xe_hw_engine_id id; > > + u32 logical_mask = 0; > > + > > + for_each_hw_engine(hwe, gt, id) { > > + if (xe_hw_engine_is_reserved(hwe)) > > + continue; > > + > > + if (hwe->class == class) { > > + logical_mask |= BIT(hwe->logical_instance); > > + if (!hwe0) > > + hwe0 = hwe; > > + } > > + } > > + > > + if (!logical_mask) > > + return ERR_PTR(-ENODEV); > > + > > + return xe_exec_queue_create(xe, vm, logical_mask, 1, hwe0, flags); > > +} > > + > > +void xe_exec_queue_destroy(struct kref *ref) > > +{ > > + struct xe_exec_queue *q = container_of(ref, struct xe_exec_queue, refcount); > > + struct xe_exec_queue *eq, *next; > > + > > + if (!(q->flags & EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD)) { > > + list_for_each_entry_safe(eq, next, &q->multi_gt_list, > > + multi_gt_link) > > + xe_exec_queue_put(eq); > > + } > > + > > + q->ops->fini(q); > > +} > > + > > +void xe_exec_queue_fini(struct xe_exec_queue *q) > > +{ > > + int i; > > + > > + for (i = 0; i < q->width; ++i) > > + xe_lrc_finish(q->lrc + i); > > + if (q->vm) > > + xe_vm_put(q->vm); > > + if (q->flags & EXEC_QUEUE_FLAG_VM) > > + xe_device_mem_access_put(gt_to_xe(q->gt)); > > + > > + kfree(q); > > +} > > + > > +struct xe_exec_queue *xe_exec_queue_lookup(struct xe_file *xef, u32 id) > > +{ > > + struct xe_exec_queue *q; > > + > > + mutex_lock(&xef->exec_queue.lock); > > + q = xa_load(&xef->exec_queue.xa, id); > > + if (q) > > + xe_exec_queue_get(q); > > + mutex_unlock(&xef->exec_queue.lock); > > + > > + return q; > > +} > > + > > +enum drm_sched_priority > > +xe_exec_queue_device_get_max_priority(struct xe_device *xe) > > +{ > > + return capable(CAP_SYS_NICE) ? DRM_SCHED_PRIORITY_HIGH : > > + DRM_SCHED_PRIORITY_NORMAL; > > +} > > + > > +static int exec_queue_set_priority(struct xe_device *xe, struct xe_exec_queue *q, > > + u64 value, bool create) > > +{ > > + if (XE_IOCTL_DBG(xe, value > DRM_SCHED_PRIORITY_HIGH)) > > + return -EINVAL; > > + > > + if (XE_IOCTL_DBG(xe, value > xe_exec_queue_device_get_max_priority(xe))) > > + return -EPERM; > > + > > + return q->ops->set_priority(q, value); > > +} > > + > > +static int exec_queue_set_timeslice(struct xe_device *xe, struct xe_exec_queue *q, > > + u64 value, bool create) > > +{ > > + if (!capable(CAP_SYS_NICE)) > > + return -EPERM; > > + > > + return q->ops->set_timeslice(q, value); > > +} > > + > > +static int exec_queue_set_preemption_timeout(struct xe_device *xe, > > + struct xe_exec_queue *q, u64 value, > > + bool create) > > +{ > > + if (!capable(CAP_SYS_NICE)) > > + return -EPERM; > > + > > + return q->ops->set_preempt_timeout(q, value); > > +} > > + > > +static int exec_queue_set_compute_mode(struct xe_device *xe, struct xe_exec_queue *q, > > + u64 value, bool create) > > +{ > > + if (XE_IOCTL_DBG(xe, !create)) > > + return -EINVAL; > > + > > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_COMPUTE_MODE)) > > + return -EINVAL; > > + > > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_VM)) > > + return -EINVAL; > > + > > + if (value) { > > + struct xe_vm *vm = q->vm; > > + int err; > > + > > + if (XE_IOCTL_DBG(xe, xe_vm_in_fault_mode(vm))) > > + return -EOPNOTSUPP; > > + > > + if (XE_IOCTL_DBG(xe, !xe_vm_in_compute_mode(vm))) > > + return -EOPNOTSUPP; > > + > > + if (XE_IOCTL_DBG(xe, q->width != 1)) > > + return -EINVAL; > > + > > + q->compute.context = dma_fence_context_alloc(1); > > + spin_lock_init(&q->compute.lock); > > + > > + err = xe_vm_add_compute_exec_queue(vm, q); > > + if (XE_IOCTL_DBG(xe, err)) > > + return err; > > + > > + q->flags |= EXEC_QUEUE_FLAG_COMPUTE_MODE; > > + q->flags &= ~EXEC_QUEUE_FLAG_PERSISTENT; > > + } > > + > > + return 0; > > +} > > + > > +static int exec_queue_set_persistence(struct xe_device *xe, struct xe_exec_queue *q, > > + u64 value, bool create) > > +{ > > + if (XE_IOCTL_DBG(xe, !create)) > > + return -EINVAL; > > + > > + if (XE_IOCTL_DBG(xe, q->flags & EXEC_QUEUE_FLAG_COMPUTE_MODE)) > > + return -EINVAL; > > + > > + if (value) > > + q->flags |= EXEC_QUEUE_FLAG_PERSISTENT; > > + else > > + q->flags &= ~EXEC_QUEUE_FLAG_PERSISTENT; > > + > > + return 0; > > +} > > + > > +static int exec_queue_set_job_timeout(struct xe_device *xe, struct xe_exec_queue *q, > > + u64 value, bool create) > > +{ > > + if (XE_IOCTL_DBG(xe, !create)) > > + return -EINVAL; > > + > > + if (!capable(CAP_SYS_NICE)) > > + return -EPERM; > > + > > + return q->ops->set_job_timeout(q, value); > > +} > > + > > +static int exec_queue_set_acc_trigger(struct xe_device *xe, struct xe_exec_queue *q, > > + u64 value, bool create) > > +{ > > + if (XE_IOCTL_DBG(xe, !create)) > > + return -EINVAL; > > + > > + if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > > + return -EINVAL; > > + > > + q->usm.acc_trigger = value; > > + > > + return 0; > > +} > > + > > +static int exec_queue_set_acc_notify(struct xe_device *xe, struct xe_exec_queue *q, > > + u64 value, bool create) > > +{ > > + if (XE_IOCTL_DBG(xe, !create)) > > + return -EINVAL; > > + > > + if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > > + return -EINVAL; > > + > > + q->usm.acc_notify = value; > > + > > + return 0; > > +} > > + > > +static int exec_queue_set_acc_granularity(struct xe_device *xe, struct xe_exec_queue *q, > > + u64 value, bool create) > > +{ > > + if (XE_IOCTL_DBG(xe, !create)) > > + return -EINVAL; > > + > > + if (XE_IOCTL_DBG(xe, !xe->info.supports_usm)) > > + return -EINVAL; > > + > > + q->usm.acc_granularity = value; > > + > > + return 0; > > +} > > + > > +typedef int (*xe_exec_queue_set_property_fn)(struct xe_device *xe, > > + struct xe_exec_queue *q, > > + u64 value, bool create); > > + > > +static const xe_exec_queue_set_property_fn exec_queue_set_property_funcs[] = { > > + [XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY] = exec_queue_set_priority, > > + [XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE] = exec_queue_set_timeslice, > > + [XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT] = exec_queue_set_preemption_timeout, > > + [XE_EXEC_QUEUE_SET_PROPERTY_COMPUTE_MODE] = exec_queue_set_compute_mode, > > + [XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE] = exec_queue_set_persistence, > > + [XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT] = exec_queue_set_job_timeout, > > + [XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER] = exec_queue_set_acc_trigger, > > + [XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY] = exec_queue_set_acc_notify, > > + [XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY] = exec_queue_set_acc_granularity, > > +}; > > + > > +static int exec_queue_user_ext_set_property(struct xe_device *xe, > > + struct xe_exec_queue *q, > > + u64 extension, > > + bool create) > > +{ > > + u64 __user *address = u64_to_user_ptr(extension); > > + struct drm_xe_ext_exec_queue_set_property ext; > > + int err; > > + u32 idx; > > + > > + err = __copy_from_user(&ext, address, sizeof(ext)); > > + if (XE_IOCTL_DBG(xe, err)) > > + return -EFAULT; > > + > > + if (XE_IOCTL_DBG(xe, ext.property >= > > + ARRAY_SIZE(exec_queue_set_property_funcs)) || > > + XE_IOCTL_DBG(xe, ext.pad)) > > + return -EINVAL; > > + > > + idx = array_index_nospec(ext.property, ARRAY_SIZE(exec_queue_set_property_funcs)); > > + return exec_queue_set_property_funcs[idx](xe, q, ext.value, create); > > +} > > + > > +typedef int (*xe_exec_queue_user_extension_fn)(struct xe_device *xe, > > + struct xe_exec_queue *q, > > + u64 extension, > > + bool create); > > + > > +static const xe_exec_queue_set_property_fn exec_queue_user_extension_funcs[] = { > > + [XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY] = exec_queue_user_ext_set_property, > > +}; > > + > > +#define MAX_USER_EXTENSIONS 16 > > +static int exec_queue_user_extensions(struct xe_device *xe, struct xe_exec_queue *q, > > + u64 extensions, int ext_number, bool create) > > +{ > > + u64 __user *address = u64_to_user_ptr(extensions); > > + struct xe_user_extension ext; > > + int err; > > + u32 idx; > > + > > + if (XE_IOCTL_DBG(xe, ext_number >= MAX_USER_EXTENSIONS)) > > + return -E2BIG; > > + > > + err = __copy_from_user(&ext, address, sizeof(ext)); > > + if (XE_IOCTL_DBG(xe, err)) > > + return -EFAULT; > > + > > + if (XE_IOCTL_DBG(xe, ext.pad) || > > + XE_IOCTL_DBG(xe, ext.name >= > > + ARRAY_SIZE(exec_queue_user_extension_funcs))) > > + return -EINVAL; > > + > > + idx = array_index_nospec(ext.name, > > + ARRAY_SIZE(exec_queue_user_extension_funcs)); > > + err = exec_queue_user_extension_funcs[idx](xe, q, extensions, create); > > + if (XE_IOCTL_DBG(xe, err)) > > + return err; > > + > > + if (ext.next_extension) > > + return exec_queue_user_extensions(xe, q, ext.next_extension, > > + ++ext_number, create); > > + > > + return 0; > > +} > > + > > +static const enum xe_engine_class user_to_xe_engine_class[] = { > > + [DRM_XE_ENGINE_CLASS_RENDER] = XE_ENGINE_CLASS_RENDER, > > + [DRM_XE_ENGINE_CLASS_COPY] = XE_ENGINE_CLASS_COPY, > > + [DRM_XE_ENGINE_CLASS_VIDEO_DECODE] = XE_ENGINE_CLASS_VIDEO_DECODE, > > + [DRM_XE_ENGINE_CLASS_VIDEO_ENHANCE] = XE_ENGINE_CLASS_VIDEO_ENHANCE, > > + [DRM_XE_ENGINE_CLASS_COMPUTE] = XE_ENGINE_CLASS_COMPUTE, > > +}; > > + > > +static struct xe_hw_engine * > > +find_hw_engine(struct xe_device *xe, > > + struct drm_xe_engine_class_instance eci) > > +{ > > + u32 idx; > > + > > + if (eci.engine_class > ARRAY_SIZE(user_to_xe_engine_class)) > > + return NULL; > > + > > + if (eci.gt_id >= xe->info.gt_count) > > + return NULL; > > + > > + idx = array_index_nospec(eci.engine_class, > > + ARRAY_SIZE(user_to_xe_engine_class)); > > + > > + return xe_gt_hw_engine(xe_device_get_gt(xe, eci.gt_id), > > + user_to_xe_engine_class[idx], > > + eci.engine_instance, true); > > +} > > + > > +static u32 bind_exec_queue_logical_mask(struct xe_device *xe, struct xe_gt *gt, > > + struct drm_xe_engine_class_instance *eci, > > + u16 width, u16 num_placements) > > +{ > > + struct xe_hw_engine *hwe; > > + enum xe_hw_engine_id id; > > + u32 logical_mask = 0; > > + > > + if (XE_IOCTL_DBG(xe, width != 1)) > > + return 0; > > + if (XE_IOCTL_DBG(xe, num_placements != 1)) > > + return 0; > > + if (XE_IOCTL_DBG(xe, eci[0].engine_instance != 0)) > > + return 0; > > + > > + eci[0].engine_class = DRM_XE_ENGINE_CLASS_COPY; > > + > > + for_each_hw_engine(hwe, gt, id) { > > + if (xe_hw_engine_is_reserved(hwe)) > > + continue; > > + > > + if (hwe->class == > > + user_to_xe_engine_class[DRM_XE_ENGINE_CLASS_COPY]) > > + logical_mask |= BIT(hwe->logical_instance); > > + } > > + > > + return logical_mask; > > +} > > + > > +static u32 calc_validate_logical_mask(struct xe_device *xe, struct xe_gt *gt, > > + struct drm_xe_engine_class_instance *eci, > > + u16 width, u16 num_placements) > > +{ > > + int len = width * num_placements; > > + int i, j, n; > > + u16 class; > > + u16 gt_id; > > + u32 return_mask = 0, prev_mask; > > + > > + if (XE_IOCTL_DBG(xe, !xe_device_guc_submission_enabled(xe) && > > + len > 1)) > > + return 0; > > + > > + for (i = 0; i < width; ++i) { > > + u32 current_mask = 0; > > + > > + for (j = 0; j < num_placements; ++j) { > > + struct xe_hw_engine *hwe; > > + > > + n = j * width + i; > > + > > + hwe = find_hw_engine(xe, eci[n]); > > + if (XE_IOCTL_DBG(xe, !hwe)) > > + return 0; > > + > > + if (XE_IOCTL_DBG(xe, xe_hw_engine_is_reserved(hwe))) > > + return 0; > > + > > + if (XE_IOCTL_DBG(xe, n && eci[n].gt_id != gt_id) || > > + XE_IOCTL_DBG(xe, n && eci[n].engine_class != class)) > > + return 0; > > + > > + class = eci[n].engine_class; > > + gt_id = eci[n].gt_id; > > + > > + if (width == 1 || !i) > > + return_mask |= BIT(eci[n].engine_instance); > > + current_mask |= BIT(eci[n].engine_instance); > > + } > > + > > + /* Parallel submissions must be logically contiguous */ > > + if (i && XE_IOCTL_DBG(xe, current_mask != prev_mask << 1)) > > + return 0; > > + > > + prev_mask = current_mask; > > + } > > + > > + return return_mask; > > +} > > + > > +int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data, > > + struct drm_file *file) > > +{ > > + struct xe_device *xe = to_xe_device(dev); > > + struct xe_file *xef = to_xe_file(file); > > + struct drm_xe_exec_queue_create *args = data; > > + struct drm_xe_engine_class_instance eci[XE_HW_ENGINE_MAX_INSTANCE]; > > + struct drm_xe_engine_class_instance __user *user_eci = > > + u64_to_user_ptr(args->instances); > > + struct xe_hw_engine *hwe; > > + struct xe_vm *vm, *migrate_vm; > > + struct xe_gt *gt; > > + struct xe_exec_queue *q = NULL; > > + u32 logical_mask; > > + u32 id; > > + u32 len; > > + int err; > > + > > + if (XE_IOCTL_DBG(xe, args->flags) || > > + XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > > + return -EINVAL; > > + > > + len = args->width * args->num_placements; > > + if (XE_IOCTL_DBG(xe, !len || len > XE_HW_ENGINE_MAX_INSTANCE)) > > + return -EINVAL; > > + > > + err = __copy_from_user(eci, user_eci, > > + sizeof(struct drm_xe_engine_class_instance) * > > + len); > > + if (XE_IOCTL_DBG(xe, err)) > > + return -EFAULT; > > + > > + if (XE_IOCTL_DBG(xe, eci[0].gt_id >= xe->info.gt_count)) > > + return -EINVAL; > > + > > + if (eci[0].engine_class == DRM_XE_ENGINE_CLASS_VM_BIND) { > > + for_each_gt(gt, xe, id) { > > + struct xe_exec_queue *new; > > + > > + if (xe_gt_is_media_type(gt)) > > + continue; > > + > > + eci[0].gt_id = gt->info.id; > > + logical_mask = bind_exec_queue_logical_mask(xe, gt, eci, > > + args->width, > > + args->num_placements); > > + if (XE_IOCTL_DBG(xe, !logical_mask)) > > + return -EINVAL; > > + > > + hwe = find_hw_engine(xe, eci[0]); > > + if (XE_IOCTL_DBG(xe, !hwe)) > > + return -EINVAL; > > + > > + /* The migration vm doesn't hold rpm ref */ > > + xe_device_mem_access_get(xe); > > + > > + migrate_vm = xe_migrate_get_vm(gt_to_tile(gt)->migrate); > > + new = xe_exec_queue_create(xe, migrate_vm, logical_mask, > > + args->width, hwe, > > + EXEC_QUEUE_FLAG_PERSISTENT | > > + EXEC_QUEUE_FLAG_VM | > > + (id ? > > + EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD : > > + 0)); > > + > > + xe_device_mem_access_put(xe); /* now held by engine */ > > + > > + xe_vm_put(migrate_vm); > > + if (IS_ERR(new)) { > > + err = PTR_ERR(new); > > + if (q) > > + goto put_exec_queue; > > + return err; > > + } > > + if (id == 0) > > + q = new; > > + else > > + list_add_tail(&new->multi_gt_list, > > + &q->multi_gt_link); > > + } > > + } else { > > + gt = xe_device_get_gt(xe, eci[0].gt_id); > > + logical_mask = calc_validate_logical_mask(xe, gt, eci, > > + args->width, > > + args->num_placements); > > + if (XE_IOCTL_DBG(xe, !logical_mask)) > > + return -EINVAL; > > + > > + hwe = find_hw_engine(xe, eci[0]); > > + if (XE_IOCTL_DBG(xe, !hwe)) > > + return -EINVAL; > > + > > + vm = xe_vm_lookup(xef, args->vm_id); > > + if (XE_IOCTL_DBG(xe, !vm)) > > + return -ENOENT; > > + > > + err = down_read_interruptible(&vm->lock); > > + if (err) { > > + xe_vm_put(vm); > > + return err; > > + } > > + > > + if (XE_IOCTL_DBG(xe, xe_vm_is_closed_or_banned(vm))) { > > + up_read(&vm->lock); > > + xe_vm_put(vm); > > + return -ENOENT; > > + } > > + > > + q = xe_exec_queue_create(xe, vm, logical_mask, > > + args->width, hwe, > > + xe_vm_no_dma_fences(vm) ? 0 : > > + EXEC_QUEUE_FLAG_PERSISTENT); > > + up_read(&vm->lock); > > + xe_vm_put(vm); > > + if (IS_ERR(q)) > > + return PTR_ERR(q); > > + } > > + > > + if (args->extensions) { > > + err = exec_queue_user_extensions(xe, q, args->extensions, 0, true); > > + if (XE_IOCTL_DBG(xe, err)) > > + goto put_exec_queue; > > + } > > + > > + if (XE_IOCTL_DBG(xe, q->vm && xe_vm_in_compute_mode(q->vm) != > > + !!(q->flags & EXEC_QUEUE_FLAG_COMPUTE_MODE))) { > > + err = -EOPNOTSUPP; > > + goto put_exec_queue; > > + } > > + > > + q->persistent.xef = xef; > > + > > + mutex_lock(&xef->exec_queue.lock); > > + err = xa_alloc(&xef->exec_queue.xa, &id, q, xa_limit_32b, GFP_KERNEL); > > + mutex_unlock(&xef->exec_queue.lock); > > + if (err) > > + goto put_exec_queue; > > + > > + args->exec_queue_id = id; > > + > > + return 0; > > + > > +put_exec_queue: > > + xe_exec_queue_kill(q); > > + xe_exec_queue_put(q); > > + return err; > > +} > > + > > +int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data, > > + struct drm_file *file) > > +{ > > + struct xe_device *xe = to_xe_device(dev); > > + struct xe_file *xef = to_xe_file(file); > > + struct drm_xe_exec_queue_get_property *args = data; > > + struct xe_exec_queue *q; > > + int ret; > > + > > + if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > > + return -EINVAL; > > + > > + q = xe_exec_queue_lookup(xef, args->exec_queue_id); > > + if (XE_IOCTL_DBG(xe, !q)) > > + return -ENOENT; > > + > > + switch (args->property) { > > + case XE_EXEC_QUEUE_GET_PROPERTY_BAN: > > + args->value = !!(q->flags & EXEC_QUEUE_FLAG_BANNED); > > + ret = 0; > > + break; > > + default: > > + ret = -EINVAL; > > + } > > + > > + xe_exec_queue_put(q); > > + > > + return ret; > > +} > > + > > +static void exec_queue_kill_compute(struct xe_exec_queue *q) > > +{ > > + if (!xe_vm_in_compute_mode(q->vm)) > > + return; > > + > > + down_write(&q->vm->lock); > > + list_del(&q->compute.link); > > + --q->vm->preempt.num_engines; > > + if (q->compute.pfence) { > > + dma_fence_enable_sw_signaling(q->compute.pfence); > > + dma_fence_put(q->compute.pfence); > > + q->compute.pfence = NULL; > > + } > > + up_write(&q->vm->lock); > > +} > > + > > +/** > > + * xe_exec_queue_is_lr() - Whether an exec_queue is long-running > > + * @q: The exec_queue > > + * > > + * Return: True if the exec_queue is long-running, false otherwise. > > + */ > > +bool xe_exec_queue_is_lr(struct xe_exec_queue *q) > > +{ > > + return q->vm && xe_vm_no_dma_fences(q->vm) && > > + !(q->flags & EXEC_QUEUE_FLAG_VM); > > +} > > + > > +static s32 xe_exec_queue_num_job_inflight(struct xe_exec_queue *q) > > +{ > > + return q->lrc->fence_ctx.next_seqno - xe_lrc_seqno(q->lrc) - 1; > > +} > > + > > +/** > > + * xe_exec_queue_ring_full() - Whether an exec_queue's ring is full > > + * @q: The exec_queue > > + * > > + * Return: True if the exec_queue's ring is full, false otherwise. > > + */ > > +bool xe_exec_queue_ring_full(struct xe_exec_queue *q) > > +{ > > + struct xe_lrc *lrc = q->lrc; > > + s32 max_job = lrc->ring.size / MAX_JOB_SIZE_BYTES; > > + > > + return xe_exec_queue_num_job_inflight(q) >= max_job; > > +} > > + > > +/** > > + * xe_exec_queue_is_idle() - Whether an exec_queue is idle. > > + * @q: The exec_queue > > + * > > + * FIXME: Need to determine what to use as the short-lived > > + * timeline lock for the exec_queues, so that the return value > > + * of this function becomes more than just an advisory > > + * snapshot in time. The timeline lock must protect the > > + * seqno from racing submissions on the same exec_queue. > > + * Typically vm->resv, but user-created timeline locks use the migrate vm > > + * and never grabs the migrate vm->resv so we have a race there. > > + * > > + * Return: True if the exec_queue is idle, false otherwise. > > + */ > > +bool xe_exec_queue_is_idle(struct xe_exec_queue *q) > > +{ > > + if (XE_WARN_ON(xe_exec_queue_is_parallel(q))) > > + return false; > > + > > + return xe_lrc_seqno(&q->lrc[0]) == > > + q->lrc[0].fence_ctx.next_seqno - 1; > > +} > > + > > +void xe_exec_queue_kill(struct xe_exec_queue *q) > > +{ > > + struct xe_exec_queue *eq = q, *next; > > + > > + list_for_each_entry_safe(eq, next, &eq->multi_gt_list, > > + multi_gt_link) { > > + q->ops->kill(eq); > > + exec_queue_kill_compute(eq); > > + } > > + > > + q->ops->kill(q); > > + exec_queue_kill_compute(q); > > +} > > + > > +int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data, > > + struct drm_file *file) > > +{ > > + struct xe_device *xe = to_xe_device(dev); > > + struct xe_file *xef = to_xe_file(file); > > + struct drm_xe_exec_queue_destroy *args = data; > > + struct xe_exec_queue *q; > > + > > + if (XE_IOCTL_DBG(xe, args->pad) || > > + XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > > + return -EINVAL; > > + > > + mutex_lock(&xef->exec_queue.lock); > > + q = xa_erase(&xef->exec_queue.xa, args->exec_queue_id); > > + mutex_unlock(&xef->exec_queue.lock); > > + if (XE_IOCTL_DBG(xe, !q)) > > + return -ENOENT; > > + > > + if (!(q->flags & EXEC_QUEUE_FLAG_PERSISTENT)) > > + xe_exec_queue_kill(q); > > + else > > + xe_device_add_persistent_exec_queues(xe, q); > > + > > + trace_xe_exec_queue_close(q); > > + xe_exec_queue_put(q); > > + > > + return 0; > > +} > > + > > +int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data, > > + struct drm_file *file) > > +{ > > + struct xe_device *xe = to_xe_device(dev); > > + struct xe_file *xef = to_xe_file(file); > > + struct drm_xe_exec_queue_set_property *args = data; > > + struct xe_exec_queue *q; > > + int ret; > > + u32 idx; > > + > > + if (XE_IOCTL_DBG(xe, args->reserved[0] || args->reserved[1])) > > + return -EINVAL; > > + > > + q = xe_exec_queue_lookup(xef, args->exec_queue_id); > > + if (XE_IOCTL_DBG(xe, !q)) > > + return -ENOENT; > > + > > + if (XE_IOCTL_DBG(xe, args->property >= > > + ARRAY_SIZE(exec_queue_set_property_funcs))) { > > + ret = -EINVAL; > > + goto out; > > + } > > + > > + idx = array_index_nospec(args->property, > > + ARRAY_SIZE(exec_queue_set_property_funcs)); > > + ret = exec_queue_set_property_funcs[idx](xe, q, args->value, false); > > + if (XE_IOCTL_DBG(xe, ret)) > > + goto out; > > + > > + if (args->extensions) > > + ret = exec_queue_user_extensions(xe, q, args->extensions, 0, > > + false); > > +out: > > + xe_exec_queue_put(q); > > + > > + return ret; > > +} > > diff --git a/drivers/gpu/drm/xe/xe_exec_queue.h b/drivers/gpu/drm/xe/xe_exec_queue.h > > new file mode 100644 > > index 000000000000..024bc26a7006 > > --- /dev/null > > +++ b/drivers/gpu/drm/xe/xe_exec_queue.h > > @@ -0,0 +1,63 @@ > > +/* SPDX-License-Identifier: MIT */ > > +/* > > + * Copyright © 2021 Intel Corporation > > + */ > > + > > +#ifndef _XE_EXEC_QUEUE_H_ > > +#define _XE_EXEC_QUEUE_H_ > > + > > +#include "xe_exec_queue_types.h" > > +#include "xe_vm_types.h" > > + > > +struct drm_device; > > +struct drm_file; > > +struct xe_device; > > +struct xe_file; > > + > > +struct xe_exec_queue *xe_exec_queue_create(struct xe_device *xe, struct xe_vm *vm, > > + u32 logical_mask, u16 width, > > + struct xe_hw_engine *hw_engine, u32 flags); > > +struct xe_exec_queue *xe_exec_queue_create_class(struct xe_device *xe, struct xe_gt *gt, > > + struct xe_vm *vm, > > + enum xe_engine_class class, u32 flags); > > + > > +void xe_exec_queue_fini(struct xe_exec_queue *q); > > +void xe_exec_queue_destroy(struct kref *ref); > > + > > +struct xe_exec_queue *xe_exec_queue_lookup(struct xe_file *xef, u32 id); > > + > > +static inline struct xe_exec_queue *xe_exec_queue_get(struct xe_exec_queue *q) > > +{ > > + kref_get(&q->refcount); > > + return q; > > +} > > + > > +static inline void xe_exec_queue_put(struct xe_exec_queue *q) > > +{ > > + kref_put(&q->refcount, xe_exec_queue_destroy); > > +} > > + > > +static inline bool xe_exec_queue_is_parallel(struct xe_exec_queue *q) > > +{ > > + return q->width > 1; > > +} > > + > > +bool xe_exec_queue_is_lr(struct xe_exec_queue *q); > > + > > +bool xe_exec_queue_ring_full(struct xe_exec_queue *q); > > + > > +bool xe_exec_queue_is_idle(struct xe_exec_queue *q); > > + > > +void xe_exec_queue_kill(struct xe_exec_queue *q); > > + > > +int xe_exec_queue_create_ioctl(struct drm_device *dev, void *data, > > + struct drm_file *file); > > +int xe_exec_queue_destroy_ioctl(struct drm_device *dev, void *data, > > + struct drm_file *file); > > +int xe_exec_queue_set_property_ioctl(struct drm_device *dev, void *data, > > + struct drm_file *file); > > +int xe_exec_queue_get_property_ioctl(struct drm_device *dev, void *data, > > + struct drm_file *file); > > +enum drm_sched_priority xe_exec_queue_device_get_max_priority(struct xe_device *xe); > > + > > +#endif > > diff --git a/drivers/gpu/drm/xe/xe_engine_types.h b/drivers/gpu/drm/xe/xe_exec_queue_types.h > > similarity index 52% > > rename from drivers/gpu/drm/xe/xe_engine_types.h > > rename to drivers/gpu/drm/xe/xe_exec_queue_types.h > > index 7aa5d9ef7896..e3ae11b63e4a 100644 > > --- a/drivers/gpu/drm/xe/xe_engine_types.h > > +++ b/drivers/gpu/drm/xe/xe_exec_queue_types.h > > @@ -3,8 +3,8 @@ > > * Copyright © 2022 Intel Corporation > > */ > > > > -#ifndef _XE_ENGINE_TYPES_H_ > > -#define _XE_ENGINE_TYPES_H_ > > +#ifndef _XE_EXEC_QUEUE_TYPES_H_ > > +#define _XE_EXEC_QUEUE_TYPES_H_ > > > > #include <linux/kref.h> > > > > @@ -14,20 +14,20 @@ > > #include "xe_hw_fence_types.h" > > #include "xe_lrc_types.h" > > > > -struct xe_execlist_engine; > > +struct xe_execlist_exec_queue; > > struct xe_gt; > > -struct xe_guc_engine; > > +struct xe_guc_exec_queue; > > struct xe_hw_engine; > > struct xe_vm; > > > > /** > > - * struct xe_engine - Submission engine > > + * struct xe_exec_queue - Execution queue > > * > > * Contains all state necessary for submissions. Can either be a user object or > > * a kernel object. > > */ > > -struct xe_engine { > > - /** @gt: graphics tile this engine can submit to */ > > +struct xe_exec_queue { > > + /** @gt: graphics tile this exec queue can submit to */ > > struct xe_gt *gt; > > /** > > * @hwe: A hardware of the same class. May (physical engine) or may not > > @@ -35,34 +35,34 @@ struct xe_engine { > > * really be used for submissions. > > */ > > struct xe_hw_engine *hwe; > > - /** @refcount: ref count of this engine */ > > + /** @refcount: ref count of this exec queue */ > > struct kref refcount; > > - /** @vm: VM (address space) for this engine */ > > + /** @vm: VM (address space) for this exec queue */ > > struct xe_vm *vm; > > - /** @class: class of this engine */ > > + /** @class: class of this exec queue */ > > enum xe_engine_class class; > > /** > > - * @logical_mask: logical mask of where job submitted to engine can run > > + * @logical_mask: logical mask of where job submitted to exec queue can run > > */ > > u32 logical_mask; > > - /** @name: name of this engine */ > > + /** @name: name of this exec queue */ > > char name[MAX_FENCE_NAME_LEN]; > > - /** @width: width (number BB submitted per exec) of this engine */ > > + /** @width: width (number BB submitted per exec) of this exec queue */ > > u16 width; > > /** @fence_irq: fence IRQ used to signal job completion */ > > struct xe_hw_fence_irq *fence_irq; > > > > -#define ENGINE_FLAG_BANNED BIT(0) > > -#define ENGINE_FLAG_KERNEL BIT(1) > > -#define ENGINE_FLAG_PERSISTENT BIT(2) > > -#define ENGINE_FLAG_COMPUTE_MODE BIT(3) > > -/* Caller needs to hold rpm ref when creating engine with ENGINE_FLAG_VM */ > > -#define ENGINE_FLAG_VM BIT(4) > > -#define ENGINE_FLAG_BIND_ENGINE_CHILD BIT(5) > > -#define ENGINE_FLAG_WA BIT(6) > > +#define EXEC_QUEUE_FLAG_BANNED BIT(0) > > +#define EXEC_QUEUE_FLAG_KERNEL BIT(1) > > +#define EXEC_QUEUE_FLAG_PERSISTENT BIT(2) > > +#define EXEC_QUEUE_FLAG_COMPUTE_MODE BIT(3) > > +/* Caller needs to hold rpm ref when creating engine with EXEC_QUEUE_FLAG_VM */ > > +#define EXEC_QUEUE_FLAG_VM BIT(4) > > +#define EXEC_QUEUE_FLAG_BIND_ENGINE_CHILD BIT(5) > > +#define EXEC_QUEUE_FLAG_WA BIT(6) > > > > /** > > - * @flags: flags for this engine, should statically setup aside from ban > > + * @flags: flags for this exec queue, should statically setup aside from ban > > * bit > > */ > > unsigned long flags; > > @@ -75,19 +75,19 @@ struct xe_engine { > > }; > > > > union { > > - /** @execlist: execlist backend specific state for engine */ > > - struct xe_execlist_engine *execlist; > > - /** @guc: GuC backend specific state for engine */ > > - struct xe_guc_engine *guc; > > + /** @execlist: execlist backend specific state for exec queue */ > > + struct xe_execlist_exec_queue *execlist; > > + /** @guc: GuC backend specific state for exec queue */ > > + struct xe_guc_exec_queue *guc; > > }; > > > > /** > > - * @persistent: persistent engine state > > + * @persistent: persistent exec queue state > > */ > > struct { > > - /** @xef: file which this engine belongs to */ > > + /** @xef: file which this exec queue belongs to */ > > struct xe_file *xef; > > - /** @link: link in list of persistent engines */ > > + /** @link: link in list of persistent exec queues */ > > struct list_head link; > > } persistent; > > > > @@ -144,53 +144,53 @@ struct xe_engine { > > u32 acc_granularity; > > } usm; > > > > - /** @ops: submission backend engine operations */ > > - const struct xe_engine_ops *ops; > > + /** @ops: submission backend exec queue operations */ > > + const struct xe_exec_queue_ops *ops; > > > > - /** @ring_ops: ring operations for this engine */ > > + /** @ring_ops: ring operations for this exec queue */ > > const struct xe_ring_ops *ring_ops; > > - /** @entity: DRM sched entity for this engine (1 to 1 relationship) */ > > + /** @entity: DRM sched entity for this exec queue (1 to 1 relationship) */ > > struct drm_sched_entity *entity; > > - /** @lrc: logical ring context for this engine */ > > + /** @lrc: logical ring context for this exec queue */ > > struct xe_lrc lrc[]; > > }; > > > > /** > > - * struct xe_engine_ops - Submission backend engine operations > > + * struct xe_exec_queue_ops - Submission backend exec queue operations > > */ > > -struct xe_engine_ops { > > - /** @init: Initialize engine for submission backend */ > > - int (*init)(struct xe_engine *e); > > +struct xe_exec_queue_ops { > > + /** @init: Initialize exec queue for submission backend */ > > + int (*init)(struct xe_exec_queue *q); > > /** @kill: Kill inflight submissions for backend */ > > - void (*kill)(struct xe_engine *e); > > - /** @fini: Fini engine for submission backend */ > > - void (*fini)(struct xe_engine *e); > > - /** @set_priority: Set priority for engine */ > > - int (*set_priority)(struct xe_engine *e, > > + void (*kill)(struct xe_exec_queue *q); > > + /** @fini: Fini exec queue for submission backend */ > > + void (*fini)(struct xe_exec_queue *q); > > + /** @set_priority: Set priority for exec queue */ > > + int (*set_priority)(struct xe_exec_queue *q, > > enum drm_sched_priority priority); > > - /** @set_timeslice: Set timeslice for engine */ > > - int (*set_timeslice)(struct xe_engine *e, u32 timeslice_us); > > - /** @set_preempt_timeout: Set preemption timeout for engine */ > > - int (*set_preempt_timeout)(struct xe_engine *e, u32 preempt_timeout_us); > > - /** @set_job_timeout: Set job timeout for engine */ > > - int (*set_job_timeout)(struct xe_engine *e, u32 job_timeout_ms); > > + /** @set_timeslice: Set timeslice for exec queue */ > > + int (*set_timeslice)(struct xe_exec_queue *q, u32 timeslice_us); > > + /** @set_preempt_timeout: Set preemption timeout for exec queue */ > > + int (*set_preempt_timeout)(struct xe_exec_queue *q, u32 preempt_timeout_us); > > + /** @set_job_timeout: Set job timeout for exec queue */ > > + int (*set_job_timeout)(struct xe_exec_queue *q, u32 job_timeout_ms); > > /** > > - * @suspend: Suspend engine from executing, allowed to be called > > + * @suspend: Suspend exec queue from executing, allowed to be called > > * multiple times in a row before resume with the caveat that > > * suspend_wait returns before calling suspend again. > > */ > > - int (*suspend)(struct xe_engine *e); > > + int (*suspend)(struct xe_exec_queue *q); > > /** > > - * @suspend_wait: Wait for an engine to suspend executing, should be > > + * @suspend_wait: Wait for an exec queue to suspend executing, should be > > * call after suspend. > > */ > > - void (*suspend_wait)(struct xe_engine *e); > > + void (*suspend_wait)(struct xe_exec_queue *q); > > /** > > - * @resume: Resume engine execution, engine must be in a suspended > > + * @resume: Resume exec queue execution, exec queue must be in a suspended > > * state and dma fence returned from most recent suspend call must be > > * signalled when this function is called. > > */ > > - void (*resume)(struct xe_engine *e); > > + void (*resume)(struct xe_exec_queue *q); > > }; > > > > #endif > > diff --git a/drivers/gpu/drm/xe/xe_execlist.c b/drivers/gpu/drm/xe/xe_execlist.c > > index 0f9d919405b0..8ef98c7fd8e2 100644 > > --- a/drivers/gpu/drm/xe/xe_execlist.c > > +++ b/drivers/gpu/drm/xe/xe_execlist.c > > @@ -14,7 +14,7 @@ > > #include "regs/xe_regs.h" > > #include "xe_bo.h" > > #include "xe_device.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_gt.h" > > #include "xe_hw_fence.h" > > #include "xe_lrc.h" > > @@ -91,7 +91,7 @@ static void __start_lrc(struct xe_hw_engine *hwe, struct xe_lrc *lrc, > > } > > > > static void __xe_execlist_port_start(struct xe_execlist_port *port, > > - struct xe_execlist_engine *exl) > > + struct xe_execlist_exec_queue *exl) > > { > > struct xe_device *xe = gt_to_xe(port->hwe->gt); > > int max_ctx = FIELD_MAX(GEN11_SW_CTX_ID); > > @@ -109,7 +109,7 @@ static void __xe_execlist_port_start(struct xe_execlist_port *port, > > port->last_ctx_id = 1; > > } > > > > - __start_lrc(port->hwe, exl->engine->lrc, port->last_ctx_id); > > + __start_lrc(port->hwe, exl->q->lrc, port->last_ctx_id); > > port->running_exl = exl; > > exl->has_run = true; > > } > > @@ -128,16 +128,16 @@ static void __xe_execlist_port_idle(struct xe_execlist_port *port) > > port->running_exl = NULL; > > } > > > > -static bool xe_execlist_is_idle(struct xe_execlist_engine *exl) > > +static bool xe_execlist_is_idle(struct xe_execlist_exec_queue *exl) > > { > > - struct xe_lrc *lrc = exl->engine->lrc; > > + struct xe_lrc *lrc = exl->q->lrc; > > > > return lrc->ring.tail == lrc->ring.old_tail; > > } > > > > static void __xe_execlist_port_start_next_active(struct xe_execlist_port *port) > > { > > - struct xe_execlist_engine *exl = NULL; > > + struct xe_execlist_exec_queue *exl = NULL; > > int i; > > > > xe_execlist_port_assert_held(port); > > @@ -145,7 +145,7 @@ static void __xe_execlist_port_start_next_active(struct xe_execlist_port *port) > > for (i = ARRAY_SIZE(port->active) - 1; i >= 0; i--) { > > while (!list_empty(&port->active[i])) { > > exl = list_first_entry(&port->active[i], > > - struct xe_execlist_engine, > > + struct xe_execlist_exec_queue, > > active_link); > > list_del(&exl->active_link); > > > > @@ -208,7 +208,7 @@ static void xe_execlist_port_wake_locked(struct xe_execlist_port *port, > > __xe_execlist_port_start_next_active(port); > > } > > > > -static void xe_execlist_make_active(struct xe_execlist_engine *exl) > > +static void xe_execlist_make_active(struct xe_execlist_exec_queue *exl) > > { > > struct xe_execlist_port *port = exl->port; > > enum drm_sched_priority priority = exl->entity.priority; > > @@ -293,10 +293,10 @@ static struct dma_fence * > > execlist_run_job(struct drm_sched_job *drm_job) > > { > > struct xe_sched_job *job = to_xe_sched_job(drm_job); > > - struct xe_engine *e = job->engine; > > - struct xe_execlist_engine *exl = job->engine->execlist; > > + struct xe_exec_queue *q = job->q; > > + struct xe_execlist_exec_queue *exl = job->q->execlist; > > > > - e->ring_ops->emit_job(job); > > + q->ring_ops->emit_job(job); > > xe_execlist_make_active(exl); > > > > return dma_fence_get(job->fence); > > @@ -314,11 +314,11 @@ static const struct drm_sched_backend_ops drm_sched_ops = { > > .free_job = execlist_job_free, > > }; > > > > -static int execlist_engine_init(struct xe_engine *e) > > +static int execlist_exec_queue_init(struct xe_exec_queue *q) > > { > > struct drm_gpu_scheduler *sched; > > - struct xe_execlist_engine *exl; > > - struct xe_device *xe = gt_to_xe(e->gt); > > + struct xe_execlist_exec_queue *exl; > > + struct xe_device *xe = gt_to_xe(q->gt); > > int err; > > > > XE_WARN_ON(xe_device_guc_submission_enabled(xe)); > > @@ -329,14 +329,14 @@ static int execlist_engine_init(struct xe_engine *e) > > if (!exl) > > return -ENOMEM; > > > > - exl->engine = e; > > + exl->q = q; > > > > err = drm_sched_init(&exl->sched, &drm_sched_ops, NULL, > > - e->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, > > + q->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, > > XE_SCHED_HANG_LIMIT, XE_SCHED_JOB_TIMEOUT, > > - NULL, NULL, e->hwe->name, > > + NULL, NULL, q->hwe->name, > > DRM_SCHED_POLICY_SINGLE_ENTITY, > > - gt_to_xe(e->gt)->drm.dev); > > + gt_to_xe(q->gt)->drm.dev); > > if (err) > > goto err_free; > > > > @@ -346,30 +346,30 @@ static int execlist_engine_init(struct xe_engine *e) > > if (err) > > goto err_sched; > > > > - exl->port = e->hwe->exl_port; > > + exl->port = q->hwe->exl_port; > > exl->has_run = false; > > exl->active_priority = DRM_SCHED_PRIORITY_UNSET; > > - e->execlist = exl; > > - e->entity = &exl->entity; > > + q->execlist = exl; > > + q->entity = &exl->entity; > > > > - switch (e->class) { > > + switch (q->class) { > > case XE_ENGINE_CLASS_RENDER: > > - sprintf(e->name, "rcs%d", ffs(e->logical_mask) - 1); > > + sprintf(q->name, "rcs%d", ffs(q->logical_mask) - 1); > > break; > > case XE_ENGINE_CLASS_VIDEO_DECODE: > > - sprintf(e->name, "vcs%d", ffs(e->logical_mask) - 1); > > + sprintf(q->name, "vcs%d", ffs(q->logical_mask) - 1); > > break; > > case XE_ENGINE_CLASS_VIDEO_ENHANCE: > > - sprintf(e->name, "vecs%d", ffs(e->logical_mask) - 1); > > + sprintf(q->name, "vecs%d", ffs(q->logical_mask) - 1); > > break; > > case XE_ENGINE_CLASS_COPY: > > - sprintf(e->name, "bcs%d", ffs(e->logical_mask) - 1); > > + sprintf(q->name, "bcs%d", ffs(q->logical_mask) - 1); > > break; > > case XE_ENGINE_CLASS_COMPUTE: > > - sprintf(e->name, "ccs%d", ffs(e->logical_mask) - 1); > > + sprintf(q->name, "ccs%d", ffs(q->logical_mask) - 1); > > break; > > default: > > - XE_WARN_ON(e->class); > > + XE_WARN_ON(q->class); > > } > > > > return 0; > > @@ -381,96 +381,96 @@ static int execlist_engine_init(struct xe_engine *e) > > return err; > > } > > > > -static void execlist_engine_fini_async(struct work_struct *w) > > +static void execlist_exec_queue_fini_async(struct work_struct *w) > > { > > - struct xe_execlist_engine *ee = > > - container_of(w, struct xe_execlist_engine, fini_async); > > - struct xe_engine *e = ee->engine; > > - struct xe_execlist_engine *exl = e->execlist; > > + struct xe_execlist_exec_queue *ee = > > + container_of(w, struct xe_execlist_exec_queue, fini_async); > > + struct xe_exec_queue *q = ee->q; > > + struct xe_execlist_exec_queue *exl = q->execlist; > > unsigned long flags; > > > > - XE_WARN_ON(xe_device_guc_submission_enabled(gt_to_xe(e->gt))); > > + XE_WARN_ON(xe_device_guc_submission_enabled(gt_to_xe(q->gt))); > > > > spin_lock_irqsave(&exl->port->lock, flags); > > if (WARN_ON(exl->active_priority != DRM_SCHED_PRIORITY_UNSET)) > > list_del(&exl->active_link); > > spin_unlock_irqrestore(&exl->port->lock, flags); > > > > - if (e->flags & ENGINE_FLAG_PERSISTENT) > > - xe_device_remove_persistent_engines(gt_to_xe(e->gt), e); > > + if (q->flags & EXEC_QUEUE_FLAG_PERSISTENT) > > + xe_device_remove_persistent_exec_queues(gt_to_xe(q->gt), q); > > drm_sched_entity_fini(&exl->entity); > > drm_sched_fini(&exl->sched); > > kfree(exl); > > > > - xe_engine_fini(e); > > + xe_exec_queue_fini(q); > > } > > > > -static void execlist_engine_kill(struct xe_engine *e) > > +static void execlist_exec_queue_kill(struct xe_exec_queue *q) > > { > > /* NIY */ > > } > > > > -static void execlist_engine_fini(struct xe_engine *e) > > +static void execlist_exec_queue_fini(struct xe_exec_queue *q) > > { > > - INIT_WORK(&e->execlist->fini_async, execlist_engine_fini_async); > > - queue_work(system_unbound_wq, &e->execlist->fini_async); > > + INIT_WORK(&q->execlist->fini_async, execlist_exec_queue_fini_async); > > + queue_work(system_unbound_wq, &q->execlist->fini_async); > > } > > > > -static int execlist_engine_set_priority(struct xe_engine *e, > > - enum drm_sched_priority priority) > > +static int execlist_exec_queue_set_priority(struct xe_exec_queue *q, > > + enum drm_sched_priority priority) > > { > > /* NIY */ > > return 0; > > } > > > > -static int execlist_engine_set_timeslice(struct xe_engine *e, u32 timeslice_us) > > +static int execlist_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us) > > { > > /* NIY */ > > return 0; > > } > > > > -static int execlist_engine_set_preempt_timeout(struct xe_engine *e, > > - u32 preempt_timeout_us) > > +static int execlist_exec_queue_set_preempt_timeout(struct xe_exec_queue *q, > > + u32 preempt_timeout_us) > > { > > /* NIY */ > > return 0; > > } > > > > -static int execlist_engine_set_job_timeout(struct xe_engine *e, > > - u32 job_timeout_ms) > > +static int execlist_exec_queue_set_job_timeout(struct xe_exec_queue *q, > > + u32 job_timeout_ms) > > { > > /* NIY */ > > return 0; > > } > > > > -static int execlist_engine_suspend(struct xe_engine *e) > > +static int execlist_exec_queue_suspend(struct xe_exec_queue *q) > > { > > /* NIY */ > > return 0; > > } > > > > -static void execlist_engine_suspend_wait(struct xe_engine *e) > > +static void execlist_exec_queue_suspend_wait(struct xe_exec_queue *q) > > > > { > > /* NIY */ > > } > > > > -static void execlist_engine_resume(struct xe_engine *e) > > +static void execlist_exec_queue_resume(struct xe_exec_queue *q) > > { > > /* NIY */ > > } > > > > -static const struct xe_engine_ops execlist_engine_ops = { > > - .init = execlist_engine_init, > > - .kill = execlist_engine_kill, > > - .fini = execlist_engine_fini, > > - .set_priority = execlist_engine_set_priority, > > - .set_timeslice = execlist_engine_set_timeslice, > > - .set_preempt_timeout = execlist_engine_set_preempt_timeout, > > - .set_job_timeout = execlist_engine_set_job_timeout, > > - .suspend = execlist_engine_suspend, > > - .suspend_wait = execlist_engine_suspend_wait, > > - .resume = execlist_engine_resume, > > +static const struct xe_exec_queue_ops execlist_exec_queue_ops = { > > + .init = execlist_exec_queue_init, > > + .kill = execlist_exec_queue_kill, > > + .fini = execlist_exec_queue_fini, > > + .set_priority = execlist_exec_queue_set_priority, > > + .set_timeslice = execlist_exec_queue_set_timeslice, > > + .set_preempt_timeout = execlist_exec_queue_set_preempt_timeout, > > + .set_job_timeout = execlist_exec_queue_set_job_timeout, > > + .suspend = execlist_exec_queue_suspend, > > + .suspend_wait = execlist_exec_queue_suspend_wait, > > + .resume = execlist_exec_queue_resume, > > }; > > > > int xe_execlist_init(struct xe_gt *gt) > > @@ -479,7 +479,7 @@ int xe_execlist_init(struct xe_gt *gt) > > if (xe_device_guc_submission_enabled(gt_to_xe(gt))) > > return 0; > > > > - gt->engine_ops = &execlist_engine_ops; > > + gt->exec_queue_ops = &execlist_exec_queue_ops; > > > > return 0; > > } > > diff --git a/drivers/gpu/drm/xe/xe_execlist_types.h b/drivers/gpu/drm/xe/xe_execlist_types.h > > index 05a620940209..ee1fccd4ee8b 100644 > > --- a/drivers/gpu/drm/xe/xe_execlist_types.h > > +++ b/drivers/gpu/drm/xe/xe_execlist_types.h > > @@ -13,7 +13,7 @@ > > #include <drm/gpu_scheduler.h> > > > > struct xe_hw_engine; > > -struct xe_execlist_engine; > > +struct xe_execlist_exec_queue; > > > > struct xe_execlist_port { > > struct xe_hw_engine *hwe; > > @@ -24,13 +24,13 @@ struct xe_execlist_port { > > > > u32 last_ctx_id; > > > > - struct xe_execlist_engine *running_exl; > > + struct xe_execlist_exec_queue *running_exl; > > > > struct timer_list irq_fail; > > }; > > > > -struct xe_execlist_engine { > > - struct xe_engine *engine; > > +struct xe_execlist_exec_queue { > > + struct xe_exec_queue *q; > > > > struct drm_gpu_scheduler sched; > > > > diff --git a/drivers/gpu/drm/xe/xe_gt.c b/drivers/gpu/drm/xe/xe_gt.c > > index 28bf577c7bf2..3077faa1e792 100644 > > --- a/drivers/gpu/drm/xe/xe_gt.c > > +++ b/drivers/gpu/drm/xe/xe_gt.c > > @@ -14,7 +14,7 @@ > > #include "xe_bb.h" > > #include "xe_bo.h" > > #include "xe_device.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_execlist.h" > > #include "xe_force_wake.h" > > #include "xe_ggtt.h" > > @@ -26,7 +26,7 @@ > > #include "xe_gt_sysfs.h" > > #include "xe_gt_tlb_invalidation.h" > > #include "xe_gt_topology.h" > > -#include "xe_guc_engine_types.h" > > +#include "xe_guc_exec_queue_types.h" > > #include "xe_hw_fence.h" > > #include "xe_irq.h" > > #include "xe_lrc.h" > > @@ -81,7 +81,7 @@ static void gt_fini(struct drm_device *drm, void *arg) > > > > static void gt_reset_worker(struct work_struct *w); > > > > -static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e) > > +static int emit_nop_job(struct xe_gt *gt, struct xe_exec_queue *q) > > { > > struct xe_sched_job *job; > > struct xe_bb *bb; > > @@ -94,7 +94,7 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e) > > return PTR_ERR(bb); > > > > batch_ofs = xe_bo_ggtt_addr(gt_to_tile(gt)->mem.kernel_bb_pool->bo); > > - job = xe_bb_create_wa_job(e, bb, batch_ofs); > > + job = xe_bb_create_wa_job(q, bb, batch_ofs); > > if (IS_ERR(job)) { > > xe_bb_free(bb, NULL); > > return PTR_ERR(job); > > @@ -115,9 +115,9 @@ static int emit_nop_job(struct xe_gt *gt, struct xe_engine *e) > > return 0; > > } > > > > -static int emit_wa_job(struct xe_gt *gt, struct xe_engine *e) > > +static int emit_wa_job(struct xe_gt *gt, struct xe_exec_queue *q) > > { > > - struct xe_reg_sr *sr = &e->hwe->reg_lrc; > > + struct xe_reg_sr *sr = &q->hwe->reg_lrc; > > struct xe_reg_sr_entry *entry; > > unsigned long reg; > > struct xe_sched_job *job; > > @@ -143,7 +143,7 @@ static int emit_wa_job(struct xe_gt *gt, struct xe_engine *e) > > } > > > > batch_ofs = xe_bo_ggtt_addr(gt_to_tile(gt)->mem.kernel_bb_pool->bo); > > - job = xe_bb_create_wa_job(e, bb, batch_ofs); > > + job = xe_bb_create_wa_job(q, bb, batch_ofs); > > if (IS_ERR(job)) { > > xe_bb_free(bb, NULL); > > return PTR_ERR(job); > > @@ -173,7 +173,7 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) > > int err = 0; > > > > for_each_hw_engine(hwe, gt, id) { > > - struct xe_engine *e, *nop_e; > > + struct xe_exec_queue *q, *nop_q; > > struct xe_vm *vm; > > void *default_lrc; > > > > @@ -192,58 +192,58 @@ int xe_gt_record_default_lrcs(struct xe_gt *gt) > > return -ENOMEM; > > > > vm = xe_migrate_get_vm(tile->migrate); > > - e = xe_engine_create(xe, vm, BIT(hwe->logical_instance), 1, > > - hwe, ENGINE_FLAG_WA); > > - if (IS_ERR(e)) { > > - err = PTR_ERR(e); > > - xe_gt_err(gt, "hwe %s: xe_engine_create failed (%pe)\n", > > - hwe->name, e); > > + q = xe_exec_queue_create(xe, vm, BIT(hwe->logical_instance), 1, > > + hwe, EXEC_QUEUE_FLAG_WA); > > + if (IS_ERR(q)) { > > + err = PTR_ERR(q); > > + xe_gt_err(gt, "hwe %s: xe_exec_queue_create failed (%pe)\n", > > + hwe->name, q); > > goto put_vm; > > } > > > > /* Prime golden LRC with known good state */ > > - err = emit_wa_job(gt, e); > > + err = emit_wa_job(gt, q); > > if (err) { > > xe_gt_err(gt, "hwe %s: emit_wa_job failed (%pe) guc_id=%u\n", > > - hwe->name, ERR_PTR(err), e->guc->id); > > - goto put_engine; > > + hwe->name, ERR_PTR(err), q->guc->id); > > + goto put_exec_queue; > > } > > > > - nop_e = xe_engine_create(xe, vm, BIT(hwe->logical_instance), > > - 1, hwe, ENGINE_FLAG_WA); > > - if (IS_ERR(nop_e)) { > > - err = PTR_ERR(nop_e); > > - xe_gt_err(gt, "hwe %s: nop xe_engine_create failed (%pe)\n", > > - hwe->name, nop_e); > > - goto put_engine; > > + nop_q = xe_exec_queue_create(xe, vm, BIT(hwe->logical_instance), > > + 1, hwe, EXEC_QUEUE_FLAG_WA); > > + if (IS_ERR(nop_q)) { > > + err = PTR_ERR(nop_q); > > + xe_gt_err(gt, "hwe %s: nop xe_exec_queue_create failed (%pe)\n", > > + hwe->name, nop_q); > > + goto put_exec_queue; > > } > > > > /* Switch to different LRC */ > > - err = emit_nop_job(gt, nop_e); > > + err = emit_nop_job(gt, nop_q); > > if (err) { > > xe_gt_err(gt, "hwe %s: nop emit_nop_job failed (%pe) guc_id=%u\n", > > - hwe->name, ERR_PTR(err), nop_e->guc->id); > > - goto put_nop_e; > > + hwe->name, ERR_PTR(err), nop_q->guc->id); > > + goto put_nop_q; > > } > > > > /* Reload golden LRC to record the effect of any indirect W/A */ > > - err = emit_nop_job(gt, e); > > + err = emit_nop_job(gt, q); > > if (err) { > > xe_gt_err(gt, "hwe %s: emit_nop_job failed (%pe) guc_id=%u\n", > > - hwe->name, ERR_PTR(err), e->guc->id); > > - goto put_nop_e; > > + hwe->name, ERR_PTR(err), q->guc->id); > > + goto put_nop_q; > > } > > > > xe_map_memcpy_from(xe, default_lrc, > > - &e->lrc[0].bo->vmap, > > - xe_lrc_pphwsp_offset(&e->lrc[0]), > > + &q->lrc[0].bo->vmap, > > + xe_lrc_pphwsp_offset(&q->lrc[0]), > > xe_lrc_size(xe, hwe->class)); > > > > gt->default_lrc[hwe->class] = default_lrc; > > -put_nop_e: > > - xe_engine_put(nop_e); > > -put_engine: > > - xe_engine_put(e); > > +put_nop_q: > > + xe_exec_queue_put(nop_q); > > +put_exec_queue: > > + xe_exec_queue_put(q); > > put_vm: > > xe_vm_put(vm); > > if (err) > > diff --git a/drivers/gpu/drm/xe/xe_gt_types.h b/drivers/gpu/drm/xe/xe_gt_types.h > > index 78a9fe9f0bd3..c326932e53d7 100644 > > --- a/drivers/gpu/drm/xe/xe_gt_types.h > > +++ b/drivers/gpu/drm/xe/xe_gt_types.h > > @@ -14,7 +14,7 @@ > > #include "xe_sa_types.h" > > #include "xe_uc_types.h" > > > > -struct xe_engine_ops; > > +struct xe_exec_queue_ops; > > struct xe_migrate; > > struct xe_ring_ops; > > > > @@ -269,8 +269,8 @@ struct xe_gt { > > /** @gtidle: idle properties of GT */ > > struct xe_gt_idle gtidle; > > > > - /** @engine_ops: submission backend engine operations */ > > - const struct xe_engine_ops *engine_ops; > > + /** @exec_queue_ops: submission backend exec queue operations */ > > + const struct xe_exec_queue_ops *exec_queue_ops; > > > > /** > > * @ring_ops: ring operations for this hw engine (1 per engine class) > > diff --git a/drivers/gpu/drm/xe/xe_guc_ads.c b/drivers/gpu/drm/xe/xe_guc_ads.c > > index a7da29be2e51..7d1244df959d 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_ads.c > > +++ b/drivers/gpu/drm/xe/xe_guc_ads.c > > @@ -495,7 +495,7 @@ static void guc_mmio_reg_state_init(struct xe_guc_ads *ads) > > u8 gc; > > > > /* > > - * 1. Write all MMIO entries for this engine to the table. No > > + * 1. Write all MMIO entries for this exec queue to the table. No > > * need to worry about fused-off engines and when there are > > * entries in the regset: the reg_state_list has been zero'ed > > * by xe_guc_ads_populate() > > diff --git a/drivers/gpu/drm/xe/xe_guc_ct.c b/drivers/gpu/drm/xe/xe_guc_ct.c > > index 7fb2690425f8..3d705c64b85d 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_ct.c > > +++ b/drivers/gpu/drm/xe/xe_guc_ct.c > > @@ -889,11 +889,11 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len) > > ret = xe_guc_deregister_done_handler(guc, payload, adj_len); > > break; > > case XE_GUC_ACTION_CONTEXT_RESET_NOTIFICATION: > > - ret = xe_guc_engine_reset_handler(guc, payload, adj_len); > > + ret = xe_guc_exec_queue_reset_handler(guc, payload, adj_len); > > break; > > case XE_GUC_ACTION_ENGINE_FAILURE_NOTIFICATION: > > - ret = xe_guc_engine_reset_failure_handler(guc, payload, > > - adj_len); > > + ret = xe_guc_exec_queue_reset_failure_handler(guc, payload, > > + adj_len); > > break; > > case XE_GUC_ACTION_SCHED_ENGINE_MODE_DONE: > > /* Selftest only at the moment */ > > @@ -903,8 +903,8 @@ static int process_g2h_msg(struct xe_guc_ct *ct, u32 *msg, u32 len) > > /* FIXME: Handle this */ > > break; > > case XE_GUC_ACTION_NOTIFY_MEMORY_CAT_ERROR: > > - ret = xe_guc_engine_memory_cat_error_handler(guc, payload, > > - adj_len); > > + ret = xe_guc_exec_queue_memory_cat_error_handler(guc, payload, > > + adj_len); > > break; > > case XE_GUC_ACTION_REPORT_PAGE_FAULT_REQ_DESC: > > ret = xe_guc_pagefault_handler(guc, payload, adj_len); > > diff --git a/drivers/gpu/drm/xe/xe_guc_engine_types.h b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h > > similarity index 88% > > rename from drivers/gpu/drm/xe/xe_guc_engine_types.h > > rename to drivers/gpu/drm/xe/xe_guc_exec_queue_types.h > > index 5d83132034a6..395ed3fba218 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_engine_types.h > > +++ b/drivers/gpu/drm/xe/xe_guc_exec_queue_types.h > > @@ -12,14 +12,14 @@ > > #include <drm/gpu_scheduler.h> > > > > struct dma_fence; > > -struct xe_engine; > > +struct xe_exec_queue; > > > > /** > > - * struct xe_guc_engine - GuC specific state for an xe_engine > > + * struct xe_guc_exec_queue - GuC specific state for an xe_engine > > */ > > -struct xe_guc_engine { > > +struct xe_guc_exec_queue { > > /** @engine: Backpointer to parent xe_engine */ > > - struct xe_engine *engine; > > + struct xe_exec_queue *q; > > /** @sched: GPU scheduler for this xe_engine */ > > struct drm_gpu_scheduler sched; > > /** @entity: Scheduler entity for this xe_engine */ > > @@ -43,7 +43,7 @@ struct xe_guc_engine { > > u32 wqi_head; > > /** @wqi_tail: work queue item tail */ > > u32 wqi_tail; > > - /** @id: GuC id for this xe_engine */ > > + /** @id: GuC id for this exec_queue */ > > u16 id; > > /** @suspend_wait: wait queue used to wait on pending suspends */ > > wait_queue_head_t suspend_wait; > > diff --git a/drivers/gpu/drm/xe/xe_guc_fwif.h b/drivers/gpu/drm/xe/xe_guc_fwif.h > > index 7515d7fbb723..4216a6d9e478 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_fwif.h > > +++ b/drivers/gpu/drm/xe/xe_guc_fwif.h > > @@ -69,13 +69,13 @@ struct guc_klv_generic_dw_t { > > } __packed; > > > > /* Format of the UPDATE_CONTEXT_POLICIES H2G data packet */ > > -struct guc_update_engine_policy_header { > > +struct guc_update_exec_queue_policy_header { > > u32 action; > > u32 guc_id; > > } __packed; > > > > -struct guc_update_engine_policy { > > - struct guc_update_engine_policy_header header; > > +struct guc_update_exec_queue_policy { > > + struct guc_update_exec_queue_policy_header header; > > struct guc_klv_generic_dw_t klv[GUC_CONTEXT_POLICIES_KLV_NUM_IDS]; > > } __packed; > > > > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.c b/drivers/gpu/drm/xe/xe_guc_submit.c > > index 8d2b50e03ed2..448075411191 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_submit.c > > +++ b/drivers/gpu/drm/xe/xe_guc_submit.c > > @@ -16,12 +16,12 @@ > > #include "regs/xe_lrc_layout.h" > > #include "xe_devcoredump.h" > > #include "xe_device.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_force_wake.h" > > #include "xe_gt.h" > > #include "xe_guc.h" > > #include "xe_guc_ct.h" > > -#include "xe_guc_engine_types.h" > > +#include "xe_guc_exec_queue_types.h" > > #include "xe_guc_submit_types.h" > > #include "xe_hw_engine.h" > > #include "xe_hw_fence.h" > > @@ -47,9 +47,9 @@ guc_to_xe(struct xe_guc *guc) > > } > > > > static struct xe_guc * > > -engine_to_guc(struct xe_engine *e) > > +exec_queue_to_guc(struct xe_exec_queue *q) > > { > > - return &e->gt->uc.guc; > > + return &q->gt->uc.guc; > > } > > > > /* > > @@ -57,140 +57,140 @@ engine_to_guc(struct xe_engine *e) > > * as the same time (e.g. a suspend can be happning at the same time as schedule > > * engine done being processed). > > */ > > -#define ENGINE_STATE_REGISTERED (1 << 0) > > +#define EXEC_QUEUE_STATE_REGISTERED (1 << 0) > > #define ENGINE_STATE_ENABLED (1 << 1) > > -#define ENGINE_STATE_PENDING_ENABLE (1 << 2) > > -#define ENGINE_STATE_PENDING_DISABLE (1 << 3) > > -#define ENGINE_STATE_DESTROYED (1 << 4) > > +#define EXEC_QUEUE_STATE_PENDING_ENABLE (1 << 2) > > +#define EXEC_QUEUE_STATE_PENDING_DISABLE (1 << 3) > > +#define EXEC_QUEUE_STATE_DESTROYED (1 << 4) > > #define ENGINE_STATE_SUSPENDED (1 << 5) > > -#define ENGINE_STATE_RESET (1 << 6) > > +#define EXEC_QUEUE_STATE_RESET (1 << 6) > > #define ENGINE_STATE_KILLED (1 << 7) > > > > -static bool engine_registered(struct xe_engine *e) > > +static bool exec_queue_registered(struct xe_exec_queue *q) > > { > > - return atomic_read(&e->guc->state) & ENGINE_STATE_REGISTERED; > > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_REGISTERED; > > } > > > > -static void set_engine_registered(struct xe_engine *e) > > +static void set_exec_queue_registered(struct xe_exec_queue *q) > > { > > - atomic_or(ENGINE_STATE_REGISTERED, &e->guc->state); > > + atomic_or(EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); > > } > > > > -static void clear_engine_registered(struct xe_engine *e) > > +static void clear_exec_queue_registered(struct xe_exec_queue *q) > > { > > - atomic_and(~ENGINE_STATE_REGISTERED, &e->guc->state); > > + atomic_and(~EXEC_QUEUE_STATE_REGISTERED, &q->guc->state); > > } > > > > -static bool engine_enabled(struct xe_engine *e) > > +static bool exec_queue_enabled(struct xe_exec_queue *q) > > { > > - return atomic_read(&e->guc->state) & ENGINE_STATE_ENABLED; > > + return atomic_read(&q->guc->state) & ENGINE_STATE_ENABLED; > > } > > > > -static void set_engine_enabled(struct xe_engine *e) > > +static void set_exec_queue_enabled(struct xe_exec_queue *q) > > { > > - atomic_or(ENGINE_STATE_ENABLED, &e->guc->state); > > + atomic_or(ENGINE_STATE_ENABLED, &q->guc->state); > > } > > > > -static void clear_engine_enabled(struct xe_engine *e) > > +static void clear_exec_queue_enabled(struct xe_exec_queue *q) > > { > > - atomic_and(~ENGINE_STATE_ENABLED, &e->guc->state); > > + atomic_and(~ENGINE_STATE_ENABLED, &q->guc->state); > > } > > > > -static bool engine_pending_enable(struct xe_engine *e) > > +static bool exec_queue_pending_enable(struct xe_exec_queue *q) > > { > > - return atomic_read(&e->guc->state) & ENGINE_STATE_PENDING_ENABLE; > > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_ENABLE; > > } > > > > -static void set_engine_pending_enable(struct xe_engine *e) > > +static void set_exec_queue_pending_enable(struct xe_exec_queue *q) > > { > > - atomic_or(ENGINE_STATE_PENDING_ENABLE, &e->guc->state); > > + atomic_or(EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); > > } > > > > -static void clear_engine_pending_enable(struct xe_engine *e) > > +static void clear_exec_queue_pending_enable(struct xe_exec_queue *q) > > { > > - atomic_and(~ENGINE_STATE_PENDING_ENABLE, &e->guc->state); > > + atomic_and(~EXEC_QUEUE_STATE_PENDING_ENABLE, &q->guc->state); > > } > > > > -static bool engine_pending_disable(struct xe_engine *e) > > +static bool exec_queue_pending_disable(struct xe_exec_queue *q) > > { > > - return atomic_read(&e->guc->state) & ENGINE_STATE_PENDING_DISABLE; > > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_PENDING_DISABLE; > > } > > > > -static void set_engine_pending_disable(struct xe_engine *e) > > +static void set_exec_queue_pending_disable(struct xe_exec_queue *q) > > { > > - atomic_or(ENGINE_STATE_PENDING_DISABLE, &e->guc->state); > > + atomic_or(EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); > > } > > > > -static void clear_engine_pending_disable(struct xe_engine *e) > > +static void clear_exec_queue_pending_disable(struct xe_exec_queue *q) > > { > > - atomic_and(~ENGINE_STATE_PENDING_DISABLE, &e->guc->state); > > + atomic_and(~EXEC_QUEUE_STATE_PENDING_DISABLE, &q->guc->state); > > } > > > > -static bool engine_destroyed(struct xe_engine *e) > > +static bool exec_queue_destroyed(struct xe_exec_queue *q) > > { > > - return atomic_read(&e->guc->state) & ENGINE_STATE_DESTROYED; > > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_DESTROYED; > > } > > > > -static void set_engine_destroyed(struct xe_engine *e) > > +static void set_exec_queue_destroyed(struct xe_exec_queue *q) > > { > > - atomic_or(ENGINE_STATE_DESTROYED, &e->guc->state); > > + atomic_or(EXEC_QUEUE_STATE_DESTROYED, &q->guc->state); > > } > > > > -static bool engine_banned(struct xe_engine *e) > > +static bool exec_queue_banned(struct xe_exec_queue *q) > > { > > - return (e->flags & ENGINE_FLAG_BANNED); > > + return (q->flags & EXEC_QUEUE_FLAG_BANNED); > > } > > > > -static void set_engine_banned(struct xe_engine *e) > > +static void set_exec_queue_banned(struct xe_exec_queue *q) > > { > > - e->flags |= ENGINE_FLAG_BANNED; > > + q->flags |= EXEC_QUEUE_FLAG_BANNED; > > } > > > > -static bool engine_suspended(struct xe_engine *e) > > +static bool exec_queue_suspended(struct xe_exec_queue *q) > > { > > - return atomic_read(&e->guc->state) & ENGINE_STATE_SUSPENDED; > > + return atomic_read(&q->guc->state) & ENGINE_STATE_SUSPENDED; > > } > > > > -static void set_engine_suspended(struct xe_engine *e) > > +static void set_exec_queue_suspended(struct xe_exec_queue *q) > > { > > - atomic_or(ENGINE_STATE_SUSPENDED, &e->guc->state); > > + atomic_or(ENGINE_STATE_SUSPENDED, &q->guc->state); > > } > > > > -static void clear_engine_suspended(struct xe_engine *e) > > +static void clear_exec_queue_suspended(struct xe_exec_queue *q) > > { > > - atomic_and(~ENGINE_STATE_SUSPENDED, &e->guc->state); > > + atomic_and(~ENGINE_STATE_SUSPENDED, &q->guc->state); > > } > > > > -static bool engine_reset(struct xe_engine *e) > > +static bool exec_queue_reset(struct xe_exec_queue *q) > > { > > - return atomic_read(&e->guc->state) & ENGINE_STATE_RESET; > > + return atomic_read(&q->guc->state) & EXEC_QUEUE_STATE_RESET; > > } > > > > -static void set_engine_reset(struct xe_engine *e) > > +static void set_exec_queue_reset(struct xe_exec_queue *q) > > { > > - atomic_or(ENGINE_STATE_RESET, &e->guc->state); > > + atomic_or(EXEC_QUEUE_STATE_RESET, &q->guc->state); > > } > > > > -static bool engine_killed(struct xe_engine *e) > > +static bool exec_queue_killed(struct xe_exec_queue *q) > > { > > - return atomic_read(&e->guc->state) & ENGINE_STATE_KILLED; > > + return atomic_read(&q->guc->state) & ENGINE_STATE_KILLED; > > } > > > > -static void set_engine_killed(struct xe_engine *e) > > +static void set_exec_queue_killed(struct xe_exec_queue *q) > > { > > - atomic_or(ENGINE_STATE_KILLED, &e->guc->state); > > + atomic_or(ENGINE_STATE_KILLED, &q->guc->state); > > } > > > > -static bool engine_killed_or_banned(struct xe_engine *e) > > +static bool exec_queue_killed_or_banned(struct xe_exec_queue *q) > > { > > - return engine_killed(e) || engine_banned(e); > > + return exec_queue_killed(q) || exec_queue_banned(q); > > } > > > > static void guc_submit_fini(struct drm_device *drm, void *arg) > > { > > struct xe_guc *guc = arg; > > > > - xa_destroy(&guc->submission_state.engine_lookup); > > + xa_destroy(&guc->submission_state.exec_queue_lookup); > > ida_destroy(&guc->submission_state.guc_ids); > > bitmap_free(guc->submission_state.guc_ids_bitmap); > > } > > @@ -200,7 +200,7 @@ static void guc_submit_fini(struct drm_device *drm, void *arg) > > #define GUC_ID_NUMBER_SLRC (GUC_ID_MAX - GUC_ID_NUMBER_MLRC) > > #define GUC_ID_START_MLRC GUC_ID_NUMBER_SLRC > > > > -static const struct xe_engine_ops guc_engine_ops; > > +static const struct xe_exec_queue_ops guc_exec_queue_ops; > > > > static void primelockdep(struct xe_guc *guc) > > { > > @@ -227,10 +227,10 @@ int xe_guc_submit_init(struct xe_guc *guc) > > if (!guc->submission_state.guc_ids_bitmap) > > return -ENOMEM; > > > > - gt->engine_ops = &guc_engine_ops; > > + gt->exec_queue_ops = &guc_exec_queue_ops; > > > > mutex_init(&guc->submission_state.lock); > > - xa_init(&guc->submission_state.engine_lookup); > > + xa_init(&guc->submission_state.exec_queue_lookup); > > ida_init(&guc->submission_state.guc_ids); > > > > spin_lock_init(&guc->submission_state.suspend.lock); > > @@ -245,7 +245,7 @@ int xe_guc_submit_init(struct xe_guc *guc) > > return 0; > > } > > > > -static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) > > +static int alloc_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) > > { > > int ret; > > void *ptr; > > @@ -259,11 +259,11 @@ static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) > > */ > > lockdep_assert_held(&guc->submission_state.lock); > > > > - if (xe_engine_is_parallel(e)) { > > + if (xe_exec_queue_is_parallel(q)) { > > void *bitmap = guc->submission_state.guc_ids_bitmap; > > > > ret = bitmap_find_free_region(bitmap, GUC_ID_NUMBER_MLRC, > > - order_base_2(e->width)); > > + order_base_2(q->width)); > > } else { > > ret = ida_simple_get(&guc->submission_state.guc_ids, 0, > > GUC_ID_NUMBER_SLRC, GFP_NOWAIT); > > @@ -271,12 +271,12 @@ static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) > > if (ret < 0) > > return ret; > > > > - e->guc->id = ret; > > - if (xe_engine_is_parallel(e)) > > - e->guc->id += GUC_ID_START_MLRC; > > + q->guc->id = ret; > > + if (xe_exec_queue_is_parallel(q)) > > + q->guc->id += GUC_ID_START_MLRC; > > > > - ptr = xa_store(&guc->submission_state.engine_lookup, > > - e->guc->id, e, GFP_NOWAIT); > > + ptr = xa_store(&guc->submission_state.exec_queue_lookup, > > + q->guc->id, q, GFP_NOWAIT); > > if (IS_ERR(ptr)) { > > ret = PTR_ERR(ptr); > > goto err_release; > > @@ -285,29 +285,29 @@ static int alloc_guc_id(struct xe_guc *guc, struct xe_engine *e) > > return 0; > > > > err_release: > > - ida_simple_remove(&guc->submission_state.guc_ids, e->guc->id); > > + ida_simple_remove(&guc->submission_state.guc_ids, q->guc->id); > > return ret; > > } > > > > -static void release_guc_id(struct xe_guc *guc, struct xe_engine *e) > > +static void release_guc_id(struct xe_guc *guc, struct xe_exec_queue *q) > > { > > mutex_lock(&guc->submission_state.lock); > > - xa_erase(&guc->submission_state.engine_lookup, e->guc->id); > > - if (xe_engine_is_parallel(e)) > > + xa_erase(&guc->submission_state.exec_queue_lookup, q->guc->id); > > + if (xe_exec_queue_is_parallel(q)) > > bitmap_release_region(guc->submission_state.guc_ids_bitmap, > > - e->guc->id - GUC_ID_START_MLRC, > > - order_base_2(e->width)); > > + q->guc->id - GUC_ID_START_MLRC, > > + order_base_2(q->width)); > > else > > - ida_simple_remove(&guc->submission_state.guc_ids, e->guc->id); > > + ida_simple_remove(&guc->submission_state.guc_ids, q->guc->id); > > mutex_unlock(&guc->submission_state.lock); > > } > > > > -struct engine_policy { > > +struct exec_queue_policy { > > u32 count; > > - struct guc_update_engine_policy h2g; > > + struct guc_update_exec_queue_policy h2g; > > }; > > > > -static u32 __guc_engine_policy_action_size(struct engine_policy *policy) > > +static u32 __guc_exec_queue_policy_action_size(struct exec_queue_policy *policy) > > { > > size_t bytes = sizeof(policy->h2g.header) + > > (sizeof(policy->h2g.klv[0]) * policy->count); > > @@ -315,8 +315,8 @@ static u32 __guc_engine_policy_action_size(struct engine_policy *policy) > > return bytes / sizeof(u32); > > } > > > > -static void __guc_engine_policy_start_klv(struct engine_policy *policy, > > - u16 guc_id) > > +static void __guc_exec_queue_policy_start_klv(struct exec_queue_policy *policy, > > + u16 guc_id) > > { > > policy->h2g.header.action = > > XE_GUC_ACTION_HOST2GUC_UPDATE_CONTEXT_POLICIES; > > @@ -324,8 +324,8 @@ static void __guc_engine_policy_start_klv(struct engine_policy *policy, > > policy->count = 0; > > } > > > > -#define MAKE_ENGINE_POLICY_ADD(func, id) \ > > -static void __guc_engine_policy_add_##func(struct engine_policy *policy, \ > > +#define MAKE_EXEC_QUEUE_POLICY_ADD(func, id) \ > > +static void __guc_exec_queue_policy_add_##func(struct exec_queue_policy *policy, \ > > u32 data) \ > > { \ > > XE_WARN_ON(policy->count >= GUC_CONTEXT_POLICIES_KLV_NUM_IDS); \ > > @@ -338,10 +338,10 @@ static void __guc_engine_policy_add_##func(struct engine_policy *policy, \ > > policy->count++; \ > > } > > > > -MAKE_ENGINE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM) > > -MAKE_ENGINE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT) > > -MAKE_ENGINE_POLICY_ADD(priority, SCHEDULING_PRIORITY) > > -#undef MAKE_ENGINE_POLICY_ADD > > +MAKE_EXEC_QUEUE_POLICY_ADD(execution_quantum, EXECUTION_QUANTUM) > > +MAKE_EXEC_QUEUE_POLICY_ADD(preemption_timeout, PREEMPTION_TIMEOUT) > > +MAKE_EXEC_QUEUE_POLICY_ADD(priority, SCHEDULING_PRIORITY) > > +#undef MAKE_EXEC_QUEUE_POLICY_ADD > > > > static const int drm_sched_prio_to_guc[] = { > > [DRM_SCHED_PRIORITY_MIN] = GUC_CLIENT_PRIORITY_NORMAL, > > @@ -350,33 +350,33 @@ static const int drm_sched_prio_to_guc[] = { > > [DRM_SCHED_PRIORITY_KERNEL] = GUC_CLIENT_PRIORITY_KMD_HIGH, > > }; > > > > -static void init_policies(struct xe_guc *guc, struct xe_engine *e) > > +static void init_policies(struct xe_guc *guc, struct xe_exec_queue *q) > > { > > - struct engine_policy policy; > > - enum drm_sched_priority prio = e->entity->priority; > > - u32 timeslice_us = e->sched_props.timeslice_us; > > - u32 preempt_timeout_us = e->sched_props.preempt_timeout_us; > > + struct exec_queue_policy policy; > > + enum drm_sched_priority prio = q->entity->priority; > > + u32 timeslice_us = q->sched_props.timeslice_us; > > + u32 preempt_timeout_us = q->sched_props.preempt_timeout_us; > > > > - XE_WARN_ON(!engine_registered(e)); > > + XE_WARN_ON(!exec_queue_registered(q)); > > > > - __guc_engine_policy_start_klv(&policy, e->guc->id); > > - __guc_engine_policy_add_priority(&policy, drm_sched_prio_to_guc[prio]); > > - __guc_engine_policy_add_execution_quantum(&policy, timeslice_us); > > - __guc_engine_policy_add_preemption_timeout(&policy, preempt_timeout_us); > > + __guc_exec_queue_policy_start_klv(&policy, q->guc->id); > > + __guc_exec_queue_policy_add_priority(&policy, drm_sched_prio_to_guc[prio]); > > + __guc_exec_queue_policy_add_execution_quantum(&policy, timeslice_us); > > + __guc_exec_queue_policy_add_preemption_timeout(&policy, preempt_timeout_us); > > > > xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, > > - __guc_engine_policy_action_size(&policy), 0, 0); > > + __guc_exec_queue_policy_action_size(&policy), 0, 0); > > } > > > > -static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_engine *e) > > +static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_exec_queue *q) > > { > > - struct engine_policy policy; > > + struct exec_queue_policy policy; > > > > - __guc_engine_policy_start_klv(&policy, e->guc->id); > > - __guc_engine_policy_add_preemption_timeout(&policy, 1); > > + __guc_exec_queue_policy_start_klv(&policy, q->guc->id); > > + __guc_exec_queue_policy_add_preemption_timeout(&policy, 1); > > > > xe_guc_ct_send(&guc->ct, (u32 *)&policy.h2g, > > - __guc_engine_policy_action_size(&policy), 0, 0); > > + __guc_exec_queue_policy_action_size(&policy), 0, 0); > > } > > > > #define parallel_read(xe_, map_, field_) \ > > @@ -387,7 +387,7 @@ static void set_min_preemption_timeout(struct xe_guc *guc, struct xe_engine *e) > > field_, val_) > > > > static void __register_mlrc_engine(struct xe_guc *guc, > > - struct xe_engine *e, > > + struct xe_exec_queue *q, > > struct guc_ctxt_registration_info *info) > > { > > #define MAX_MLRC_REG_SIZE (13 + XE_HW_ENGINE_MAX_INSTANCE * 2) > > @@ -395,7 +395,7 @@ static void __register_mlrc_engine(struct xe_guc *guc, > > int len = 0; > > int i; > > > > - XE_WARN_ON(!xe_engine_is_parallel(e)); > > + XE_WARN_ON(!xe_exec_queue_is_parallel(q)); > > > > action[len++] = XE_GUC_ACTION_REGISTER_CONTEXT_MULTI_LRC; > > action[len++] = info->flags; > > @@ -407,12 +407,12 @@ static void __register_mlrc_engine(struct xe_guc *guc, > > action[len++] = info->wq_base_lo; > > action[len++] = info->wq_base_hi; > > action[len++] = info->wq_size; > > - action[len++] = e->width; > > + action[len++] = q->width; > > action[len++] = info->hwlrca_lo; > > action[len++] = info->hwlrca_hi; > > > > - for (i = 1; i < e->width; ++i) { > > - struct xe_lrc *lrc = e->lrc + i; > > + for (i = 1; i < q->width; ++i) { > > + struct xe_lrc *lrc = q->lrc + i; > > > > action[len++] = lower_32_bits(xe_lrc_descriptor(lrc)); > > action[len++] = upper_32_bits(xe_lrc_descriptor(lrc)); > > @@ -445,24 +445,24 @@ static void __register_engine(struct xe_guc *guc, > > xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0); > > } > > > > -static void register_engine(struct xe_engine *e) > > +static void register_engine(struct xe_exec_queue *q) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > struct xe_device *xe = guc_to_xe(guc); > > - struct xe_lrc *lrc = e->lrc; > > + struct xe_lrc *lrc = q->lrc; > > struct guc_ctxt_registration_info info; > > > > - XE_WARN_ON(engine_registered(e)); > > + XE_WARN_ON(exec_queue_registered(q)); > > > > memset(&info, 0, sizeof(info)); > > - info.context_idx = e->guc->id; > > - info.engine_class = xe_engine_class_to_guc_class(e->class); > > - info.engine_submit_mask = e->logical_mask; > > + info.context_idx = q->guc->id; > > + info.engine_class = xe_engine_class_to_guc_class(q->class); > > + info.engine_submit_mask = q->logical_mask; > > info.hwlrca_lo = lower_32_bits(xe_lrc_descriptor(lrc)); > > info.hwlrca_hi = upper_32_bits(xe_lrc_descriptor(lrc)); > > info.flags = CONTEXT_REGISTRATION_FLAG_KMD; > > > > - if (xe_engine_is_parallel(e)) { > > + if (xe_exec_queue_is_parallel(q)) { > > u32 ggtt_addr = xe_lrc_parallel_ggtt_addr(lrc); > > struct iosys_map map = xe_lrc_parallel_map(lrc); > > > > @@ -476,8 +476,8 @@ static void register_engine(struct xe_engine *e) > > offsetof(struct guc_submit_parallel_scratch, wq[0])); > > info.wq_size = WQ_SIZE; > > > > - e->guc->wqi_head = 0; > > - e->guc->wqi_tail = 0; > > + q->guc->wqi_head = 0; > > + q->guc->wqi_tail = 0; > > xe_map_memset(xe, &map, 0, 0, PARALLEL_SCRATCH_SIZE - WQ_SIZE); > > parallel_write(xe, map, wq_desc.wq_status, WQ_STATUS_ACTIVE); > > } > > @@ -487,38 +487,38 @@ static void register_engine(struct xe_engine *e) > > * the GuC as jobs signal immediately and can't destroy an engine if the > > * GuC has a reference to it. > > */ > > - if (xe_engine_is_lr(e)) > > - xe_engine_get(e); > > + if (xe_exec_queue_is_lr(q)) > > + xe_exec_queue_get(q); > > > > - set_engine_registered(e); > > - trace_xe_engine_register(e); > > - if (xe_engine_is_parallel(e)) > > - __register_mlrc_engine(guc, e, &info); > > + set_exec_queue_registered(q); > > + trace_xe_exec_queue_register(q); > > + if (xe_exec_queue_is_parallel(q)) > > + __register_mlrc_engine(guc, q, &info); > > else > > __register_engine(guc, &info); > > - init_policies(guc, e); > > + init_policies(guc, q); > > } > > > > -static u32 wq_space_until_wrap(struct xe_engine *e) > > +static u32 wq_space_until_wrap(struct xe_exec_queue *q) > > { > > - return (WQ_SIZE - e->guc->wqi_tail); > > + return (WQ_SIZE - q->guc->wqi_tail); > > } > > > > -static int wq_wait_for_space(struct xe_engine *e, u32 wqi_size) > > +static int wq_wait_for_space(struct xe_exec_queue *q, u32 wqi_size) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > struct xe_device *xe = guc_to_xe(guc); > > - struct iosys_map map = xe_lrc_parallel_map(e->lrc); > > + struct iosys_map map = xe_lrc_parallel_map(q->lrc); > > unsigned int sleep_period_ms = 1; > > > > #define AVAILABLE_SPACE \ > > - CIRC_SPACE(e->guc->wqi_tail, e->guc->wqi_head, WQ_SIZE) > > + CIRC_SPACE(q->guc->wqi_tail, q->guc->wqi_head, WQ_SIZE) > > if (wqi_size > AVAILABLE_SPACE) { > > try_again: > > - e->guc->wqi_head = parallel_read(xe, map, wq_desc.head); > > + q->guc->wqi_head = parallel_read(xe, map, wq_desc.head); > > if (wqi_size > AVAILABLE_SPACE) { > > if (sleep_period_ms == 1024) { > > - xe_gt_reset_async(e->gt); > > + xe_gt_reset_async(q->gt); > > return -ENODEV; > > } > > > > @@ -532,52 +532,52 @@ static int wq_wait_for_space(struct xe_engine *e, u32 wqi_size) > > return 0; > > } > > > > -static int wq_noop_append(struct xe_engine *e) > > +static int wq_noop_append(struct xe_exec_queue *q) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > struct xe_device *xe = guc_to_xe(guc); > > - struct iosys_map map = xe_lrc_parallel_map(e->lrc); > > - u32 len_dw = wq_space_until_wrap(e) / sizeof(u32) - 1; > > + struct iosys_map map = xe_lrc_parallel_map(q->lrc); > > + u32 len_dw = wq_space_until_wrap(q) / sizeof(u32) - 1; > > > > - if (wq_wait_for_space(e, wq_space_until_wrap(e))) > > + if (wq_wait_for_space(q, wq_space_until_wrap(q))) > > return -ENODEV; > > > > XE_WARN_ON(!FIELD_FIT(WQ_LEN_MASK, len_dw)); > > > > - parallel_write(xe, map, wq[e->guc->wqi_tail / sizeof(u32)], > > + parallel_write(xe, map, wq[q->guc->wqi_tail / sizeof(u32)], > > FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_NOOP) | > > FIELD_PREP(WQ_LEN_MASK, len_dw)); > > - e->guc->wqi_tail = 0; > > + q->guc->wqi_tail = 0; > > > > return 0; > > } > > > > -static void wq_item_append(struct xe_engine *e) > > +static void wq_item_append(struct xe_exec_queue *q) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > struct xe_device *xe = guc_to_xe(guc); > > - struct iosys_map map = xe_lrc_parallel_map(e->lrc); > > + struct iosys_map map = xe_lrc_parallel_map(q->lrc); > > #define WQ_HEADER_SIZE 4 /* Includes 1 LRC address too */ > > u32 wqi[XE_HW_ENGINE_MAX_INSTANCE + (WQ_HEADER_SIZE - 1)]; > > - u32 wqi_size = (e->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32); > > + u32 wqi_size = (q->width + (WQ_HEADER_SIZE - 1)) * sizeof(u32); > > u32 len_dw = (wqi_size / sizeof(u32)) - 1; > > int i = 0, j; > > > > - if (wqi_size > wq_space_until_wrap(e)) { > > - if (wq_noop_append(e)) > > + if (wqi_size > wq_space_until_wrap(q)) { > > + if (wq_noop_append(q)) > > return; > > } > > - if (wq_wait_for_space(e, wqi_size)) > > + if (wq_wait_for_space(q, wqi_size)) > > return; > > > > wqi[i++] = FIELD_PREP(WQ_TYPE_MASK, WQ_TYPE_MULTI_LRC) | > > FIELD_PREP(WQ_LEN_MASK, len_dw); > > - wqi[i++] = xe_lrc_descriptor(e->lrc); > > - wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, e->guc->id) | > > - FIELD_PREP(WQ_RING_TAIL_MASK, e->lrc->ring.tail / sizeof(u64)); > > + wqi[i++] = xe_lrc_descriptor(q->lrc); > > + wqi[i++] = FIELD_PREP(WQ_GUC_ID_MASK, q->guc->id) | > > + FIELD_PREP(WQ_RING_TAIL_MASK, q->lrc->ring.tail / sizeof(u64)); > > wqi[i++] = 0; > > - for (j = 1; j < e->width; ++j) { > > - struct xe_lrc *lrc = e->lrc + j; > > + for (j = 1; j < q->width; ++j) { > > + struct xe_lrc *lrc = q->lrc + j; > > > > wqi[i++] = lrc->ring.tail / sizeof(u64); > > } > > @@ -585,55 +585,55 @@ static void wq_item_append(struct xe_engine *e) > > XE_WARN_ON(i != wqi_size / sizeof(u32)); > > > > iosys_map_incr(&map, offsetof(struct guc_submit_parallel_scratch, > > - wq[e->guc->wqi_tail / sizeof(u32)])); > > + wq[q->guc->wqi_tail / sizeof(u32)])); > > xe_map_memcpy_to(xe, &map, 0, wqi, wqi_size); > > - e->guc->wqi_tail += wqi_size; > > - XE_WARN_ON(e->guc->wqi_tail > WQ_SIZE); > > + q->guc->wqi_tail += wqi_size; > > + XE_WARN_ON(q->guc->wqi_tail > WQ_SIZE); > > > > xe_device_wmb(xe); > > > > - map = xe_lrc_parallel_map(e->lrc); > > - parallel_write(xe, map, wq_desc.tail, e->guc->wqi_tail); > > + map = xe_lrc_parallel_map(q->lrc); > > + parallel_write(xe, map, wq_desc.tail, q->guc->wqi_tail); > > } > > > > #define RESUME_PENDING ~0x0ull > > -static void submit_engine(struct xe_engine *e) > > +static void submit_exec_queue(struct xe_exec_queue *q) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > - struct xe_lrc *lrc = e->lrc; > > + struct xe_guc *guc = exec_queue_to_guc(q); > > + struct xe_lrc *lrc = q->lrc; > > u32 action[3]; > > u32 g2h_len = 0; > > u32 num_g2h = 0; > > int len = 0; > > bool extra_submit = false; > > > > - XE_WARN_ON(!engine_registered(e)); > > + XE_WARN_ON(!exec_queue_registered(q)); > > > > - if (xe_engine_is_parallel(e)) > > - wq_item_append(e); > > + if (xe_exec_queue_is_parallel(q)) > > + wq_item_append(q); > > else > > xe_lrc_write_ctx_reg(lrc, CTX_RING_TAIL, lrc->ring.tail); > > > > - if (engine_suspended(e) && !xe_engine_is_parallel(e)) > > + if (exec_queue_suspended(q) && !xe_exec_queue_is_parallel(q)) > > return; > > > > - if (!engine_enabled(e) && !engine_suspended(e)) { > > + if (!exec_queue_enabled(q) && !exec_queue_suspended(q)) { > > action[len++] = XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET; > > - action[len++] = e->guc->id; > > + action[len++] = q->guc->id; > > action[len++] = GUC_CONTEXT_ENABLE; > > g2h_len = G2H_LEN_DW_SCHED_CONTEXT_MODE_SET; > > num_g2h = 1; > > - if (xe_engine_is_parallel(e)) > > + if (xe_exec_queue_is_parallel(q)) > > extra_submit = true; > > > > - e->guc->resume_time = RESUME_PENDING; > > - set_engine_pending_enable(e); > > - set_engine_enabled(e); > > - trace_xe_engine_scheduling_enable(e); > > + q->guc->resume_time = RESUME_PENDING; > > + set_exec_queue_pending_enable(q); > > + set_exec_queue_enabled(q); > > + trace_xe_exec_queue_scheduling_enable(q); > > } else { > > action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; > > - action[len++] = e->guc->id; > > - trace_xe_engine_submit(e); > > + action[len++] = q->guc->id; > > + trace_xe_exec_queue_submit(q); > > } > > > > xe_guc_ct_send(&guc->ct, action, len, g2h_len, num_g2h); > > @@ -641,31 +641,31 @@ static void submit_engine(struct xe_engine *e) > > if (extra_submit) { > > len = 0; > > action[len++] = XE_GUC_ACTION_SCHED_CONTEXT; > > - action[len++] = e->guc->id; > > - trace_xe_engine_submit(e); > > + action[len++] = q->guc->id; > > + trace_xe_exec_queue_submit(q); > > > > xe_guc_ct_send(&guc->ct, action, len, 0, 0); > > } > > } > > > > static struct dma_fence * > > -guc_engine_run_job(struct drm_sched_job *drm_job) > > +guc_exec_queue_run_job(struct drm_sched_job *drm_job) > > { > > struct xe_sched_job *job = to_xe_sched_job(drm_job); > > - struct xe_engine *e = job->engine; > > - bool lr = xe_engine_is_lr(e); > > + struct xe_exec_queue *q = job->q; > > + bool lr = xe_exec_queue_is_lr(q); > > > > - XE_WARN_ON((engine_destroyed(e) || engine_pending_disable(e)) && > > - !engine_banned(e) && !engine_suspended(e)); > > + XE_WARN_ON((exec_queue_destroyed(q) || exec_queue_pending_disable(q)) && > > + !exec_queue_banned(q) && !exec_queue_suspended(q)); > > > > trace_xe_sched_job_run(job); > > > > - if (!engine_killed_or_banned(e) && !xe_sched_job_is_error(job)) { > > - if (!engine_registered(e)) > > - register_engine(e); > > + if (!exec_queue_killed_or_banned(q) && !xe_sched_job_is_error(job)) { > > + if (!exec_queue_registered(q)) > > + register_engine(q); > > if (!lr) /* LR jobs are emitted in the exec IOCTL */ > > - e->ring_ops->emit_job(job); > > - submit_engine(e); > > + q->ring_ops->emit_job(job); > > + submit_exec_queue(q); > > } > > > > if (lr) { > > @@ -678,7 +678,7 @@ guc_engine_run_job(struct drm_sched_job *drm_job) > > } > > } > > > > -static void guc_engine_free_job(struct drm_sched_job *drm_job) > > +static void guc_exec_queue_free_job(struct drm_sched_job *drm_job) > > { > > struct xe_sched_job *job = to_xe_sched_job(drm_job); > > > > @@ -691,38 +691,38 @@ static int guc_read_stopped(struct xe_guc *guc) > > return atomic_read(&guc->submission_state.stopped); > > } > > > > -#define MAKE_SCHED_CONTEXT_ACTION(e, enable_disable) \ > > +#define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable) \ > > u32 action[] = { \ > > XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET, \ > > - e->guc->id, \ > > + q->guc->id, \ > > GUC_CONTEXT_##enable_disable, \ > > } > > #define MIN_SCHED_TIMEOUT 1 > > > > static void disable_scheduling_deregister(struct xe_guc *guc, > > - struct xe_engine *e) > > + struct xe_exec_queue *q) > > { > > - MAKE_SCHED_CONTEXT_ACTION(e, DISABLE); > > + MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); > > int ret; > > > > - set_min_preemption_timeout(guc, e); > > + set_min_preemption_timeout(guc, q); > > smp_rmb(); > > - ret = wait_event_timeout(guc->ct.wq, !engine_pending_enable(e) || > > + ret = wait_event_timeout(guc->ct.wq, !exec_queue_pending_enable(q) || > > guc_read_stopped(guc), HZ * 5); > > if (!ret) { > > - struct drm_gpu_scheduler *sched = &e->guc->sched; > > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > > > XE_WARN_ON("Pending enable failed to respond"); > > sched->timeout = MIN_SCHED_TIMEOUT; > > drm_sched_run_wq_start(sched); > > - xe_gt_reset_async(e->gt); > > + xe_gt_reset_async(q->gt); > > return; > > } > > > > - clear_engine_enabled(e); > > - set_engine_pending_disable(e); > > - set_engine_destroyed(e); > > - trace_xe_engine_scheduling_disable(e); > > + clear_exec_queue_enabled(q); > > + set_exec_queue_pending_disable(q); > > + set_exec_queue_destroyed(q); > > + trace_xe_exec_queue_scheduling_disable(q); > > > > /* > > * Reserve space for both G2H here as the 2nd G2H is sent from a G2H > > @@ -733,27 +733,27 @@ static void disable_scheduling_deregister(struct xe_guc *guc, > > G2H_LEN_DW_DEREGISTER_CONTEXT, 2); > > } > > > > -static void guc_engine_print(struct xe_engine *e, struct drm_printer *p); > > +static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p); > > > > #if IS_ENABLED(CONFIG_DRM_XE_SIMPLE_ERROR_CAPTURE) > > -static void simple_error_capture(struct xe_engine *e) > > +static void simple_error_capture(struct xe_exec_queue *q) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > struct drm_printer p = drm_err_printer(""); > > struct xe_hw_engine *hwe; > > enum xe_hw_engine_id id; > > - u32 adj_logical_mask = e->logical_mask; > > - u32 width_mask = (0x1 << e->width) - 1; > > + u32 adj_logical_mask = q->logical_mask; > > + u32 width_mask = (0x1 << q->width) - 1; > > int i; > > bool cookie; > > > > - if (e->vm && !e->vm->error_capture.capture_once) { > > - e->vm->error_capture.capture_once = true; > > + if (q->vm && !q->vm->error_capture.capture_once) { > > + q->vm->error_capture.capture_once = true; > > cookie = dma_fence_begin_signalling(); > > - for (i = 0; e->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { > > + for (i = 0; q->width > 1 && i < XE_HW_ENGINE_MAX_INSTANCE;) { > > if (adj_logical_mask & BIT(i)) { > > adj_logical_mask |= width_mask << i; > > - i += e->width; > > + i += q->width; > > } else { > > ++i; > > } > > @@ -761,66 +761,66 @@ static void simple_error_capture(struct xe_engine *e) > > > > xe_force_wake_get(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL); > > xe_guc_ct_print(&guc->ct, &p, true); > > - guc_engine_print(e, &p); > > + guc_exec_queue_print(q, &p); > > for_each_hw_engine(hwe, guc_to_gt(guc), id) { > > - if (hwe->class != e->hwe->class || > > + if (hwe->class != q->hwe->class || > > !(BIT(hwe->logical_instance) & adj_logical_mask)) > > continue; > > xe_hw_engine_print(hwe, &p); > > } > > - xe_analyze_vm(&p, e->vm, e->gt->info.id); > > + xe_analyze_vm(&p, q->vm, q->gt->info.id); > > xe_force_wake_put(gt_to_fw(guc_to_gt(guc)), XE_FORCEWAKE_ALL); > > dma_fence_end_signalling(cookie); > > } > > } > > #else > > -static void simple_error_capture(struct xe_engine *e) > > +static void simple_error_capture(struct xe_exec_queue *q) > > { > > } > > #endif > > > > -static void xe_guc_engine_trigger_cleanup(struct xe_engine *e) > > +static void xe_guc_exec_queue_trigger_cleanup(struct xe_exec_queue *q) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > > > - if (xe_engine_is_lr(e)) > > - queue_work(guc_to_gt(guc)->ordered_wq, &e->guc->lr_tdr); > > + if (xe_exec_queue_is_lr(q)) > > + queue_work(guc_to_gt(guc)->ordered_wq, &q->guc->lr_tdr); > > else > > - drm_sched_set_timeout(&e->guc->sched, MIN_SCHED_TIMEOUT); > > + drm_sched_set_timeout(&q->guc->sched, MIN_SCHED_TIMEOUT); > > } > > > > -static void xe_guc_engine_lr_cleanup(struct work_struct *w) > > +static void xe_guc_exec_queue_lr_cleanup(struct work_struct *w) > > { > > - struct xe_guc_engine *ge = > > - container_of(w, struct xe_guc_engine, lr_tdr); > > - struct xe_engine *e = ge->engine; > > + struct xe_guc_exec_queue *ge = > > + container_of(w, struct xe_guc_exec_queue, lr_tdr); > > + struct xe_exec_queue *q = ge->q; > > struct drm_gpu_scheduler *sched = &ge->sched; > > > > - XE_WARN_ON(!xe_engine_is_lr(e)); > > - trace_xe_engine_lr_cleanup(e); > > + XE_WARN_ON(!xe_exec_queue_is_lr(q)); > > + trace_xe_exec_queue_lr_cleanup(q); > > > > /* Kill the run_job / process_msg entry points */ > > drm_sched_run_wq_stop(sched); > > > > /* Engine state now stable, disable scheduling / deregister if needed */ > > - if (engine_registered(e)) { > > - struct xe_guc *guc = engine_to_guc(e); > > + if (exec_queue_registered(q)) { > > + struct xe_guc *guc = exec_queue_to_guc(q); > > int ret; > > > > - set_engine_banned(e); > > - disable_scheduling_deregister(guc, e); > > + set_exec_queue_banned(q); > > + disable_scheduling_deregister(guc, q); > > > > /* > > * Must wait for scheduling to be disabled before signalling > > * any fences, if GT broken the GT reset code should signal us. > > */ > > ret = wait_event_timeout(guc->ct.wq, > > - !engine_pending_disable(e) || > > + !exec_queue_pending_disable(q) || > > guc_read_stopped(guc), HZ * 5); > > if (!ret) { > > XE_WARN_ON("Schedule disable failed to respond"); > > drm_sched_run_wq_start(sched); > > - xe_gt_reset_async(e->gt); > > + xe_gt_reset_async(q->gt); > > return; > > } > > } > > @@ -829,27 +829,27 @@ static void xe_guc_engine_lr_cleanup(struct work_struct *w) > > } > > > > static enum drm_gpu_sched_stat > > -guc_engine_timedout_job(struct drm_sched_job *drm_job) > > +guc_exec_queue_timedout_job(struct drm_sched_job *drm_job) > > { > > struct xe_sched_job *job = to_xe_sched_job(drm_job); > > struct xe_sched_job *tmp_job; > > - struct xe_engine *e = job->engine; > > - struct drm_gpu_scheduler *sched = &e->guc->sched; > > - struct xe_device *xe = guc_to_xe(engine_to_guc(e)); > > + struct xe_exec_queue *q = job->q; > > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > + struct xe_device *xe = guc_to_xe(exec_queue_to_guc(q)); > > int err = -ETIME; > > int i = 0; > > > > if (!test_bit(DMA_FENCE_FLAG_SIGNALED_BIT, &job->fence->flags)) { > > - XE_WARN_ON(e->flags & ENGINE_FLAG_KERNEL); > > - XE_WARN_ON(e->flags & ENGINE_FLAG_VM && !engine_killed(e)); > > + XE_WARN_ON(q->flags & EXEC_QUEUE_FLAG_KERNEL); > > + XE_WARN_ON(q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q)); > > > > drm_warn(&xe->drm, "Timedout job: seqno=%u, guc_id=%d, flags=0x%lx", > > - xe_sched_job_seqno(job), e->guc->id, e->flags); > > - simple_error_capture(e); > > - xe_devcoredump(e); > > + xe_sched_job_seqno(job), q->guc->id, q->flags); > > + simple_error_capture(q); > > + xe_devcoredump(q); > > } else { > > drm_dbg(&xe->drm, "Timedout signaled job: seqno=%u, guc_id=%d, flags=0x%lx", > > - xe_sched_job_seqno(job), e->guc->id, e->flags); > > + xe_sched_job_seqno(job), q->guc->id, q->flags); > > } > > trace_xe_sched_job_timedout(job); > > > > @@ -860,26 +860,26 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) > > * Kernel jobs should never fail, nor should VM jobs if they do > > * somethings has gone wrong and the GT needs a reset > > */ > > - if (e->flags & ENGINE_FLAG_KERNEL || > > - (e->flags & ENGINE_FLAG_VM && !engine_killed(e))) { > > + if (q->flags & EXEC_QUEUE_FLAG_KERNEL || > > + (q->flags & EXEC_QUEUE_FLAG_VM && !exec_queue_killed(q))) { > > if (!drm_sched_invalidate_job(drm_job, 2)) { > > list_add(&drm_job->list, &sched->pending_list); > > drm_sched_run_wq_start(sched); > > - xe_gt_reset_async(e->gt); > > + xe_gt_reset_async(q->gt); > > goto out; > > } > > } > > > > /* Engine state now stable, disable scheduling if needed */ > > - if (engine_enabled(e)) { > > - struct xe_guc *guc = engine_to_guc(e); > > + if (exec_queue_enabled(q)) { > > + struct xe_guc *guc = exec_queue_to_guc(q); > > int ret; > > > > - if (engine_reset(e)) > > + if (exec_queue_reset(q)) > > err = -EIO; > > - set_engine_banned(e); > > - xe_engine_get(e); > > - disable_scheduling_deregister(guc, e); > > + set_exec_queue_banned(q); > > + xe_exec_queue_get(q); > > + disable_scheduling_deregister(guc, q); > > > > /* > > * Must wait for scheduling to be disabled before signalling > > @@ -891,20 +891,20 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) > > */ > > smp_rmb(); > > ret = wait_event_timeout(guc->ct.wq, > > - !engine_pending_disable(e) || > > + !exec_queue_pending_disable(q) || > > guc_read_stopped(guc), HZ * 5); > > if (!ret) { > > XE_WARN_ON("Schedule disable failed to respond"); > > sched->timeout = MIN_SCHED_TIMEOUT; > > list_add(&drm_job->list, &sched->pending_list); > > drm_sched_run_wq_start(sched); > > - xe_gt_reset_async(e->gt); > > + xe_gt_reset_async(q->gt); > > goto out; > > } > > } > > > > /* Stop fence signaling */ > > - xe_hw_fence_irq_stop(e->fence_irq); > > + xe_hw_fence_irq_stop(q->fence_irq); > > > > /* > > * Fence state now stable, stop / start scheduler which cleans up any > > @@ -912,7 +912,7 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) > > */ > > list_add(&drm_job->list, &sched->pending_list); > > drm_sched_run_wq_start(sched); > > - xe_guc_engine_trigger_cleanup(e); > > + xe_guc_exec_queue_trigger_cleanup(q); > > > > /* Mark all outstanding jobs as bad, thus completing them */ > > spin_lock(&sched->job_list_lock); > > @@ -921,53 +921,53 @@ guc_engine_timedout_job(struct drm_sched_job *drm_job) > > spin_unlock(&sched->job_list_lock); > > > > /* Start fence signaling */ > > - xe_hw_fence_irq_start(e->fence_irq); > > + xe_hw_fence_irq_start(q->fence_irq); > > > > out: > > return DRM_GPU_SCHED_STAT_NOMINAL; > > } > > > > -static void __guc_engine_fini_async(struct work_struct *w) > > +static void __guc_exec_queue_fini_async(struct work_struct *w) > > { > > - struct xe_guc_engine *ge = > > - container_of(w, struct xe_guc_engine, fini_async); > > - struct xe_engine *e = ge->engine; > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc_exec_queue *ge = > > + container_of(w, struct xe_guc_exec_queue, fini_async); > > + struct xe_exec_queue *q = ge->q; > > + struct xe_guc *guc = exec_queue_to_guc(q); > > > > - trace_xe_engine_destroy(e); > > + trace_xe_exec_queue_destroy(q); > > > > - if (xe_engine_is_lr(e)) > > + if (xe_exec_queue_is_lr(q)) > > cancel_work_sync(&ge->lr_tdr); > > - if (e->flags & ENGINE_FLAG_PERSISTENT) > > - xe_device_remove_persistent_engines(gt_to_xe(e->gt), e); > > - release_guc_id(guc, e); > > + if (q->flags & EXEC_QUEUE_FLAG_PERSISTENT) > > + xe_device_remove_persistent_exec_queues(gt_to_xe(q->gt), q); > > + release_guc_id(guc, q); > > drm_sched_entity_fini(&ge->entity); > > drm_sched_fini(&ge->sched); > > > > - if (!(e->flags & ENGINE_FLAG_KERNEL)) { > > + if (!(q->flags & EXEC_QUEUE_FLAG_KERNEL)) { > > kfree(ge); > > - xe_engine_fini(e); > > + xe_exec_queue_fini(q); > > } > > } > > > > -static void guc_engine_fini_async(struct xe_engine *e) > > +static void guc_exec_queue_fini_async(struct xe_exec_queue *q) > > { > > - bool kernel = e->flags & ENGINE_FLAG_KERNEL; > > + bool kernel = q->flags & EXEC_QUEUE_FLAG_KERNEL; > > > > - INIT_WORK(&e->guc->fini_async, __guc_engine_fini_async); > > - queue_work(system_wq, &e->guc->fini_async); > > + INIT_WORK(&q->guc->fini_async, __guc_exec_queue_fini_async); > > + queue_work(system_wq, &q->guc->fini_async); > > > > /* We must block on kernel engines so slabs are empty on driver unload */ > > if (kernel) { > > - struct xe_guc_engine *ge = e->guc; > > + struct xe_guc_exec_queue *ge = q->guc; > > > > flush_work(&ge->fini_async); > > kfree(ge); > > - xe_engine_fini(e); > > + xe_exec_queue_fini(q); > > } > > } > > > > -static void __guc_engine_fini(struct xe_guc *guc, struct xe_engine *e) > > +static void __guc_exec_queue_fini(struct xe_guc *guc, struct xe_exec_queue *q) > > { > > /* > > * Might be done from within the GPU scheduler, need to do async as we > > @@ -976,104 +976,104 @@ static void __guc_engine_fini(struct xe_guc *guc, struct xe_engine *e) > > * this we and don't really care when everything is fini'd, just that it > > * is. > > */ > > - guc_engine_fini_async(e); > > + guc_exec_queue_fini_async(q); > > } > > > > -static void __guc_engine_process_msg_cleanup(struct drm_sched_msg *msg) > > +static void __guc_exec_queue_process_msg_cleanup(struct drm_sched_msg *msg) > > { > > - struct xe_engine *e = msg->private_data; > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_exec_queue *q = msg->private_data; > > + struct xe_guc *guc = exec_queue_to_guc(q); > > > > - XE_WARN_ON(e->flags & ENGINE_FLAG_KERNEL); > > - trace_xe_engine_cleanup_entity(e); > > + XE_WARN_ON(q->flags & EXEC_QUEUE_FLAG_KERNEL); > > + trace_xe_exec_queue_cleanup_entity(q); > > > > - if (engine_registered(e)) > > - disable_scheduling_deregister(guc, e); > > + if (exec_queue_registered(q)) > > + disable_scheduling_deregister(guc, q); > > else > > - __guc_engine_fini(guc, e); > > + __guc_exec_queue_fini(guc, q); > > } > > > > -static bool guc_engine_allowed_to_change_state(struct xe_engine *e) > > +static bool guc_exec_queue_allowed_to_change_state(struct xe_exec_queue *q) > > { > > - return !engine_killed_or_banned(e) && engine_registered(e); > > + return !exec_queue_killed_or_banned(q) && exec_queue_registered(q); > > } > > > > -static void __guc_engine_process_msg_set_sched_props(struct drm_sched_msg *msg) > > +static void __guc_exec_queue_process_msg_set_sched_props(struct drm_sched_msg *msg) > > { > > - struct xe_engine *e = msg->private_data; > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_exec_queue *q = msg->private_data; > > + struct xe_guc *guc = exec_queue_to_guc(q); > > > > - if (guc_engine_allowed_to_change_state(e)) > > - init_policies(guc, e); > > + if (guc_exec_queue_allowed_to_change_state(q)) > > + init_policies(guc, q); > > kfree(msg); > > } > > > > -static void suspend_fence_signal(struct xe_engine *e) > > +static void suspend_fence_signal(struct xe_exec_queue *q) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > > > - XE_WARN_ON(!engine_suspended(e) && !engine_killed(e) && > > + XE_WARN_ON(!exec_queue_suspended(q) && !exec_queue_killed(q) && > > !guc_read_stopped(guc)); > > - XE_WARN_ON(!e->guc->suspend_pending); > > + XE_WARN_ON(!q->guc->suspend_pending); > > > > - e->guc->suspend_pending = false; > > + q->guc->suspend_pending = false; > > smp_wmb(); > > - wake_up(&e->guc->suspend_wait); > > + wake_up(&q->guc->suspend_wait); > > } > > > > -static void __guc_engine_process_msg_suspend(struct drm_sched_msg *msg) > > +static void __guc_exec_queue_process_msg_suspend(struct drm_sched_msg *msg) > > { > > - struct xe_engine *e = msg->private_data; > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_exec_queue *q = msg->private_data; > > + struct xe_guc *guc = exec_queue_to_guc(q); > > > > - if (guc_engine_allowed_to_change_state(e) && !engine_suspended(e) && > > - engine_enabled(e)) { > > - wait_event(guc->ct.wq, e->guc->resume_time != RESUME_PENDING || > > + if (guc_exec_queue_allowed_to_change_state(q) && !exec_queue_suspended(q) && > > + exec_queue_enabled(q)) { > > + wait_event(guc->ct.wq, q->guc->resume_time != RESUME_PENDING || > > guc_read_stopped(guc)); > > > > if (!guc_read_stopped(guc)) { > > - MAKE_SCHED_CONTEXT_ACTION(e, DISABLE); > > + MAKE_SCHED_CONTEXT_ACTION(q, DISABLE); > > s64 since_resume_ms = > > ktime_ms_delta(ktime_get(), > > - e->guc->resume_time); > > - s64 wait_ms = e->vm->preempt.min_run_period_ms - > > + q->guc->resume_time); > > + s64 wait_ms = q->vm->preempt.min_run_period_ms - > > since_resume_ms; > > > > - if (wait_ms > 0 && e->guc->resume_time) > > + if (wait_ms > 0 && q->guc->resume_time) > > msleep(wait_ms); > > > > - set_engine_suspended(e); > > - clear_engine_enabled(e); > > - set_engine_pending_disable(e); > > - trace_xe_engine_scheduling_disable(e); > > + set_exec_queue_suspended(q); > > + clear_exec_queue_enabled(q); > > + set_exec_queue_pending_disable(q); > > + trace_xe_exec_queue_scheduling_disable(q); > > > > xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), > > G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); > > } > > - } else if (e->guc->suspend_pending) { > > - set_engine_suspended(e); > > - suspend_fence_signal(e); > > + } else if (q->guc->suspend_pending) { > > + set_exec_queue_suspended(q); > > + suspend_fence_signal(q); > > } > > } > > > > -static void __guc_engine_process_msg_resume(struct drm_sched_msg *msg) > > +static void __guc_exec_queue_process_msg_resume(struct drm_sched_msg *msg) > > { > > - struct xe_engine *e = msg->private_data; > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_exec_queue *q = msg->private_data; > > + struct xe_guc *guc = exec_queue_to_guc(q); > > > > - if (guc_engine_allowed_to_change_state(e)) { > > - MAKE_SCHED_CONTEXT_ACTION(e, ENABLE); > > + if (guc_exec_queue_allowed_to_change_state(q)) { > > + MAKE_SCHED_CONTEXT_ACTION(q, ENABLE); > > > > - e->guc->resume_time = RESUME_PENDING; > > - clear_engine_suspended(e); > > - set_engine_pending_enable(e); > > - set_engine_enabled(e); > > - trace_xe_engine_scheduling_enable(e); > > + q->guc->resume_time = RESUME_PENDING; > > + clear_exec_queue_suspended(q); > > + set_exec_queue_pending_enable(q); > > + set_exec_queue_enabled(q); > > + trace_xe_exec_queue_scheduling_enable(q); > > > > xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), > > G2H_LEN_DW_SCHED_CONTEXT_MODE_SET, 1); > > } else { > > - clear_engine_suspended(e); > > + clear_exec_queue_suspended(q); > > } > > } > > > > @@ -1082,22 +1082,22 @@ static void __guc_engine_process_msg_resume(struct drm_sched_msg *msg) > > #define SUSPEND 3 > > #define RESUME 4 > > > > -static void guc_engine_process_msg(struct drm_sched_msg *msg) > > +static void guc_exec_queue_process_msg(struct drm_sched_msg *msg) > > { > > trace_drm_sched_msg_recv(msg); > > > > switch (msg->opcode) { > > case CLEANUP: > > - __guc_engine_process_msg_cleanup(msg); > > + __guc_exec_queue_process_msg_cleanup(msg); > > break; > > case SET_SCHED_PROPS: > > - __guc_engine_process_msg_set_sched_props(msg); > > + __guc_exec_queue_process_msg_set_sched_props(msg); > > break; > > case SUSPEND: > > - __guc_engine_process_msg_suspend(msg); > > + __guc_exec_queue_process_msg_suspend(msg); > > break; > > case RESUME: > > - __guc_engine_process_msg_resume(msg); > > + __guc_exec_queue_process_msg_resume(msg); > > break; > > default: > > XE_WARN_ON("Unknown message type"); > > @@ -1105,17 +1105,17 @@ static void guc_engine_process_msg(struct drm_sched_msg *msg) > > } > > > > static const struct drm_sched_backend_ops drm_sched_ops = { > > - .run_job = guc_engine_run_job, > > - .free_job = guc_engine_free_job, > > - .timedout_job = guc_engine_timedout_job, > > - .process_msg = guc_engine_process_msg, > > + .run_job = guc_exec_queue_run_job, > > + .free_job = guc_exec_queue_free_job, > > + .timedout_job = guc_exec_queue_timedout_job, > > + .process_msg = guc_exec_queue_process_msg, > > }; > > > > -static int guc_engine_init(struct xe_engine *e) > > +static int guc_exec_queue_init(struct xe_exec_queue *q) > > { > > struct drm_gpu_scheduler *sched; > > - struct xe_guc *guc = engine_to_guc(e); > > - struct xe_guc_engine *ge; > > + struct xe_guc *guc = exec_queue_to_guc(q); > > + struct xe_guc_exec_queue *ge; > > long timeout; > > int err; > > > > @@ -1125,16 +1125,16 @@ static int guc_engine_init(struct xe_engine *e) > > if (!ge) > > return -ENOMEM; > > > > - e->guc = ge; > > - ge->engine = e; > > + q->guc = ge; > > + ge->q = q; > > init_waitqueue_head(&ge->suspend_wait); > > > > - timeout = xe_vm_no_dma_fences(e->vm) ? MAX_SCHEDULE_TIMEOUT : HZ * 5; > > + timeout = xe_vm_no_dma_fences(q->vm) ? MAX_SCHEDULE_TIMEOUT : HZ * 5; > > err = drm_sched_init(&ge->sched, &drm_sched_ops, NULL, > > - e->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, > > + q->lrc[0].ring.size / MAX_JOB_SIZE_BYTES, > > 64, timeout, guc_to_gt(guc)->ordered_wq, NULL, > > - e->name, DRM_SCHED_POLICY_SINGLE_ENTITY, > > - gt_to_xe(e->gt)->drm.dev); > > + q->name, DRM_SCHED_POLICY_SINGLE_ENTITY, > > + gt_to_xe(q->gt)->drm.dev); > > if (err) > > goto err_free; > > > > @@ -1144,43 +1144,43 @@ static int guc_engine_init(struct xe_engine *e) > > if (err) > > goto err_sched; > > > > - if (xe_engine_is_lr(e)) > > - INIT_WORK(&e->guc->lr_tdr, xe_guc_engine_lr_cleanup); > > + if (xe_exec_queue_is_lr(q)) > > + INIT_WORK(&q->guc->lr_tdr, xe_guc_exec_queue_lr_cleanup); > > > > mutex_lock(&guc->submission_state.lock); > > > > - err = alloc_guc_id(guc, e); > > + err = alloc_guc_id(guc, q); > > if (err) > > goto err_entity; > > > > - e->entity = &ge->entity; > > + q->entity = &ge->entity; > > > > if (guc_read_stopped(guc)) > > drm_sched_stop(sched, NULL); > > > > mutex_unlock(&guc->submission_state.lock); > > > > - switch (e->class) { > > + switch (q->class) { > > case XE_ENGINE_CLASS_RENDER: > > - sprintf(e->name, "rcs%d", e->guc->id); > > + sprintf(q->name, "rcs%d", q->guc->id); > > break; > > case XE_ENGINE_CLASS_VIDEO_DECODE: > > - sprintf(e->name, "vcs%d", e->guc->id); > > + sprintf(q->name, "vcs%d", q->guc->id); > > break; > > case XE_ENGINE_CLASS_VIDEO_ENHANCE: > > - sprintf(e->name, "vecs%d", e->guc->id); > > + sprintf(q->name, "vecs%d", q->guc->id); > > break; > > case XE_ENGINE_CLASS_COPY: > > - sprintf(e->name, "bcs%d", e->guc->id); > > + sprintf(q->name, "bcs%d", q->guc->id); > > break; > > case XE_ENGINE_CLASS_COMPUTE: > > - sprintf(e->name, "ccs%d", e->guc->id); > > + sprintf(q->name, "ccs%d", q->guc->id); > > break; > > default: > > - XE_WARN_ON(e->class); > > + XE_WARN_ON(q->class); > > } > > > > - trace_xe_engine_create(e); > > + trace_xe_exec_queue_create(q); > > > > return 0; > > > > @@ -1194,132 +1194,132 @@ static int guc_engine_init(struct xe_engine *e) > > return err; > > } > > > > -static void guc_engine_kill(struct xe_engine *e) > > +static void guc_exec_queue_kill(struct xe_exec_queue *q) > > { > > - trace_xe_engine_kill(e); > > - set_engine_killed(e); > > - xe_guc_engine_trigger_cleanup(e); > > + trace_xe_exec_queue_kill(q); > > + set_exec_queue_killed(q); > > + xe_guc_exec_queue_trigger_cleanup(q); > > } > > > > -static void guc_engine_add_msg(struct xe_engine *e, struct drm_sched_msg *msg, > > - u32 opcode) > > +static void guc_exec_queue_add_msg(struct xe_exec_queue *q, struct drm_sched_msg *msg, > > + u32 opcode) > > { > > INIT_LIST_HEAD(&msg->link); > > msg->opcode = opcode; > > - msg->private_data = e; > > + msg->private_data = q; > > > > trace_drm_sched_msg_add(msg); > > - drm_sched_add_msg(&e->guc->sched, msg); > > + drm_sched_add_msg(&q->guc->sched, msg); > > } > > > > #define STATIC_MSG_CLEANUP 0 > > #define STATIC_MSG_SUSPEND 1 > > #define STATIC_MSG_RESUME 2 > > -static void guc_engine_fini(struct xe_engine *e) > > +static void guc_exec_queue_fini(struct xe_exec_queue *q) > > { > > - struct drm_sched_msg *msg = e->guc->static_msgs + STATIC_MSG_CLEANUP; > > + struct drm_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_CLEANUP; > > > > - if (!(e->flags & ENGINE_FLAG_KERNEL)) > > - guc_engine_add_msg(e, msg, CLEANUP); > > + if (!(q->flags & EXEC_QUEUE_FLAG_KERNEL)) > > + guc_exec_queue_add_msg(q, msg, CLEANUP); > > else > > - __guc_engine_fini(engine_to_guc(e), e); > > + __guc_exec_queue_fini(exec_queue_to_guc(q), q); > > } > > > > -static int guc_engine_set_priority(struct xe_engine *e, > > - enum drm_sched_priority priority) > > +static int guc_exec_queue_set_priority(struct xe_exec_queue *q, > > + enum drm_sched_priority priority) > > { > > struct drm_sched_msg *msg; > > > > - if (e->entity->priority == priority || engine_killed_or_banned(e)) > > + if (q->entity->priority == priority || exec_queue_killed_or_banned(q)) > > return 0; > > > > msg = kmalloc(sizeof(*msg), GFP_KERNEL); > > if (!msg) > > return -ENOMEM; > > > > - guc_engine_add_msg(e, msg, SET_SCHED_PROPS); > > + guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); > > > > return 0; > > } > > > > -static int guc_engine_set_timeslice(struct xe_engine *e, u32 timeslice_us) > > +static int guc_exec_queue_set_timeslice(struct xe_exec_queue *q, u32 timeslice_us) > > { > > struct drm_sched_msg *msg; > > > > - if (e->sched_props.timeslice_us == timeslice_us || > > - engine_killed_or_banned(e)) > > + if (q->sched_props.timeslice_us == timeslice_us || > > + exec_queue_killed_or_banned(q)) > > return 0; > > > > msg = kmalloc(sizeof(*msg), GFP_KERNEL); > > if (!msg) > > return -ENOMEM; > > > > - e->sched_props.timeslice_us = timeslice_us; > > - guc_engine_add_msg(e, msg, SET_SCHED_PROPS); > > + q->sched_props.timeslice_us = timeslice_us; > > + guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); > > > > return 0; > > } > > > > -static int guc_engine_set_preempt_timeout(struct xe_engine *e, > > - u32 preempt_timeout_us) > > +static int guc_exec_queue_set_preempt_timeout(struct xe_exec_queue *q, > > + u32 preempt_timeout_us) > > { > > struct drm_sched_msg *msg; > > > > - if (e->sched_props.preempt_timeout_us == preempt_timeout_us || > > - engine_killed_or_banned(e)) > > + if (q->sched_props.preempt_timeout_us == preempt_timeout_us || > > + exec_queue_killed_or_banned(q)) > > return 0; > > > > msg = kmalloc(sizeof(*msg), GFP_KERNEL); > > if (!msg) > > return -ENOMEM; > > > > - e->sched_props.preempt_timeout_us = preempt_timeout_us; > > - guc_engine_add_msg(e, msg, SET_SCHED_PROPS); > > + q->sched_props.preempt_timeout_us = preempt_timeout_us; > > + guc_exec_queue_add_msg(q, msg, SET_SCHED_PROPS); > > > > return 0; > > } > > > > -static int guc_engine_set_job_timeout(struct xe_engine *e, u32 job_timeout_ms) > > +static int guc_exec_queue_set_job_timeout(struct xe_exec_queue *q, u32 job_timeout_ms) > > { > > - struct drm_gpu_scheduler *sched = &e->guc->sched; > > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > > > - XE_WARN_ON(engine_registered(e)); > > - XE_WARN_ON(engine_banned(e)); > > - XE_WARN_ON(engine_killed(e)); > > + XE_WARN_ON(exec_queue_registered(q)); > > + XE_WARN_ON(exec_queue_banned(q)); > > + XE_WARN_ON(exec_queue_killed(q)); > > > > sched->timeout = job_timeout_ms; > > > > return 0; > > } > > > > -static int guc_engine_suspend(struct xe_engine *e) > > +static int guc_exec_queue_suspend(struct xe_exec_queue *q) > > { > > - struct drm_sched_msg *msg = e->guc->static_msgs + STATIC_MSG_SUSPEND; > > + struct drm_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_SUSPEND; > > > > - if (engine_killed_or_banned(e) || e->guc->suspend_pending) > > + if (exec_queue_killed_or_banned(q) || q->guc->suspend_pending) > > return -EINVAL; > > > > - e->guc->suspend_pending = true; > > - guc_engine_add_msg(e, msg, SUSPEND); > > + q->guc->suspend_pending = true; > > + guc_exec_queue_add_msg(q, msg, SUSPEND); > > > > return 0; > > } > > > > -static void guc_engine_suspend_wait(struct xe_engine *e) > > +static void guc_exec_queue_suspend_wait(struct xe_exec_queue *q) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > > > - wait_event(e->guc->suspend_wait, !e->guc->suspend_pending || > > + wait_event(q->guc->suspend_wait, !q->guc->suspend_pending || > > guc_read_stopped(guc)); > > } > > > > -static void guc_engine_resume(struct xe_engine *e) > > +static void guc_exec_queue_resume(struct xe_exec_queue *q) > > { > > - struct drm_sched_msg *msg = e->guc->static_msgs + STATIC_MSG_RESUME; > > + struct drm_sched_msg *msg = q->guc->static_msgs + STATIC_MSG_RESUME; > > > > - XE_WARN_ON(e->guc->suspend_pending); > > + XE_WARN_ON(q->guc->suspend_pending); > > > > - guc_engine_add_msg(e, msg, RESUME); > > + guc_exec_queue_add_msg(q, msg, RESUME); > > } > > > > /* > > @@ -1328,49 +1328,49 @@ static void guc_engine_resume(struct xe_engine *e) > > * really shouldn't do much other than trap into the DRM scheduler which > > * synchronizes these operations. > > */ > > -static const struct xe_engine_ops guc_engine_ops = { > > - .init = guc_engine_init, > > - .kill = guc_engine_kill, > > - .fini = guc_engine_fini, > > - .set_priority = guc_engine_set_priority, > > - .set_timeslice = guc_engine_set_timeslice, > > - .set_preempt_timeout = guc_engine_set_preempt_timeout, > > - .set_job_timeout = guc_engine_set_job_timeout, > > - .suspend = guc_engine_suspend, > > - .suspend_wait = guc_engine_suspend_wait, > > - .resume = guc_engine_resume, > > +static const struct xe_exec_queue_ops guc_exec_queue_ops = { > > + .init = guc_exec_queue_init, > > + .kill = guc_exec_queue_kill, > > + .fini = guc_exec_queue_fini, > > + .set_priority = guc_exec_queue_set_priority, > > + .set_timeslice = guc_exec_queue_set_timeslice, > > + .set_preempt_timeout = guc_exec_queue_set_preempt_timeout, > > + .set_job_timeout = guc_exec_queue_set_job_timeout, > > + .suspend = guc_exec_queue_suspend, > > + .suspend_wait = guc_exec_queue_suspend_wait, > > + .resume = guc_exec_queue_resume, > > }; > > > > -static void guc_engine_stop(struct xe_guc *guc, struct xe_engine *e) > > +static void guc_exec_queue_stop(struct xe_guc *guc, struct xe_exec_queue *q) > > { > > - struct drm_gpu_scheduler *sched = &e->guc->sched; > > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > > > /* Stop scheduling + flush any DRM scheduler operations */ > > drm_sched_run_wq_stop(sched); > > > > /* Clean up lost G2H + reset engine state */ > > - if (engine_registered(e)) { > > - if ((engine_banned(e) && engine_destroyed(e)) || > > - xe_engine_is_lr(e)) > > - xe_engine_put(e); > > - else if (engine_destroyed(e)) > > - __guc_engine_fini(guc, e); > > + if (exec_queue_registered(q)) { > > + if ((exec_queue_banned(q) && exec_queue_destroyed(q)) || > > + xe_exec_queue_is_lr(q)) > > + xe_exec_queue_put(q); > > + else if (exec_queue_destroyed(q)) > > + __guc_exec_queue_fini(guc, q); > > } > > - if (e->guc->suspend_pending) { > > - set_engine_suspended(e); > > - suspend_fence_signal(e); > > + if (q->guc->suspend_pending) { > > + set_exec_queue_suspended(q); > > + suspend_fence_signal(q); > > } > > - atomic_and(ENGINE_STATE_DESTROYED | ENGINE_STATE_SUSPENDED, > > - &e->guc->state); > > - e->guc->resume_time = 0; > > - trace_xe_engine_stop(e); > > + atomic_and(EXEC_QUEUE_STATE_DESTROYED | ENGINE_STATE_SUSPENDED, > > + &q->guc->state); > > + q->guc->resume_time = 0; > > + trace_xe_exec_queue_stop(q); > > > > /* > > * Ban any engine (aside from kernel and engines used for VM ops) with a > > * started but not complete job or if a job has gone through a GT reset > > * more than twice. > > */ > > - if (!(e->flags & (ENGINE_FLAG_KERNEL | ENGINE_FLAG_VM))) { > > + if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM))) { > > struct drm_sched_job *drm_job = > > list_first_entry_or_null(&sched->pending_list, > > struct drm_sched_job, list); > > @@ -1383,7 +1383,7 @@ static void guc_engine_stop(struct xe_guc *guc, struct xe_engine *e) > > drm_sched_invalidate_job(drm_job, 2)) { > > trace_xe_sched_job_ban(job); > > sched->timeout = MIN_SCHED_TIMEOUT; > > - set_engine_banned(e); > > + set_exec_queue_banned(q); > > } > > } > > } > > @@ -1414,15 +1414,15 @@ void xe_guc_submit_reset_wait(struct xe_guc *guc) > > > > int xe_guc_submit_stop(struct xe_guc *guc) > > { > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > unsigned long index; > > > > XE_WARN_ON(guc_read_stopped(guc) != 1); > > > > mutex_lock(&guc->submission_state.lock); > > > > - xa_for_each(&guc->submission_state.engine_lookup, index, e) > > - guc_engine_stop(guc, e); > > + xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) > > + guc_exec_queue_stop(guc, q); > > > > mutex_unlock(&guc->submission_state.lock); > > > > @@ -1434,16 +1434,16 @@ int xe_guc_submit_stop(struct xe_guc *guc) > > return 0; > > } > > > > -static void guc_engine_start(struct xe_engine *e) > > +static void guc_exec_queue_start(struct xe_exec_queue *q) > > { > > - struct drm_gpu_scheduler *sched = &e->guc->sched; > > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > > > - if (!engine_killed_or_banned(e)) { > > + if (!exec_queue_killed_or_banned(q)) { > > int i; > > > > - trace_xe_engine_resubmit(e); > > - for (i = 0; i < e->width; ++i) > > - xe_lrc_set_ring_head(e->lrc + i, e->lrc[i].ring.tail); > > + trace_xe_exec_queue_resubmit(q); > > + for (i = 0; i < q->width; ++i) > > + xe_lrc_set_ring_head(q->lrc + i, q->lrc[i].ring.tail); > > drm_sched_resubmit_jobs(sched); > > } > > > > @@ -1453,15 +1453,15 @@ static void guc_engine_start(struct xe_engine *e) > > > > int xe_guc_submit_start(struct xe_guc *guc) > > { > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > unsigned long index; > > > > XE_WARN_ON(guc_read_stopped(guc) != 1); > > > > mutex_lock(&guc->submission_state.lock); > > atomic_dec(&guc->submission_state.stopped); > > - xa_for_each(&guc->submission_state.engine_lookup, index, e) > > - guc_engine_start(e); > > + xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) > > + guc_exec_queue_start(q); > > mutex_unlock(&guc->submission_state.lock); > > > > wake_up_all(&guc->ct.wq); > > @@ -1469,36 +1469,36 @@ int xe_guc_submit_start(struct xe_guc *guc) > > return 0; > > } > > > > -static struct xe_engine * > > -g2h_engine_lookup(struct xe_guc *guc, u32 guc_id) > > +static struct xe_exec_queue * > > +g2h_exec_queue_lookup(struct xe_guc *guc, u32 guc_id) > > { > > struct xe_device *xe = guc_to_xe(guc); > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > > > if (unlikely(guc_id >= GUC_ID_MAX)) { > > drm_err(&xe->drm, "Invalid guc_id %u", guc_id); > > return NULL; > > } > > > > - e = xa_load(&guc->submission_state.engine_lookup, guc_id); > > - if (unlikely(!e)) { > > + q = xa_load(&guc->submission_state.exec_queue_lookup, guc_id); > > + if (unlikely(!q)) { > > drm_err(&xe->drm, "Not engine present for guc_id %u", guc_id); > > return NULL; > > } > > > > - XE_WARN_ON(e->guc->id != guc_id); > > + XE_WARN_ON(q->guc->id != guc_id); > > > > - return e; > > + return q; > > } > > > > -static void deregister_engine(struct xe_guc *guc, struct xe_engine *e) > > +static void deregister_exec_queue(struct xe_guc *guc, struct xe_exec_queue *q) > > { > > u32 action[] = { > > XE_GUC_ACTION_DEREGISTER_CONTEXT, > > - e->guc->id, > > + q->guc->id, > > }; > > > > - trace_xe_engine_deregister(e); > > + trace_xe_exec_queue_deregister(q); > > > > xe_guc_ct_send_g2h_handler(&guc->ct, action, ARRAY_SIZE(action)); > > } > > @@ -1506,7 +1506,7 @@ static void deregister_engine(struct xe_guc *guc, struct xe_engine *e) > > int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > > { > > struct xe_device *xe = guc_to_xe(guc); > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > u32 guc_id = msg[0]; > > > > if (unlikely(len < 2)) { > > @@ -1514,34 +1514,34 @@ int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > > return -EPROTO; > > } > > > > - e = g2h_engine_lookup(guc, guc_id); > > - if (unlikely(!e)) > > + q = g2h_exec_queue_lookup(guc, guc_id); > > + if (unlikely(!q)) > > return -EPROTO; > > > > - if (unlikely(!engine_pending_enable(e) && > > - !engine_pending_disable(e))) { > > + if (unlikely(!exec_queue_pending_enable(q) && > > + !exec_queue_pending_disable(q))) { > > drm_err(&xe->drm, "Unexpected engine state 0x%04x", > > - atomic_read(&e->guc->state)); > > + atomic_read(&q->guc->state)); > > return -EPROTO; > > } > > > > - trace_xe_engine_scheduling_done(e); > > + trace_xe_exec_queue_scheduling_done(q); > > > > - if (engine_pending_enable(e)) { > > - e->guc->resume_time = ktime_get(); > > - clear_engine_pending_enable(e); > > + if (exec_queue_pending_enable(q)) { > > + q->guc->resume_time = ktime_get(); > > + clear_exec_queue_pending_enable(q); > > smp_wmb(); > > wake_up_all(&guc->ct.wq); > > } else { > > - clear_engine_pending_disable(e); > > - if (e->guc->suspend_pending) { > > - suspend_fence_signal(e); > > + clear_exec_queue_pending_disable(q); > > + if (q->guc->suspend_pending) { > > + suspend_fence_signal(q); > > } else { > > - if (engine_banned(e)) { > > + if (exec_queue_banned(q)) { > > smp_wmb(); > > wake_up_all(&guc->ct.wq); > > } > > - deregister_engine(guc, e); > > + deregister_exec_queue(guc, q); > > } > > } > > > > @@ -1551,7 +1551,7 @@ int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > > int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > > { > > struct xe_device *xe = guc_to_xe(guc); > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > u32 guc_id = msg[0]; > > > > if (unlikely(len < 1)) { > > @@ -1559,33 +1559,33 @@ int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len) > > return -EPROTO; > > } > > > > - e = g2h_engine_lookup(guc, guc_id); > > - if (unlikely(!e)) > > + q = g2h_exec_queue_lookup(guc, guc_id); > > + if (unlikely(!q)) > > return -EPROTO; > > > > - if (!engine_destroyed(e) || engine_pending_disable(e) || > > - engine_pending_enable(e) || engine_enabled(e)) { > > + if (!exec_queue_destroyed(q) || exec_queue_pending_disable(q) || > > + exec_queue_pending_enable(q) || exec_queue_enabled(q)) { > > drm_err(&xe->drm, "Unexpected engine state 0x%04x", > > - atomic_read(&e->guc->state)); > > + atomic_read(&q->guc->state)); > > return -EPROTO; > > } > > > > - trace_xe_engine_deregister_done(e); > > + trace_xe_exec_queue_deregister_done(q); > > > > - clear_engine_registered(e); > > + clear_exec_queue_registered(q); > > > > - if (engine_banned(e) || xe_engine_is_lr(e)) > > - xe_engine_put(e); > > + if (exec_queue_banned(q) || xe_exec_queue_is_lr(q)) > > + xe_exec_queue_put(q); > > else > > - __guc_engine_fini(guc, e); > > + __guc_exec_queue_fini(guc, q); > > > > return 0; > > } > > > > -int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) > > +int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) > > { > > struct xe_device *xe = guc_to_xe(guc); > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > u32 guc_id = msg[0]; > > > > if (unlikely(len < 1)) { > > @@ -1593,34 +1593,34 @@ int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len) > > return -EPROTO; > > } > > > > - e = g2h_engine_lookup(guc, guc_id); > > - if (unlikely(!e)) > > + q = g2h_exec_queue_lookup(guc, guc_id); > > + if (unlikely(!q)) > > return -EPROTO; > > > > drm_warn(&xe->drm, "Engine reset: guc_id=%d", guc_id); > > > > /* FIXME: Do error capture, most likely async */ > > > > - trace_xe_engine_reset(e); > > + trace_xe_exec_queue_reset(q); > > > > /* > > * A banned engine is a NOP at this point (came from > > - * guc_engine_timedout_job). Otherwise, kick drm scheduler to cancel > > + * guc_exec_queue_timedout_job). Otherwise, kick drm scheduler to cancel > > * jobs by setting timeout of the job to the minimum value kicking > > - * guc_engine_timedout_job. > > + * guc_exec_queue_timedout_job. > > */ > > - set_engine_reset(e); > > - if (!engine_banned(e)) > > - xe_guc_engine_trigger_cleanup(e); > > + set_exec_queue_reset(q); > > + if (!exec_queue_banned(q)) > > + xe_guc_exec_queue_trigger_cleanup(q); > > > > return 0; > > } > > > > -int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > > - u32 len) > > +int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > > + u32 len) > > { > > struct xe_device *xe = guc_to_xe(guc); > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > u32 guc_id = msg[0]; > > > > if (unlikely(len < 1)) { > > @@ -1628,22 +1628,22 @@ int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > > return -EPROTO; > > } > > > > - e = g2h_engine_lookup(guc, guc_id); > > - if (unlikely(!e)) > > + q = g2h_exec_queue_lookup(guc, guc_id); > > + if (unlikely(!q)) > > return -EPROTO; > > > > drm_warn(&xe->drm, "Engine memory cat error: guc_id=%d", guc_id); > > - trace_xe_engine_memory_cat_error(e); > > + trace_xe_exec_queue_memory_cat_error(q); > > > > /* Treat the same as engine reset */ > > - set_engine_reset(e); > > - if (!engine_banned(e)) > > - xe_guc_engine_trigger_cleanup(e); > > + set_exec_queue_reset(q); > > + if (!exec_queue_banned(q)) > > + xe_guc_exec_queue_trigger_cleanup(q); > > > > return 0; > > } > > > > -int xe_guc_engine_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) > > +int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) > > { > > struct xe_device *xe = guc_to_xe(guc); > > u8 guc_class, instance; > > @@ -1668,16 +1668,16 @@ int xe_guc_engine_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len) > > } > > > > static void > > -guc_engine_wq_snapshot_capture(struct xe_engine *e, > > - struct xe_guc_submit_engine_snapshot *snapshot) > > +guc_exec_queue_wq_snapshot_capture(struct xe_exec_queue *q, > > + struct xe_guc_submit_exec_queue_snapshot *snapshot) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > struct xe_device *xe = guc_to_xe(guc); > > - struct iosys_map map = xe_lrc_parallel_map(e->lrc); > > + struct iosys_map map = xe_lrc_parallel_map(q->lrc); > > int i; > > > > - snapshot->guc.wqi_head = e->guc->wqi_head; > > - snapshot->guc.wqi_tail = e->guc->wqi_tail; > > + snapshot->guc.wqi_head = q->guc->wqi_head; > > + snapshot->guc.wqi_tail = q->guc->wqi_tail; > > snapshot->parallel.wq_desc.head = parallel_read(xe, map, wq_desc.head); > > snapshot->parallel.wq_desc.tail = parallel_read(xe, map, wq_desc.tail); > > snapshot->parallel.wq_desc.status = parallel_read(xe, map, > > @@ -1694,8 +1694,8 @@ guc_engine_wq_snapshot_capture(struct xe_engine *e, > > } > > > > static void > > -guc_engine_wq_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > > - struct drm_printer *p) > > +guc_exec_queue_wq_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, > > + struct drm_printer *p) > > { > > int i; > > > > @@ -1716,23 +1716,23 @@ guc_engine_wq_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > > } > > > > /** > > - * xe_guc_engine_snapshot_capture - Take a quick snapshot of the GuC Engine. > > + * xe_guc_exec_queue_snapshot_capture - Take a quick snapshot of the GuC Engine. > > * @e: Xe Engine. > > * > > * This can be printed out in a later stage like during dev_coredump > > * analysis. > > * > > * Returns: a GuC Submit Engine snapshot object that must be freed by the > > - * caller, using `xe_guc_engine_snapshot_free`. > > + * caller, using `xe_guc_exec_queue_snapshot_free`. > > */ > > -struct xe_guc_submit_engine_snapshot * > > -xe_guc_engine_snapshot_capture(struct xe_engine *e) > > +struct xe_guc_submit_exec_queue_snapshot * > > +xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q) > > { > > - struct xe_guc *guc = engine_to_guc(e); > > + struct xe_guc *guc = exec_queue_to_guc(q); > > struct xe_device *xe = guc_to_xe(guc); > > - struct drm_gpu_scheduler *sched = &e->guc->sched; > > + struct drm_gpu_scheduler *sched = &q->guc->sched; > > struct xe_sched_job *job; > > - struct xe_guc_submit_engine_snapshot *snapshot; > > + struct xe_guc_submit_exec_queue_snapshot *snapshot; > > int i; > > > > snapshot = kzalloc(sizeof(*snapshot), GFP_ATOMIC); > > @@ -1742,25 +1742,25 @@ xe_guc_engine_snapshot_capture(struct xe_engine *e) > > return NULL; > > } > > > > - snapshot->guc.id = e->guc->id; > > - memcpy(&snapshot->name, &e->name, sizeof(snapshot->name)); > > - snapshot->class = e->class; > > - snapshot->logical_mask = e->logical_mask; > > - snapshot->width = e->width; > > - snapshot->refcount = kref_read(&e->refcount); > > + snapshot->guc.id = q->guc->id; > > + memcpy(&snapshot->name, &q->name, sizeof(snapshot->name)); > > + snapshot->class = q->class; > > + snapshot->logical_mask = q->logical_mask; > > + snapshot->width = q->width; > > + snapshot->refcount = kref_read(&q->refcount); > > snapshot->sched_timeout = sched->timeout; > > - snapshot->sched_props.timeslice_us = e->sched_props.timeslice_us; > > + snapshot->sched_props.timeslice_us = q->sched_props.timeslice_us; > > snapshot->sched_props.preempt_timeout_us = > > - e->sched_props.preempt_timeout_us; > > + q->sched_props.preempt_timeout_us; > > > > - snapshot->lrc = kmalloc_array(e->width, sizeof(struct lrc_snapshot), > > + snapshot->lrc = kmalloc_array(q->width, sizeof(struct lrc_snapshot), > > GFP_ATOMIC); > > > > if (!snapshot->lrc) { > > drm_err(&xe->drm, "Skipping GuC Engine LRC snapshot.\n"); > > } else { > > - for (i = 0; i < e->width; ++i) { > > - struct xe_lrc *lrc = e->lrc + i; > > + for (i = 0; i < q->width; ++i) { > > + struct xe_lrc *lrc = q->lrc + i; > > > > snapshot->lrc[i].context_desc = > > lower_32_bits(xe_lrc_ggtt_addr(lrc)); > > @@ -1773,12 +1773,12 @@ xe_guc_engine_snapshot_capture(struct xe_engine *e) > > } > > } > > > > - snapshot->schedule_state = atomic_read(&e->guc->state); > > - snapshot->engine_flags = e->flags; > > + snapshot->schedule_state = atomic_read(&q->guc->state); > > + snapshot->exec_queue_flags = q->flags; > > > > - snapshot->parallel_execution = xe_engine_is_parallel(e); > > + snapshot->parallel_execution = xe_exec_queue_is_parallel(q); > > if (snapshot->parallel_execution) > > - guc_engine_wq_snapshot_capture(e, snapshot); > > + guc_exec_queue_wq_snapshot_capture(q, snapshot); > > > > spin_lock(&sched->job_list_lock); > > snapshot->pending_list_size = list_count_nodes(&sched->pending_list); > > @@ -1808,15 +1808,15 @@ xe_guc_engine_snapshot_capture(struct xe_engine *e) > > } > > > > /** > > - * xe_guc_engine_snapshot_print - Print out a given GuC Engine snapshot. > > + * xe_guc_exec_queue_snapshot_print - Print out a given GuC Engine snapshot. > > * @snapshot: GuC Submit Engine snapshot object. > > * @p: drm_printer where it will be printed out. > > * > > * This function prints out a given GuC Submit Engine snapshot object. > > */ > > void > > -xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > > - struct drm_printer *p) > > +xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, > > + struct drm_printer *p) > > { > > int i; > > > > @@ -1848,10 +1848,10 @@ xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > > drm_printf(p, "\tSeqno: (memory) %d\n", snapshot->lrc[i].seqno); > > } > > drm_printf(p, "\tSchedule State: 0x%x\n", snapshot->schedule_state); > > - drm_printf(p, "\tFlags: 0x%lx\n", snapshot->engine_flags); > > + drm_printf(p, "\tFlags: 0x%lx\n", snapshot->exec_queue_flags); > > > > if (snapshot->parallel_execution) > > - guc_engine_wq_snapshot_print(snapshot, p); > > + guc_exec_queue_wq_snapshot_print(snapshot, p); > > > > for (i = 0; snapshot->pending_list && i < snapshot->pending_list_size; > > i++) > > @@ -1862,14 +1862,14 @@ xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > > } > > > > /** > > - * xe_guc_engine_snapshot_free - Free all allocated objects for a given > > + * xe_guc_exec_queue_snapshot_free - Free all allocated objects for a given > > * snapshot. > > * @snapshot: GuC Submit Engine snapshot object. > > * > > * This function free all the memory that needed to be allocated at capture > > * time. > > */ > > -void xe_guc_engine_snapshot_free(struct xe_guc_submit_engine_snapshot *snapshot) > > +void xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot) > > { > > if (!snapshot) > > return; > > @@ -1879,13 +1879,13 @@ void xe_guc_engine_snapshot_free(struct xe_guc_submit_engine_snapshot *snapshot) > > kfree(snapshot); > > } > > > > -static void guc_engine_print(struct xe_engine *e, struct drm_printer *p) > > +static void guc_exec_queue_print(struct xe_exec_queue *q, struct drm_printer *p) > > { > > - struct xe_guc_submit_engine_snapshot *snapshot; > > + struct xe_guc_submit_exec_queue_snapshot *snapshot; > > > > - snapshot = xe_guc_engine_snapshot_capture(e); > > - xe_guc_engine_snapshot_print(snapshot, p); > > - xe_guc_engine_snapshot_free(snapshot); > > + snapshot = xe_guc_exec_queue_snapshot_capture(q); > > + xe_guc_exec_queue_snapshot_print(snapshot, p); > > + xe_guc_exec_queue_snapshot_free(snapshot); > > } > > > > /** > > @@ -1897,14 +1897,14 @@ static void guc_engine_print(struct xe_engine *e, struct drm_printer *p) > > */ > > void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p) > > { > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > unsigned long index; > > > > if (!xe_device_guc_submission_enabled(guc_to_xe(guc))) > > return; > > > > mutex_lock(&guc->submission_state.lock); > > - xa_for_each(&guc->submission_state.engine_lookup, index, e) > > - guc_engine_print(e, p); > > + xa_for_each(&guc->submission_state.exec_queue_lookup, index, q) > > + guc_exec_queue_print(q, p); > > mutex_unlock(&guc->submission_state.lock); > > } > > diff --git a/drivers/gpu/drm/xe/xe_guc_submit.h b/drivers/gpu/drm/xe/xe_guc_submit.h > > index 4153c2d22013..fc97869c5b86 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_submit.h > > +++ b/drivers/gpu/drm/xe/xe_guc_submit.h > > @@ -9,7 +9,7 @@ > > #include <linux/types.h> > > > > struct drm_printer; > > -struct xe_engine; > > +struct xe_exec_queue; > > struct xe_guc; > > > > int xe_guc_submit_init(struct xe_guc *guc); > > @@ -21,18 +21,18 @@ int xe_guc_submit_start(struct xe_guc *guc); > > > > int xe_guc_sched_done_handler(struct xe_guc *guc, u32 *msg, u32 len); > > int xe_guc_deregister_done_handler(struct xe_guc *guc, u32 *msg, u32 len); > > -int xe_guc_engine_reset_handler(struct xe_guc *guc, u32 *msg, u32 len); > > -int xe_guc_engine_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > > - u32 len); > > -int xe_guc_engine_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len); > > +int xe_guc_exec_queue_reset_handler(struct xe_guc *guc, u32 *msg, u32 len); > > +int xe_guc_exec_queue_memory_cat_error_handler(struct xe_guc *guc, u32 *msg, > > + u32 len); > > +int xe_guc_exec_queue_reset_failure_handler(struct xe_guc *guc, u32 *msg, u32 len); > > > > -struct xe_guc_submit_engine_snapshot * > > -xe_guc_engine_snapshot_capture(struct xe_engine *e); > > +struct xe_guc_submit_exec_queue_snapshot * > > +xe_guc_exec_queue_snapshot_capture(struct xe_exec_queue *q); > > void > > -xe_guc_engine_snapshot_print(struct xe_guc_submit_engine_snapshot *snapshot, > > - struct drm_printer *p); > > +xe_guc_exec_queue_snapshot_print(struct xe_guc_submit_exec_queue_snapshot *snapshot, > > + struct drm_printer *p); > > void > > -xe_guc_engine_snapshot_free(struct xe_guc_submit_engine_snapshot *snapshot); > > +xe_guc_exec_queue_snapshot_free(struct xe_guc_submit_exec_queue_snapshot *snapshot); > > void xe_guc_submit_print(struct xe_guc *guc, struct drm_printer *p); > > > > #endif > > diff --git a/drivers/gpu/drm/xe/xe_guc_submit_types.h b/drivers/gpu/drm/xe/xe_guc_submit_types.h > > index 6765b2c6eab1..649b0a852692 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_submit_types.h > > +++ b/drivers/gpu/drm/xe/xe_guc_submit_types.h > > @@ -79,20 +79,20 @@ struct pending_list_snapshot { > > }; > > > > /** > > - * struct xe_guc_submit_engine_snapshot - Snapshot for devcoredump > > + * struct xe_guc_submit_exec_queue_snapshot - Snapshot for devcoredump > > */ > > -struct xe_guc_submit_engine_snapshot { > > - /** @name: name of this engine */ > > +struct xe_guc_submit_exec_queue_snapshot { > > + /** @name: name of this exec queue */ > > char name[MAX_FENCE_NAME_LEN]; > > - /** @class: class of this engine */ > > + /** @class: class of this exec queue */ > > enum xe_engine_class class; > > /** > > - * @logical_mask: logical mask of where job submitted to engine can run > > + * @logical_mask: logical mask of where job submitted to exec queue can run > > */ > > u32 logical_mask; > > - /** @width: width (number BB submitted per exec) of this engine */ > > + /** @width: width (number BB submitted per exec) of this exec queue */ > > u16 width; > > - /** @refcount: ref count of this engine */ > > + /** @refcount: ref count of this exec queue */ > > u32 refcount; > > /** > > * @sched_timeout: the time after which a job is removed from the > > @@ -113,8 +113,8 @@ struct xe_guc_submit_engine_snapshot { > > > > /** @schedule_state: Schedule State at the moment of Crash */ > > u32 schedule_state; > > - /** @engine_flags: Flags of the faulty engine */ > > - unsigned long engine_flags; > > + /** @exec_queue_flags: Flags of the faulty exec_queue */ > > + unsigned long exec_queue_flags; > > > > /** @guc: GuC Engine Snapshot */ > > struct { > > @@ -122,7 +122,7 @@ struct xe_guc_submit_engine_snapshot { > > u32 wqi_head; > > /** @wqi_tail: work queue item tail */ > > u32 wqi_tail; > > - /** @id: GuC id for this xe_engine */ > > + /** @id: GuC id for this exec_queue */ > > u16 id; > > } guc; > > > > diff --git a/drivers/gpu/drm/xe/xe_guc_types.h b/drivers/gpu/drm/xe/xe_guc_types.h > > index a304dce4e9f4..a5e58917a499 100644 > > --- a/drivers/gpu/drm/xe/xe_guc_types.h > > +++ b/drivers/gpu/drm/xe/xe_guc_types.h > > @@ -33,8 +33,8 @@ struct xe_guc { > > struct xe_guc_pc pc; > > /** @submission_state: GuC submission state */ > > struct { > > - /** @engine_lookup: Lookup an xe_engine from guc_id */ > > - struct xarray engine_lookup; > > + /** @exec_queue_lookup: Lookup an xe_engine from guc_id */ > > + struct xarray exec_queue_lookup; > > /** @guc_ids: used to allocate new guc_ids, single-lrc */ > > struct ida guc_ids; > > /** @guc_ids_bitmap: used to allocate new guc_ids, multi-lrc */ > > diff --git a/drivers/gpu/drm/xe/xe_lrc.c b/drivers/gpu/drm/xe/xe_lrc.c > > index 05f3d8d68379..09db8da261a3 100644 > > --- a/drivers/gpu/drm/xe/xe_lrc.c > > +++ b/drivers/gpu/drm/xe/xe_lrc.c > > @@ -12,7 +12,7 @@ > > #include "regs/xe_regs.h" > > #include "xe_bo.h" > > #include "xe_device.h" > > -#include "xe_engine_types.h" > > +#include "xe_exec_queue_types.h" > > #include "xe_gt.h" > > #include "xe_hw_fence.h" > > #include "xe_map.h" > > @@ -604,7 +604,7 @@ static void xe_lrc_set_ppgtt(struct xe_lrc *lrc, struct xe_vm *vm) > > #define ACC_NOTIFY_S 16 > > > > int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, > > - struct xe_engine *e, struct xe_vm *vm, u32 ring_size) > > + struct xe_exec_queue *q, struct xe_vm *vm, u32 ring_size) > > { > > struct xe_gt *gt = hwe->gt; > > struct xe_tile *tile = gt_to_tile(gt); > > @@ -669,12 +669,12 @@ int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, > > RING_CTL_SIZE(lrc->ring.size) | RING_VALID); > > if (xe->info.has_asid && vm) > > xe_lrc_write_ctx_reg(lrc, PVC_CTX_ASID, > > - (e->usm.acc_granularity << > > + (q->usm.acc_granularity << > > ACC_GRANULARITY_S) | vm->usm.asid); > > if (xe->info.supports_usm && vm) > > xe_lrc_write_ctx_reg(lrc, PVC_CTX_ACC_CTR_THOLD, > > - (e->usm.acc_notify << ACC_NOTIFY_S) | > > - e->usm.acc_trigger); > > + (q->usm.acc_notify << ACC_NOTIFY_S) | > > + q->usm.acc_trigger); > > > > lrc->desc = GEN8_CTX_VALID; > > lrc->desc |= INTEL_LEGACY_64B_CONTEXT << GEN8_CTX_ADDRESSING_MODE_SHIFT; > > diff --git a/drivers/gpu/drm/xe/xe_lrc.h b/drivers/gpu/drm/xe/xe_lrc.h > > index e37f89e75ef8..3a6e8fc5a837 100644 > > --- a/drivers/gpu/drm/xe/xe_lrc.h > > +++ b/drivers/gpu/drm/xe/xe_lrc.h > > @@ -8,7 +8,7 @@ > > #include "xe_lrc_types.h" > > > > struct xe_device; > > -struct xe_engine; > > +struct xe_exec_queue; > > enum xe_engine_class; > > struct xe_hw_engine; > > struct xe_vm; > > @@ -16,7 +16,7 @@ struct xe_vm; > > #define LRC_PPHWSP_SCRATCH_ADDR (0x34 * 4) > > > > int xe_lrc_init(struct xe_lrc *lrc, struct xe_hw_engine *hwe, > > - struct xe_engine *e, struct xe_vm *vm, u32 ring_size); > > + struct xe_exec_queue *q, struct xe_vm *vm, u32 ring_size); > > void xe_lrc_finish(struct xe_lrc *lrc); > > > > size_t xe_lrc_size(struct xe_device *xe, enum xe_engine_class class); > > diff --git a/drivers/gpu/drm/xe/xe_migrate.c b/drivers/gpu/drm/xe/xe_migrate.c > > index 414f93cddb28..7af2d74833c0 100644 > > --- a/drivers/gpu/drm/xe/xe_migrate.c > > +++ b/drivers/gpu/drm/xe/xe_migrate.c > > @@ -16,7 +16,7 @@ > > #include "tests/xe_test.h" > > #include "xe_bb.h" > > #include "xe_bo.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_ggtt.h" > > #include "xe_gt.h" > > #include "xe_hw_engine.h" > > @@ -35,7 +35,7 @@ > > */ > > struct xe_migrate { > > /** @eng: Default engine used for migration */ > > - struct xe_engine *eng; > > + struct xe_exec_queue *q; > > /** @tile: Backpointer to the tile this struct xe_migrate belongs to. */ > > struct xe_tile *tile; > > /** @job_mutex: Timeline mutex for @eng. */ > > @@ -78,9 +78,9 @@ struct xe_migrate { > > * > > * Return: The default migrate engine > > */ > > -struct xe_engine *xe_tile_migrate_engine(struct xe_tile *tile) > > +struct xe_exec_queue *xe_tile_migrate_engine(struct xe_tile *tile) > > { > > - return tile->migrate->eng; > > + return tile->migrate->q; > > } > > > > static void xe_migrate_fini(struct drm_device *dev, void *arg) > > @@ -88,11 +88,11 @@ static void xe_migrate_fini(struct drm_device *dev, void *arg) > > struct xe_migrate *m = arg; > > struct ww_acquire_ctx ww; > > > > - xe_vm_lock(m->eng->vm, &ww, 0, false); > > + xe_vm_lock(m->q->vm, &ww, 0, false); > > xe_bo_unpin(m->pt_bo); > > if (m->cleared_bo) > > xe_bo_unpin(m->cleared_bo); > > - xe_vm_unlock(m->eng->vm, &ww); > > + xe_vm_unlock(m->q->vm, &ww); > > > > dma_fence_put(m->fence); > > if (m->cleared_bo) > > @@ -100,8 +100,8 @@ static void xe_migrate_fini(struct drm_device *dev, void *arg) > > xe_bo_put(m->pt_bo); > > drm_suballoc_manager_fini(&m->vm_update_sa); > > mutex_destroy(&m->job_mutex); > > - xe_vm_close_and_put(m->eng->vm); > > - xe_engine_put(m->eng); > > + xe_vm_close_and_put(m->q->vm); > > + xe_exec_queue_put(m->q); > > } > > > > static u64 xe_migrate_vm_addr(u64 slot, u32 level) > > @@ -341,20 +341,20 @@ struct xe_migrate *xe_migrate_init(struct xe_tile *tile) > > if (!hwe) > > return ERR_PTR(-EINVAL); > > > > - m->eng = xe_engine_create(xe, vm, > > - BIT(hwe->logical_instance), 1, > > - hwe, ENGINE_FLAG_KERNEL); > > + m->q = xe_exec_queue_create(xe, vm, > > + BIT(hwe->logical_instance), 1, > > + hwe, EXEC_QUEUE_FLAG_KERNEL); > > } else { > > - m->eng = xe_engine_create_class(xe, primary_gt, vm, > > - XE_ENGINE_CLASS_COPY, > > - ENGINE_FLAG_KERNEL); > > + m->q = xe_exec_queue_create_class(xe, primary_gt, vm, > > + XE_ENGINE_CLASS_COPY, > > + EXEC_QUEUE_FLAG_KERNEL); > > } > > - if (IS_ERR(m->eng)) { > > + if (IS_ERR(m->q)) { > > xe_vm_close_and_put(vm); > > - return ERR_CAST(m->eng); > > + return ERR_CAST(m->q); > > } > > if (xe->info.supports_usm) > > - m->eng->entity->priority = DRM_SCHED_PRIORITY_KERNEL; > > + m->q->entity->priority = DRM_SCHED_PRIORITY_KERNEL; > > > > mutex_init(&m->job_mutex); > > > > @@ -456,7 +456,7 @@ static void emit_pte(struct xe_migrate *m, > > addr = xe_res_dma(cur) & PAGE_MASK; > > if (is_vram) { > > /* Is this a 64K PTE entry? */ > > - if ((m->eng->vm->flags & XE_VM_FLAG_64K) && > > + if ((m->q->vm->flags & XE_VM_FLAG_64K) && > > !(cur_ofs & (16 * 8 - 1))) { > > XE_WARN_ON(!IS_ALIGNED(addr, SZ_64K)); > > addr |= XE_PTE_PS64; > > @@ -714,7 +714,7 @@ struct dma_fence *xe_migrate_copy(struct xe_migrate *m, > > src_L0, ccs_ofs, copy_ccs); > > > > mutex_lock(&m->job_mutex); > > - job = xe_bb_create_migration_job(m->eng, bb, > > + job = xe_bb_create_migration_job(m->q, bb, > > xe_migrate_batch_base(m, usm), > > update_idx); > > if (IS_ERR(job)) { > > @@ -938,7 +938,7 @@ struct dma_fence *xe_migrate_clear(struct xe_migrate *m, > > } > > > > mutex_lock(&m->job_mutex); > > - job = xe_bb_create_migration_job(m->eng, bb, > > + job = xe_bb_create_migration_job(m->q, bb, > > xe_migrate_batch_base(m, usm), > > update_idx); > > if (IS_ERR(job)) { > > @@ -1024,7 +1024,7 @@ static void write_pgtable(struct xe_tile *tile, struct xe_bb *bb, u64 ppgtt_ofs, > > > > struct xe_vm *xe_migrate_get_vm(struct xe_migrate *m) > > { > > - return xe_vm_get(m->eng->vm); > > + return xe_vm_get(m->q->vm); > > } > > > > #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) > > @@ -1132,7 +1132,7 @@ struct dma_fence * > > xe_migrate_update_pgtables(struct xe_migrate *m, > > struct xe_vm *vm, > > struct xe_bo *bo, > > - struct xe_engine *eng, > > + struct xe_exec_queue *q, > > const struct xe_vm_pgtable_update *updates, > > u32 num_updates, > > struct xe_sync_entry *syncs, u32 num_syncs, > > @@ -1150,13 +1150,13 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > > u32 i, batch_size, ppgtt_ofs, update_idx, page_ofs = 0; > > u64 addr; > > int err = 0; > > - bool usm = !eng && xe->info.supports_usm; > > + bool usm = !q && xe->info.supports_usm; > > bool first_munmap_rebind = vma && > > vma->gpuva.flags & XE_VMA_FIRST_REBIND; > > - struct xe_engine *eng_override = !eng ? m->eng : eng; > > + struct xe_exec_queue *q_override = !q ? m->q : q; > > > > /* Use the CPU if no in syncs and engine is idle */ > > - if (no_in_syncs(syncs, num_syncs) && xe_engine_is_idle(eng_override)) { > > + if (no_in_syncs(syncs, num_syncs) && xe_exec_queue_is_idle(q_override)) { > > fence = xe_migrate_update_pgtables_cpu(m, vm, bo, updates, > > num_updates, > > first_munmap_rebind, > > @@ -1186,14 +1186,14 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > > */ > > XE_WARN_ON(batch_size >= SZ_128K); > > > > - bb = xe_bb_new(gt, batch_size, !eng && xe->info.supports_usm); > > + bb = xe_bb_new(gt, batch_size, !q && xe->info.supports_usm); > > if (IS_ERR(bb)) > > return ERR_CAST(bb); > > > > /* For sysmem PTE's, need to map them in our hole.. */ > > if (!IS_DGFX(xe)) { > > ppgtt_ofs = NUM_KERNEL_PDE - 1; > > - if (eng) { > > + if (q) { > > XE_WARN_ON(num_updates > NUM_VMUSA_WRITES_PER_UNIT); > > > > sa_bo = drm_suballoc_new(&m->vm_update_sa, 1, > > @@ -1249,10 +1249,10 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > > write_pgtable(tile, bb, 0, &updates[i], pt_update); > > } > > > > - if (!eng) > > + if (!q) > > mutex_lock(&m->job_mutex); > > > > - job = xe_bb_create_migration_job(eng ?: m->eng, bb, > > + job = xe_bb_create_migration_job(q ?: m->q, bb, > > xe_migrate_batch_base(m, usm), > > update_idx); > > if (IS_ERR(job)) { > > @@ -1295,7 +1295,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > > fence = dma_fence_get(&job->drm.s_fence->finished); > > xe_sched_job_push(job); > > > > - if (!eng) > > + if (!q) > > mutex_unlock(&m->job_mutex); > > > > xe_bb_free(bb, fence); > > @@ -1306,7 +1306,7 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > > err_job: > > xe_sched_job_put(job); > > err_bb: > > - if (!eng) > > + if (!q) > > mutex_unlock(&m->job_mutex); > > xe_bb_free(bb, NULL); > > err: > > diff --git a/drivers/gpu/drm/xe/xe_migrate.h b/drivers/gpu/drm/xe/xe_migrate.h > > index 0d62aff6421c..c729241776ad 100644 > > --- a/drivers/gpu/drm/xe/xe_migrate.h > > +++ b/drivers/gpu/drm/xe/xe_migrate.h > > @@ -14,7 +14,7 @@ struct ttm_resource; > > > > struct xe_bo; > > struct xe_gt; > > -struct xe_engine; > > +struct xe_exec_queue; > > struct xe_migrate; > > struct xe_migrate_pt_update; > > struct xe_sync_entry; > > @@ -97,7 +97,7 @@ struct dma_fence * > > xe_migrate_update_pgtables(struct xe_migrate *m, > > struct xe_vm *vm, > > struct xe_bo *bo, > > - struct xe_engine *eng, > > + struct xe_exec_queue *q, > > const struct xe_vm_pgtable_update *updates, > > u32 num_updates, > > struct xe_sync_entry *syncs, u32 num_syncs, > > @@ -105,5 +105,5 @@ xe_migrate_update_pgtables(struct xe_migrate *m, > > > > void xe_migrate_wait(struct xe_migrate *m); > > > > -struct xe_engine *xe_tile_migrate_engine(struct xe_tile *tile); > > +struct xe_exec_queue *xe_tile_migrate_engine(struct xe_tile *tile); > > #endif > > diff --git a/drivers/gpu/drm/xe/xe_mocs.c b/drivers/gpu/drm/xe/xe_mocs.c > > index ccc852500eda..c9653978fc9f 100644 > > --- a/drivers/gpu/drm/xe/xe_mocs.c > > +++ b/drivers/gpu/drm/xe/xe_mocs.c > > @@ -8,7 +8,7 @@ > > #include "regs/xe_gt_regs.h" > > #include "xe_bo.h" > > #include "xe_device.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_gt.h" > > #include "xe_mmio.h" > > #include "xe_platform_types.h" > > diff --git a/drivers/gpu/drm/xe/xe_mocs.h b/drivers/gpu/drm/xe/xe_mocs.h > > index 25f7b35a76da..d0f1ec4b0336 100644 > > --- a/drivers/gpu/drm/xe/xe_mocs.h > > +++ b/drivers/gpu/drm/xe/xe_mocs.h > > @@ -8,7 +8,7 @@ > > > > #include <linux/types.h> > > > > -struct xe_engine; > > +struct xe_exec_queue; > > struct xe_gt; > > > > void xe_mocs_init_early(struct xe_gt *gt); > > diff --git a/drivers/gpu/drm/xe/xe_preempt_fence.c b/drivers/gpu/drm/xe/xe_preempt_fence.c > > index 219eefeb90ff..e0ce1588a734 100644 > > --- a/drivers/gpu/drm/xe/xe_preempt_fence.c > > +++ b/drivers/gpu/drm/xe/xe_preempt_fence.c > > @@ -7,7 +7,7 @@ > > > > #include <linux/slab.h> > > > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_vm.h" > > > > static void preempt_fence_work_func(struct work_struct *w) > > @@ -15,19 +15,19 @@ static void preempt_fence_work_func(struct work_struct *w) > > bool cookie = dma_fence_begin_signalling(); > > struct xe_preempt_fence *pfence = > > container_of(w, typeof(*pfence), preempt_work); > > - struct xe_engine *e = pfence->engine; > > + struct xe_exec_queue *q = pfence->q; > > > > if (pfence->error) > > dma_fence_set_error(&pfence->base, pfence->error); > > else > > - e->ops->suspend_wait(e); > > + q->ops->suspend_wait(q); > > > > dma_fence_signal(&pfence->base); > > dma_fence_end_signalling(cookie); > > > > - xe_vm_queue_rebind_worker(e->vm); > > + xe_vm_queue_rebind_worker(q->vm); > > > > - xe_engine_put(e); > > + xe_exec_queue_put(q); > > } > > > > static const char * > > @@ -46,9 +46,9 @@ static bool preempt_fence_enable_signaling(struct dma_fence *fence) > > { > > struct xe_preempt_fence *pfence = > > container_of(fence, typeof(*pfence), base); > > - struct xe_engine *e = pfence->engine; > > + struct xe_exec_queue *q = pfence->q; > > > > - pfence->error = e->ops->suspend(e); > > + pfence->error = q->ops->suspend(q); > > queue_work(system_unbound_wq, &pfence->preempt_work); > > return true; > > } > > @@ -104,43 +104,43 @@ void xe_preempt_fence_free(struct xe_preempt_fence *pfence) > > * xe_preempt_fence_alloc(). > > * @pfence: The struct xe_preempt_fence pointer returned from > > * xe_preempt_fence_alloc(). > > - * @e: The struct xe_engine used for arming. > > + * @e: The struct xe_exec_queue used for arming. > > * @context: The dma-fence context used for arming. > > * @seqno: The dma-fence seqno used for arming. > > * > > * Inserts the preempt fence into @context's timeline, takes @link off any > > - * list, and registers the struct xe_engine as the xe_engine to be preempted. > > + * list, and registers the struct xe_exec_queue as the xe_engine to be preempted. > > * > > * Return: A pointer to a struct dma_fence embedded into the preempt fence. > > * This function doesn't error. > > */ > > struct dma_fence * > > -xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_engine *e, > > +xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_exec_queue *q, > > u64 context, u32 seqno) > > { > > list_del_init(&pfence->link); > > - pfence->engine = xe_engine_get(e); > > + pfence->q = xe_exec_queue_get(q); > > dma_fence_init(&pfence->base, &preempt_fence_ops, > > - &e->compute.lock, context, seqno); > > + &q->compute.lock, context, seqno); > > > > return &pfence->base; > > } > > > > /** > > * xe_preempt_fence_create() - Helper to create and arm a preempt fence. > > - * @e: The struct xe_engine used for arming. > > + * @e: The struct xe_exec_queue used for arming. > > * @context: The dma-fence context used for arming. > > * @seqno: The dma-fence seqno used for arming. > > * > > * Allocates and inserts the preempt fence into @context's timeline, > > - * and registers @e as the struct xe_engine to be preempted. > > + * and registers @e as the struct xe_exec_queue to be preempted. > > * > > * Return: A pointer to the resulting struct dma_fence on success. An error > > * pointer on error. In particular if allocation fails it returns > > * ERR_PTR(-ENOMEM); > > */ > > struct dma_fence * > > -xe_preempt_fence_create(struct xe_engine *e, > > +xe_preempt_fence_create(struct xe_exec_queue *q, > > u64 context, u32 seqno) > > { > > struct xe_preempt_fence *pfence; > > @@ -149,7 +149,7 @@ xe_preempt_fence_create(struct xe_engine *e, > > if (IS_ERR(pfence)) > > return ERR_CAST(pfence); > > > > - return xe_preempt_fence_arm(pfence, e, context, seqno); > > + return xe_preempt_fence_arm(pfence, q, context, seqno); > > } > > > > bool xe_fence_is_xe_preempt(const struct dma_fence *fence) > > diff --git a/drivers/gpu/drm/xe/xe_preempt_fence.h b/drivers/gpu/drm/xe/xe_preempt_fence.h > > index 4f3966103203..9406c6fea525 100644 > > --- a/drivers/gpu/drm/xe/xe_preempt_fence.h > > +++ b/drivers/gpu/drm/xe/xe_preempt_fence.h > > @@ -11,7 +11,7 @@ > > struct list_head; > > > > struct dma_fence * > > -xe_preempt_fence_create(struct xe_engine *e, > > +xe_preempt_fence_create(struct xe_exec_queue *q, > > u64 context, u32 seqno); > > > > struct xe_preempt_fence *xe_preempt_fence_alloc(void); > > @@ -19,7 +19,7 @@ struct xe_preempt_fence *xe_preempt_fence_alloc(void); > > void xe_preempt_fence_free(struct xe_preempt_fence *pfence); > > > > struct dma_fence * > > -xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_engine *e, > > +xe_preempt_fence_arm(struct xe_preempt_fence *pfence, struct xe_exec_queue *q, > > u64 context, u32 seqno); > > > > static inline struct xe_preempt_fence * > > diff --git a/drivers/gpu/drm/xe/xe_preempt_fence_types.h b/drivers/gpu/drm/xe/xe_preempt_fence_types.h > > index 9d9efd8ff0ed..176ea1e9e204 100644 > > --- a/drivers/gpu/drm/xe/xe_preempt_fence_types.h > > +++ b/drivers/gpu/drm/xe/xe_preempt_fence_types.h > > @@ -9,12 +9,11 @@ > > #include <linux/dma-fence.h> > > #include <linux/workqueue.h> > > > > -struct xe_engine; > > +struct xe_exec_queue; > > > > /** > > * struct xe_preempt_fence - XE preempt fence > > * > > - * A preemption fence which suspends the execution of an xe_engine on the > > * hardware and triggers a callback once the xe_engine is complete. > > */ > > struct xe_preempt_fence { > > @@ -23,7 +22,7 @@ struct xe_preempt_fence { > > /** @link: link into list of pending preempt fences */ > > struct list_head link; > > /** @engine: xe engine for this preempt fence */ > > - struct xe_engine *engine; > > + struct xe_exec_queue *q; > > /** @preempt_work: work struct which issues preemption */ > > struct work_struct preempt_work; > > /** @error: preempt fence is in error state */ > > diff --git a/drivers/gpu/drm/xe/xe_pt.c b/drivers/gpu/drm/xe/xe_pt.c > > index 9b034272d82f..5709518e314b 100644 > > --- a/drivers/gpu/drm/xe/xe_pt.c > > +++ b/drivers/gpu/drm/xe/xe_pt.c > > @@ -1307,7 +1307,7 @@ static void xe_pt_calc_rfence_interval(struct xe_vma *vma, > > * address range. > > * @tile: The tile to bind for. > > * @vma: The vma to bind. > > - * @e: The engine with which to do pipelined page-table updates. > > + * @q: The exec_queue with which to do pipelined page-table updates. > > * @syncs: Entries to sync on before binding the built tree to the live vm tree. > > * @num_syncs: Number of @sync entries. > > * @rebind: Whether we're rebinding this vma to the same address range without > > @@ -1325,7 +1325,7 @@ static void xe_pt_calc_rfence_interval(struct xe_vma *vma, > > * on success, an error pointer on error. > > */ > > struct dma_fence * > > -__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > > +__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, > > struct xe_sync_entry *syncs, u32 num_syncs, > > bool rebind) > > { > > @@ -1351,7 +1351,7 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > > > > vm_dbg(&xe_vma_vm(vma)->xe->drm, > > "Preparing bind, with range [%llx...%llx) engine %p.\n", > > - xe_vma_start(vma), xe_vma_end(vma) - 1, e); > > + xe_vma_start(vma), xe_vma_end(vma) - 1, q); > > > > err = xe_pt_prepare_bind(tile, vma, entries, &num_entries, rebind); > > if (err) > > @@ -1388,7 +1388,7 @@ __xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > > } > > > > fence = xe_migrate_update_pgtables(tile->migrate, > > - vm, xe_vma_bo(vma), e, > > + vm, xe_vma_bo(vma), q, > > entries, num_entries, > > syncs, num_syncs, > > &bind_pt_update.base); > > @@ -1663,7 +1663,7 @@ static const struct xe_migrate_pt_update_ops userptr_unbind_ops = { > > * address range. > > * @tile: The tile to unbind for. > > * @vma: The vma to unbind. > > - * @e: The engine with which to do pipelined page-table updates. > > + * @q: The exec_queue with which to do pipelined page-table updates. > > * @syncs: Entries to sync on before disconnecting the tree to be destroyed. > > * @num_syncs: Number of @sync entries. > > * > > @@ -1679,7 +1679,7 @@ static const struct xe_migrate_pt_update_ops userptr_unbind_ops = { > > * on success, an error pointer on error. > > */ > > struct dma_fence * > > -__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > > +__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, > > struct xe_sync_entry *syncs, u32 num_syncs) > > { > > struct xe_vm_pgtable_update entries[XE_VM_MAX_LEVEL * 2 + 1]; > > @@ -1704,7 +1704,7 @@ __xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e > > > > vm_dbg(&xe_vma_vm(vma)->xe->drm, > > "Preparing unbind, with range [%llx...%llx) engine %p.\n", > > - xe_vma_start(vma), xe_vma_end(vma) - 1, e); > > + xe_vma_start(vma), xe_vma_end(vma) - 1, q); > > > > num_entries = xe_pt_stage_unbind(tile, vma, entries); > > XE_WARN_ON(num_entries > ARRAY_SIZE(entries)); > > @@ -1729,8 +1729,8 @@ __xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e > > * lower level, because it needs to be more conservative. > > */ > > fence = xe_migrate_update_pgtables(tile->migrate, > > - vm, NULL, e ? e : > > - vm->eng[tile->id], > > + vm, NULL, q ? q : > > + vm->q[tile->id], > > entries, num_entries, > > syncs, num_syncs, > > &unbind_pt_update.base); > > diff --git a/drivers/gpu/drm/xe/xe_pt.h b/drivers/gpu/drm/xe/xe_pt.h > > index bbb00d6461ff..01be7ab08f87 100644 > > --- a/drivers/gpu/drm/xe/xe_pt.h > > +++ b/drivers/gpu/drm/xe/xe_pt.h > > @@ -12,7 +12,7 @@ > > struct dma_fence; > > struct xe_bo; > > struct xe_device; > > -struct xe_engine; > > +struct xe_exec_queue; > > struct xe_sync_entry; > > struct xe_tile; > > struct xe_vm; > > @@ -35,12 +35,12 @@ void xe_pt_populate_empty(struct xe_tile *tile, struct xe_vm *vm, > > void xe_pt_destroy(struct xe_pt *pt, u32 flags, struct llist_head *deferred); > > > > struct dma_fence * > > -__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > > +__xe_pt_bind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, > > struct xe_sync_entry *syncs, u32 num_syncs, > > bool rebind); > > > > struct dma_fence * > > -__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_engine *e, > > +__xe_pt_unbind_vma(struct xe_tile *tile, struct xe_vma *vma, struct xe_exec_queue *q, > > struct xe_sync_entry *syncs, u32 num_syncs); > > > > bool xe_pt_zap_ptes(struct xe_tile *tile, struct xe_vma *vma); > > diff --git a/drivers/gpu/drm/xe/xe_query.c b/drivers/gpu/drm/xe/xe_query.c > > index 6ba7baf7c777..7ea235c71385 100644 > > --- a/drivers/gpu/drm/xe/xe_query.c > > +++ b/drivers/gpu/drm/xe/xe_query.c > > @@ -12,7 +12,7 @@ > > > > #include "xe_bo.h" > > #include "xe_device.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_ggtt.h" > > #include "xe_gt.h" > > #include "xe_guc_hwconfig.h" > > @@ -203,7 +203,7 @@ static int query_config(struct xe_device *xe, struct drm_xe_device_query *query) > > config->info[XE_QUERY_CONFIG_MEM_REGION_COUNT] = > > hweight_long(xe->info.mem_region_mask); > > config->info[XE_QUERY_CONFIG_MAX_ENGINE_PRIORITY] = > > - xe_engine_device_get_max_priority(xe); > > + xe_exec_queue_device_get_max_priority(xe); > > > > if (copy_to_user(query_ptr, config, size)) { > > kfree(config); > > diff --git a/drivers/gpu/drm/xe/xe_ring_ops.c b/drivers/gpu/drm/xe/xe_ring_ops.c > > index c9ef44e63772..4a474ab04f96 100644 > > --- a/drivers/gpu/drm/xe/xe_ring_ops.c > > +++ b/drivers/gpu/drm/xe/xe_ring_ops.c > > @@ -10,7 +10,7 @@ > > #include "regs/xe_gt_regs.h" > > #include "regs/xe_lrc_layout.h" > > #include "regs/xe_regs.h" > > -#include "xe_engine_types.h" > > +#include "xe_exec_queue_types.h" > > #include "xe_gt.h" > > #include "xe_lrc.h" > > #include "xe_macros.h" > > @@ -156,7 +156,7 @@ static int emit_store_imm_ppgtt_posted(u64 addr, u64 value, > > > > static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i) > > { > > - struct xe_gt *gt = job->engine->gt; > > + struct xe_gt *gt = job->q->gt; > > bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); > > u32 flags; > > > > @@ -172,7 +172,7 @@ static int emit_render_cache_flush(struct xe_sched_job *job, u32 *dw, int i) > > > > if (lacks_render) > > flags &= ~PIPE_CONTROL_3D_ARCH_FLAGS; > > - else if (job->engine->class == XE_ENGINE_CLASS_COMPUTE) > > + else if (job->q->class == XE_ENGINE_CLASS_COMPUTE) > > flags &= ~PIPE_CONTROL_3D_ENGINE_FLAGS; > > > > dw[i++] = GFX_OP_PIPE_CONTROL(6) | PIPE_CONTROL0_HDC_PIPELINE_FLUSH; > > @@ -202,7 +202,7 @@ static int emit_pipe_imm_ggtt(u32 addr, u32 value, bool stall_only, u32 *dw, > > > > static u32 get_ppgtt_flag(struct xe_sched_job *job) > > { > > - return !(job->engine->flags & ENGINE_FLAG_WA) ? BIT(8) : 0; > > + return !(job->q->flags & EXEC_QUEUE_FLAG_WA) ? BIT(8) : 0; > > } > > > > static void __emit_job_gen12_copy(struct xe_sched_job *job, struct xe_lrc *lrc, > > @@ -210,7 +210,7 @@ static void __emit_job_gen12_copy(struct xe_sched_job *job, struct xe_lrc *lrc, > > { > > u32 dw[MAX_JOB_SIZE_DW], i = 0; > > u32 ppgtt_flag = get_ppgtt_flag(job); > > - struct xe_vm *vm = job->engine->vm; > > + struct xe_vm *vm = job->q->vm; > > > > if (vm->batch_invalidate_tlb) { > > dw[i++] = preparser_disable(true); > > @@ -255,10 +255,10 @@ static void __emit_job_gen12_video(struct xe_sched_job *job, struct xe_lrc *lrc, > > { > > u32 dw[MAX_JOB_SIZE_DW], i = 0; > > u32 ppgtt_flag = get_ppgtt_flag(job); > > - struct xe_gt *gt = job->engine->gt; > > + struct xe_gt *gt = job->q->gt; > > struct xe_device *xe = gt_to_xe(gt); > > - bool decode = job->engine->class == XE_ENGINE_CLASS_VIDEO_DECODE; > > - struct xe_vm *vm = job->engine->vm; > > + bool decode = job->q->class == XE_ENGINE_CLASS_VIDEO_DECODE; > > + struct xe_vm *vm = job->q->vm; > > > > dw[i++] = preparser_disable(true); > > > > @@ -302,16 +302,16 @@ static void __emit_job_gen12_render_compute(struct xe_sched_job *job, > > { > > u32 dw[MAX_JOB_SIZE_DW], i = 0; > > u32 ppgtt_flag = get_ppgtt_flag(job); > > - struct xe_gt *gt = job->engine->gt; > > + struct xe_gt *gt = job->q->gt; > > struct xe_device *xe = gt_to_xe(gt); > > bool lacks_render = !(gt->info.engine_mask & XE_HW_ENGINE_RCS_MASK); > > - struct xe_vm *vm = job->engine->vm; > > + struct xe_vm *vm = job->q->vm; > > u32 mask_flags = 0; > > > > dw[i++] = preparser_disable(true); > > if (lacks_render) > > mask_flags = PIPE_CONTROL_3D_ARCH_FLAGS; > > - else if (job->engine->class == XE_ENGINE_CLASS_COMPUTE) > > + else if (job->q->class == XE_ENGINE_CLASS_COMPUTE) > > mask_flags = PIPE_CONTROL_3D_ENGINE_FLAGS; > > > > /* See __xe_pt_bind_vma() for a discussion on TLB invalidations. */ > > @@ -378,14 +378,14 @@ static void emit_job_gen12_copy(struct xe_sched_job *job) > > { > > int i; > > > > - if (xe_sched_job_is_migration(job->engine)) { > > - emit_migration_job_gen12(job, job->engine->lrc, > > + if (xe_sched_job_is_migration(job->q)) { > > + emit_migration_job_gen12(job, job->q->lrc, > > xe_sched_job_seqno(job)); > > return; > > } > > > > - for (i = 0; i < job->engine->width; ++i) > > - __emit_job_gen12_copy(job, job->engine->lrc + i, > > + for (i = 0; i < job->q->width; ++i) > > + __emit_job_gen12_copy(job, job->q->lrc + i, > > job->batch_addr[i], > > xe_sched_job_seqno(job)); > > } > > @@ -395,8 +395,8 @@ static void emit_job_gen12_video(struct xe_sched_job *job) > > int i; > > > > /* FIXME: Not doing parallel handshake for now */ > > - for (i = 0; i < job->engine->width; ++i) > > - __emit_job_gen12_video(job, job->engine->lrc + i, > > + for (i = 0; i < job->q->width; ++i) > > + __emit_job_gen12_video(job, job->q->lrc + i, > > job->batch_addr[i], > > xe_sched_job_seqno(job)); > > } > > @@ -405,8 +405,8 @@ static void emit_job_gen12_render_compute(struct xe_sched_job *job) > > { > > int i; > > > > - for (i = 0; i < job->engine->width; ++i) > > - __emit_job_gen12_render_compute(job, job->engine->lrc + i, > > + for (i = 0; i < job->q->width; ++i) > > + __emit_job_gen12_render_compute(job, job->q->lrc + i, > > job->batch_addr[i], > > xe_sched_job_seqno(job)); > > } > > diff --git a/drivers/gpu/drm/xe/xe_sched_job.c b/drivers/gpu/drm/xe/xe_sched_job.c > > index b5bf14b828f9..753aab0cc6f4 100644 > > --- a/drivers/gpu/drm/xe/xe_sched_job.c > > +++ b/drivers/gpu/drm/xe/xe_sched_job.c > > @@ -9,7 +9,7 @@ > > #include <linux/slab.h> > > > > #include "xe_device.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_gt.h" > > #include "xe_hw_engine_types.h" > > #include "xe_hw_fence.h" > > @@ -57,58 +57,58 @@ static struct xe_sched_job *job_alloc(bool parallel) > > xe_sched_job_slab, GFP_KERNEL); > > } > > > > -bool xe_sched_job_is_migration(struct xe_engine *e) > > +bool xe_sched_job_is_migration(struct xe_exec_queue *q) > > { > > - return e->vm && (e->vm->flags & XE_VM_FLAG_MIGRATION) && > > - !(e->flags & ENGINE_FLAG_WA); > > + return q->vm && (q->vm->flags & XE_VM_FLAG_MIGRATION) && > > + !(q->flags & EXEC_QUEUE_FLAG_WA); > > } > > > > static void job_free(struct xe_sched_job *job) > > { > > - struct xe_engine *e = job->engine; > > - bool is_migration = xe_sched_job_is_migration(e); > > + struct xe_exec_queue *q = job->q; > > + bool is_migration = xe_sched_job_is_migration(q); > > > > - kmem_cache_free(xe_engine_is_parallel(job->engine) || is_migration ? > > + kmem_cache_free(xe_exec_queue_is_parallel(job->q) || is_migration ? > > xe_sched_job_parallel_slab : xe_sched_job_slab, job); > > } > > > > static struct xe_device *job_to_xe(struct xe_sched_job *job) > > { > > - return gt_to_xe(job->engine->gt); > > + return gt_to_xe(job->q->gt); > > } > > > > -struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > > +struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q, > > u64 *batch_addr) > > { > > struct xe_sched_job *job; > > struct dma_fence **fences; > > - bool is_migration = xe_sched_job_is_migration(e); > > + bool is_migration = xe_sched_job_is_migration(q); > > int err; > > int i, j; > > u32 width; > > > > /* Migration and kernel engines have their own locking */ > > - if (!(e->flags & (ENGINE_FLAG_KERNEL | ENGINE_FLAG_VM | > > - ENGINE_FLAG_WA))) { > > - lockdep_assert_held(&e->vm->lock); > > - if (!xe_vm_no_dma_fences(e->vm)) > > - xe_vm_assert_held(e->vm); > > + if (!(q->flags & (EXEC_QUEUE_FLAG_KERNEL | EXEC_QUEUE_FLAG_VM | > > + EXEC_QUEUE_FLAG_WA))) { > > + lockdep_assert_held(&q->vm->lock); > > + if (!xe_vm_no_dma_fences(q->vm)) > > + xe_vm_assert_held(q->vm); > > } > > > > - job = job_alloc(xe_engine_is_parallel(e) || is_migration); > > + job = job_alloc(xe_exec_queue_is_parallel(q) || is_migration); > > if (!job) > > return ERR_PTR(-ENOMEM); > > > > - job->engine = e; > > + job->q = q; > > kref_init(&job->refcount); > > - xe_engine_get(job->engine); > > + xe_exec_queue_get(job->q); > > > > - err = drm_sched_job_init(&job->drm, e->entity, NULL); > > + err = drm_sched_job_init(&job->drm, q->entity, NULL); > > if (err) > > goto err_free; > > > > - if (!xe_engine_is_parallel(e)) { > > - job->fence = xe_lrc_create_seqno_fence(e->lrc); > > + if (!xe_exec_queue_is_parallel(q)) { > > + job->fence = xe_lrc_create_seqno_fence(q->lrc); > > if (IS_ERR(job->fence)) { > > err = PTR_ERR(job->fence); > > goto err_sched_job; > > @@ -116,38 +116,38 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > > } else { > > struct dma_fence_array *cf; > > > > - fences = kmalloc_array(e->width, sizeof(*fences), GFP_KERNEL); > > + fences = kmalloc_array(q->width, sizeof(*fences), GFP_KERNEL); > > if (!fences) { > > err = -ENOMEM; > > goto err_sched_job; > > } > > > > - for (j = 0; j < e->width; ++j) { > > - fences[j] = xe_lrc_create_seqno_fence(e->lrc + j); > > + for (j = 0; j < q->width; ++j) { > > + fences[j] = xe_lrc_create_seqno_fence(q->lrc + j); > > if (IS_ERR(fences[j])) { > > err = PTR_ERR(fences[j]); > > goto err_fences; > > } > > } > > > > - cf = dma_fence_array_create(e->width, fences, > > - e->parallel.composite_fence_ctx, > > - e->parallel.composite_fence_seqno++, > > + cf = dma_fence_array_create(q->width, fences, > > + q->parallel.composite_fence_ctx, > > + q->parallel.composite_fence_seqno++, > > false); > > if (!cf) { > > - --e->parallel.composite_fence_seqno; > > + --q->parallel.composite_fence_seqno; > > err = -ENOMEM; > > goto err_fences; > > } > > > > /* Sanity check */ > > - for (j = 0; j < e->width; ++j) > > + for (j = 0; j < q->width; ++j) > > XE_WARN_ON(cf->base.seqno != fences[j]->seqno); > > > > job->fence = &cf->base; > > } > > > > - width = e->width; > > + width = q->width; > > if (is_migration) > > width = 2; > > > > @@ -155,7 +155,7 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > > job->batch_addr[i] = batch_addr[i]; > > > > /* All other jobs require a VM to be open which has a ref */ > > - if (unlikely(e->flags & ENGINE_FLAG_KERNEL)) > > + if (unlikely(q->flags & EXEC_QUEUE_FLAG_KERNEL)) > > xe_device_mem_access_get(job_to_xe(job)); > > xe_device_assert_mem_access(job_to_xe(job)); > > > > @@ -164,14 +164,14 @@ struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > > > > err_fences: > > for (j = j - 1; j >= 0; --j) { > > - --e->lrc[j].fence_ctx.next_seqno; > > + --q->lrc[j].fence_ctx.next_seqno; > > dma_fence_put(fences[j]); > > } > > kfree(fences); > > err_sched_job: > > drm_sched_job_cleanup(&job->drm); > > err_free: > > - xe_engine_put(e); > > + xe_exec_queue_put(q); > > job_free(job); > > return ERR_PTR(err); > > } > > @@ -188,9 +188,9 @@ void xe_sched_job_destroy(struct kref *ref) > > struct xe_sched_job *job = > > container_of(ref, struct xe_sched_job, refcount); > > > > - if (unlikely(job->engine->flags & ENGINE_FLAG_KERNEL)) > > + if (unlikely(job->q->flags & EXEC_QUEUE_FLAG_KERNEL)) > > xe_device_mem_access_put(job_to_xe(job)); > > - xe_engine_put(job->engine); > > + xe_exec_queue_put(job->q); > > dma_fence_put(job->fence); > > drm_sched_job_cleanup(&job->drm); > > job_free(job); > > @@ -222,12 +222,12 @@ void xe_sched_job_set_error(struct xe_sched_job *job, int error) > > trace_xe_sched_job_set_error(job); > > > > dma_fence_enable_sw_signaling(job->fence); > > - xe_hw_fence_irq_run(job->engine->fence_irq); > > + xe_hw_fence_irq_run(job->q->fence_irq); > > } > > > > bool xe_sched_job_started(struct xe_sched_job *job) > > { > > - struct xe_lrc *lrc = job->engine->lrc; > > + struct xe_lrc *lrc = job->q->lrc; > > > > return !__dma_fence_is_later(xe_sched_job_seqno(job), > > xe_lrc_start_seqno(lrc), > > @@ -236,7 +236,7 @@ bool xe_sched_job_started(struct xe_sched_job *job) > > > > bool xe_sched_job_completed(struct xe_sched_job *job) > > { > > - struct xe_lrc *lrc = job->engine->lrc; > > + struct xe_lrc *lrc = job->q->lrc; > > > > /* > > * Can safely check just LRC[0] seqno as that is last seqno written when > > diff --git a/drivers/gpu/drm/xe/xe_sched_job.h b/drivers/gpu/drm/xe/xe_sched_job.h > > index 5315ad8656c2..6ca1d426c036 100644 > > --- a/drivers/gpu/drm/xe/xe_sched_job.h > > +++ b/drivers/gpu/drm/xe/xe_sched_job.h > > @@ -14,7 +14,7 @@ > > int xe_sched_job_module_init(void); > > void xe_sched_job_module_exit(void); > > > > -struct xe_sched_job *xe_sched_job_create(struct xe_engine *e, > > +struct xe_sched_job *xe_sched_job_create(struct xe_exec_queue *q, > > u64 *batch_addr); > > void xe_sched_job_destroy(struct kref *ref); > > > > @@ -71,6 +71,6 @@ xe_sched_job_add_migrate_flush(struct xe_sched_job *job, u32 flags) > > job->migrate_flush_flags = flags; > > } > > > > -bool xe_sched_job_is_migration(struct xe_engine *e); > > +bool xe_sched_job_is_migration(struct xe_exec_queue *q); > > > > #endif > > diff --git a/drivers/gpu/drm/xe/xe_sched_job_types.h b/drivers/gpu/drm/xe/xe_sched_job_types.h > > index 5534bfacaa16..08db0db7814b 100644 > > --- a/drivers/gpu/drm/xe/xe_sched_job_types.h > > +++ b/drivers/gpu/drm/xe/xe_sched_job_types.h > > @@ -10,7 +10,7 @@ > > > > #include <drm/gpu_scheduler.h> > > > > -struct xe_engine; > > +struct xe_exec_queue; > > > > /** > > * struct xe_sched_job - XE schedule job (batch buffer tracking) > > @@ -18,8 +18,8 @@ struct xe_engine; > > struct xe_sched_job { > > /** @drm: base DRM scheduler job */ > > struct drm_sched_job drm; > > - /** @engine: XE submission engine */ > > - struct xe_engine *engine; > > + /** @exec_queue: Exec queue */ > > + struct xe_exec_queue *q; > > /** @refcount: ref count of this job */ > > struct kref refcount; > > /** > > diff --git a/drivers/gpu/drm/xe/xe_trace.h b/drivers/gpu/drm/xe/xe_trace.h > > index 463152528281..e32f1cad51d9 100644 > > --- a/drivers/gpu/drm/xe/xe_trace.h > > +++ b/drivers/gpu/drm/xe/xe_trace.h > > @@ -13,10 +13,10 @@ > > #include <linux/types.h> > > > > #include "xe_bo_types.h" > > -#include "xe_engine_types.h" > > +#include "xe_exec_queue_types.h" > > #include "xe_gt_tlb_invalidation_types.h" > > #include "xe_gt_types.h" > > -#include "xe_guc_engine_types.h" > > +#include "xe_guc_exec_queue_types.h" > > #include "xe_sched_job.h" > > #include "xe_vm.h" > > > > @@ -104,9 +104,9 @@ DEFINE_EVENT(xe_bo, xe_bo_move, > > TP_ARGS(bo) > > ); > > > > -DECLARE_EVENT_CLASS(xe_engine, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e), > > +DECLARE_EVENT_CLASS(xe_exec_queue, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q), > > > > TP_STRUCT__entry( > > __field(enum xe_engine_class, class) > > @@ -119,13 +119,13 @@ DECLARE_EVENT_CLASS(xe_engine, > > ), > > > > TP_fast_assign( > > - __entry->class = e->class; > > - __entry->logical_mask = e->logical_mask; > > - __entry->gt_id = e->gt->info.id; > > - __entry->width = e->width; > > - __entry->guc_id = e->guc->id; > > - __entry->guc_state = atomic_read(&e->guc->state); > > - __entry->flags = e->flags; > > + __entry->class = q->class; > > + __entry->logical_mask = q->logical_mask; > > + __entry->gt_id = q->gt->info.id; > > + __entry->width = q->width; > > + __entry->guc_id = q->guc->id; > > + __entry->guc_state = atomic_read(&q->guc->state); > > + __entry->flags = q->flags; > > ), > > > > TP_printk("%d:0x%x, gt=%d, width=%d, guc_id=%d, guc_state=0x%x, flags=0x%x", > > @@ -134,94 +134,94 @@ DECLARE_EVENT_CLASS(xe_engine, > > __entry->guc_state, __entry->flags) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_create, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_create, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_supress_resume, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_supress_resume, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_submit, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_submit, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_scheduling_enable, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_enable, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_scheduling_disable, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_disable, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_scheduling_done, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_scheduling_done, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_register, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_register, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_deregister, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_deregister, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_deregister_done, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_deregister_done, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_close, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_close, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_kill, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_kill, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_cleanup_entity, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_cleanup_entity, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_destroy, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_destroy, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_reset, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_reset, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_memory_cat_error, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_memory_cat_error, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_stop, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_stop, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_resubmit, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_resubmit, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > -DEFINE_EVENT(xe_engine, xe_engine_lr_cleanup, > > - TP_PROTO(struct xe_engine *e), > > - TP_ARGS(e) > > +DEFINE_EVENT(xe_exec_queue, xe_exec_queue_lr_cleanup, > > + TP_PROTO(struct xe_exec_queue *q), > > + TP_ARGS(q) > > ); > > > > DECLARE_EVENT_CLASS(xe_sched_job, > > @@ -240,10 +240,10 @@ DECLARE_EVENT_CLASS(xe_sched_job, > > > > TP_fast_assign( > > __entry->seqno = xe_sched_job_seqno(job); > > - __entry->guc_id = job->engine->guc->id; > > + __entry->guc_id = job->q->guc->id; > > __entry->guc_state = > > - atomic_read(&job->engine->guc->state); > > - __entry->flags = job->engine->flags; > > + atomic_read(&job->q->guc->state); > > + __entry->flags = job->q->flags; > > __entry->error = job->fence->error; > > __entry->fence = (unsigned long)job->fence; > > __entry->batch_addr = (u64)job->batch_addr[0]; > > @@ -302,7 +302,7 @@ DECLARE_EVENT_CLASS(drm_sched_msg, > > TP_fast_assign( > > __entry->opcode = msg->opcode; > > __entry->guc_id = > > - ((struct xe_engine *)msg->private_data)->guc->id; > > + ((struct xe_exec_queue *)msg->private_data)->guc->id; > > ), > > > > TP_printk("guc_id=%d, opcode=%u", __entry->guc_id, > > diff --git a/drivers/gpu/drm/xe/xe_vm.c b/drivers/gpu/drm/xe/xe_vm.c > > index 44df7b9d801e..cb28dbc2bdbb 100644 > > --- a/drivers/gpu/drm/xe/xe_vm.c > > +++ b/drivers/gpu/drm/xe/xe_vm.c > > @@ -18,7 +18,7 @@ > > > > #include "xe_bo.h" > > #include "xe_device.h" > > -#include "xe_engine.h" > > +#include "xe_exec_queue.h" > > #include "xe_gt.h" > > #include "xe_gt_pagefault.h" > > #include "xe_gt_tlb_invalidation.h" > > @@ -165,15 +165,15 @@ int xe_vma_userptr_pin_pages(struct xe_vma *vma) > > > > static bool preempt_fences_waiting(struct xe_vm *vm) > > { > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > > > lockdep_assert_held(&vm->lock); > > xe_vm_assert_held(vm); > > > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > > - if (!e->compute.pfence || (e->compute.pfence && > > - test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, > > - &e->compute.pfence->flags))) { > > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > > + if (!q->compute.pfence || > > + (q->compute.pfence && test_bit(DMA_FENCE_FLAG_ENABLE_SIGNAL_BIT, > > + &q->compute.pfence->flags))) { > > return true; > > } > > } > > @@ -212,18 +212,18 @@ static int alloc_preempt_fences(struct xe_vm *vm, struct list_head *list, > > > > static int wait_for_existing_preempt_fences(struct xe_vm *vm) > > { > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > > > xe_vm_assert_held(vm); > > > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > > - if (e->compute.pfence) { > > - long timeout = dma_fence_wait(e->compute.pfence, false); > > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > > + if (q->compute.pfence) { > > + long timeout = dma_fence_wait(q->compute.pfence, false); > > > > if (timeout < 0) > > return -ETIME; > > - dma_fence_put(e->compute.pfence); > > - e->compute.pfence = NULL; > > + dma_fence_put(q->compute.pfence); > > + q->compute.pfence = NULL; > > } > > } > > > > @@ -232,11 +232,11 @@ static int wait_for_existing_preempt_fences(struct xe_vm *vm) > > > > static bool xe_vm_is_idle(struct xe_vm *vm) > > { > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > > > xe_vm_assert_held(vm); > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > > - if (!xe_engine_is_idle(e)) > > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > > + if (!xe_exec_queue_is_idle(q)) > > return false; > > } > > > > @@ -246,25 +246,25 @@ static bool xe_vm_is_idle(struct xe_vm *vm) > > static void arm_preempt_fences(struct xe_vm *vm, struct list_head *list) > > { > > struct list_head *link; > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > > struct dma_fence *fence; > > > > link = list->next; > > XE_WARN_ON(link == list); > > > > fence = xe_preempt_fence_arm(to_preempt_fence_from_link(link), > > - e, e->compute.context, > > - ++e->compute.seqno); > > - dma_fence_put(e->compute.pfence); > > - e->compute.pfence = fence; > > + q, q->compute.context, > > + ++q->compute.seqno); > > + dma_fence_put(q->compute.pfence); > > + q->compute.pfence = fence; > > } > > } > > > > static int add_preempt_fences(struct xe_vm *vm, struct xe_bo *bo) > > { > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > struct ww_acquire_ctx ww; > > int err; > > > > @@ -272,10 +272,10 @@ static int add_preempt_fences(struct xe_vm *vm, struct xe_bo *bo) > > if (err) > > return err; > > > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) > > - if (e->compute.pfence) { > > + list_for_each_entry(q, &vm->preempt.engines, compute.link) > > + if (q->compute.pfence) { > > dma_resv_add_fence(bo->ttm.base.resv, > > - e->compute.pfence, > > + q->compute.pfence, > > DMA_RESV_USAGE_BOOKKEEP); > > } > > > > @@ -304,22 +304,22 @@ void xe_vm_fence_all_extobjs(struct xe_vm *vm, struct dma_fence *fence, > > > > static void resume_and_reinstall_preempt_fences(struct xe_vm *vm) > > { > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > > > lockdep_assert_held(&vm->lock); > > xe_vm_assert_held(vm); > > > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) { > > - e->ops->resume(e); > > + list_for_each_entry(q, &vm->preempt.engines, compute.link) { > > + q->ops->resume(q); > > > > - dma_resv_add_fence(&vm->resv, e->compute.pfence, > > + dma_resv_add_fence(&vm->resv, q->compute.pfence, > > DMA_RESV_USAGE_BOOKKEEP); > > - xe_vm_fence_all_extobjs(vm, e->compute.pfence, > > + xe_vm_fence_all_extobjs(vm, q->compute.pfence, > > DMA_RESV_USAGE_BOOKKEEP); > > } > > } > > > > -int xe_vm_add_compute_engine(struct xe_vm *vm, struct xe_engine *e) > > +int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q) > > { > > struct ttm_validate_buffer tv_onstack[XE_ONSTACK_TV]; > > struct ttm_validate_buffer *tv; > > @@ -337,16 +337,16 @@ int xe_vm_add_compute_engine(struct xe_vm *vm, struct xe_engine *e) > > if (err) > > goto out_unlock_outer; > > > > - pfence = xe_preempt_fence_create(e, e->compute.context, > > - ++e->compute.seqno); > > + pfence = xe_preempt_fence_create(q, q->compute.context, > > + ++q->compute.seqno); > > if (!pfence) { > > err = -ENOMEM; > > goto out_unlock; > > } > > > > - list_add(&e->compute.link, &vm->preempt.engines); > > + list_add(&q->compute.link, &vm->preempt.engines); > > ++vm->preempt.num_engines; > > - e->compute.pfence = pfence; > > + q->compute.pfence = pfence; > > > > down_read(&vm->userptr.notifier_lock); > > > > @@ -518,7 +518,7 @@ void xe_vm_unlock_dma_resv(struct xe_vm *vm, > > static void xe_vm_kill(struct xe_vm *vm) > > { > > struct ww_acquire_ctx ww; > > - struct xe_engine *e; > > + struct xe_exec_queue *q; > > > > lockdep_assert_held(&vm->lock); > > > > @@ -526,8 +526,8 @@ static void xe_vm_kill(struct xe_vm *vm) > > vm->flags |= XE_VM_FLAG_BANNED; > > trace_xe_vm_kill(vm); > > > > - list_for_each_entry(e, &vm->preempt.engines, compute.link) > > - e->ops->kill(e); > > + list_for_each_entry(q, &vm->preempt.engines, compute.link) > > + q->ops->kill(q); > > xe_vm_unlock(vm, &ww); > > > > /* TODO: Inform user the VM is banned */ > > @@ -833,7 +833,7 @@ int xe_vm_userptr_check_repin(struct xe_vm *vm) > > } > > > > static struct dma_fence * > > -xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, > > +xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q, > > struct xe_sync_entry *syncs, u32 num_syncs, > > bool first_op, bool last_op); > > > > @@ -1297,21 +1297,21 @@ struct xe_vm *xe_vm_create(struct xe_device *xe, u32 flags) > > for_each_tile(tile, xe, id) { > > struct xe_gt *gt = tile->primary_gt; > > struct xe_vm *migrate_vm; > > - struct xe_engine *eng; > > + struct xe_exec_queue *q; > > > > if (!vm->pt_root[id]) > > continue; > > > > migrate_vm = xe_migrate_get_vm(tile->migrate); > > - eng = xe_engine_create_class(xe, gt, migrate_vm, > > - XE_ENGINE_CLASS_COPY, > > - ENGINE_FLAG_VM); > > + q = xe_exec_queue_create_class(xe, gt, migrate_vm, > > + XE_ENGINE_CLASS_COPY, > > + EXEC_QUEUE_FLAG_VM); > > xe_vm_put(migrate_vm); > > - if (IS_ERR(eng)) { > > + if (IS_ERR(q)) { > > xe_vm_close_and_put(vm); > > - return ERR_CAST(eng); > > + return ERR_CAST(q); > > } > > - vm->eng[id] = eng; > > + vm->q[id] = q; > > number_tiles++; > > } > > } > > @@ -1422,10 +1422,10 @@ void xe_vm_close_and_put(struct xe_vm *vm) > > flush_work(&vm->preempt.rebind_work); > > > > for_each_tile(tile, xe, id) { > > - if (vm->eng[id]) { > > - xe_engine_kill(vm->eng[id]); > > - xe_engine_put(vm->eng[id]); > > - vm->eng[id] = NULL; > > + if (vm->q[id]) { > > + xe_exec_queue_kill(vm->q[id]); > > + xe_exec_queue_put(vm->q[id]); > > + vm->q[id] = NULL; > > } > > } > > > > @@ -1576,7 +1576,7 @@ u64 xe_vm_pdp4_descriptor(struct xe_vm *vm, struct xe_tile *tile) > > } > > > > static struct dma_fence * > > -xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, > > +xe_vm_unbind_vma(struct xe_vma *vma, struct xe_exec_queue *q, > > struct xe_sync_entry *syncs, u32 num_syncs, > > bool first_op, bool last_op) > > { > > @@ -1603,7 +1603,7 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, > > if (!(vma->tile_present & BIT(id))) > > goto next; > > > > - fence = __xe_pt_unbind_vma(tile, vma, e, first_op ? syncs : NULL, > > + fence = __xe_pt_unbind_vma(tile, vma, q, first_op ? syncs : NULL, > > first_op ? num_syncs : 0); > > if (IS_ERR(fence)) { > > err = PTR_ERR(fence); > > @@ -1614,8 +1614,8 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, > > fences[cur_fence++] = fence; > > > > next: > > - if (e && vm->pt_root[id] && !list_empty(&e->multi_gt_list)) > > - e = list_next_entry(e, multi_gt_list); > > + if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list)) > > + q = list_next_entry(q, multi_gt_list); > > } > > > > if (fences) { > > @@ -1651,7 +1651,7 @@ xe_vm_unbind_vma(struct xe_vma *vma, struct xe_engine *e, > > } > > > > static struct dma_fence * > > -xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, > > +xe_vm_bind_vma(struct xe_vma *vma, struct xe_exec_queue *q, > > struct xe_sync_entry *syncs, u32 num_syncs, > > bool first_op, bool last_op) > > { > > @@ -1678,7 +1678,7 @@ xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, > > if (!(vma->tile_mask & BIT(id))) > > goto next; > > > > - fence = __xe_pt_bind_vma(tile, vma, e ? e : vm->eng[id], > > + fence = __xe_pt_bind_vma(tile, vma, q ? q : vm->q[id], > > first_op ? syncs : NULL, > > first_op ? num_syncs : 0, > > vma->tile_present & BIT(id)); > > @@ -1691,8 +1691,8 @@ xe_vm_bind_vma(struct xe_vma *vma, struct xe_engine *e, > > fences[cur_fence++] = fence; > > > > next: > > - if (e && vm->pt_root[id] && !list_empty(&e->multi_gt_list)) > > - e = list_next_entry(e, multi_gt_list); > > + if (q && vm->pt_root[id] && !list_empty(&q->multi_gt_list)) > > + q = list_next_entry(q, multi_gt_list); > > } > > > > if (fences) { > > @@ -1808,7 +1808,7 @@ int xe_vm_async_fence_wait_start(struct dma_fence *fence) > > } > > > > static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, > > - struct xe_engine *e, struct xe_sync_entry *syncs, > > + struct xe_exec_queue *q, struct xe_sync_entry *syncs, > > u32 num_syncs, struct async_op_fence *afence, > > bool immediate, bool first_op, bool last_op) > > { > > @@ -1817,7 +1817,7 @@ static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, > > xe_vm_assert_held(vm); > > > > if (immediate) { > > - fence = xe_vm_bind_vma(vma, e, syncs, num_syncs, first_op, > > + fence = xe_vm_bind_vma(vma, q, syncs, num_syncs, first_op, > > last_op); > > if (IS_ERR(fence)) > > return PTR_ERR(fence); > > @@ -1839,7 +1839,7 @@ static int __xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, > > return 0; > > } > > > > -static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_engine *e, > > +static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_exec_queue *q, > > struct xe_bo *bo, struct xe_sync_entry *syncs, > > u32 num_syncs, struct async_op_fence *afence, > > bool immediate, bool first_op, bool last_op) > > @@ -1855,12 +1855,12 @@ static int xe_vm_bind(struct xe_vm *vm, struct xe_vma *vma, struct xe_engine *e, > > return err; > > } > > > > - return __xe_vm_bind(vm, vma, e, syncs, num_syncs, afence, immediate, > > + return __xe_vm_bind(vm, vma, q, syncs, num_syncs, afence, immediate, > > first_op, last_op); > > } > > > > static int xe_vm_unbind(struct xe_vm *vm, struct xe_vma *vma, > > - struct xe_engine *e, struct xe_sync_entry *syncs, > > + struct xe_exec_queue *q, struct xe_sync_entry *syncs, > > u32 num_syncs, struct async_op_fence *afence, > > bool first_op, bool last_op) > > { > > @@ -1869,7 +1869,7 @@ static int xe_vm_unbind(struct xe_vm *vm, struct xe_vma *vma, > > xe_vm_assert_held(vm); > > xe_bo_assert_held(xe_vma_bo(vma)); > > > > - fence = xe_vm_unbind_vma(vma, e, syncs, num_syncs, first_op, last_op); > > + fence = xe_vm_unbind_vma(vma, q, syncs, num_syncs, first_op, last_op); > > if (IS_ERR(fence)) > > return PTR_ERR(fence); > > if (afence) > > @@ -2096,7 +2096,7 @@ static const u32 region_to_mem_type[] = { > > }; > > > > static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma, > > - struct xe_engine *e, u32 region, > > + struct xe_exec_queue *q, u32 region, > > struct xe_sync_entry *syncs, u32 num_syncs, > > struct async_op_fence *afence, bool first_op, > > bool last_op) > > @@ -2112,7 +2112,7 @@ static int xe_vm_prefetch(struct xe_vm *vm, struct xe_vma *vma, > > } > > > > if (vma->tile_mask != (vma->tile_present & ~vma->usm.tile_invalidated)) { > > - return xe_vm_bind(vm, vma, e, xe_vma_bo(vma), syncs, num_syncs, > > + return xe_vm_bind(vm, vma, q, xe_vma_bo(vma), syncs, num_syncs, > > afence, true, first_op, last_op); > > } else { > > int i; > > @@ -2410,7 +2410,7 @@ static u64 xe_vma_max_pte_size(struct xe_vma *vma) > > * Parse operations list and create any resources needed for the operations > > * prior to fully committing to the operations. This setup can fail. > > */ > > -static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_engine *e, > > +static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_exec_queue *q, > > struct drm_gpuva_ops **ops, int num_ops_list, > > struct xe_sync_entry *syncs, u32 num_syncs, > > struct list_head *ops_list, bool async) > > @@ -2430,9 +2430,9 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_engine *e, > > if (!fence) > > return -ENOMEM; > > > > - seqno = e ? ++e->bind.fence_seqno : ++vm->async_ops.fence.seqno; > > + seqno = q ? ++q->bind.fence_seqno : ++vm->async_ops.fence.seqno; > > dma_fence_init(&fence->fence, &async_op_fence_ops, > > - &vm->async_ops.lock, e ? e->bind.fence_ctx : > > + &vm->async_ops.lock, q ? q->bind.fence_ctx : > > vm->async_ops.fence.context, seqno); > > > > if (!xe_vm_no_dma_fences(vm)) { > > @@ -2463,7 +2463,7 @@ static int vm_bind_ioctl_ops_parse(struct xe_vm *vm, struct xe_engine *e, > > op->syncs = syncs; > > } > > > > - op->engine = e; > > + op->q = q; > > > > switch (op->base.op) { > > case DRM_GPUVA_OP_MAP: > > @@ -2673,7 +2673,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > > > > switch (op->base.op) { > > case DRM_GPUVA_OP_MAP: > > - err = xe_vm_bind(vm, vma, op->engine, xe_vma_bo(vma), > > + err = xe_vm_bind(vm, vma, op->q, xe_vma_bo(vma), > > op->syncs, op->num_syncs, op->fence, > > op->map.immediate || !xe_vm_in_fault_mode(vm), > > op->flags & XE_VMA_OP_FIRST, > > @@ -2689,7 +2689,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > > vm->async_ops.munmap_rebind_inflight = true; > > vma->gpuva.flags |= XE_VMA_FIRST_REBIND; > > } > > - err = xe_vm_unbind(vm, vma, op->engine, op->syncs, > > + err = xe_vm_unbind(vm, vma, op->q, op->syncs, > > op->num_syncs, > > !prev && !next ? op->fence : NULL, > > op->flags & XE_VMA_OP_FIRST, > > @@ -2702,7 +2702,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > > > > if (prev) { > > op->remap.prev->gpuva.flags |= XE_VMA_LAST_REBIND; > > - err = xe_vm_bind(vm, op->remap.prev, op->engine, > > + err = xe_vm_bind(vm, op->remap.prev, op->q, > > xe_vma_bo(op->remap.prev), op->syncs, > > op->num_syncs, > > !next ? op->fence : NULL, true, false, > > @@ -2715,7 +2715,7 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > > > > if (next) { > > op->remap.next->gpuva.flags |= XE_VMA_LAST_REBIND; > > - err = xe_vm_bind(vm, op->remap.next, op->engine, > > + err = xe_vm_bind(vm, op->remap.next, op->q, > > xe_vma_bo(op->remap.next), > > op->syncs, op->num_syncs, > > op->fence, true, false, > > @@ -2730,13 +2730,13 @@ static int __xe_vma_op_execute(struct xe_vm *vm, struct xe_vma *vma, > > break; > > } > > case DRM_GPUVA_OP_UNMAP: > > - err = xe_vm_unbind(vm, vma, op->engine, op->syncs, > > + err = xe_vm_unbind(vm, vma, op->q, op->syncs, > > op->num_syncs, op->fence, > > op->flags & XE_VMA_OP_FIRST, > > op->flags & XE_VMA_OP_LAST); > > break; > > case DRM_GPUVA_OP_PREFETCH: > > - err = xe_vm_prefetch(vm, vma, op->engine, op->prefetch.region, > > + err = xe_vm_prefetch(vm, vma, op->q, op->prefetch.region, > > op->syncs, op->num_syncs, op->fence, > > op->flags & XE_VMA_OP_FIRST, > > op->flags & XE_VMA_OP_LAST); > > @@ -2815,8 +2815,8 @@ static void xe_vma_op_cleanup(struct xe_vm *vm, struct xe_vma_op *op) > > while (op->num_syncs--) > > xe_sync_entry_cleanup(&op->syncs[op->num_syncs]); > > kfree(op->syncs); > > - if (op->engine) > > - xe_engine_put(op->engine); > > + if (op->q) > > + xe_exec_queue_put(op->q); > > if (op->fence) > > dma_fence_put(&op->fence->fence); > > } > > @@ -3170,7 +3170,7 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > struct xe_bo **bos = NULL; > > struct drm_gpuva_ops **ops = NULL; > > struct xe_vm *vm; > > - struct xe_engine *e = NULL; > > + struct xe_exec_queue *q = NULL; > > u32 num_syncs; > > struct xe_sync_entry *syncs = NULL; > > struct drm_xe_vm_bind_op *bind_ops; > > @@ -3183,23 +3183,23 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > if (err) > > return err; > > > > - if (args->engine_id) { > > - e = xe_engine_lookup(xef, args->engine_id); > > - if (XE_IOCTL_DBG(xe, !e)) { > > + if (args->exec_queue_id) { > > + q = xe_exec_queue_lookup(xef, args->exec_queue_id); > > + if (XE_IOCTL_DBG(xe, !q)) { > > err = -ENOENT; > > goto free_objs; > > } > > > > - if (XE_IOCTL_DBG(xe, !(e->flags & ENGINE_FLAG_VM))) { > > + if (XE_IOCTL_DBG(xe, !(q->flags & EXEC_QUEUE_FLAG_VM))) { > > err = -EINVAL; > > - goto put_engine; > > + goto put_exec_queue; > > } > > } > > > > vm = xe_vm_lookup(xef, args->vm_id); > > if (XE_IOCTL_DBG(xe, !vm)) { > > err = -EINVAL; > > - goto put_engine; > > + goto put_exec_queue; > > } > > > > err = down_write_killable(&vm->lock); > > @@ -3353,7 +3353,7 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > } > > } > > > > - err = vm_bind_ioctl_ops_parse(vm, e, ops, args->num_binds, > > + err = vm_bind_ioctl_ops_parse(vm, q, ops, args->num_binds, > > syncs, num_syncs, &ops_list, async); > > if (err) > > goto unwind_ops; > > @@ -3387,9 +3387,9 @@ int xe_vm_bind_ioctl(struct drm_device *dev, void *data, struct drm_file *file) > > up_write(&vm->lock); > > put_vm: > > xe_vm_put(vm); > > -put_engine: > > - if (e) > > - xe_engine_put(e); > > +put_exec_queue: > > + if (q) > > + xe_exec_queue_put(q); > > free_objs: > > kfree(bos); > > kfree(ops); > > diff --git a/drivers/gpu/drm/xe/xe_vm.h b/drivers/gpu/drm/xe/xe_vm.h > > index 4db777d7e375..6de6e3edb24a 100644 > > --- a/drivers/gpu/drm/xe/xe_vm.h > > +++ b/drivers/gpu/drm/xe/xe_vm.h > > @@ -18,7 +18,7 @@ struct drm_file; > > struct ttm_buffer_object; > > struct ttm_validate_buffer; > > > > -struct xe_engine; > > +struct xe_exec_queue; > > struct xe_file; > > struct xe_sync_entry; > > > > @@ -167,7 +167,7 @@ static inline bool xe_vm_no_dma_fences(struct xe_vm *vm) > > return xe_vm_in_compute_mode(vm) || xe_vm_in_fault_mode(vm); > > } > > > > -int xe_vm_add_compute_engine(struct xe_vm *vm, struct xe_engine *e); > > +int xe_vm_add_compute_exec_queue(struct xe_vm *vm, struct xe_exec_queue *q); > > > > int xe_vm_userptr_pin(struct xe_vm *vm); > > > > diff --git a/drivers/gpu/drm/xe/xe_vm_types.h b/drivers/gpu/drm/xe/xe_vm_types.h > > index 261a4b0e8570..3681a5ff588b 100644 > > --- a/drivers/gpu/drm/xe/xe_vm_types.h > > +++ b/drivers/gpu/drm/xe/xe_vm_types.h > > @@ -142,8 +142,8 @@ struct xe_vm { > > > > struct kref refcount; > > > > - /* engine used for (un)binding vma's */ > > - struct xe_engine *eng[XE_MAX_TILES_PER_DEVICE]; > > + /* exec queue used for (un)binding vma's */ > > + struct xe_exec_queue *q[XE_MAX_TILES_PER_DEVICE]; > > > > /** Protects @rebind_list and the page-table structures */ > > struct dma_resv resv; > > @@ -394,7 +394,7 @@ struct xe_vma_op { > > */ > > struct drm_gpuva_ops *ops; > > /** @engine: engine for this operation */ > > - struct xe_engine *engine; > > + struct xe_exec_queue *q; > > /** > > * @syncs: syncs for this operation, only used on first and last > > * operation > > diff --git a/include/uapi/drm/xe_drm.h b/include/uapi/drm/xe_drm.h > > index 3d09e9e9267b..86f16d50e9cc 100644 > > --- a/include/uapi/drm/xe_drm.h > > +++ b/include/uapi/drm/xe_drm.h > > @@ -103,14 +103,14 @@ struct xe_user_extension { > > #define DRM_XE_VM_CREATE 0x03 > > #define DRM_XE_VM_DESTROY 0x04 > > #define DRM_XE_VM_BIND 0x05 > > -#define DRM_XE_ENGINE_CREATE 0x06 > > -#define DRM_XE_ENGINE_DESTROY 0x07 > > +#define DRM_XE_EXEC_QUEUE_CREATE 0x06 > > +#define DRM_XE_EXEC_QUEUE_DESTROY 0x07 > > #define DRM_XE_EXEC 0x08 > > #define DRM_XE_MMIO 0x09 > > -#define DRM_XE_ENGINE_SET_PROPERTY 0x0a > > +#define DRM_XE_EXEC_QUEUE_SET_PROPERTY 0x0a > > #define DRM_XE_WAIT_USER_FENCE 0x0b > > #define DRM_XE_VM_MADVISE 0x0c > > -#define DRM_XE_ENGINE_GET_PROPERTY 0x0d > > +#define DRM_XE_EXEC_QUEUE_GET_PROPERTY 0x0d > > > > /* Must be kept compact -- no holes */ > > #define DRM_IOCTL_XE_DEVICE_QUERY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_DEVICE_QUERY, struct drm_xe_device_query) > > @@ -119,12 +119,12 @@ struct xe_user_extension { > > #define DRM_IOCTL_XE_VM_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_VM_CREATE, struct drm_xe_vm_create) > > #define DRM_IOCTL_XE_VM_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_DESTROY, struct drm_xe_vm_destroy) > > #define DRM_IOCTL_XE_VM_BIND DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_BIND, struct drm_xe_vm_bind) > > -#define DRM_IOCTL_XE_ENGINE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_CREATE, struct drm_xe_engine_create) > > -#define DRM_IOCTL_XE_ENGINE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_ENGINE_GET_PROPERTY, struct drm_xe_engine_get_property) > > -#define DRM_IOCTL_XE_ENGINE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_DESTROY, struct drm_xe_engine_destroy) > > +#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) > > +#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) > > +#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) > > #define DRM_IOCTL_XE_EXEC DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC, struct drm_xe_exec) > > #define DRM_IOCTL_XE_MMIO DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_MMIO, struct drm_xe_mmio) > > -#define DRM_IOCTL_XE_ENGINE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_ENGINE_SET_PROPERTY, struct drm_xe_engine_set_property) > > +#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property) > > #define DRM_IOCTL_XE_WAIT_USER_FENCE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_WAIT_USER_FENCE, struct drm_xe_wait_user_fence) > > #define DRM_IOCTL_XE_VM_MADVISE DRM_IOW(DRM_COMMAND_BASE + DRM_XE_VM_MADVISE, struct drm_xe_vm_madvise) > > > > @@ -649,11 +649,11 @@ struct drm_xe_vm_bind { > > __u32 vm_id; > > > > /** > > - * @engine_id: engine_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND > > - * and engine must have same vm_id. If zero, the default VM bind engine > > + * @exec_queue_id: exec_queue_id, must be of class DRM_XE_ENGINE_CLASS_VM_BIND > > + * and exec queue must have same vm_id. If zero, the default VM bind engine > > * is used. > > */ > > - __u32 engine_id; > > + __u32 exec_queue_id; > > > > /** @num_binds: number of binds in this IOCTL */ > > __u32 num_binds; > > @@ -685,8 +685,8 @@ struct drm_xe_vm_bind { > > __u64 reserved[2]; > > }; > > > > -/** struct drm_xe_ext_engine_set_property - engine set property extension */ > > -struct drm_xe_ext_engine_set_property { > > +/** struct drm_xe_ext_exec_queue_set_property - exec queue set property extension */ > > +struct drm_xe_ext_exec_queue_set_property { > > /** @base: base user extension */ > > struct xe_user_extension base; > > > > @@ -701,32 +701,32 @@ struct drm_xe_ext_engine_set_property { > > }; > > > > /** > > - * struct drm_xe_engine_set_property - engine set property > > + * struct drm_xe_exec_queue_set_property - exec queue set property > > * > > - * Same namespace for extensions as drm_xe_engine_create > > + * Same namespace for extensions as drm_xe_exec_queue_create > > */ > > -struct drm_xe_engine_set_property { > > +struct drm_xe_exec_queue_set_property { > > /** @extensions: Pointer to the first extension struct, if any */ > > __u64 extensions; > > > > - /** @engine_id: Engine ID */ > > - __u32 engine_id; > > + /** @exec_queue_id: Exec queue ID */ > > + __u32 exec_queue_id; > > > > -#define XE_ENGINE_SET_PROPERTY_PRIORITY 0 > > -#define XE_ENGINE_SET_PROPERTY_TIMESLICE 1 > > -#define XE_ENGINE_SET_PROPERTY_PREEMPTION_TIMEOUT 2 > > +#define XE_EXEC_QUEUE_SET_PROPERTY_PRIORITY 0 > > +#define XE_EXEC_QUEUE_SET_PROPERTY_TIMESLICE 1 > > +#define XE_EXEC_QUEUE_SET_PROPERTY_PREEMPTION_TIMEOUT 2 > > /* > > * Long running or ULLS engine mode. DMA fences not allowed in this > > * mode. Must match the value of DRM_XE_VM_CREATE_COMPUTE_MODE, serves > > * as a sanity check the UMD knows what it is doing. Can only be set at > > * engine create time. > > */ > > -#define XE_ENGINE_SET_PROPERTY_COMPUTE_MODE 3 > > -#define XE_ENGINE_SET_PROPERTY_PERSISTENCE 4 > > -#define XE_ENGINE_SET_PROPERTY_JOB_TIMEOUT 5 > > -#define XE_ENGINE_SET_PROPERTY_ACC_TRIGGER 6 > > -#define XE_ENGINE_SET_PROPERTY_ACC_NOTIFY 7 > > -#define XE_ENGINE_SET_PROPERTY_ACC_GRANULARITY 8 > > +#define XE_EXEC_QUEUE_SET_PROPERTY_COMPUTE_MODE 3 > > +#define XE_EXEC_QUEUE_SET_PROPERTY_PERSISTENCE 4 > > +#define XE_EXEC_QUEUE_SET_PROPERTY_JOB_TIMEOUT 5 > > +#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_TRIGGER 6 > > +#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_NOTIFY 7 > > +#define XE_EXEC_QUEUE_SET_PROPERTY_ACC_GRANULARITY 8 > > /** @property: property to set */ > > __u32 property; > > > > @@ -755,25 +755,25 @@ struct drm_xe_engine_class_instance { > > __u16 gt_id; > > }; > > > > -struct drm_xe_engine_create { > > -#define XE_ENGINE_EXTENSION_SET_PROPERTY 0 > > +struct drm_xe_exec_queue_create { > > +#define XE_EXEC_QUEUE_EXTENSION_SET_PROPERTY 0 > > /** @extensions: Pointer to the first extension struct, if any */ > > __u64 extensions; > > > > - /** @width: submission width (number BB per exec) for this engine */ > > + /** @width: submission width (number BB per exec) for this exec queue */ > > __u16 width; > > > > - /** @num_placements: number of valid placements for this engine */ > > + /** @num_placements: number of valid placements for this exec queue */ > > __u16 num_placements; > > > > - /** @vm_id: VM to use for this engine */ > > + /** @vm_id: VM to use for this exec queue */ > > __u32 vm_id; > > > > /** @flags: MBZ */ > > __u32 flags; > > > > - /** @engine_id: Returned engine ID */ > > - __u32 engine_id; > > + /** @exec_queue_id: Returned exec queue ID */ > > + __u32 exec_queue_id; > > > > /** > > * @instances: user pointer to a 2-d array of struct > > @@ -788,14 +788,14 @@ struct drm_xe_engine_create { > > __u64 reserved[2]; > > }; > > > > -struct drm_xe_engine_get_property { > > +struct drm_xe_exec_queue_get_property { > > /** @extensions: Pointer to the first extension struct, if any */ > > __u64 extensions; > > > > - /** @engine_id: Engine ID */ > > - __u32 engine_id; > > + /** @exec_queue_id: Exec queue ID */ > > + __u32 exec_queue_id; > > > > -#define XE_ENGINE_GET_PROPERTY_BAN 0 > > +#define XE_EXEC_QUEUE_GET_PROPERTY_BAN 0 > > /** @property: property to get */ > > __u32 property; > > > > @@ -806,9 +806,9 @@ struct drm_xe_engine_get_property { > > __u64 reserved[2]; > > }; > > > > -struct drm_xe_engine_destroy { > > - /** @engine_id: Engine ID */ > > - __u32 engine_id; > > +struct drm_xe_exec_queue_destroy { > > + /** @exec_queue_id: Exec queue ID */ > > + __u32 exec_queue_id; > > > > /** @pad: MBZ */ > > __u32 pad; > > @@ -855,8 +855,8 @@ struct drm_xe_exec { > > /** @extensions: Pointer to the first extension struct, if any */ > > __u64 extensions; > > > > - /** @engine_id: Engine ID for the batch buffer */ > > - __u32 engine_id; > > + /** @exec_queue_id: Exec queue ID for the batch buffer */ > > + __u32 exec_queue_id; > > > > /** @num_syncs: Amount of struct drm_xe_sync in array. */ > > __u32 num_syncs; > > -- > > 2.34.1 > > ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-xe] ✓ CI.Patch_applied: success for Rename engine to exec_queue 2023-07-31 16:08 [Intel-xe] [RFC PATCH 0/1] Rename engine to exec_queue Francois Dugast 2023-07-31 16:08 ` [Intel-xe] [RFC PATCH 1/1] drm/xe: " Francois Dugast @ 2023-07-31 16:12 ` Patchwork 2023-07-31 16:12 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork ` (3 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2023-07-31 16:12 UTC (permalink / raw) To: Francois Dugast; +Cc: intel-xe == Series Details == Series: Rename engine to exec_queue URL : https://patchwork.freedesktop.org/series/121627/ State : success == Summary == === Applying kernel patches on branch 'drm-xe-next' with base: === Base commit: d74e8f840 drm/xe: Prefer WARN() over BUG() to avoid crashing the kernel === git am output follows === Applying: drm/xe: Rename engine to exec_queue ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-xe] ✗ CI.checkpatch: warning for Rename engine to exec_queue 2023-07-31 16:08 [Intel-xe] [RFC PATCH 0/1] Rename engine to exec_queue Francois Dugast 2023-07-31 16:08 ` [Intel-xe] [RFC PATCH 1/1] drm/xe: " Francois Dugast 2023-07-31 16:12 ` [Intel-xe] ✓ CI.Patch_applied: success for " Patchwork @ 2023-07-31 16:12 ` Patchwork 2023-07-31 16:14 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork ` (2 subsequent siblings) 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2023-07-31 16:12 UTC (permalink / raw) To: Francois Dugast; +Cc: intel-xe == Series Details == Series: Rename engine to exec_queue URL : https://patchwork.freedesktop.org/series/121627/ State : warning == Summary == + KERNEL=/kernel + git clone https://gitlab.freedesktop.org/drm/maintainer-tools mt Cloning into 'mt'... warning: redirecting to https://gitlab.freedesktop.org/drm/maintainer-tools.git/ + git -C mt rev-list -n1 origin/master c7d32770e3cd31d9fc134ce41f329b10aa33ee15 + cd /kernel + git config --global --add safe.directory /kernel + git log -n1 commit f8ca940e0d62b9cde562dee13eb95b1ca36586fc Author: Francois Dugast <francois.dugast@intel.com> Date: Mon Jul 31 16:08:49 2023 +0000 drm/xe: Rename engine to exec_queue Engine was inappropriately used to refer to execution queues and it also created some confusion with hardware engines. Where it applies the exec_queue variable name is changed to q and comments are also updated. Link: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/162 Signed-off-by: Francois Dugast <francois.dugast@intel.com> + /mt/dim checkpatch d74e8f8407bc922b04ba50e8f4e888bedb31330a drm-intel f8ca940e0 drm/xe: Rename engine to exec_queue Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' Traceback (most recent call last): File "scripts/spdxcheck.py", line 6, in <module> from ply import lex, yacc ModuleNotFoundError: No module named 'ply' -:535: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating? #535: deleted file mode 100644 -:4129: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'q' may be better as '(q)' to avoid precedence issues #4129: FILE: drivers/gpu/drm/xe/xe_guc_submit.c:694: +#define MAKE_SCHED_CONTEXT_ACTION(q, enable_disable) \ u32 action[] = { \ XE_GUC_ACTION_SCHED_CONTEXT_MODE_SET, \ + q->guc->id, \ GUC_CONTEXT_##enable_disable, \ } -:7438: WARNING:LONG_LINE: line length of 134 exceeds 100 columns #7438: FILE: include/uapi/drm/xe_drm.h:122: +#define DRM_IOCTL_XE_EXEC_QUEUE_CREATE DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_CREATE, struct drm_xe_exec_queue_create) -:7439: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #7439: FILE: include/uapi/drm/xe_drm.h:123: +#define DRM_IOCTL_XE_EXEC_QUEUE_GET_PROPERTY DRM_IOWR(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_GET_PROPERTY, struct drm_xe_exec_queue_get_property) -:7440: WARNING:LONG_LINE: line length of 136 exceeds 100 columns #7440: FILE: include/uapi/drm/xe_drm.h:124: +#define DRM_IOCTL_XE_EXEC_QUEUE_DESTROY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_DESTROY, struct drm_xe_exec_queue_destroy) -:7444: WARNING:LONG_LINE: line length of 146 exceeds 100 columns #7444: FILE: include/uapi/drm/xe_drm.h:127: +#define DRM_IOCTL_XE_EXEC_QUEUE_SET_PROPERTY DRM_IOW(DRM_COMMAND_BASE + DRM_XE_EXEC_QUEUE_SET_PROPERTY, struct drm_xe_exec_queue_set_property) total: 0 errors, 5 warnings, 1 checks, 6194 lines checked ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-xe] ✓ CI.KUnit: success for Rename engine to exec_queue 2023-07-31 16:08 [Intel-xe] [RFC PATCH 0/1] Rename engine to exec_queue Francois Dugast ` (2 preceding siblings ...) 2023-07-31 16:12 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork @ 2023-07-31 16:14 ` Patchwork 2023-07-31 16:17 ` [Intel-xe] ✓ CI.Build: " Patchwork 2023-07-31 16:18 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2023-07-31 16:14 UTC (permalink / raw) To: Francois Dugast; +Cc: intel-xe == Series Details == Series: Rename engine to exec_queue URL : https://patchwork.freedesktop.org/series/121627/ State : success == Summary == + trap cleanup EXIT + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/xe/.kunitconfig stty: 'standard input': Inappropriate ioctl for device [16:12:48] Configuring KUnit Kernel ... Generating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [16:12:52] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make ARCH=um O=.kunit --jobs=48 [16:13:12] Starting KUnit Kernel (1/1)... [16:13:12] ============================================================ [16:13:12] ==================== xe_bo (2 subtests) ==================== [16:13:12] [SKIPPED] xe_ccs_migrate_kunit [16:13:12] [SKIPPED] xe_bo_evict_kunit [16:13:12] ===================== [SKIPPED] xe_bo ====================== [16:13:12] ================== xe_dma_buf (1 subtest) ================== [16:13:12] [SKIPPED] xe_dma_buf_kunit [16:13:12] =================== [SKIPPED] xe_dma_buf =================== [16:13:12] ================== xe_migrate (1 subtest) ================== [16:13:12] [SKIPPED] xe_migrate_sanity_kunit [16:13:12] =================== [SKIPPED] xe_migrate =================== [16:13:12] =================== xe_pci (2 subtests) ==================== [16:13:12] [PASSED] xe_gmdid_graphics_ip [16:13:12] [PASSED] xe_gmdid_media_ip [16:13:12] ===================== [PASSED] xe_pci ====================== [16:13:12] ==================== xe_rtp (1 subtest) ==================== [16:13:12] ================== xe_rtp_process_tests =================== [16:13:12] [PASSED] coalesce-same-reg [16:13:12] [PASSED] no-match-no-add [16:13:12] [PASSED] no-match-no-add-multiple-rules [16:13:12] [PASSED] two-regs-two-entries [16:13:12] [PASSED] clr-one-set-other [16:13:12] [PASSED] set-field [16:13:12] [PASSED] conflict-duplicate [16:13:12] [PASSED] conflict-not-disjoint [16:13:12] [PASSED] conflict-reg-type [16:13:12] ============== [PASSED] xe_rtp_process_tests =============== [16:13:12] ===================== [PASSED] xe_rtp ====================== [16:13:12] ==================== xe_wa (1 subtest) ===================== [16:13:12] ======================== xe_wa_gt ========================= [16:13:12] [PASSED] TIGERLAKE (B0) [16:13:12] [PASSED] DG1 (A0) [16:13:12] [PASSED] DG1 (B0) [16:13:12] [PASSED] ALDERLAKE_S (A0) [16:13:12] [PASSED] ALDERLAKE_S (B0) [16:13:12] [PASSED] ALDERLAKE_S (C0) [16:13:12] [PASSED] ALDERLAKE_S (D0) [16:13:12] [PASSED] ALDERLAKE_P (A0) [16:13:12] [PASSED] ALDERLAKE_P (B0) [16:13:12] [PASSED] ALDERLAKE_P (C0) [16:13:12] [PASSED] DG2_G10 (A0) [16:13:12] [PASSED] DG2_G10 (A1) [16:13:12] [PASSED] DG2_G10 (B0) [16:13:12] [PASSED] DG2_G10 (C0) [16:13:12] [PASSED] DG2_G11 (A0) [16:13:12] [PASSED] DG2_G11 (B0) [16:13:12] [PASSED] DG2_G11 (B1) [16:13:12] [PASSED] DG2_G12 (A0) [16:13:12] [PASSED] DG2_G12 (A1) [16:13:12] [PASSED] PVC (B0) [16:13:12] [PASSED] PVC (B1) [16:13:12] [PASSED] PVC (C0) [16:13:12] ==================== [PASSED] xe_wa_gt ===================== [16:13:12] ====================== [PASSED] xe_wa ====================== [16:13:12] ============================================================ [16:13:12] Testing complete. Ran 37 tests: passed: 33, skipped: 4 [16:13:12] Elapsed time: 23.866s total, 4.231s configuring, 19.467s building, 0.149s running + /kernel/tools/testing/kunit/kunit.py run --kunitconfig /kernel/drivers/gpu/drm/tests/.kunitconfig [16:13:12] Configuring KUnit Kernel ... Regenerating .config ... Populating config with: $ make ARCH=um O=.kunit olddefconfig [16:13:14] Building KUnit Kernel ... Populating config with: $ make ARCH=um O=.kunit olddefconfig Building with: $ make ARCH=um O=.kunit --jobs=48 [16:13:32] Starting KUnit Kernel (1/1)... [16:13:32] ============================================================ [16:13:32] ============ drm_test_pick_cmdline (2 subtests) ============ [16:13:32] [PASSED] drm_test_pick_cmdline_res_1920_1080_60 [16:13:32] =============== drm_test_pick_cmdline_named =============== [16:13:32] [PASSED] NTSC [16:13:32] [PASSED] NTSC-J [16:13:32] [PASSED] PAL [16:13:32] [PASSED] PAL-M [16:13:32] =========== [PASSED] drm_test_pick_cmdline_named =========== [16:13:32] ============== [PASSED] drm_test_pick_cmdline ============== [16:13:32] ================== drm_buddy (6 subtests) ================== [16:13:32] [PASSED] drm_test_buddy_alloc_limit [16:13:32] [PASSED] drm_test_buddy_alloc_range [16:13:32] [PASSED] drm_test_buddy_alloc_optimistic [16:13:32] [PASSED] drm_test_buddy_alloc_pessimistic [16:13:32] [PASSED] drm_test_buddy_alloc_smoke [16:13:32] [PASSED] drm_test_buddy_alloc_pathological [16:13:32] ==================== [PASSED] drm_buddy ==================== [16:13:32] ============= drm_cmdline_parser (40 subtests) ============= [16:13:32] [PASSED] drm_test_cmdline_force_d_only [16:13:32] [PASSED] drm_test_cmdline_force_D_only_dvi [16:13:32] [PASSED] drm_test_cmdline_force_D_only_hdmi [16:13:32] [PASSED] drm_test_cmdline_force_D_only_not_digital [16:13:32] [PASSED] drm_test_cmdline_force_e_only [16:13:32] [PASSED] drm_test_cmdline_res [16:13:32] [PASSED] drm_test_cmdline_res_vesa [16:13:32] [PASSED] drm_test_cmdline_res_vesa_rblank [16:13:32] [PASSED] drm_test_cmdline_res_rblank [16:13:32] [PASSED] drm_test_cmdline_res_bpp [16:13:32] [PASSED] drm_test_cmdline_res_refresh [16:13:32] [PASSED] drm_test_cmdline_res_bpp_refresh [16:13:32] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced [16:13:32] [PASSED] drm_test_cmdline_res_bpp_refresh_margins [16:13:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_off [16:13:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on [16:13:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_analog [16:13:32] [PASSED] drm_test_cmdline_res_bpp_refresh_force_on_digital [16:13:32] [PASSED] drm_test_cmdline_res_bpp_refresh_interlaced_margins_force_on [16:13:32] [PASSED] drm_test_cmdline_res_margins_force_on [16:13:32] [PASSED] drm_test_cmdline_res_vesa_margins [16:13:32] [PASSED] drm_test_cmdline_name [16:13:32] [PASSED] drm_test_cmdline_name_bpp [16:13:32] [PASSED] drm_test_cmdline_name_option [16:13:32] [PASSED] drm_test_cmdline_name_bpp_option [16:13:32] [PASSED] drm_test_cmdline_rotate_0 [16:13:32] [PASSED] drm_test_cmdline_rotate_90 [16:13:32] [PASSED] drm_test_cmdline_rotate_180 [16:13:32] [PASSED] drm_test_cmdline_rotate_270 [16:13:32] [PASSED] drm_test_cmdline_hmirror [16:13:32] [PASSED] drm_test_cmdline_vmirror [16:13:32] [PASSED] drm_test_cmdline_margin_options [16:13:32] [PASSED] drm_test_cmdline_multiple_options [16:13:32] [PASSED] drm_test_cmdline_bpp_extra_and_option [16:13:32] [PASSED] drm_test_cmdline_extra_and_option [16:13:32] [PASSED] drm_test_cmdline_freestanding_options [16:13:32] [PASSED] drm_test_cmdline_freestanding_force_e_and_options [16:13:32] [PASSED] drm_test_cmdline_panel_orientation [16:13:32] ================ drm_test_cmdline_invalid ================= [16:13:32] [PASSED] margin_only [16:13:32] [PASSED] interlace_only [16:13:32] [PASSED] res_missing_x [16:13:32] [PASSED] res_missing_y [16:13:32] [PASSED] res_bad_y [16:13:32] [PASSED] res_missing_y_bpp [16:13:32] [PASSED] res_bad_bpp [16:13:32] [PASSED] res_bad_refresh [16:13:32] [PASSED] res_bpp_refresh_force_on_off [16:13:32] [PASSED] res_invalid_mode [16:13:32] [PASSED] res_bpp_wrong_place_mode [16:13:32] [PASSED] name_bpp_refresh [16:13:32] [PASSED] name_refresh [16:13:32] [PASSED] name_refresh_wrong_mode [16:13:32] [PASSED] name_refresh_invalid_mode [16:13:32] [PASSED] rotate_multiple [16:13:32] [PASSED] rotate_invalid_val [16:13:32] [PASSED] rotate_truncated [16:13:32] [PASSED] invalid_option [16:13:32] [PASSED] invalid_tv_option [16:13:32] [PASSED] truncated_tv_option [16:13:32] ============ [PASSED] drm_test_cmdline_invalid ============= [16:13:32] =============== drm_test_cmdline_tv_options =============== [16:13:32] [PASSED] NTSC [16:13:32] [PASSED] NTSC_443 [16:13:32] [PASSED] NTSC_J [16:13:32] [PASSED] PAL [16:13:32] [PASSED] PAL_M [16:13:32] [PASSED] PAL_N [16:13:32] [PASSED] SECAM [16:13:32] =========== [PASSED] drm_test_cmdline_tv_options =========== [16:13:32] =============== [PASSED] drm_cmdline_parser ================ [16:13:32] ========== drm_get_tv_mode_from_name (2 subtests) ========== [16:13:32] ========== drm_test_get_tv_mode_from_name_valid =========== [16:13:32] [PASSED] NTSC [16:13:32] [PASSED] NTSC-443 [16:13:32] [PASSED] NTSC-J [16:13:32] [PASSED] PAL [16:13:32] [PASSED] PAL-M [16:13:32] [PASSED] PAL-N [16:13:32] [PASSED] SECAM [16:13:32] ====== [PASSED] drm_test_get_tv_mode_from_name_valid ======= [16:13:32] [PASSED] drm_test_get_tv_mode_from_name_truncated [16:13:32] ============ [PASSED] drm_get_tv_mode_from_name ============ [16:13:32] ============= drm_damage_helper (21 subtests) ============== [16:13:32] [PASSED] drm_test_damage_iter_no_damage [16:13:32] [PASSED] drm_test_damage_iter_no_damage_fractional_src [16:13:32] [PASSED] drm_test_damage_iter_no_damage_src_moved [16:13:32] [PASSED] drm_test_damage_iter_no_damage_fractional_src_moved [16:13:32] [PASSED] drm_test_damage_iter_no_damage_not_visible [16:13:32] [PASSED] drm_test_damage_iter_no_damage_no_crtc [16:13:32] [PASSED] drm_test_damage_iter_no_damage_no_fb [16:13:32] [PASSED] drm_test_damage_iter_simple_damage [16:13:32] [PASSED] drm_test_damage_iter_single_damage [16:13:32] [PASSED] drm_test_damage_iter_single_damage_intersect_src [16:13:32] [PASSED] drm_test_damage_iter_single_damage_outside_src [16:13:32] [PASSED] drm_test_damage_iter_single_damage_fractional_src [16:13:32] [PASSED] drm_test_damage_iter_single_damage_intersect_fractional_src [16:13:32] [PASSED] drm_test_damage_iter_single_damage_outside_fractional_src [16:13:32] [PASSED] drm_test_damage_iter_single_damage_src_moved [16:13:32] [PASSED] drm_test_damage_iter_single_damage_fractional_src_moved [16:13:32] [PASSED] drm_test_damage_iter_damage [16:13:32] [PASSED] drm_test_damage_iter_damage_one_intersect [16:13:32] [PASSED] drm_test_damage_iter_damage_one_outside [16:13:32] [PASSED] drm_test_damage_iter_damage_src_moved [16:13:32] [PASSED] drm_test_damage_iter_damage_not_visible [16:13:32] ================ [PASSED] drm_damage_helper ================ [16:13:32] ============== drm_dp_mst_helper (2 subtests) ============== [16:13:32] ============== drm_test_dp_mst_calc_pbn_mode ============== [16:13:32] [PASSED] Clock 154000 BPP 30 DSC disabled [16:13:32] [PASSED] Clock 234000 BPP 30 DSC disabled [16:13:32] [PASSED] Clock 297000 BPP 24 DSC disabled [16:13:32] [PASSED] Clock 332880 BPP 24 DSC enabled [16:13:32] [PASSED] Clock 324540 BPP 24 DSC enabled [16:13:32] ========== [PASSED] drm_test_dp_mst_calc_pbn_mode ========== [16:13:32] ========= drm_test_dp_mst_sideband_msg_req_decode ========= [16:13:32] [PASSED] DP_ENUM_PATH_RESOURCES with port number [16:13:32] [PASSED] DP_POWER_UP_PHY with port number [16:13:32] [PASSED] DP_POWER_DOWN_PHY with port number [16:13:32] [PASSED] DP_ALLOCATE_PAYLOAD with SDP stream sinks [16:13:32] [PASSED] DP_ALLOCATE_PAYLOAD with port number [16:13:32] [PASSED] DP_ALLOCATE_PAYLOAD with VCPI [16:13:32] [PASSED] DP_ALLOCATE_PAYLOAD with PBN [16:13:32] [PASSED] DP_QUERY_PAYLOAD with port number [16:13:32] [PASSED] DP_QUERY_PAYLOAD with VCPI [16:13:32] [PASSED] DP_REMOTE_DPCD_READ with port number [16:13:32] [PASSED] DP_REMOTE_DPCD_READ with DPCD address [16:13:32] [PASSED] DP_REMOTE_DPCD_READ with max number of bytes [16:13:32] [PASSED] DP_REMOTE_DPCD_WRITE with port number [16:13:32] [PASSED] DP_REMOTE_DPCD_WRITE with DPCD address [16:13:32] [PASSED] DP_REMOTE_DPCD_WRITE with data array [16:13:32] [PASSED] DP_REMOTE_I2C_READ with port number [16:13:32] [PASSED] DP_REMOTE_I2C_READ with I2C device ID [16:13:32] [PASSED] DP_REMOTE_I2C_READ with transactions array [16:13:32] [PASSED] DP_REMOTE_I2C_WRITE with port number [16:13:32] [PASSED] DP_REMOTE_I2C_WRITE with I2C device ID [16:13:32] [PASSED] DP_REMOTE_I2C_WRITE with data array [16:13:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream ID [16:13:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with client ID [16:13:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream event [16:13:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with valid stream event [16:13:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with stream behavior [16:13:32] [PASSED] DP_QUERY_STREAM_ENC_STATUS with a valid stream behavior [16:13:32] ===== [PASSED] drm_test_dp_mst_sideband_msg_req_decode ===== [16:13:32] ================ [PASSED] drm_dp_mst_helper ================ [16:13:32] =========== drm_format_helper_test (11 subtests) =========== [16:13:32] ============== drm_test_fb_xrgb8888_to_gray8 ============== [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ========== [PASSED] drm_test_fb_xrgb8888_to_gray8 ========== [16:13:32] ============= drm_test_fb_xrgb8888_to_rgb332 ============== [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb332 ========== [16:13:32] ============= drm_test_fb_xrgb8888_to_rgb565 ============== [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb565 ========== [16:13:32] ============ drm_test_fb_xrgb8888_to_xrgb1555 ============= [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ======== [PASSED] drm_test_fb_xrgb8888_to_xrgb1555 ========= [16:13:32] ============ drm_test_fb_xrgb8888_to_argb1555 ============= [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ======== [PASSED] drm_test_fb_xrgb8888_to_argb1555 ========= [16:13:32] ============ drm_test_fb_xrgb8888_to_rgba5551 ============= [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ======== [PASSED] drm_test_fb_xrgb8888_to_rgba5551 ========= [16:13:32] ============= drm_test_fb_xrgb8888_to_rgb888 ============== [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ========= [PASSED] drm_test_fb_xrgb8888_to_rgb888 ========== [16:13:32] ============ drm_test_fb_xrgb8888_to_argb8888 ============= [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ======== [PASSED] drm_test_fb_xrgb8888_to_argb8888 ========= [16:13:32] =========== drm_test_fb_xrgb8888_to_xrgb2101010 =========== [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ======= [PASSED] drm_test_fb_xrgb8888_to_xrgb2101010 ======= [16:13:32] =========== drm_test_fb_xrgb8888_to_argb2101010 =========== [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ======= [PASSED] drm_test_fb_xrgb8888_to_argb2101010 ======= [16:13:32] ============== drm_test_fb_xrgb8888_to_mono =============== [16:13:32] [PASSED] single_pixel_source_buffer [16:13:32] [PASSED] single_pixel_clip_rectangle [16:13:32] [PASSED] well_known_colors [16:13:32] [PASSED] destination_pitch [16:13:32] ========== [PASSED] drm_test_fb_xrgb8888_to_mono =========== [16:13:32] ============= [PASSED] drm_format_helper_test ============== [16:13:32] ================= drm_format (18 subtests) ================= [16:13:32] [PASSED] drm_test_format_block_width_invalid [16:13:32] [PASSED] drm_test_format_block_width_one_plane [16:13:32] [PASSED] drm_test_format_block_width_two_plane [16:13:32] [PASSED] drm_test_format_block_width_three_plane [16:13:32] [PASSED] drm_test_format_block_width_tiled [16:13:32] [PASSED] drm_test_format_block_height_invalid [16:13:32] [PASSED] drm_test_format_block_height_one_plane [16:13:32] [PASSED] drm_test_format_block_height_two_plane [16:13:32] [PASSED] drm_test_format_block_height_three_plane [16:13:32] [PASSED] drm_test_format_block_height_tiled [16:13:32] [PASSED] drm_test_format_min_pitch_invalid [16:13:32] [PASSED] drm_test_format_min_pitch_one_plane_8bpp [16:13:32] [PASSED] drm_test_format_min_pitch_one_plane_16bpp [16:13:32] [PASSED] drm_test_format_min_pitch_one_plane_24bpp [16:13:32] [PASSED] drm_test_format_min_pitch_one_plane_32bpp [16:13:32] [PASSED] drm_test_format_min_pitch_two_plane [16:13:32] [PASSED] drm_test_format_min_pitch_three_plane_8bpp [16:13:32] [PASSED] drm_test_format_min_pitch_tiled [16:13:32] =================== [PASSED] drm_format ==================== [16:13:32] =============== drm_framebuffer (1 subtest) ================ [16:13:32] =============== drm_test_framebuffer_create =============== [16:13:32] [PASSED] ABGR8888 normal sizes [16:13:32] [PASSED] ABGR8888 max sizes [16:13:32] [PASSED] ABGR8888 pitch greater than min required [16:13:32] [PASSED] ABGR8888 pitch less than min required [16:13:32] [PASSED] ABGR8888 Invalid width [16:13:32] [PASSED] ABGR8888 Invalid buffer handle [16:13:32] [PASSED] No pixel format [16:13:32] [PASSED] ABGR8888 Width 0 [16:13:32] [PASSED] ABGR8888 Height 0 [16:13:32] [PASSED] ABGR8888 Out of bound height * pitch combination [16:13:32] [PASSED] ABGR8888 Large buffer offset [16:13:32] [PASSED] ABGR8888 Set DRM_MODE_FB_MODIFIERS without modifiers [16:13:32] [PASSED] ABGR8888 Valid buffer modifier [16:13:32] [PASSED] ABGR8888 Invalid buffer modifier(DRM_FORMAT_MOD_SAMSUNG_64_32_TILE) [16:13:32] [PASSED] ABGR8888 Extra pitches without DRM_MODE_FB_MODIFIERS [16:13:32] [PASSED] ABGR8888 Extra pitches with DRM_MODE_FB_MODIFIERS [16:13:32] [PASSED] NV12 Normal sizes [16:13:32] [PASSED] NV12 Max sizes [16:13:32] [PASSED] NV12 Invalid pitch [16:13:32] [PASSED] NV12 Invalid modifier/missing DRM_MODE_FB_MODIFIERS flag [16:13:32] [PASSED] NV12 different modifier per-plane [16:13:32] [PASSED] NV12 with DRM_FORMAT_MOD_SAMSUNG_64_32_TILE [16:13:32] [PASSED] NV12 Valid modifiers without DRM_MODE_FB_MODIFIERS [16:13:32] [PASSED] NV12 Modifier for inexistent plane [16:13:32] [PASSED] NV12 Handle for inexistent plane [16:13:32] [PASSED] NV12 Handle for inexistent plane without DRM_MODE_FB_MODIFIERS [16:13:32] [PASSED] YVU420 DRM_MODE_FB_MODIFIERS set without modifier [16:13:32] [PASSED] YVU420 Normal sizes [16:13:32] [PASSED] YVU420 Max sizes [16:13:32] [PASSED] YVU420 Invalid pitch [16:13:32] [PASSED] YVU420 Different pitches [16:13:32] [PASSED] YVU420 Different buffer offsets/pitches [16:13:32] [PASSED] YVU420 Modifier set just for plane 0, without DRM_MODE_FB_MODIFIERS [16:13:32] [PASSED] YVU420 Modifier set just for planes 0, 1, without DRM_MODE_FB_MODIFIERS [16:13:32] [PASSED] YVU420 Modifier set just for plane 0, 1, with DRM_MODE_FB_MODIFIERS [16:13:32] [PASSED] YVU420 Valid modifier [16:13:32] [PASSED] YVU420 Different modifiers per plane [16:13:32] [PASSED] YVU420 Modifier for inexistent plane [16:13:32] [PASSED] X0L2 Normal sizes [16:13:32] [PASSED] X0L2 Max sizes [16:13:32] [PASSED] X0L2 Invalid pitch [16:13:32] [PASSED] X0L2 Pitch greater than minimum required stty: 'standard input': Inappropriate ioctl for device [16:13:32] [PASSED] X0L2 Handle for inexistent plane [16:13:32] [PASSED] X0L2 Offset for inexistent plane, without DRM_MODE_FB_MODIFIERS set [16:13:32] [PASSED] X0L2 Modifier without DRM_MODE_FB_MODIFIERS set [16:13:32] [PASSED] X0L2 Valid modifier [16:13:32] [PASSED] X0L2 Modifier for inexistent plane [16:13:32] =========== [PASSED] drm_test_framebuffer_create =========== [16:13:32] ================= [PASSED] drm_framebuffer ================= [16:13:32] =============== drm-test-managed (1 subtest) =============== [16:13:32] [PASSED] drm_test_managed_run_action [16:13:32] ================ [PASSED] drm-test-managed ================= [16:13:32] =================== drm_mm (19 subtests) =================== [16:13:32] [PASSED] drm_test_mm_init [16:13:32] [PASSED] drm_test_mm_debug [16:13:42] [PASSED] drm_test_mm_reserve [16:13:52] [PASSED] drm_test_mm_insert [16:13:52] [PASSED] drm_test_mm_replace [16:13:52] [PASSED] drm_test_mm_insert_range [16:13:52] [PASSED] drm_test_mm_frag [16:13:52] [PASSED] drm_test_mm_align [16:13:52] [PASSED] drm_test_mm_align32 [16:13:53] [PASSED] drm_test_mm_align64 [16:13:53] [PASSED] drm_test_mm_evict [16:13:53] [PASSED] drm_test_mm_evict_range [16:13:53] [PASSED] drm_test_mm_topdown [16:13:53] [PASSED] drm_test_mm_bottomup [16:13:53] [PASSED] drm_test_mm_lowest [16:13:53] [PASSED] drm_test_mm_highest [16:13:54] [PASSED] drm_test_mm_color [16:13:54] [PASSED] drm_test_mm_color_evict [16:13:54] [PASSED] drm_test_mm_color_evict_range [16:13:54] ===================== [PASSED] drm_mm ====================== [16:13:54] ============= drm_modes_analog_tv (4 subtests) ============= [16:13:54] [PASSED] drm_test_modes_analog_tv_ntsc_480i [16:13:54] [PASSED] drm_test_modes_analog_tv_ntsc_480i_inlined [16:13:54] [PASSED] drm_test_modes_analog_tv_pal_576i [16:13:54] [PASSED] drm_test_modes_analog_tv_pal_576i_inlined [16:13:54] =============== [PASSED] drm_modes_analog_tv =============== [16:13:54] ============== drm_plane_helper (2 subtests) =============== [16:13:54] =============== drm_test_check_plane_state ================ [16:13:54] [PASSED] clipping_simple [16:13:54] [PASSED] clipping_rotate_reflect [16:13:54] [PASSED] positioning_simple [16:13:54] [PASSED] upscaling [16:13:54] [PASSED] downscaling [16:13:54] [PASSED] rounding1 [16:13:54] [PASSED] rounding2 [16:13:54] [PASSED] rounding3 [16:13:54] [PASSED] rounding4 [16:13:54] =========== [PASSED] drm_test_check_plane_state ============ [16:13:54] =========== drm_test_check_invalid_plane_state ============ [16:13:54] [PASSED] positioning_invalid [16:13:54] [PASSED] upscaling_invalid [16:13:54] [PASSED] downscaling_invalid [16:13:54] ======= [PASSED] drm_test_check_invalid_plane_state ======== [16:13:54] ================ [PASSED] drm_plane_helper ================= [16:13:54] ====== drm_connector_helper_tv_get_modes (1 subtest) ======= [16:13:54] ====== drm_test_connector_helper_tv_get_modes_check ======= [16:13:54] [PASSED] None [16:13:54] [PASSED] PAL [16:13:54] [PASSED] NTSC [16:13:54] [PASSED] Both, NTSC Default [16:13:54] [PASSED] Both, PAL Default [16:13:54] [PASSED] Both, NTSC Default, with PAL on command-line [16:13:54] [PASSED] Both, PAL Default, with NTSC on command-line [16:13:54] == [PASSED] drm_test_connector_helper_tv_get_modes_check === [16:13:54] ======== [PASSED] drm_connector_helper_tv_get_modes ======== [16:13:54] ================== drm_rect (9 subtests) =================== [16:13:54] [PASSED] drm_test_rect_clip_scaled_div_by_zero [16:13:54] [PASSED] drm_test_rect_clip_scaled_not_clipped [16:13:54] [PASSED] drm_test_rect_clip_scaled_clipped [16:13:54] [PASSED] drm_test_rect_clip_scaled_signed_vs_unsigned [16:13:54] ================= drm_test_rect_intersect ================= [16:13:54] [PASSED] top-left x bottom-right: 2x2+1+1 x 2x2+0+0 [16:13:54] [PASSED] top-right x bottom-left: 2x2+0+0 x 2x2+1-1 [16:13:54] [PASSED] bottom-left x top-right: 2x2+1-1 x 2x2+0+0 [16:13:54] [PASSED] bottom-right x top-left: 2x2+0+0 x 2x2+1+1 [16:13:54] [PASSED] right x left: 2x1+0+0 x 3x1+1+0 [16:13:54] [PASSED] left x right: 3x1+1+0 x 2x1+0+0 [16:13:54] [PASSED] up x bottom: 1x2+0+0 x 1x3+0-1 [16:13:54] [PASSED] bottom x up: 1x3+0-1 x 1x2+0+0 [16:13:54] [PASSED] touching corner: 1x1+0+0 x 2x2+1+1 [16:13:54] [PASSED] touching side: 1x1+0+0 x 1x1+1+0 [16:13:54] [PASSED] equal rects: 2x2+0+0 x 2x2+0+0 [16:13:54] [PASSED] inside another: 2x2+0+0 x 1x1+1+1 [16:13:54] [PASSED] far away: 1x1+0+0 x 1x1+3+6 [16:13:54] [PASSED] points intersecting: 0x0+5+10 x 0x0+5+10 [16:13:54] [PASSED] points not intersecting: 0x0+0+0 x 0x0+5+10 [16:13:54] ============= [PASSED] drm_test_rect_intersect ============= [16:13:54] ================ drm_test_rect_calc_hscale ================ [16:13:54] [PASSED] normal use [16:13:54] [PASSED] out of max range [16:13:54] [PASSED] out of min range [16:13:54] [PASSED] zero dst [16:13:54] [PASSED] negative src [16:13:54] [PASSED] negative dst [16:13:54] ============ [PASSED] drm_test_rect_calc_hscale ============ [16:13:54] ================ drm_test_rect_calc_vscale ================ [16:13:54] [PASSED] normal use [16:13:54] [PASSED] out of max range [16:13:54] [PASSED] out of min range [16:13:54] [PASSED] zero dst [16:13:54] [PASSED] negative src [16:13:54] [PASSED] negative dst [16:13:54] ============ [PASSED] drm_test_rect_calc_vscale ============ [16:13:54] ================== drm_test_rect_rotate =================== [16:13:54] [PASSED] reflect-x [16:13:54] [PASSED] reflect-y [16:13:54] [PASSED] rotate-0 [16:13:54] [PASSED] rotate-90 [16:13:54] [PASSED] rotate-180 [16:13:54] [PASSED] rotate-270 [16:13:54] ============== [PASSED] drm_test_rect_rotate =============== [16:13:54] ================ drm_test_rect_rotate_inv ================= [16:13:54] [PASSED] reflect-x [16:13:54] [PASSED] reflect-y [16:13:54] [PASSED] rotate-0 [16:13:54] [PASSED] rotate-90 [16:13:54] [PASSED] rotate-180 [16:13:54] [PASSED] rotate-270 [16:13:54] ============ [PASSED] drm_test_rect_rotate_inv ============= [16:13:54] ==================== [PASSED] drm_rect ===================== [16:13:54] ============================================================ [16:13:54] Testing complete. Ran 333 tests: passed: 333 [16:13:55] Elapsed time: 42.637s total, 1.711s configuring, 18.347s building, 22.569s running + cleanup ++ stat -c %u:%g /kernel + chown -R 1003:1003 /kernel ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-xe] ✓ CI.Build: success for Rename engine to exec_queue 2023-07-31 16:08 [Intel-xe] [RFC PATCH 0/1] Rename engine to exec_queue Francois Dugast ` (3 preceding siblings ...) 2023-07-31 16:14 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork @ 2023-07-31 16:17 ` Patchwork 2023-07-31 16:18 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2023-07-31 16:17 UTC (permalink / raw) To: Francois Dugast; +Cc: intel-xe == Series Details == Series: Rename engine to exec_queue URL : https://patchwork.freedesktop.org/series/121627/ State : success == Summary == + trap cleanup EXIT + cd /kernel + git clone https://gitlab.freedesktop.org/drm/xe/ci.git .ci Cloning into '.ci'... ++ date +%s + echo -e '\e[0Ksection_start:1690820048:build_x86_64[collapsed=true]\r\e[0KBuild x86-64' + mkdir -p build64 ^[[0Ksection_start:1690820048:build_x86_64[collapsed=true] ^[[0KBuild x86-64 + cat .ci/kernel/kconfig + make O=build64 olddefconfig make[1]: Entering directory '/kernel/build64' GEN Makefile HOSTCC scripts/basic/fixdep HOSTCC scripts/kconfig/conf.o HOSTCC scripts/kconfig/confdata.o HOSTCC scripts/kconfig/expr.o LEX scripts/kconfig/lexer.lex.c YACC scripts/kconfig/parser.tab.[ch] HOSTCC scripts/kconfig/lexer.lex.o HOSTCC scripts/kconfig/menu.o HOSTCC scripts/kconfig/parser.tab.o HOSTCC scripts/kconfig/preprocess.o HOSTCC scripts/kconfig/symbol.o HOSTCC scripts/kconfig/util.o HOSTLD scripts/kconfig/conf # # configuration written to .config # make[1]: Leaving directory '/kernel/build64' ++ nproc + make O=build64 -j48 make[1]: Entering directory '/kernel/build64' GEN Makefile WRAP arch/x86/include/generated/uapi/asm/bpf_perf_event.h WRAP arch/x86/include/generated/uapi/asm/errno.h SYSHDR arch/x86/include/generated/uapi/asm/unistd_64.h SYSHDR arch/x86/include/generated/uapi/asm/unistd_32.h WRAP arch/x86/include/generated/uapi/asm/fcntl.h SYSHDR arch/x86/include/generated/uapi/asm/unistd_x32.h WRAP arch/x86/include/generated/uapi/asm/ioctl.h GEN arch/x86/include/generated/asm/orc_hash.h WRAP arch/x86/include/generated/uapi/asm/ioctls.h SYSTBL arch/x86/include/generated/asm/syscalls_32.h WRAP arch/x86/include/generated/uapi/asm/ipcbuf.h SYSHDR arch/x86/include/generated/asm/unistd_32_ia32.h WRAP arch/x86/include/generated/uapi/asm/param.h WRAP arch/x86/include/generated/uapi/asm/poll.h SYSHDR arch/x86/include/generated/asm/unistd_64_x32.h WRAP arch/x86/include/generated/uapi/asm/resource.h SYSTBL arch/x86/include/generated/asm/syscalls_64.h WRAP arch/x86/include/generated/uapi/asm/socket.h WRAP arch/x86/include/generated/uapi/asm/sockios.h WRAP arch/x86/include/generated/uapi/asm/termbits.h WRAP arch/x86/include/generated/uapi/asm/termios.h WRAP arch/x86/include/generated/uapi/asm/types.h HOSTCC arch/x86/tools/relocs_32.o HOSTCC arch/x86/tools/relocs_64.o HOSTCC arch/x86/tools/relocs_common.o WRAP arch/x86/include/generated/asm/early_ioremap.h WRAP arch/x86/include/generated/asm/export.h WRAP arch/x86/include/generated/asm/mcs_spinlock.h WRAP arch/x86/include/generated/asm/irq_regs.h WRAP arch/x86/include/generated/asm/kmap_size.h WRAP arch/x86/include/generated/asm/local64.h WRAP arch/x86/include/generated/asm/mmiowb.h UPD include/generated/uapi/linux/version.h WRAP arch/x86/include/generated/asm/module.lds.h WRAP arch/x86/include/generated/asm/rwonce.h WRAP arch/x86/include/generated/asm/unaligned.h UPD include/config/kernel.release UPD include/generated/compile.h HOSTCC scripts/kallsyms HOSTCC scripts/unifdef HOSTCC scripts/sorttable HOSTCC scripts/asn1_compiler UPD include/generated/utsrelease.h DESCEND objtool HOSTCC /kernel/build64/tools/objtool/fixdep.o HOSTLD /kernel/build64/tools/objtool/fixdep-in.o LINK /kernel/build64/tools/objtool/fixdep INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/exec-cmd.h INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/help.h INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/pager.h INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/parse-options.h INSTALL /kernel/build64/tools/objtool/libsubcmd/include/subcmd/run-command.h CC /kernel/build64/tools/objtool/libsubcmd/exec-cmd.o CC /kernel/build64/tools/objtool/libsubcmd/help.o CC /kernel/build64/tools/objtool/libsubcmd/pager.o CC /kernel/build64/tools/objtool/libsubcmd/parse-options.o CC /kernel/build64/tools/objtool/libsubcmd/run-command.o INSTALL libsubcmd_headers CC /kernel/build64/tools/objtool/libsubcmd/sigchain.o CC /kernel/build64/tools/objtool/libsubcmd/subcmd-config.o HOSTLD arch/x86/tools/relocs CC scripts/mod/empty.o HOSTCC scripts/mod/mk_elfconfig CC scripts/mod/devicetable-offsets.s HDRINST usr/include/video/edid.h HDRINST usr/include/video/sisfb.h HDRINST usr/include/video/uvesafb.h HDRINST usr/include/drm/amdgpu_drm.h HDRINST usr/include/drm/qaic_accel.h HDRINST usr/include/drm/i915_drm.h HDRINST usr/include/drm/vgem_drm.h HDRINST usr/include/drm/virtgpu_drm.h HDRINST usr/include/drm/xe_drm.h HDRINST usr/include/drm/omap_drm.h HDRINST usr/include/drm/radeon_drm.h HDRINST usr/include/drm/tegra_drm.h HDRINST usr/include/drm/drm_mode.h HDRINST usr/include/drm/ivpu_accel.h HDRINST usr/include/drm/exynos_drm.h HDRINST usr/include/drm/drm_sarea.h HDRINST usr/include/drm/v3d_drm.h HDRINST usr/include/drm/qxl_drm.h HDRINST usr/include/drm/drm_fourcc.h HDRINST usr/include/drm/nouveau_drm.h HDRINST usr/include/drm/habanalabs_accel.h HDRINST usr/include/drm/msm_drm.h HDRINST usr/include/drm/vmwgfx_drm.h HDRINST usr/include/drm/etnaviv_drm.h HDRINST usr/include/drm/vc4_drm.h HDRINST usr/include/drm/panfrost_drm.h HDRINST usr/include/drm/lima_drm.h HDRINST usr/include/drm/drm.h HDRINST usr/include/drm/armada_drm.h HDRINST usr/include/mtd/inftl-user.h HDRINST usr/include/mtd/mtd-user.h HDRINST usr/include/mtd/nftl-user.h HDRINST usr/include/mtd/ubi-user.h HDRINST usr/include/mtd/mtd-abi.h HDRINST usr/include/xen/gntdev.h HDRINST usr/include/xen/gntalloc.h HDRINST usr/include/xen/evtchn.h HDRINST usr/include/xen/privcmd.h HDRINST usr/include/asm-generic/auxvec.h HDRINST usr/include/asm-generic/bitsperlong.h HDRINST usr/include/asm-generic/posix_types.h HDRINST usr/include/asm-generic/ioctls.h HDRINST usr/include/asm-generic/shmbuf.h HDRINST usr/include/asm-generic/mman.h HDRINST usr/include/asm-generic/bpf_perf_event.h HDRINST usr/include/asm-generic/types.h HDRINST usr/include/asm-generic/poll.h HDRINST usr/include/asm-generic/msgbuf.h HDRINST usr/include/asm-generic/swab.h HDRINST usr/include/asm-generic/statfs.h HDRINST usr/include/asm-generic/unistd.h HDRINST usr/include/asm-generic/hugetlb_encode.h HDRINST usr/include/asm-generic/resource.h HDRINST usr/include/asm-generic/param.h HDRINST usr/include/asm-generic/termbits-common.h HDRINST usr/include/asm-generic/sockios.h HDRINST usr/include/asm-generic/kvm_para.h HDRINST usr/include/asm-generic/errno.h HDRINST usr/include/asm-generic/termios.h HDRINST usr/include/asm-generic/mman-common.h UPD scripts/mod/devicetable-offsets.h HDRINST usr/include/asm-generic/ioctl.h HDRINST usr/include/asm-generic/socket.h HDRINST usr/include/asm-generic/signal-defs.h HDRINST usr/include/asm-generic/termbits.h HDRINST usr/include/asm-generic/int-ll64.h HDRINST usr/include/asm-generic/signal.h HDRINST usr/include/asm-generic/siginfo.h HDRINST usr/include/asm-generic/stat.h HDRINST usr/include/asm-generic/int-l64.h HDRINST usr/include/asm-generic/errno-base.h HDRINST usr/include/asm-generic/fcntl.h HDRINST usr/include/asm-generic/setup.h HDRINST usr/include/asm-generic/ipcbuf.h HDRINST usr/include/asm-generic/sembuf.h HDRINST usr/include/asm-generic/ucontext.h HDRINST usr/include/rdma/mlx5_user_ioctl_cmds.h HDRINST usr/include/rdma/irdma-abi.h HDRINST usr/include/rdma/mana-abi.h HDRINST usr/include/rdma/hfi/hfi1_user.h HDRINST usr/include/rdma/hfi/hfi1_ioctl.h HDRINST usr/include/rdma/rdma_user_rxe.h HDRINST usr/include/rdma/rdma_user_ioctl.h HDRINST usr/include/rdma/mlx5_user_ioctl_verbs.h HDRINST usr/include/rdma/bnxt_re-abi.h HDRINST usr/include/rdma/hns-abi.h HDRINST usr/include/rdma/qedr-abi.h HDRINST usr/include/rdma/ib_user_ioctl_cmds.h HDRINST usr/include/rdma/vmw_pvrdma-abi.h HDRINST usr/include/rdma/ib_user_sa.h HDRINST usr/include/rdma/ib_user_ioctl_verbs.h HDRINST usr/include/rdma/rvt-abi.h HDRINST usr/include/rdma/mlx5-abi.h HDRINST usr/include/rdma/rdma_netlink.h HDRINST usr/include/rdma/erdma-abi.h HDRINST usr/include/rdma/rdma_user_ioctl_cmds.h HDRINST usr/include/rdma/rdma_user_cm.h HDRINST usr/include/rdma/ib_user_verbs.h HDRINST usr/include/rdma/efa-abi.h HDRINST usr/include/rdma/siw-abi.h HDRINST usr/include/rdma/mlx4-abi.h HDRINST usr/include/rdma/mthca-abi.h HDRINST usr/include/rdma/ib_user_mad.h HDRINST usr/include/rdma/ocrdma-abi.h HDRINST usr/include/rdma/cxgb4-abi.h HDRINST usr/include/misc/xilinx_sdfec.h HDRINST usr/include/misc/uacce/hisi_qm.h HDRINST usr/include/misc/uacce/uacce.h HDRINST usr/include/misc/cxl.h HDRINST usr/include/misc/ocxl.h HDRINST usr/include/misc/fastrpc.h HDRINST usr/include/misc/pvpanic.h HDRINST usr/include/linux/i8k.h HDRINST usr/include/linux/acct.h HDRINST usr/include/linux/atmmpc.h HDRINST usr/include/linux/fs.h HDRINST usr/include/linux/cifs/cifs_mount.h HDRINST usr/include/linux/cifs/cifs_netlink.h HDRINST usr/include/linux/if_packet.h MKELF scripts/mod/elfconfig.h HDRINST usr/include/linux/route.h HDRINST usr/include/linux/patchkey.h HDRINST usr/include/linux/tc_ematch/tc_em_cmp.h HDRINST usr/include/linux/tc_ematch/tc_em_ipt.h HDRINST usr/include/linux/tc_ematch/tc_em_meta.h HDRINST usr/include/linux/tc_ematch/tc_em_nbyte.h HOSTCC scripts/mod/modpost.o HDRINST usr/include/linux/tc_ematch/tc_em_text.h HOSTCC scripts/mod/file2alias.o HDRINST usr/include/linux/virtio_pmem.h HDRINST usr/include/linux/rkisp1-config.h HDRINST usr/include/linux/vhost.h HOSTCC scripts/mod/sumversion.o HDRINST usr/include/linux/cec-funcs.h HDRINST usr/include/linux/ppdev.h HDRINST usr/include/linux/isdn/capicmd.h HDRINST usr/include/linux/virtio_fs.h HDRINST usr/include/linux/netfilter_ipv6.h HDRINST usr/include/linux/lirc.h HDRINST usr/include/linux/mroute6.h HDRINST usr/include/linux/nl80211-vnd-intel.h HDRINST usr/include/linux/ivtvfb.h HDRINST usr/include/linux/auxvec.h HDRINST usr/include/linux/dm-log-userspace.h HDRINST usr/include/linux/dccp.h HDRINST usr/include/linux/virtio_scmi.h HDRINST usr/include/linux/atmarp.h HDRINST usr/include/linux/arcfb.h HDRINST usr/include/linux/nbd-netlink.h HDRINST usr/include/linux/sched/types.h HDRINST usr/include/linux/tcp.h HDRINST usr/include/linux/neighbour.h HDRINST usr/include/linux/dlm_device.h HDRINST usr/include/linux/wmi.h HDRINST usr/include/linux/btrfs_tree.h HDRINST usr/include/linux/virtio_crypto.h HDRINST usr/include/linux/vbox_err.h HDRINST usr/include/linux/edd.h HDRINST usr/include/linux/loop.h HDRINST usr/include/linux/nvme_ioctl.h HDRINST usr/include/linux/mmtimer.h HDRINST usr/include/linux/if_pppol2tp.h HDRINST usr/include/linux/mtio.h HDRINST usr/include/linux/if_arcnet.h HDRINST usr/include/linux/romfs_fs.h HDRINST usr/include/linux/posix_types.h HDRINST usr/include/linux/rtc.h HDRINST usr/include/linux/landlock.h HDRINST usr/include/linux/gpio.h HDRINST usr/include/linux/selinux_netlink.h HDRINST usr/include/linux/pps.h HDRINST usr/include/linux/ndctl.h HDRINST usr/include/linux/virtio_gpu.h HDRINST usr/include/linux/android/binderfs.h HDRINST usr/include/linux/android/binder.h HDRINST usr/include/linux/virtio_vsock.h HDRINST usr/include/linux/sound.h HDRINST usr/include/linux/vtpm_proxy.h HDRINST usr/include/linux/nfs_fs.h HDRINST usr/include/linux/elf-fdpic.h HDRINST usr/include/linux/adfs_fs.h HDRINST usr/include/linux/target_core_user.h HDRINST usr/include/linux/netlink_diag.h HDRINST usr/include/linux/const.h HDRINST usr/include/linux/firewire-cdev.h HDRINST usr/include/linux/vdpa.h HDRINST usr/include/linux/if_infiniband.h HDRINST usr/include/linux/serial.h HDRINST usr/include/linux/iio/types.h HDRINST usr/include/linux/iio/buffer.h HDRINST usr/include/linux/iio/events.h HDRINST usr/include/linux/baycom.h HDRINST usr/include/linux/major.h HDRINST usr/include/linux/atmppp.h HDRINST usr/include/linux/ipv6_route.h HDRINST usr/include/linux/spi/spidev.h HDRINST usr/include/linux/spi/spi.h HDRINST usr/include/linux/virtio_ring.h HDRINST usr/include/linux/hdlc/ioctl.h HDRINST usr/include/linux/remoteproc_cdev.h HDRINST usr/include/linux/hyperv.h HDRINST usr/include/linux/rpl_iptunnel.h HDRINST usr/include/linux/sync_file.h HDRINST usr/include/linux/igmp.h HDRINST usr/include/linux/v4l2-dv-timings.h HDRINST usr/include/linux/virtio_i2c.h HDRINST usr/include/linux/xfrm.h HDRINST usr/include/linux/capability.h HDRINST usr/include/linux/gtp.h HDRINST usr/include/linux/xdp_diag.h HDRINST usr/include/linux/pkt_cls.h HDRINST usr/include/linux/suspend_ioctls.h HDRINST usr/include/linux/vt.h HDRINST usr/include/linux/loadpin.h HDRINST usr/include/linux/dlm_plock.h HDRINST usr/include/linux/fb.h HDRINST usr/include/linux/max2175.h HDRINST usr/include/linux/sunrpc/debug.h HDRINST usr/include/linux/gsmmux.h HDRINST usr/include/linux/watchdog.h HDRINST usr/include/linux/vhost_types.h HDRINST usr/include/linux/vduse.h HDRINST usr/include/linux/ila.h HDRINST usr/include/linux/tdx-guest.h HDRINST usr/include/linux/close_range.h HDRINST usr/include/linux/ivtv.h HDRINST usr/include/linux/cryptouser.h HDRINST usr/include/linux/netfilter/xt_string.h HDRINST usr/include/linux/netfilter/nfnetlink_compat.h HDRINST usr/include/linux/netfilter/nf_nat.h HDRINST usr/include/linux/netfilter/xt_recent.h HDRINST usr/include/linux/netfilter/xt_addrtype.h HDRINST usr/include/linux/netfilter/nf_conntrack_tcp.h HDRINST usr/include/linux/netfilter/xt_MARK.h HDRINST usr/include/linux/netfilter/xt_SYNPROXY.h HDRINST usr/include/linux/netfilter/xt_multiport.h HDRINST usr/include/linux/netfilter/nfnetlink.h HDRINST usr/include/linux/netfilter/xt_cgroup.h HDRINST usr/include/linux/netfilter/nf_synproxy.h HDRINST usr/include/linux/netfilter/xt_TCPOPTSTRIP.h HDRINST usr/include/linux/netfilter/nfnetlink_log.h HDRINST usr/include/linux/netfilter/xt_TPROXY.h HDRINST usr/include/linux/netfilter/xt_u32.h HDRINST usr/include/linux/netfilter/nfnetlink_osf.h HDRINST usr/include/linux/netfilter/xt_ecn.h HDRINST usr/include/linux/netfilter/xt_esp.h HDRINST usr/include/linux/netfilter/nfnetlink_hook.h HDRINST usr/include/linux/netfilter/xt_mac.h HDRINST usr/include/linux/netfilter/xt_comment.h HDRINST usr/include/linux/netfilter/xt_NFQUEUE.h HDRINST usr/include/linux/netfilter/xt_osf.h HDRINST usr/include/linux/netfilter/xt_hashlimit.h HDRINST usr/include/linux/netfilter/nf_conntrack_sctp.h HDRINST usr/include/linux/netfilter/xt_socket.h HDRINST usr/include/linux/netfilter/xt_connmark.h HDRINST usr/include/linux/netfilter/xt_sctp.h HDRINST usr/include/linux/netfilter/xt_tcpudp.h HDRINST usr/include/linux/netfilter/xt_DSCP.h HDRINST usr/include/linux/netfilter/xt_time.h HDRINST usr/include/linux/netfilter/xt_IDLETIMER.h HDRINST usr/include/linux/netfilter/xt_policy.h HDRINST usr/include/linux/netfilter/xt_rpfilter.h HDRINST usr/include/linux/netfilter/xt_nfacct.h HDRINST usr/include/linux/netfilter/xt_SECMARK.h HDRINST usr/include/linux/netfilter/xt_length.h HDRINST usr/include/linux/netfilter/nfnetlink_cthelper.h HDRINST usr/include/linux/netfilter/xt_quota.h HDRINST usr/include/linux/netfilter/xt_CLASSIFY.h HDRINST usr/include/linux/netfilter/xt_ipcomp.h HDRINST usr/include/linux/netfilter/xt_iprange.h HDRINST usr/include/linux/netfilter/xt_bpf.h HDRINST usr/include/linux/netfilter/xt_LOG.h HDRINST usr/include/linux/netfilter/xt_rateest.h HDRINST usr/include/linux/netfilter/xt_CONNSECMARK.h HDRINST usr/include/linux/netfilter/xt_HMARK.h HDRINST usr/include/linux/netfilter/xt_CONNMARK.h HDRINST usr/include/linux/netfilter/xt_pkttype.h HDRINST usr/include/linux/netfilter/xt_ipvs.h HDRINST usr/include/linux/netfilter/xt_devgroup.h HDRINST usr/include/linux/netfilter/xt_AUDIT.h HDRINST usr/include/linux/netfilter/xt_realm.h HDRINST usr/include/linux/netfilter/nf_conntrack_common.h HDRINST usr/include/linux/netfilter/xt_set.h HDRINST usr/include/linux/netfilter/xt_LED.h HDRINST usr/include/linux/netfilter/xt_connlabel.h HDRINST usr/include/linux/netfilter/xt_owner.h HDRINST usr/include/linux/netfilter/xt_dccp.h HDRINST usr/include/linux/netfilter/xt_limit.h HDRINST usr/include/linux/netfilter/xt_conntrack.h HDRINST usr/include/linux/netfilter/xt_TEE.h HDRINST usr/include/linux/netfilter/xt_RATEEST.h HDRINST usr/include/linux/netfilter/xt_connlimit.h HDRINST usr/include/linux/netfilter/ipset/ip_set.h HDRINST usr/include/linux/netfilter/ipset/ip_set_list.h HDRINST usr/include/linux/netfilter/ipset/ip_set_hash.h HDRINST usr/include/linux/netfilter/ipset/ip_set_bitmap.h HDRINST usr/include/linux/netfilter/x_tables.h HDRINST usr/include/linux/netfilter/xt_dscp.h HDRINST usr/include/linux/netfilter/nf_conntrack_ftp.h HDRINST usr/include/linux/netfilter/xt_cluster.h HDRINST usr/include/linux/netfilter/nf_conntrack_tuple_common.h HDRINST usr/include/linux/netfilter/nf_log.h HDRINST usr/include/linux/netfilter/xt_tcpmss.h HDRINST usr/include/linux/netfilter/xt_NFLOG.h HDRINST usr/include/linux/netfilter/xt_l2tp.h HDRINST usr/include/linux/netfilter/xt_helper.h HDRINST usr/include/linux/netfilter/xt_statistic.h HDRINST usr/include/linux/netfilter/nfnetlink_queue.h HDRINST usr/include/linux/netfilter/nfnetlink_cttimeout.h HDRINST usr/include/linux/netfilter/xt_CT.h HDRINST usr/include/linux/netfilter/xt_CHECKSUM.h HDRINST usr/include/linux/netfilter/xt_connbytes.h HDRINST usr/include/linux/netfilter/xt_state.h HDRINST usr/include/linux/netfilter/nf_tables.h HDRINST usr/include/linux/netfilter/xt_mark.h HDRINST usr/include/linux/netfilter/xt_cpu.h HDRINST usr/include/linux/netfilter/nf_tables_compat.h HDRINST usr/include/linux/netfilter/xt_physdev.h HDRINST usr/include/linux/netfilter/nfnetlink_conntrack.h HDRINST usr/include/linux/netfilter/nfnetlink_acct.h HDRINST usr/include/linux/netfilter/xt_TCPMSS.h HDRINST usr/include/linux/tty_flags.h HDRINST usr/include/linux/if_phonet.h HDRINST usr/include/linux/elf-em.h HDRINST usr/include/linux/vm_sockets.h HDRINST usr/include/linux/dlmconstants.h HDRINST usr/include/linux/bsg.h HDRINST usr/include/linux/matroxfb.h HDRINST usr/include/linux/sysctl.h HDRINST usr/include/linux/unix_diag.h HDRINST usr/include/linux/pcitest.h HDRINST usr/include/linux/mman.h HDRINST usr/include/linux/if_plip.h HDRINST usr/include/linux/virtio_balloon.h HDRINST usr/include/linux/pidfd.h HDRINST usr/include/linux/f2fs.h HDRINST usr/include/linux/x25.h HDRINST usr/include/linux/if_cablemodem.h HDRINST usr/include/linux/utsname.h HDRINST usr/include/linux/counter.h HDRINST usr/include/linux/atm_tcp.h HDRINST usr/include/linux/atalk.h HDRINST usr/include/linux/virtio_rng.h HDRINST usr/include/linux/vboxguest.h HDRINST usr/include/linux/bpf_perf_event.h HDRINST usr/include/linux/ipmi_ssif_bmc.h HDRINST usr/include/linux/nfs_mount.h HDRINST usr/include/linux/sonet.h HDRINST usr/include/linux/netfilter.h HDRINST usr/include/linux/keyctl.h HDRINST usr/include/linux/nl80211.h HDRINST usr/include/linux/misc/bcm_vk.h HDRINST usr/include/linux/audit.h HDRINST usr/include/linux/tipc_config.h HDRINST usr/include/linux/tipc_sockets_diag.h HDRINST usr/include/linux/futex.h HDRINST usr/include/linux/sev-guest.h HDRINST usr/include/linux/ublk_cmd.h HDRINST usr/include/linux/types.h HDRINST usr/include/linux/virtio_input.h HDRINST usr/include/linux/if_slip.h HDRINST usr/include/linux/personality.h HDRINST usr/include/linux/openat2.h HDRINST usr/include/linux/poll.h HDRINST usr/include/linux/posix_acl.h HDRINST usr/include/linux/smc_diag.h HDRINST usr/include/linux/snmp.h HDRINST usr/include/linux/errqueue.h HDRINST usr/include/linux/if_tunnel.h HDRINST usr/include/linux/fanotify.h HDRINST usr/include/linux/kernel.h HDRINST usr/include/linux/rtnetlink.h HDRINST usr/include/linux/rpl.h HDRINST usr/include/linux/memfd.h HDRINST usr/include/linux/serial_core.h HDRINST usr/include/linux/dns_resolver.h HDRINST usr/include/linux/pr.h HDRINST usr/include/linux/atm_eni.h HDRINST usr/include/linux/lp.h HDRINST usr/include/linux/virtio_mem.h HDRINST usr/include/linux/ultrasound.h HDRINST usr/include/linux/sctp.h HDRINST usr/include/linux/uio.h HDRINST usr/include/linux/tcp_metrics.h HDRINST usr/include/linux/wwan.h HDRINST usr/include/linux/atmbr2684.h HDRINST usr/include/linux/in_route.h HDRINST usr/include/linux/qemu_fw_cfg.h HDRINST usr/include/linux/if_macsec.h HDRINST usr/include/linux/usb/charger.h HDRINST usr/include/linux/usb/g_uvc.h HDRINST usr/include/linux/usb/gadgetfs.h HDRINST usr/include/linux/usb/raw_gadget.h HDRINST usr/include/linux/usb/cdc-wdm.h HDRINST usr/include/linux/usb/g_printer.h HDRINST usr/include/linux/usb/midi.h HDRINST usr/include/linux/usb/tmc.h HDRINST usr/include/linux/usb/video.h HDRINST usr/include/linux/usb/functionfs.h HDRINST usr/include/linux/usb/audio.h HDRINST usr/include/linux/usb/ch11.h HDRINST usr/include/linux/usb/ch9.h HDRINST usr/include/linux/usb/cdc.h HDRINST usr/include/linux/jffs2.h HDRINST usr/include/linux/ax25.h HDRINST usr/include/linux/auto_fs.h HDRINST usr/include/linux/tiocl.h HDRINST usr/include/linux/scc.h HDRINST usr/include/linux/psci.h HDRINST usr/include/linux/swab.h HDRINST usr/include/linux/cec.h HDRINST usr/include/linux/kfd_ioctl.h HDRINST usr/include/linux/smc.h HDRINST usr/include/linux/qrtr.h HDRINST usr/include/linux/screen_info.h HDRINST usr/include/linux/nfsacl.h HDRINST usr/include/linux/seg6_hmac.h HDRINST usr/include/linux/gameport.h HDRINST usr/include/linux/wireless.h HDRINST usr/include/linux/fdreg.h HDRINST usr/include/linux/cciss_defs.h HDRINST usr/include/linux/serial_reg.h HDRINST usr/include/linux/perf_event.h HDRINST usr/include/linux/in6.h HDRINST usr/include/linux/hid.h HDRINST usr/include/linux/netlink.h HDRINST usr/include/linux/fuse.h HDRINST usr/include/linux/magic.h HDRINST usr/include/linux/ioam6_iptunnel.h HDRINST usr/include/linux/stm.h HDRINST usr/include/linux/vsockmon.h HDRINST usr/include/linux/seg6.h HDRINST usr/include/linux/idxd.h HDRINST usr/include/linux/nitro_enclaves.h HDRINST usr/include/linux/ptrace.h HDRINST usr/include/linux/ioam6_genl.h HDRINST usr/include/linux/qnx4_fs.h HDRINST usr/include/linux/fsl_mc.h HDRINST usr/include/linux/net_tstamp.h HDRINST usr/include/linux/msg.h HDRINST usr/include/linux/netfilter_ipv4/ipt_TTL.h HDRINST usr/include/linux/netfilter_ipv4/ipt_ttl.h HDRINST usr/include/linux/netfilter_ipv4/ipt_ah.h HDRINST usr/include/linux/netfilter_ipv4/ipt_ECN.h HDRINST usr/include/linux/netfilter_ipv4/ip_tables.h HDRINST usr/include/linux/netfilter_ipv4/ipt_ecn.h HDRINST usr/include/linux/netfilter_ipv4/ipt_CLUSTERIP.h HDRINST usr/include/linux/netfilter_ipv4/ipt_REJECT.h HDRINST usr/include/linux/netfilter_ipv4/ipt_LOG.h HDRINST usr/include/linux/sem.h HDRINST usr/include/linux/net_namespace.h HDRINST usr/include/linux/radeonfb.h HDRINST usr/include/linux/tee.h HDRINST usr/include/linux/udp.h HDRINST usr/include/linux/virtio_bt.h HDRINST usr/include/linux/v4l2-subdev.h HDRINST usr/include/linux/posix_acl_xattr.h HDRINST usr/include/linux/v4l2-mediabus.h HDRINST usr/include/linux/atmapi.h HDRINST usr/include/linux/raid/md_p.h HDRINST usr/include/linux/raid/md_u.h HDRINST usr/include/linux/zorro_ids.h HDRINST usr/include/linux/nbd.h HDRINST usr/include/linux/isst_if.h HDRINST usr/include/linux/rxrpc.h HDRINST usr/include/linux/unistd.h HDRINST usr/include/linux/if_arp.h HDRINST usr/include/linux/atm_zatm.h HDRINST usr/include/linux/io_uring.h HDRINST usr/include/linux/if_fddi.h HDRINST usr/include/linux/bpqether.h HDRINST usr/include/linux/sysinfo.h HDRINST usr/include/linux/auto_dev-ioctl.h HDRINST usr/include/linux/nfs4_mount.h HDRINST usr/include/linux/keyboard.h HDRINST usr/include/linux/virtio_mmio.h HDRINST usr/include/linux/input.h HDRINST usr/include/linux/qnxtypes.h HDRINST usr/include/linux/mdio.h HDRINST usr/include/linux/lwtunnel.h HDRINST usr/include/linux/gfs2_ondisk.h HDRINST usr/include/linux/nfs4.h HDRINST usr/include/linux/ptp_clock.h HDRINST usr/include/linux/nubus.h HDRINST usr/include/linux/if_bonding.h HDRINST usr/include/linux/kcov.h HDRINST usr/include/linux/fadvise.h HDRINST usr/include/linux/taskstats.h HDRINST usr/include/linux/veth.h HDRINST usr/include/linux/atm.h HDRINST usr/include/linux/ipmi.h HDRINST usr/include/linux/kdev_t.h HDRINST usr/include/linux/mount.h HDRINST usr/include/linux/shm.h HDRINST usr/include/linux/resource.h HDRINST usr/include/linux/prctl.h HDRINST usr/include/linux/watch_queue.h HDRINST usr/include/linux/sched.h HDRINST usr/include/linux/phonet.h HDRINST usr/include/linux/random.h HDRINST usr/include/linux/tty.h HDRINST usr/include/linux/apm_bios.h HDRINST usr/include/linux/fd.h HDRINST usr/include/linux/um_timetravel.h HDRINST usr/include/linux/tls.h HDRINST usr/include/linux/rpmsg_types.h HDRINST usr/include/linux/pfrut.h HDRINST usr/include/linux/mei.h HDRINST usr/include/linux/fsi.h HDRINST usr/include/linux/rds.h HDRINST usr/include/linux/if_x25.h HDRINST usr/include/linux/param.h HDRINST usr/include/linux/netdevice.h HDRINST usr/include/linux/binfmts.h HDRINST usr/include/linux/if_pppox.h HDRINST usr/include/linux/sockios.h HDRINST usr/include/linux/kcm.h HDRINST usr/include/linux/virtio_9p.h HDRINST usr/include/linux/genwqe/genwqe_card.h HDRINST usr/include/linux/if_tun.h HDRINST usr/include/linux/ext4.h HDRINST usr/include/linux/if_ether.h HDRINST usr/include/linux/kvm_para.h HDRINST usr/include/linux/kernel-page-flags.h HDRINST usr/include/linux/cdrom.h HDRINST usr/include/linux/un.h HDRINST usr/include/linux/module.h HDRINST usr/include/linux/mqueue.h HDRINST usr/include/linux/a.out.h HDRINST usr/include/linux/input-event-codes.h HDRINST usr/include/linux/coda.h HDRINST usr/include/linux/rio_mport_cdev.h HDRINST usr/include/linux/ipsec.h HDRINST usr/include/linux/blkpg.h HDRINST usr/include/linux/blkzoned.h HDRINST usr/include/linux/netfilter_bridge/ebt_arpreply.h HDRINST usr/include/linux/netfilter_bridge/ebt_redirect.h HDRINST usr/include/linux/netfilter_bridge/ebt_nflog.h HDRINST usr/include/linux/netfilter_bridge/ebt_802_3.h HDRINST usr/include/linux/netfilter_bridge/ebt_nat.h HDRINST usr/include/linux/netfilter_bridge/ebt_mark_m.h HDRINST usr/include/linux/netfilter_bridge/ebtables.h HDRINST usr/include/linux/netfilter_bridge/ebt_vlan.h HDRINST usr/include/linux/netfilter_bridge/ebt_limit.h HDRINST usr/include/linux/netfilter_bridge/ebt_log.h HDRINST usr/include/linux/netfilter_bridge/ebt_stp.h HDRINST usr/include/linux/netfilter_bridge/ebt_pkttype.h HDRINST usr/include/linux/netfilter_bridge/ebt_ip.h HDRINST usr/include/linux/netfilter_bridge/ebt_ip6.h HDRINST usr/include/linux/netfilter_bridge/ebt_arp.h HDRINST usr/include/linux/netfilter_bridge/ebt_mark_t.h HDRINST usr/include/linux/netfilter_bridge/ebt_among.h HDRINST usr/include/linux/reiserfs_fs.h HDRINST usr/include/linux/cciss_ioctl.h HDRINST usr/include/linux/fsmap.h HDRINST usr/include/linux/smiapp.h HDRINST usr/include/linux/switchtec_ioctl.h HDRINST usr/include/linux/atmdev.h HDRINST usr/include/linux/hpet.h HDRINST usr/include/linux/virtio_config.h HDRINST usr/include/linux/string.h HDRINST usr/include/linux/kfd_sysfs.h HDRINST usr/include/linux/inet_diag.h HDRINST usr/include/linux/netdev.h HDRINST usr/include/linux/xattr.h HDRINST usr/include/linux/iommufd.h HDRINST usr/include/linux/user_events.h HDRINST usr/include/linux/errno.h HDRINST usr/include/linux/icmp.h HDRINST usr/include/linux/i2o-dev.h HDRINST usr/include/linux/pg.h HDRINST usr/include/linux/thermal.h HDRINST usr/include/linux/if_bridge.h HDRINST usr/include/linux/uinput.h HDRINST usr/include/linux/handshake.h LD /kernel/build64/tools/objtool/libsubcmd/libsubcmd-in.o HDRINST usr/include/linux/dqblk_xfs.h HDRINST usr/include/linux/v4l2-common.h HDRINST usr/include/linux/nvram.h HDRINST usr/include/linux/if_vlan.h HDRINST usr/include/linux/uhid.h HDRINST usr/include/linux/omap3isp.h HDRINST usr/include/linux/rose.h HDRINST usr/include/linux/phantom.h HDRINST usr/include/linux/ipmi_msgdefs.h HDRINST usr/include/linux/bcm933xx_hcs.h HDRINST usr/include/linux/bpf.h HDRINST usr/include/linux/mempolicy.h HDRINST usr/include/linux/efs_fs_sb.h HDRINST usr/include/linux/nexthop.h HDRINST usr/include/linux/net_dropmon.h HDRINST usr/include/linux/surface_aggregator/cdev.h HDRINST usr/include/linux/surface_aggregator/dtx.h HDRINST usr/include/linux/net.h HDRINST usr/include/linux/mii.h HDRINST usr/include/linux/virtio_pcidev.h HDRINST usr/include/linux/termios.h HDRINST usr/include/linux/cgroupstats.h HDRINST usr/include/linux/mpls.h HDRINST usr/include/linux/iommu.h HDRINST usr/include/linux/toshiba.h HDRINST usr/include/linux/virtio_scsi.h HDRINST usr/include/linux/zorro.h HDRINST usr/include/linux/chio.h HDRINST usr/include/linux/pkt_sched.h HDRINST usr/include/linux/cramfs_fs.h HDRINST usr/include/linux/nfs3.h HDRINST usr/include/linux/vfio_ccw.h HDRINST usr/include/linux/atm_nicstar.h AR /kernel/build64/tools/objtool/libsubcmd/libsubcmd.a HDRINST usr/include/linux/ncsi.h HDRINST usr/include/linux/virtio_net.h HDRINST usr/include/linux/ioctl.h HDRINST usr/include/linux/stddef.h HDRINST usr/include/linux/limits.h HDRINST usr/include/linux/ipmi_bmc.h HDRINST usr/include/linux/netfilter_arp.h HDRINST usr/include/linux/if_addr.h HDRINST usr/include/linux/rpmsg.h HDRINST usr/include/linux/media-bus-format.h HDRINST usr/include/linux/kernelcapi.h HDRINST usr/include/linux/ppp_defs.h HDRINST usr/include/linux/ethtool.h HDRINST usr/include/linux/aspeed-video.h HDRINST usr/include/linux/hdlc.h HDRINST usr/include/linux/fscrypt.h HDRINST usr/include/linux/batadv_packet.h HDRINST usr/include/linux/uuid.h HDRINST usr/include/linux/capi.h HDRINST usr/include/linux/mptcp.h HDRINST usr/include/linux/hidraw.h HDRINST usr/include/linux/virtio_console.h HDRINST usr/include/linux/irqnr.h HDRINST usr/include/linux/coresight-stm.h HDRINST usr/include/linux/cxl_mem.h HDRINST usr/include/linux/iso_fs.h HDRINST usr/include/linux/virtio_blk.h HDRINST usr/include/linux/udf_fs_i.h HDRINST usr/include/linux/coff.h HDRINST usr/include/linux/dma-buf.h HDRINST usr/include/linux/ife.h HDRINST usr/include/linux/agpgart.h HDRINST usr/include/linux/socket.h HDRINST usr/include/linux/nilfs2_ondisk.h HDRINST usr/include/linux/connector.h HDRINST usr/include/linux/auto_fs4.h HDRINST usr/include/linux/bt-bmc.h HDRINST usr/include/linux/map_to_7segment.h HDRINST usr/include/linux/tc_act/tc_skbedit.h HDRINST usr/include/linux/tc_act/tc_ctinfo.h HDRINST usr/include/linux/tc_act/tc_defact.h HDRINST usr/include/linux/tc_act/tc_gact.h HDRINST usr/include/linux/tc_act/tc_vlan.h HDRINST usr/include/linux/tc_act/tc_skbmod.h HDRINST usr/include/linux/tc_act/tc_sample.h HDRINST usr/include/linux/tc_act/tc_tunnel_key.h HDRINST usr/include/linux/tc_act/tc_gate.h HDRINST usr/include/linux/tc_act/tc_mirred.h HDRINST usr/include/linux/tc_act/tc_nat.h HDRINST usr/include/linux/tc_act/tc_csum.h HDRINST usr/include/linux/tc_act/tc_connmark.h HDRINST usr/include/linux/tc_act/tc_ife.h HDRINST usr/include/linux/tc_act/tc_mpls.h HDRINST usr/include/linux/tc_act/tc_ct.h HDRINST usr/include/linux/tc_act/tc_pedit.h HDRINST usr/include/linux/tc_act/tc_bpf.h HDRINST usr/include/linux/tc_act/tc_ipt.h HDRINST usr/include/linux/netrom.h HDRINST usr/include/linux/joystick.h HDRINST usr/include/linux/falloc.h HDRINST usr/include/linux/cycx_cfm.h HDRINST usr/include/linux/omapfb.h HDRINST usr/include/linux/msdos_fs.h HDRINST usr/include/linux/virtio_types.h HDRINST usr/include/linux/mroute.h HDRINST usr/include/linux/psample.h HDRINST usr/include/linux/ipv6.h HDRINST usr/include/linux/dw100.h HDRINST usr/include/linux/psp-sev.h CC /kernel/build64/tools/objtool/weak.o HDRINST usr/include/linux/vfio.h CC /kernel/build64/tools/objtool/check.o MKDIR /kernel/build64/tools/objtool/arch/x86/ CC /kernel/build64/tools/objtool/special.o HDRINST usr/include/linux/if_ppp.h HDRINST usr/include/linux/byteorder/big_endian.h HDRINST usr/include/linux/byteorder/little_endian.h CC /kernel/build64/tools/objtool/builtin-check.o MKDIR /kernel/build64/tools/objtool/arch/x86/lib/ HDRINST usr/include/linux/comedi.h CC /kernel/build64/tools/objtool/arch/x86/special.o HDRINST usr/include/linux/scif_ioctl.h CC /kernel/build64/tools/objtool/elf.o CC /kernel/build64/tools/objtool/objtool.o HDRINST usr/include/linux/timerfd.h GEN /kernel/build64/tools/objtool/arch/x86/lib/inat-tables.c HDRINST usr/include/linux/time_types.h CC /kernel/build64/tools/objtool/orc_gen.o HDRINST usr/include/linux/firewire-constants.h HDRINST usr/include/linux/virtio_snd.h CC /kernel/build64/tools/objtool/orc_dump.o HDRINST usr/include/linux/ppp-ioctl.h HDRINST usr/include/linux/fib_rules.h HDRINST usr/include/linux/gen_stats.h CC /kernel/build64/tools/objtool/libstring.o CC /kernel/build64/tools/objtool/libctype.o HDRINST usr/include/linux/virtio_iommu.h CC /kernel/build64/tools/objtool/str_error_r.o HDRINST usr/include/linux/genetlink.h CC /kernel/build64/tools/objtool/librbtree.o HDRINST usr/include/linux/uvcvideo.h HDRINST usr/include/linux/pfkeyv2.h HDRINST usr/include/linux/soundcard.h HDRINST usr/include/linux/times.h HDRINST usr/include/linux/nfc.h HDRINST usr/include/linux/affs_hardblocks.h HDRINST usr/include/linux/nilfs2_api.h HDRINST usr/include/linux/rseq.h HDRINST usr/include/linux/caif/caif_socket.h HDRINST usr/include/linux/caif/if_caif.h HDRINST usr/include/linux/i2c-dev.h HDRINST usr/include/linux/cuda.h HDRINST usr/include/linux/mei_uuid.h HDRINST usr/include/linux/cn_proc.h HDRINST usr/include/linux/parport.h HDRINST usr/include/linux/v4l2-controls.h HDRINST usr/include/linux/hsi/cs-protocol.h HDRINST usr/include/linux/hsi/hsi_char.h HDRINST usr/include/linux/seg6_genl.h HDRINST usr/include/linux/am437x-vpfe.h HDRINST usr/include/linux/amt.h HDRINST usr/include/linux/netconf.h HDRINST usr/include/linux/erspan.h HDRINST usr/include/linux/nsfs.h HDRINST usr/include/linux/xilinx-v4l2-controls.h HDRINST usr/include/linux/aspeed-p2a-ctrl.h HDRINST usr/include/linux/vfio_zdev.h HDRINST usr/include/linux/serio.h HDRINST usr/include/linux/acrn.h HDRINST usr/include/linux/nfs2.h HDRINST usr/include/linux/virtio_pci.h HDRINST usr/include/linux/ipc.h HDRINST usr/include/linux/ethtool_netlink.h HDRINST usr/include/linux/kd.h HDRINST usr/include/linux/elf.h HDRINST usr/include/linux/videodev2.h HDRINST usr/include/linux/if_alg.h HDRINST usr/include/linux/sonypi.h HDRINST usr/include/linux/fsverity.h HDRINST usr/include/linux/if.h HDRINST usr/include/linux/btrfs.h HDRINST usr/include/linux/vm_sockets_diag.h HDRINST usr/include/linux/netfilter_bridge.h HDRINST usr/include/linux/packet_diag.h HDRINST usr/include/linux/netfilter_ipv4.h HDRINST usr/include/linux/kvm.h HDRINST usr/include/linux/pci.h HDRINST usr/include/linux/if_addrlabel.h HDRINST usr/include/linux/hdlcdrv.h HDRINST usr/include/linux/cfm_bridge.h HDRINST usr/include/linux/fiemap.h HDRINST usr/include/linux/dm-ioctl.h HDRINST usr/include/linux/aspeed-lpc-ctrl.h HDRINST usr/include/linux/atmioc.h HDRINST usr/include/linux/dlm.h HDRINST usr/include/linux/pci_regs.h HDRINST usr/include/linux/cachefiles.h HDRINST usr/include/linux/membarrier.h HDRINST usr/include/linux/nfs_idmap.h HDRINST usr/include/linux/ip.h HDRINST usr/include/linux/atm_he.h HDRINST usr/include/linux/nfsd/export.h HDRINST usr/include/linux/nfsd/stats.h HDRINST usr/include/linux/nfsd/debug.h HDRINST usr/include/linux/nfsd/cld.h HDRINST usr/include/linux/ip_vs.h HDRINST usr/include/linux/vmcore.h HDRINST usr/include/linux/vbox_vmmdev_types.h HDRINST usr/include/linux/dvb/osd.h HDRINST usr/include/linux/dvb/dmx.h HDRINST usr/include/linux/dvb/net.h HDRINST usr/include/linux/dvb/frontend.h HDRINST usr/include/linux/dvb/ca.h HDRINST usr/include/linux/dvb/version.h HDRINST usr/include/linux/dvb/video.h HDRINST usr/include/linux/dvb/audio.h HDRINST usr/include/linux/nfs.h HDRINST usr/include/linux/if_link.h CC /kernel/build64/tools/objtool/arch/x86/decode.o HDRINST usr/include/linux/wait.h HDRINST usr/include/linux/icmpv6.h HDRINST usr/include/linux/media.h HDRINST usr/include/linux/seg6_local.h HDRINST usr/include/linux/openvswitch.h HDRINST usr/include/linux/atmsap.h HDRINST usr/include/linux/bpfilter.h HDRINST usr/include/linux/fpga-dfl.h HDRINST usr/include/linux/userio.h HDRINST usr/include/linux/signal.h HDRINST usr/include/linux/map_to_14segment.h HDRINST usr/include/linux/hdreg.h HDRINST usr/include/linux/utime.h HDRINST usr/include/linux/usbdevice_fs.h HDRINST usr/include/linux/timex.h HDRINST usr/include/linux/if_fc.h HDRINST usr/include/linux/reiserfs_xattr.h HDRINST usr/include/linux/hw_breakpoint.h HDRINST usr/include/linux/quota.h HDRINST usr/include/linux/ioprio.h HDRINST usr/include/linux/eventpoll.h HDRINST usr/include/linux/atmclip.h HDRINST usr/include/linux/can.h HDRINST usr/include/linux/if_team.h HDRINST usr/include/linux/usbip.h HDRINST usr/include/linux/stat.h HDRINST usr/include/linux/fou.h HDRINST usr/include/linux/hash_info.h HDRINST usr/include/linux/ppp-comp.h HDRINST usr/include/linux/ip6_tunnel.h HDRINST usr/include/linux/tipc_netlink.h HDRINST usr/include/linux/in.h HDRINST usr/include/linux/wireguard.h HDRINST usr/include/linux/btf.h HDRINST usr/include/linux/batman_adv.h HDRINST usr/include/linux/fcntl.h HDRINST usr/include/linux/if_ltalk.h HDRINST usr/include/linux/i2c.h HDRINST usr/include/linux/atm_idt77105.h HDRINST usr/include/linux/kexec.h HDRINST usr/include/linux/arm_sdei.h HDRINST usr/include/linux/netfilter_ipv6/ip6_tables.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_ah.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_NPT.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_rt.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_REJECT.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_opts.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_srh.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_LOG.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_mh.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_HL.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_hl.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_frag.h HDRINST usr/include/linux/netfilter_ipv6/ip6t_ipv6header.h HDRINST usr/include/linux/minix_fs.h HDRINST usr/include/linux/aio_abi.h HDRINST usr/include/linux/pktcdvd.h HDRINST usr/include/linux/libc-compat.h HDRINST usr/include/linux/atmlec.h HDRINST usr/include/linux/signalfd.h HDRINST usr/include/linux/bpf_common.h HDRINST usr/include/linux/seg6_iptunnel.h HDRINST usr/include/linux/synclink.h HDRINST usr/include/linux/mpls_iptunnel.h HDRINST usr/include/linux/mctp.h HDRINST usr/include/linux/if_xdp.h HDRINST usr/include/linux/llc.h HDRINST usr/include/linux/atmsvc.h HDRINST usr/include/linux/sed-opal.h HDRINST usr/include/linux/sock_diag.h HDRINST usr/include/linux/time.h HDRINST usr/include/linux/securebits.h HDRINST usr/include/linux/fsl_hypervisor.h HDRINST usr/include/linux/if_hippi.h HDRINST usr/include/linux/seccomp.h HDRINST usr/include/linux/oom.h HDRINST usr/include/linux/filter.h HDRINST usr/include/linux/inotify.h HDRINST usr/include/linux/rfkill.h HDRINST usr/include/linux/reboot.h HDRINST usr/include/linux/can/vxcan.h HDRINST usr/include/linux/can/j1939.h HDRINST usr/include/linux/can/netlink.h HDRINST usr/include/linux/can/bcm.h HDRINST usr/include/linux/can/raw.h HDRINST usr/include/linux/can/gw.h HDRINST usr/include/linux/can/error.h HDRINST usr/include/linux/can/isotp.h HDRINST usr/include/linux/if_eql.h HDRINST usr/include/linux/hiddev.h HDRINST usr/include/linux/blktrace_api.h HDRINST usr/include/linux/ccs.h HDRINST usr/include/linux/ioam6.h HDRINST usr/include/linux/hsr_netlink.h HDRINST usr/include/linux/mmc/ioctl.h HDRINST usr/include/linux/bfs_fs.h HDRINST usr/include/linux/rio_cm_cdev.h HDRINST usr/include/linux/uleds.h HDRINST usr/include/linux/mrp_bridge.h HDRINST usr/include/linux/adb.h HDRINST usr/include/linux/pmu.h HDRINST usr/include/linux/udmabuf.h HDRINST usr/include/linux/kcmp.h HDRINST usr/include/linux/dma-heap.h HDRINST usr/include/linux/userfaultfd.h HDRINST usr/include/linux/netfilter_arp/arpt_mangle.h HDRINST usr/include/linux/netfilter_arp/arp_tables.h HDRINST usr/include/linux/tipc.h HDRINST usr/include/linux/virtio_ids.h HDRINST usr/include/linux/l2tp.h HDRINST usr/include/linux/devlink.h HDRINST usr/include/linux/virtio_gpio.h HDRINST usr/include/linux/dcbnl.h HDRINST usr/include/linux/cyclades.h HDRINST usr/include/sound/intel/avs/tokens.h HDRINST usr/include/sound/sof/fw.h HDRINST usr/include/sound/sof/abi.h HDRINST usr/include/sound/sof/tokens.h HDRINST usr/include/sound/sof/header.h HDRINST usr/include/sound/usb_stream.h HDRINST usr/include/sound/sfnt_info.h HDRINST usr/include/sound/tlv.h HDRINST usr/include/sound/asequencer.h HDRINST usr/include/sound/asound.h HDRINST usr/include/sound/sb16_csp.h HDRINST usr/include/sound/asoc.h HDRINST usr/include/sound/compress_offload.h HDRINST usr/include/sound/hdsp.h HDRINST usr/include/sound/emu10k1.h HDRINST usr/include/sound/snd_ar_tokens.h HDRINST usr/include/sound/snd_sst_tokens.h HDRINST usr/include/sound/asound_fm.h HDRINST usr/include/sound/hdspm.h HDRINST usr/include/sound/compress_params.h HDRINST usr/include/sound/firewire.h HDRINST usr/include/sound/skl-tplg-interface.h HDRINST usr/include/scsi/scsi_bsg_ufs.h HDRINST usr/include/scsi/scsi_netlink_fc.h HDRINST usr/include/scsi/scsi_bsg_mpi3mr.h HDRINST usr/include/scsi/fc/fc_ns.h HDRINST usr/include/scsi/fc/fc_fs.h HDRINST usr/include/scsi/fc/fc_els.h HDRINST usr/include/scsi/fc/fc_gs.h HDRINST usr/include/scsi/scsi_bsg_fc.h HDRINST usr/include/scsi/cxlflash_ioctl.h HDRINST usr/include/scsi/scsi_netlink.h HDRINST usr/include/linux/version.h HDRINST usr/include/asm/processor-flags.h HDRINST usr/include/asm/auxvec.h HDRINST usr/include/asm/svm.h HDRINST usr/include/asm/bitsperlong.h HDRINST usr/include/asm/kvm_perf.h HDRINST usr/include/asm/mce.h HDRINST usr/include/asm/posix_types.h HDRINST usr/include/asm/msr.h HDRINST usr/include/asm/sigcontext32.h HDRINST usr/include/asm/mman.h HDRINST usr/include/asm/shmbuf.h HDRINST usr/include/asm/e820.h HDRINST usr/include/asm/posix_types_64.h HDRINST usr/include/asm/vsyscall.h HDRINST usr/include/asm/msgbuf.h HDRINST usr/include/asm/swab.h HDRINST usr/include/asm/statfs.h HDRINST usr/include/asm/posix_types_x32.h HDRINST usr/include/asm/ptrace.h HDRINST usr/include/asm/unistd.h HDRINST usr/include/asm/ist.h HDRINST usr/include/asm/prctl.h HDRINST usr/include/asm/boot.h HDRINST usr/include/asm/sigcontext.h HDRINST usr/include/asm/posix_types_32.h HDRINST usr/include/asm/kvm_para.h HDRINST usr/include/asm/a.out.h HDRINST usr/include/asm/mtrr.h HDRINST usr/include/asm/amd_hsmp.h HDRINST usr/include/asm/hwcap2.h HDRINST usr/include/asm/ptrace-abi.h HDRINST usr/include/asm/vm86.h HDRINST usr/include/asm/vmx.h HDRINST usr/include/asm/ldt.h HDRINST usr/include/asm/perf_regs.h HDRINST usr/include/asm/kvm.h HDRINST usr/include/asm/debugreg.h HDRINST usr/include/asm/signal.h HDRINST usr/include/asm/bootparam.h HDRINST usr/include/asm/siginfo.h HDRINST usr/include/asm/hw_breakpoint.h HDRINST usr/include/asm/stat.h HDRINST usr/include/asm/setup.h HDRINST usr/include/asm/sembuf.h HDRINST usr/include/asm/sgx.h HDRINST usr/include/asm/ucontext.h HDRINST usr/include/asm/byteorder.h HDRINST usr/include/asm/unistd_64.h HDRINST usr/include/asm/ioctls.h HDRINST usr/include/asm/bpf_perf_event.h HDRINST usr/include/asm/types.h HDRINST usr/include/asm/poll.h HDRINST usr/include/asm/resource.h HDRINST usr/include/asm/param.h HDRINST usr/include/asm/sockios.h HDRINST usr/include/asm/errno.h HDRINST usr/include/asm/unistd_x32.h HDRINST usr/include/asm/termios.h HDRINST usr/include/asm/ioctl.h HDRINST usr/include/asm/socket.h HDRINST usr/include/asm/unistd_32.h HDRINST usr/include/asm/termbits.h HDRINST usr/include/asm/fcntl.h HDRINST usr/include/asm/ipcbuf.h HOSTLD scripts/mod/modpost CC kernel/bounds.s CHKSHA1 ../include/linux/atomic/atomic-arch-fallback.h CHKSHA1 ../include/linux/atomic/atomic-instrumented.h CHKSHA1 ../include/linux/atomic/atomic-long.h UPD include/generated/timeconst.h UPD include/generated/bounds.h CC arch/x86/kernel/asm-offsets.s LD /kernel/build64/tools/objtool/arch/x86/objtool-in.o UPD include/generated/asm-offsets.h CALL ../scripts/checksyscalls.sh LD /kernel/build64/tools/objtool/objtool-in.o LINK /kernel/build64/tools/objtool/objtool LDS scripts/module.lds CC ipc/compat.o CC ipc/util.o CC ipc/msgutil.o CC ipc/msg.o CC ipc/sem.o CC ipc/shm.o HOSTCC usr/gen_init_cpio CC init/main.o AR certs/built-in.a CC ipc/syscall.o CC init/do_mounts.o CC ipc/ipc_sysctl.o CC init/do_mounts_initrd.o CC init/initramfs.o CC ipc/mqueue.o AS arch/x86/lib/clear_page_64.o CC init/calibrate.o CC mm/filemap.o CC ipc/namespace.o CC arch/x86/lib/cmdline.o CC mm/mempool.o UPD init/utsversion-tmp.h CC security/commoncap.o CC io_uring/io_uring.o CC init/init_task.o CC ipc/mq_sysctl.o CC arch/x86/pci/i386.o AR arch/x86/video/built-in.a CC arch/x86/power/cpu.o CC arch/x86/realmode/init.o AR virt/lib/built-in.a CC [M] arch/x86/video/fbdev.o CC block/partitions/core.o CC net/core/sock.o CC security/keys/gc.o AR drivers/irqchip/built-in.a AS arch/x86/crypto/aesni-intel_asm.o AR sound/i2c/other/built-in.a CC arch/x86/mm/pat/set_memory.o CC arch/x86/events/amd/core.o CC sound/core/seq/seq.o CC arch/x86/crypto/aesni-intel_glue.o CC fs/notify/dnotify/dnotify.o AR sound/isa/ad1816a/built-in.a AR sound/drivers/opl3/built-in.a CC [M] virt/lib/irqbypass.o CC arch/x86/kernel/fpu/init.o AR drivers/bus/mhi/built-in.a AR sound/i2c/built-in.a AR sound/isa/ad1848/built-in.a AR sound/drivers/opl4/built-in.a AR drivers/bus/built-in.a CC security/keys/key.o AR sound/isa/cs423x/built-in.a CC arch/x86/entry/vdso/vma.o CC net/llc/llc_core.o CC lib/kunit/test.o CC mm/kasan/common.o AR sound/drivers/mpu401/built-in.a CC kernel/sched/core.o AR sound/isa/es1688/built-in.a AR sound/drivers/vx/built-in.a AR drivers/phy/allwinner/built-in.a CC arch/x86/power/hibernate_64.o AR sound/isa/galaxy/built-in.a CC crypto/api.o AR drivers/phy/amlogic/built-in.a AR sound/drivers/pcsp/built-in.a AR sound/isa/gus/built-in.a AR sound/drivers/built-in.a AR drivers/phy/broadcom/built-in.a CC crypto/cipher.o AR sound/isa/msnd/built-in.a AR drivers/phy/cadence/built-in.a AR sound/isa/opti9xx/built-in.a AR drivers/phy/freescale/built-in.a AR sound/isa/sb/built-in.a AR drivers/phy/hisilicon/built-in.a AS arch/x86/lib/cmpxchg16b_emu.o AR sound/isa/wavefront/built-in.a AR drivers/phy/ingenic/built-in.a AR sound/isa/wss/built-in.a AR drivers/phy/intel/built-in.a CC arch/x86/lib/copy_mc.o AR sound/isa/built-in.a AR drivers/phy/lantiq/built-in.a AR drivers/phy/marvell/built-in.a CC crypto/compress.o AR drivers/phy/mediatek/built-in.a AR drivers/phy/microchip/built-in.a AR drivers/phy/motorola/built-in.a AR drivers/phy/mscc/built-in.a AR drivers/phy/qualcomm/built-in.a AR drivers/phy/ralink/built-in.a GEN usr/initramfs_data.cpio AR drivers/phy/renesas/built-in.a COPY usr/initramfs_inc_data AR drivers/phy/rockchip/built-in.a AS usr/initramfs_data.o AR drivers/phy/samsung/built-in.a AR drivers/phy/socionext/built-in.a AR usr/built-in.a CC sound/core/seq/seq_lock.o CC arch/x86/kernel/fpu/bugs.o AR drivers/phy/st/built-in.a AR drivers/phy/sunplus/built-in.a AR drivers/phy/tegra/built-in.a AR drivers/phy/ti/built-in.a AR drivers/phy/xilinx/built-in.a CC drivers/phy/phy-core.o CC block/partitions/ldm.o CC sound/core/sound.o AR virt/built-in.a CC io_uring/xattr.o AS arch/x86/lib/copy_mc_64.o CC arch/x86/kernel/fpu/core.o AS arch/x86/lib/copy_page_64.o CC net/llc/llc_input.o CC net/core/request_sock.o AS arch/x86/lib/copy_user_64.o AS arch/x86/realmode/rm/header.o AS arch/x86/realmode/rm/trampoline_64.o CC arch/x86/events/amd/lbr.o CC arch/x86/events/amd/ibs.o AS arch/x86/lib/copy_user_uncached_64.o CC arch/x86/lib/cpu.o AS arch/x86/realmode/rm/stack.o CC lib/math/div64.o CC kernel/locking/mutex.o CC crypto/algapi.o AS arch/x86/realmode/rm/reboot.o CC arch/x86/events/intel/core.o CC lib/crypto/memneq.o CC kernel/power/qos.o CC kernel/printk/printk.o AS arch/x86/realmode/rm/wakeup_asm.o AR fs/notify/dnotify/built-in.a CC lib/math/gcd.o CC fs/notify/inotify/inotify_fsnotify.o CC arch/x86/realmode/rm/wakemain.o CC sound/core/seq/seq_clientmgr.o CC fs/notify/inotify/inotify_user.o CC kernel/power/main.o CC arch/x86/pci/init.o CC lib/math/lcm.o CC lib/kunit/resource.o CC arch/x86/realmode/rm/video-mode.o CC mm/kasan/report.o CC mm/kasan/init.o CC lib/math/int_pow.o CC lib/crypto/utils.o AS arch/x86/power/hibernate_asm_64.o CC arch/x86/entry/vdso/extable.o CC arch/x86/events/intel/bts.o CC arch/x86/events/intel/ds.o CC arch/x86/power/hibernate.o CC lib/math/int_sqrt.o CC arch/x86/events/zhaoxin/core.o AS arch/x86/realmode/rm/copy.o AS arch/x86/realmode/rm/bioscall.o CC lib/math/reciprocal_div.o CC arch/x86/realmode/rm/regs.o AS arch/x86/crypto/aesni-intel_avx-x86_64.o CC arch/x86/lib/delay.o CC security/keys/keyring.o CC arch/x86/realmode/rm/video-vga.o CC arch/x86/entry/vdso/vdso32-setup.o CC lib/math/rational.o CC arch/x86/pci/mmconfig_64.o CC mm/oom_kill.o CC arch/x86/realmode/rm/video-vesa.o CC arch/x86/events/core.o CC security/min_addr.o CC kernel/printk/printk_safe.o CC arch/x86/realmode/rm/video-bios.o CC lib/crypto/chacha.o CC mm/fadvise.o CC lib/kunit/static_stub.o CC lib/kunit/string-stream.o AS arch/x86/crypto/aes_ctrby8_avx-x86_64.o LDS arch/x86/entry/vdso/vdso.lds CC io_uring/nop.o CC kernel/locking/semaphore.o AS arch/x86/lib/getuser.o PASYMS arch/x86/realmode/rm/pasyms.h LDS arch/x86/realmode/rm/realmode.lds LD arch/x86/realmode/rm/realmode.elf GEN arch/x86/lib/inat-tables.c RELOCS arch/x86/realmode/rm/realmode.relocs OBJCOPY arch/x86/realmode/rm/realmode.bin AS arch/x86/realmode/rmpiggy.o CC net/llc/llc_output.o CC arch/x86/pci/direct.o AS [M] arch/x86/crypto/ghash-clmulni-intel_asm.o CC arch/x86/events/amd/uncore.o CC lib/crypto/aes.o AR arch/x86/realmode/built-in.a AR drivers/phy/built-in.a CC block/bdev.o CC arch/x86/lib/insn-eval.o CC [M] arch/x86/crypto/ghash-clmulni-intel_glue.o AR drivers/pinctrl/actions/built-in.a AR drivers/pinctrl/bcm/built-in.a AR drivers/pinctrl/cirrus/built-in.a CC [M] lib/math/prime_numbers.o AR drivers/pinctrl/freescale/built-in.a CC drivers/pinctrl/intel/pinctrl-baytrail.o CC block/fops.o CC kernel/locking/rwsem.o CC init/version.o AS arch/x86/entry/vdso/vdso-note.o CC arch/x86/entry/vdso/vclock_gettime.o CC arch/x86/mm/pat/memtype.o AR arch/x86/power/built-in.a CC block/bio.o CC arch/x86/entry/vdso/vgetcpu.o CC block/partitions/msdos.o CC kernel/printk/printk_ringbuffer.o CC mm/kasan/generic.o CC arch/x86/events/intel/knc.o AS [M] arch/x86/crypto/crc32-pclmul_asm.o AR arch/x86/events/zhaoxin/built-in.a CC arch/x86/mm/pat/memtype_interval.o CC drivers/gpio/gpiolib.o CC drivers/gpio/gpiolib-devres.o CC kernel/power/console.o CC drivers/gpio/gpiolib-legacy.o CC lib/kunit/assert.o CC drivers/gpio/gpiolib-cdev.o CC kernel/power/process.o AR init/built-in.a AR fs/notify/inotify/built-in.a CC kernel/power/suspend.o CC [M] arch/x86/crypto/crc32-pclmul_glue.o CC fs/notify/fanotify/fanotify.o CC arch/x86/kernel/fpu/regset.o CC fs/notify/fanotify/fanotify_user.o CC crypto/scatterwalk.o CC arch/x86/pci/mmconfig-shared.o CC kernel/locking/percpu-rwsem.o CC lib/kunit/try-catch.o CC fs/notify/fsnotify.o AR lib/math/built-in.a CC fs/notify/notification.o AR drivers/pinctrl/mediatek/built-in.a CC lib/crypto/gf128mul.o AR drivers/pinctrl/mvebu/built-in.a CC sound/core/init.o HOSTCC arch/x86/entry/vdso/vdso2c AR net/llc/built-in.a CC arch/x86/events/intel/lbr.o AR ipc/built-in.a CC arch/x86/events/intel/p4.o CC sound/core/seq/seq_memory.o CC security/keys/keyctl.o AS [M] arch/x86/crypto/crct10dif-pcl-asm_64.o CC fs/notify/group.o CC [M] arch/x86/crypto/crct10dif-pclmul_glue.o CC net/core/skbuff.o CC net/ethernet/eth.o AR arch/x86/events/amd/built-in.a CC net/802/p8022.o CC net/sched/sch_generic.o CC arch/x86/lib/insn.o CC net/802/psnap.o CC net/sched/sch_mq.o CC lib/kunit/executor.o LD [M] arch/x86/crypto/ghash-clmulni-intel.o LDS arch/x86/entry/vdso/vdso32/vdso32.lds AS arch/x86/entry/vdso/vdso32/note.o LD [M] arch/x86/crypto/crc32-pclmul.o CC net/core/datagram.o CC security/inode.o CC drivers/gpio/gpiolib-sysfs.o AR arch/x86/mm/pat/built-in.a AS arch/x86/entry/vdso/vdso32/system_call.o CC arch/x86/mm/init.o CC block/partitions/efi.o CC drivers/pinctrl/intel/pinctrl-intel.o AS arch/x86/entry/vdso/vdso32/sigreturn.o CC mm/kasan/report_generic.o CC arch/x86/kernel/fpu/signal.o CC crypto/proc.o CC arch/x86/entry/vdso/vdso32/vclock_gettime.o CC security/device_cgroup.o CC arch/x86/pci/fixup.o CC net/sched/sch_frag.o CC kernel/printk/sysctl.o AS arch/x86/lib/memcpy_64.o CC kernel/locking/irqflag-debug.o CC lib/crypto/blake2s.o AR arch/x86/crypto/built-in.a LD [M] arch/x86/crypto/crct10dif-pclmul.o AS arch/x86/lib/memmove_64.o CC arch/x86/entry/vdso/vdso32/vgetcpu.o AS arch/x86/lib/memset_64.o CC arch/x86/lib/misc.o AR sound/pci/ac97/built-in.a AR sound/pci/ali5451/built-in.a CC arch/x86/lib/pc-conf-reg.o CC net/core/stream.o AR sound/pci/asihpi/built-in.a CC net/core/scm.o AR sound/pci/au88x0/built-in.a CC kernel/irq/irqdesc.o AR sound/pci/aw2/built-in.a AR sound/pci/ctxfi/built-in.a CC kernel/irq/handle.o CC kernel/power/hibernate.o CC fs/notify/mark.o AR sound/pci/ca0106/built-in.a CC kernel/locking/mutex-debug.o AR sound/pci/cs46xx/built-in.a AR sound/pci/cs5535audio/built-in.a AR sound/pci/lola/built-in.a AR sound/pci/lx6464es/built-in.a AR sound/pci/echoaudio/built-in.a CC lib/kunit/hooks.o AR sound/pci/emu10k1/built-in.a AR kernel/printk/built-in.a AR sound/pci/hda/built-in.a CC kernel/irq/manage.o CC [M] sound/pci/hda/hda_bind.o AS arch/x86/lib/putuser.o CC kernel/power/snapshot.o CC sound/core/seq/seq_queue.o CC net/netlink/af_netlink.o AR drivers/pinctrl/nomadik/built-in.a AS arch/x86/lib/retpoline.o CC [M] sound/pci/hda/hda_codec.o CC arch/x86/lib/usercopy.o CC [M] sound/pci/hda/hda_jack.o CC crypto/aead.o CC lib/crypto/blake2s-generic.o CC net/802/stp.o AR net/bpf/built-in.a CC security/keys/permission.o VDSO arch/x86/entry/vdso/vdso64.so.dbg AR sound/pci/ice1712/built-in.a CC arch/x86/events/probe.o CC drivers/gpio/gpiolib-acpi.o AR lib/kunit/built-in.a CC arch/x86/events/utils.o CC arch/x86/events/rapl.o AR fs/notify/fanotify/built-in.a VDSO arch/x86/entry/vdso/vdso32.so.dbg CC kernel/irq/spurious.o OBJCOPY arch/x86/entry/vdso/vdso64.so OBJCOPY arch/x86/entry/vdso/vdso32.so VDSO2C arch/x86/entry/vdso/vdso-image-64.c VDSO2C arch/x86/entry/vdso/vdso-image-32.c CC arch/x86/entry/vdso/vdso-image-64.o CC mm/kasan/shadow.o CC arch/x86/events/intel/p6.o CC arch/x86/events/msr.o CC arch/x86/lib/usercopy_64.o CC arch/x86/lib/msr-smp.o AR block/partitions/built-in.a CC kernel/irq/resend.o CC block/elevator.o CC drivers/gpio/gpiolib-swnode.o CC arch/x86/kernel/fpu/xstate.o CC kernel/irq/chip.o CC sound/core/seq/seq_fifo.o CC arch/x86/pci/acpi.o CC arch/x86/pci/legacy.o CC sound/core/memory.o CC kernel/locking/lockdep.o CC arch/x86/mm/init_64.o CC arch/x86/entry/vdso/vdso-image-32.o AR net/ethernet/built-in.a CC mm/kasan/quarantine.o CC lib/crypto/blake2s-selftest.o CC arch/x86/pci/irq.o CC kernel/irq/dummychip.o CC kernel/locking/lockdep_proc.o CC kernel/power/swap.o AR arch/x86/entry/vdso/built-in.a CC arch/x86/entry/vsyscall/vsyscall_64.o AS arch/x86/entry/entry.o CC security/keys/process_keys.o CC kernel/power/user.o CC [M] sound/pci/hda/hda_auto_parser.o CC block/blk-core.o CC [M] drivers/pinctrl/intel/pinctrl-cherryview.o CC lib/crypto/des.o CC security/keys/request_key.o CC fs/notify/fdinfo.o CC crypto/geniv.o AS arch/x86/entry/entry_64.o CC net/core/gen_stats.o CC arch/x86/entry/syscall_64.o AR net/802/built-in.a CC kernel/rcu/update.o CC net/ethtool/ioctl.o CC kernel/rcu/sync.o CC arch/x86/lib/cache-smp.o CC kernel/rcu/srcutree.o CC arch/x86/entry/common.o CC arch/x86/lib/msr.o AS arch/x86/entry/thunk_64.o CC sound/core/control.o CC arch/x86/events/intel/pt.o AR kernel/livepatch/built-in.a AS arch/x86/entry/vsyscall/vsyscall_emu_64.o CC crypto/skcipher.o CC sound/core/seq/seq_prioq.o CC kernel/dma/mapping.o CC arch/x86/mm/fault.o CC kernel/entry/common.o CC [M] sound/pci/hda/hda_sysfs.o AR arch/x86/ia32/built-in.a CC kernel/locking/spinlock.o CC arch/x86/pci/common.o CC kernel/entry/syscall_user_dispatch.o CC kernel/dma/direct.o CC kernel/power/poweroff.o AR mm/kasan/built-in.a CC mm/maccess.o CC mm/page-writeback.o CC [M] drivers/pinctrl/intel/pinctrl-broxton.o CC net/sched/sch_api.o AR fs/notify/built-in.a AR drivers/gpio/built-in.a CC net/sched/sch_blackhole.o CC kernel/irq/devres.o CC fs/nfs_common/grace.o CC kernel/irq/autoprobe.o CC arch/x86/mm/ioremap.o CC sound/core/seq/seq_timer.o CC block/blk-sysfs.o CC security/keys/request_key_auth.o AR arch/x86/entry/vsyscall/built-in.a CC sound/core/misc.o CC sound/core/seq/seq_system.o AS arch/x86/entry/entry_64_compat.o CC arch/x86/entry/syscall_32.o CC [M] sound/pci/hda/hda_controller.o AR arch/x86/kernel/fpu/built-in.a CC arch/x86/kernel/cpu/mce/core.o CC arch/x86/kernel/cpu/mtrr/mtrr.o CC kernel/rcu/tree.o CC arch/x86/kernel/cpu/mtrr/if.o AS arch/x86/lib/msr-reg.o CC arch/x86/lib/msr-reg-export.o CC arch/x86/kernel/cpu/cacheinfo.o CC io_uring/fs.o CC arch/x86/pci/early.o CC arch/x86/kernel/cpu/mce/severity.o CC lib/crypto/sha1.o CC arch/x86/pci/bus_numa.o AS arch/x86/lib/hweight.o CC arch/x86/kernel/cpu/scattered.o CC net/netlink/genetlink.o CC arch/x86/lib/iomem.o CC arch/x86/kernel/cpu/topology.o CC sound/core/device.o CC [M] drivers/pinctrl/intel/pinctrl-geminilake.o CC kernel/entry/kvm.o AR kernel/power/built-in.a CC net/ethtool/common.o CC kernel/irq/irqdomain.o CC [M] sound/pci/hda/hda_proc.o CC arch/x86/pci/amd_bus.o CC mm/folio-compat.o CC kernel/dma/ops_helpers.o CC net/core/gen_estimator.o CC kernel/locking/osq_lock.o AR fs/nfs_common/built-in.a CC crypto/seqiv.o CC fs/iomap/trace.o CC fs/iomap/iter.o CC security/keys/user_defined.o CC sound/core/seq/seq_ports.o CC lib/crypto/sha256.o CC fs/iomap/buffered-io.o AR arch/x86/entry/built-in.a AS arch/x86/lib/iomap_copy_64.o CC [M] sound/pci/hda/hda_hwdep.o CC security/keys/compat.o CC fs/iomap/direct-io.o CC arch/x86/events/intel/uncore.o CC arch/x86/lib/inat.o CC fs/iomap/fiemap.o CC arch/x86/mm/extable.o CC kernel/rcu/rcu_segcblist.o CC kernel/module/main.o CC arch/x86/kernel/cpu/mtrr/generic.o CC security/keys/proc.o AR arch/x86/lib/built-in.a CC [M] drivers/pinctrl/intel/pinctrl-sunrisepoint.o AR arch/x86/lib/lib.a CC kernel/locking/qspinlock.o CC kernel/locking/rtmutex_api.o CC kernel/sched/fair.o CC security/keys/sysctl.o CC net/ethtool/netlink.o CC arch/x86/kernel/cpu/mtrr/cleanup.o CC sound/core/info.o CC io_uring/splice.o CC sound/core/isadma.o CC kernel/dma/dummy.o AR kernel/entry/built-in.a CC arch/x86/kernel/cpu/common.o AR arch/x86/pci/built-in.a CC arch/x86/kernel/cpu/rdrand.o CC crypto/echainiv.o CC [M] lib/crypto/arc4.o CC block/blk-flush.o CC arch/x86/kernel/cpu/match.o CC mm/readahead.o CC kernel/dma/contiguous.o CC kernel/time/time.o CC [M] sound/pci/hda/hda_generic.o AR fs/quota/built-in.a CC kernel/futex/core.o CC kernel/futex/syscalls.o CC fs/iomap/seek.o CC fs/kernfs/mount.o CC fs/sysfs/file.o AR drivers/pinctrl/intel/built-in.a AR drivers/pinctrl/nuvoton/built-in.a AR drivers/pinctrl/nxp/built-in.a CC net/ethtool/bitset.o CC fs/kernfs/inode.o AR drivers/pinctrl/sprd/built-in.a CC fs/kernfs/dir.o CC fs/proc/task_mmu.o CC sound/core/seq/seq_info.o AR drivers/pinctrl/sunplus/built-in.a AR drivers/pinctrl/ti/built-in.a CC drivers/pinctrl/core.o CC fs/sysfs/dir.o AR security/keys/built-in.a AR security/built-in.a CC net/sched/sch_fifo.o CC kernel/cgroup/cgroup.o CC arch/x86/mm/mmap.o CC kernel/trace/trace_clock.o CC kernel/irq/proc.o AR lib/crypto/built-in.a LD [M] lib/crypto/libarc4.o CC kernel/trace/ftrace.o CC lib/zlib_inflate/inffast.o CC kernel/module/strict_rwx.o CC lib/zlib_inflate/inflate.o CC kernel/trace/ring_buffer.o CC kernel/trace/trace.o CC kernel/irq/migration.o CC io_uring/sync.o CC arch/x86/events/intel/uncore_nhmex.o CC arch/x86/kernel/cpu/mce/genpool.o CC crypto/ahash.o CC kernel/trace/trace_output.o CC kernel/trace/trace_seq.o AR arch/x86/kernel/cpu/mtrr/built-in.a CC fs/sysfs/symlink.o CC net/netlink/policy.o CC kernel/dma/swiotlb.o CC arch/x86/events/intel/uncore_snb.o CC arch/x86/events/intel/uncore_snbep.o CC drivers/pinctrl/pinctrl-utils.o AR sound/core/seq/built-in.a CC fs/iomap/swapfile.o CC sound/core/vmaster.o CC kernel/sched/build_policy.o CC kernel/dma/remap.o CC block/blk-settings.o AR arch/x86/platform/atom/built-in.a AR arch/x86/net/built-in.a AR arch/x86/platform/ce4100/built-in.a CC fs/sysfs/mount.o CC arch/x86/mm/pgtable.o CC arch/x86/mm/physaddr.o CC arch/x86/platform/efi/memmap.o CC net/ethtool/strset.o CC arch/x86/platform/efi/quirks.o CC arch/x86/events/intel/uncore_discovery.o CC mm/swap.o CC kernel/irq/cpuhotplug.o CC kernel/futex/pi.o CC kernel/time/timer.o CC arch/x86/platform/efi/efi.o CC net/ethtool/linkinfo.o CC arch/x86/kernel/cpu/mce/intel.o CC lib/zlib_inflate/infutil.o CC kernel/trace/trace_stat.o CC lib/zlib_inflate/inftrees.o AR net/sched/built-in.a CC kernel/irq/pm.o CC mm/truncate.o CC io_uring/advise.o CC arch/x86/kernel/cpu/bugs.o CC fs/kernfs/file.o CC arch/x86/kernel/cpu/aperfmperf.o CC arch/x86/events/intel/cstate.o CC lib/zlib_inflate/inflate_syms.o CC sound/core/ctljack.o CC arch/x86/kernel/cpu/mce/threshold.o AR fs/iomap/built-in.a CC net/netlink/diag.o CC fs/sysfs/group.o CC net/core/net_namespace.o CC kernel/locking/spinlock_debug.o CC net/core/secure_seq.o CC crypto/shash.o CC net/core/flow_dissector.o CC drivers/pinctrl/pinmux.o CC kernel/futex/requeue.o AR arch/x86/platform/geode/built-in.a AR arch/x86/platform/iris/built-in.a CC kernel/futex/waitwake.o CC net/ethtool/linkmodes.o CC net/ethtool/rss.o CC net/ethtool/linkstate.o CC block/blk-ioc.o CC kernel/time/hrtimer.o AR sound/ppc/built-in.a AR lib/zlib_inflate/built-in.a CC kernel/module/kmod.o CC arch/x86/platform/efi/efi_64.o CC lib/zlib_deflate/deflate.o CC sound/core/jack.o CC arch/x86/mm/tlb.o CC lib/zlib_deflate/deftree.o AR kernel/dma/built-in.a CC drivers/pinctrl/pinconf.o CC arch/x86/mm/cpu_entry_area.o CC kernel/module/tree_lookup.o CC fs/proc/inode.o CC block/blk-map.o CC kernel/locking/qrwlock.o CC lib/lzo/lzo1x_compress.o CC io_uring/filetable.o CC kernel/irq/msi.o CC lib/lzo/lzo1x_decompress_safe.o CC kernel/bpf/core.o CC fs/configfs/inode.o AR fs/sysfs/built-in.a CC net/ethtool/debug.o CC fs/configfs/file.o CC mm/vmscan.o CC arch/x86/kernel/cpu/mce/apei.o AR kernel/futex/built-in.a CC crypto/akcipher.o CC fs/kernfs/symlink.o CC drivers/pinctrl/pinconf-generic.o CC mm/shmem.o AR net/netlink/built-in.a AR kernel/locking/built-in.a CC kernel/trace/trace_printk.o CC net/netfilter/core.o CC [M] net/netfilter/ipvs/ip_vs_conn.o AR net/ipv4/netfilter/built-in.a CC sound/core/timer.o CC [M] net/ipv4/netfilter/nf_defrag_ipv4.o CC [M] net/ipv4/netfilter/nf_reject_ipv4.o CC kernel/module/debug_kmemleak.o CC kernel/module/kallsyms.o CC [M] net/netfilter/ipvs/ip_vs_core.o CC [M] net/netfilter/ipvs/ip_vs_ctl.o AR lib/lzo/built-in.a CC [M] net/netfilter/ipvs/ip_vs_sched.o CC [M] net/netfilter/ipvs/ip_vs_xmit.o AS arch/x86/platform/efi/efi_stub_64.o CC [M] net/netfilter/ipvs/ip_vs_app.o CC [M] net/netfilter/ipvs/ip_vs_sync.o AR arch/x86/platform/efi/built-in.a CC arch/x86/platform/intel/iosf_mbi.o CC [M] net/netfilter/ipvs/ip_vs_est.o CC net/core/sysctl_net_core.o CC lib/zlib_deflate/deflate_syms.o CC arch/x86/kernel/cpu/cpuid-deps.o CC fs/proc/root.o CC kernel/module/procfs.o AR arch/x86/kernel/cpu/mce/built-in.a CC fs/configfs/dir.o CC crypto/kpp.o CC arch/x86/mm/maccess.o AR drivers/pinctrl/built-in.a AR drivers/pwm/built-in.a AR fs/kernfs/built-in.a CC kernel/cgroup/rstat.o CC drivers/pci/msi/pcidev_msi.o AR arch/x86/events/intel/built-in.a AR arch/x86/events/built-in.a CC block/blk-merge.o CC drivers/pci/msi/api.o CC drivers/pci/pcie/portdrv.o CC drivers/pci/hotplug/pci_hotplug_core.o CC fs/devpts/inode.o CC net/ethtool/wol.o CC drivers/pci/hotplug/acpi_pcihp.o CC drivers/pci/hotplug/pciehp_core.o CC io_uring/openclose.o AR lib/zlib_deflate/built-in.a CC lib/lz4/lz4_compress.o CC io_uring/uring_cmd.o CC arch/x86/kernel/cpu/umwait.o CC arch/x86/mm/pgprot.o CC kernel/time/timekeeping.o CC arch/x86/mm/hugetlbpage.o CC kernel/irq/affinity.o AR arch/x86/platform/intel/built-in.a AR arch/x86/platform/intel-mid/built-in.a AR arch/x86/platform/intel-quark/built-in.a AR kernel/rcu/built-in.a AR arch/x86/platform/olpc/built-in.a CC kernel/module/sysfs.o AR arch/x86/platform/scx200/built-in.a CC kernel/events/core.o AR arch/x86/platform/ts5500/built-in.a CC kernel/events/ring_buffer.o AR arch/x86/platform/uv/built-in.a AR arch/x86/platform/built-in.a CC kernel/fork.o CC fs/proc/base.o CC io_uring/epoll.o CC kernel/events/callchain.o CC crypto/acompress.o CC arch/x86/kernel/cpu/proc.o CC [M] net/netfilter/ipvs/ip_vs_proto.o CC kernel/time/ntp.o CC drivers/pci/msi/msi.o CC kernel/irq/matrix.o CC drivers/pci/pcie/rcec.o CC kernel/time/clocksource.o CC kernel/time/jiffies.o CC drivers/pci/msi/irqdomain.o AR fs/devpts/built-in.a CC net/core/dev.o CC drivers/pci/hotplug/pciehp_ctrl.o CC [M] net/ipv4/netfilter/ip_tables.o CC [M] net/netfilter/ipvs/ip_vs_pe.o CC net/core/dev_addr_lists.o CC [M] sound/pci/hda/patch_realtek.o CC block/blk-timeout.o CC arch/x86/mm/kasan_init_64.o CC sound/core/hrtimer.o CC net/ethtool/features.o CC sound/core/seq_device.o CC fs/configfs/symlink.o AR kernel/module/built-in.a CC kernel/exec_domain.o CC [M] sound/core/control_led.o CC net/ethtool/privflags.o CC net/core/dst.o CC kernel/time/timer_list.o MKCAP arch/x86/kernel/cpu/capflags.c CC crypto/scompress.o CC net/netfilter/nf_log.o CC kernel/events/hw_breakpoint.o CC io_uring/statx.o CC kernel/events/uprobes.o CC net/netfilter/nf_queue.o CC [M] net/netfilter/ipvs/ip_vs_proto_tcp.o CC net/ethtool/rings.o CC kernel/trace/pid_list.o CC drivers/pci/pcie/aspm.o CC kernel/trace/trace_sched_switch.o CC [M] sound/pci/hda/patch_analog.o CC kernel/cgroup/namespace.o CC block/blk-lib.o CC fs/proc/generic.o CC net/ipv4/route.o CC drivers/pci/hotplug/pciehp_pci.o AR drivers/pci/controller/dwc/built-in.a AR drivers/pci/controller/mobiveil/built-in.a CC arch/x86/mm/pkeys.o CC drivers/pci/controller/vmd.o CC fs/configfs/mount.o AR drivers/pci/msi/built-in.a CC net/netfilter/nf_sockopt.o CC lib/lz4/lz4hc_compress.o CC [M] arch/x86/kvm/../../../virt/kvm/kvm_main.o CC lib/lz4/lz4_decompress.o CC drivers/pci/pcie/aer.o AR kernel/bpf/built-in.a CC drivers/pci/hotplug/pciehp_hpc.o CC [M] net/netfilter/ipvs/ip_vs_proto_udp.o CC kernel/time/timeconv.o CC net/core/netevent.o CC [M] sound/core/hwdep.o CC mm/util.o AR kernel/irq/built-in.a CC block/blk-mq.o CC net/ethtool/channels.o AR drivers/pci/switch/built-in.a CC kernel/sched/build_utility.o CC crypto/algboss.o CC [M] net/ipv4/netfilter/iptable_filter.o CC io_uring/net.o CC [M] net/ipv4/netfilter/iptable_mangle.o CC kernel/cgroup/cgroup-v1.o CC net/ethtool/coalesce.o CC [M] arch/x86/kvm/../../../virt/kvm/eventfd.o CC fs/configfs/item.o CC kernel/time/timecounter.o CC [M] arch/x86/kvm/../../../virt/kvm/binary_stats.o CC kernel/trace/trace_functions.o CC arch/x86/mm/pti.o CC [M] net/ipv4/netfilter/iptable_nat.o CC [M] net/ipv4/netfilter/ipt_REJECT.o CC kernel/time/alarmtimer.o CC net/core/neighbour.o CC drivers/pci/access.o CC kernel/time/posix-timers.o CC [M] arch/x86/kvm/../../../virt/kvm/vfio.o CC drivers/pci/hotplug/acpiphp_core.o CC drivers/pci/bus.o CC [M] net/netfilter/ipvs/ip_vs_nfct.o CC net/netfilter/utils.o CC crypto/testmgr.o CC drivers/pci/probe.o CC [M] sound/core/pcm.o CC drivers/pci/hotplug/acpiphp_glue.o CC [M] net/netfilter/nfnetlink.o AR drivers/pci/controller/built-in.a CC arch/x86/kernel/acpi/boot.o CC fs/proc/array.o AR fs/configfs/built-in.a CC [M] net/netfilter/nf_conntrack_core.o CC arch/x86/kernel/acpi/sleep.o CC net/core/rtnetlink.o CC net/core/utils.o AR sound/arm/built-in.a AR lib/lz4/built-in.a CC fs/ext4/balloc.o CC lib/zstd/zstd_compress_module.o CC fs/ext4/bitmap.o CC drivers/pci/pcie/err.o CC fs/ext4/block_validity.o CC fs/ext4/dir.o AR arch/x86/mm/built-in.a CC [M] net/netfilter/ipvs/ip_vs_rr.o CC crypto/cmac.o CC [M] arch/x86/kvm/../../../virt/kvm/coalesced_mmio.o CC crypto/hmac.o CC mm/mmzone.o CC net/core/link_watch.o CC arch/x86/kernel/apic/apic.o CC drivers/video/console/dummycon.o CC kernel/trace/trace_preemptirq.o CC net/ethtool/pause.o CC arch/x86/kernel/kprobes/core.o CC drivers/pci/host-bridge.o CC drivers/video/console/vgacon.o CC drivers/video/logo/logo.o CC lib/zstd/compress/fse_compress.o HOSTCC drivers/video/logo/pnmtologo CC fs/jbd2/transaction.o AS arch/x86/kernel/acpi/wakeup_64.o CC fs/jbd2/commit.o CC kernel/cgroup/freezer.o CC [M] sound/pci/hda/patch_hdmi.o CC [M] sound/core/pcm_native.o CC [M] sound/pci/hda/hda_eld.o CC arch/x86/kernel/acpi/apei.o CC drivers/pci/pcie/aer_inject.o CC kernel/panic.o CC kernel/cpu.o CC mm/vmstat.o LOGO drivers/video/logo/logo_linux_clut224.c CC drivers/video/logo/logo_linux_clut224.o CC lib/zstd/compress/hist.o AR drivers/video/logo/built-in.a CC net/ipv4/inetpeer.o CC net/ipv4/protocol.o CC net/ipv4/ip_input.o AR drivers/pci/hotplug/built-in.a CC [M] arch/x86/kvm/../../../virt/kvm/async_pf.o CC [M] net/netfilter/nf_conntrack_standalone.o CC lib/zstd/compress/huf_compress.o CC drivers/video/backlight/backlight.o CC fs/ext4/ext4_jbd2.o CC fs/ext4/extents.o CC [M] sound/pci/hda/hda_intel.o CC fs/proc/fd.o CC drivers/pci/remove.o CC kernel/time/posix-cpu-timers.o CC drivers/video/fbdev/core/fb_notify.o CC io_uring/msg_ring.o CC kernel/trace/trace_nop.o AR drivers/video/fbdev/omap/built-in.a CC kernel/time/posix-clock.o CC drivers/pci/pci.o LD [M] net/netfilter/ipvs/ip_vs.o CC arch/x86/kernel/acpi/cppc.o CC [M] net/netfilter/nf_conntrack_expect.o CC arch/x86/kernel/kprobes/opt.o CC net/ethtool/eee.o CC [M] arch/x86/kvm/../../../virt/kvm/irqchip.o CC kernel/cgroup/legacy_freezer.o AR drivers/video/console/built-in.a CC [M] arch/x86/kvm/../../../virt/kvm/dirty_ring.o CC arch/x86/kernel/cpu/powerflags.o CC drivers/pci/pci-driver.o CC drivers/pci/pcie/pme.o CC arch/x86/kernel/acpi/cstate.o CC io_uring/timeout.o CC kernel/time/itimer.o CC arch/x86/kernel/cpu/feat_ctl.o LD [M] sound/pci/hda/snd-hda-codec.o CC net/ipv4/ip_fragment.o LD [M] sound/pci/hda/snd-hda-codec-generic.o CC [M] drivers/video/fbdev/core/fb_backlight.o AR drivers/video/fbdev/omap2/omapfb/dss/built-in.a CC fs/proc/proc_tty.o AR drivers/video/fbdev/omap2/omapfb/displays/built-in.a AR drivers/video/fbdev/omap2/omapfb/built-in.a CC fs/proc/cmdline.o AR drivers/video/fbdev/omap2/built-in.a CC [M] drivers/video/fbdev/core/fb_info.o CC mm/backing-dev.o CC kernel/trace/trace_functions_graph.o AR drivers/video/backlight/built-in.a CC kernel/time/clockevents.o CC kernel/trace/fgraph.o CC drivers/pci/pcie/dpc.o CC net/ipv4/ip_forward.o CC crypto/vmac.o CC net/ipv4/ip_options.o CC arch/x86/kernel/apic/apic_common.o CC arch/x86/kernel/cpu/intel.o AR arch/x86/kernel/acpi/built-in.a CC arch/x86/kernel/kprobes/ftrace.o CC mm/mm_init.o CC net/ipv4/ip_output.o CC [M] net/netfilter/nf_conntrack_helper.o CC [M] net/netfilter/nf_conntrack_proto.o CC [M] net/netfilter/nf_conntrack_proto_generic.o CC kernel/cgroup/pids.o CC fs/jbd2/recovery.o CC kernel/cgroup/cpuset.o CC [M] sound/core/pcm_lib.o CC mm/percpu.o CC [M] net/netfilter/nf_conntrack_proto_tcp.o CC net/ethtool/tsinfo.o CC lib/zstd/compress/zstd_compress.o LDS arch/x86/kernel/vmlinux.lds CC fs/proc/consoles.o CC net/ipv4/ip_sockglue.o AS arch/x86/kernel/head_64.o CC arch/x86/kernel/head64.o CC net/ethtool/cabletest.o CC fs/proc/cpuinfo.o CC [M] drivers/video/fbdev/core/fbmem.o CC fs/proc/devices.o CC arch/x86/kernel/apic/apic_noop.o CC kernel/time/tick-common.o CC [M] net/netfilter/nf_conntrack_proto_udp.o CC io_uring/sqpoll.o AR drivers/pci/pcie/built-in.a CC drivers/pci/search.o AR arch/x86/kernel/kprobes/built-in.a CC drivers/idle/intel_idle.o LD [M] sound/pci/hda/snd-hda-codec-realtek.o AR sound/sh/built-in.a CC drivers/pci/pci-sysfs.o CC arch/x86/kernel/ebda.o LD [M] sound/pci/hda/snd-hda-codec-analog.o AR sound/synth/emux/built-in.a CC block/blk-mq-tag.o AR sound/synth/built-in.a LD [M] sound/pci/hda/snd-hda-codec-hdmi.o CC arch/x86/kernel/platform-quirks.o CC net/core/filter.o LD [M] sound/pci/hda/snd-hda-intel.o CC arch/x86/kernel/apic/ipi.o CC [M] drivers/video/fbdev/core/fbmon.o AR sound/pci/korg1212/built-in.a AR sound/pci/mixart/built-in.a CC crypto/xcbc.o CC [M] drivers/video/fbdev/core/fbcmap.o AR sound/pci/nm256/built-in.a AR sound/pci/oxygen/built-in.a CC [M] net/netfilter/nf_conntrack_proto_icmp.o AR sound/pci/pcxhr/built-in.a AR sound/pci/riptide/built-in.a AR sound/pci/rme9652/built-in.a CC kernel/trace/blktrace.o AR sound/pci/trident/built-in.a AR sound/pci/ymfpci/built-in.a CC io_uring/fdinfo.o AR sound/pci/vx222/built-in.a AR sound/usb/misc/built-in.a AR sound/pci/built-in.a AR sound/usb/usx2y/built-in.a AR sound/usb/caiaq/built-in.a CC fs/proc/interrupts.o AR sound/usb/6fire/built-in.a CC fs/proc/loadavg.o AR sound/usb/hiface/built-in.a AR sound/usb/bcd2000/built-in.a AR sound/usb/built-in.a CC net/ipv4/inet_hashtables.o CC arch/x86/kernel/process_64.o CC mm/slab_common.o CC arch/x86/kernel/cpu/intel_pconfig.o CC arch/x86/kernel/apic/vector.o CC fs/proc/meminfo.o CC fs/proc/stat.o CC fs/jbd2/checkpoint.o CC fs/jbd2/revoke.o CC drivers/pci/rom.o CC arch/x86/kernel/signal.o CC net/ethtool/tunnels.o CC net/ipv4/inet_timewait_sock.o CC arch/x86/kernel/cpu/tsx.o CC crypto/crypto_null.o CC crypto/md5.o CC net/ipv4/inet_connection_sock.o CC net/ipv4/tcp.o CC net/ethtool/fec.o CC kernel/time/tick-broadcast.o CC [M] arch/x86/kvm/../../../virt/kvm/pfncache.o CC arch/x86/kernel/cpu/intel_epb.o CC [M] net/netfilter/nf_conntrack_extend.o CC [M] net/netfilter/nf_conntrack_acct.o CC mm/compaction.o CC arch/x86/kernel/apic/hw_nmi.o CC kernel/trace/trace_events.o CC kernel/trace/trace_export.o CC fs/ramfs/inode.o CC block/blk-stat.o CC fs/ramfs/file-mmu.o CC fs/proc/uptime.o AR drivers/idle/built-in.a CC fs/hugetlbfs/inode.o CC fs/fat/cache.o CC fs/nfs/client.o CC [M] sound/core/pcm_misc.o CC fs/fat/dir.o CC fs/nfs/dir.o CC arch/x86/kernel/cpu/amd.o CC drivers/pci/setup-res.o CC crypto/sha1_generic.o CC [M] net/netfilter/nf_conntrack_seqadj.o CC [M] sound/core/pcm_memory.o AR drivers/char/ipmi/built-in.a CC mm/interval_tree.o CC io_uring/tctx.o CC [M] drivers/video/fbdev/core/modedb.o CC net/core/sock_diag.o CC [M] net/netfilter/nf_conntrack_proto_icmpv6.o CC arch/x86/kernel/signal_64.o CC fs/jbd2/journal.o CC kernel/time/tick-broadcast-hrtimer.o AR kernel/sched/built-in.a CC fs/proc/util.o CC kernel/exit.o CC [M] drivers/video/fbdev/uvesafb.o CC fs/proc/version.o CC [M] net/netfilter/nf_conntrack_proto_dccp.o CC [M] sound/core/memalloc.o CC [M] sound/core/pcm_timer.o CC [M] arch/x86/kvm/x86.o AR fs/ramfs/built-in.a CC mm/list_lru.o CC arch/x86/kernel/traps.o CC net/ethtool/eeprom.o AR kernel/events/built-in.a CC kernel/softirq.o CC block/blk-mq-sysfs.o CC block/blk-mq-cpumap.o CC kernel/resource.o CC crypto/sha256_generic.o CC [M] arch/x86/kvm/emulate.o CC block/blk-mq-sched.o CC kernel/time/tick-oneshot.o CC fs/exportfs/expfs.o CC drivers/pci/irq.o CC arch/x86/kernel/apic/io_apic.o LD [M] sound/core/snd-ctl-led.o CC io_uring/poll.o CC net/ipv4/tcp_input.o CC mm/workingset.o CC fs/proc/softirqs.o CC arch/x86/kernel/cpu/hygon.o CC block/ioctl.o CC fs/ext4/extents_status.o CC io_uring/cancel.o CC lib/zstd/compress/zstd_compress_literals.o AR kernel/cgroup/built-in.a CC net/core/dev_ioctl.o CC fs/proc/namespaces.o CC [M] net/netfilter/nf_conntrack_proto_sctp.o CC [M] drivers/video/fbdev/core/fbcvt.o CC lib/zstd/compress/zstd_compress_sequences.o CC net/core/tso.o CC crypto/sha512_generic.o CC kernel/time/tick-sched.o CC net/ipv4/tcp_output.o AR fs/hugetlbfs/built-in.a CC arch/x86/kernel/apic/msi.o CC fs/lockd/clntlock.o CC arch/x86/kernel/apic/x2apic_phys.o CC fs/nls/nls_base.o CC drivers/pci/vpd.o CC fs/nls/nls_cp437.o CC fs/proc/self.o CC fs/nls/nls_ascii.o AR fs/exportfs/built-in.a CC fs/ext4/file.o CC arch/x86/kernel/cpu/centaur.o CC fs/fat/fatent.o LD [M] sound/core/snd-hwdep.o LD [M] sound/core/snd-pcm.o CC mm/debug.o AR sound/core/built-in.a CC fs/fat/file.o AR sound/firewire/built-in.a CC lib/zstd/compress/zstd_compress_superblock.o AR sound/sparc/built-in.a CC net/ethtool/stats.o CC [M] net/netfilter/nf_conntrack_netlink.o AR sound/spi/built-in.a AR sound/parisc/built-in.a CC [M] net/netfilter/nf_nat_core.o AR sound/pcmcia/vx/built-in.a AR sound/pcmcia/pdaudiocf/built-in.a AR sound/pcmcia/built-in.a AR sound/mips/built-in.a AR sound/soc/built-in.a AR sound/atmel/built-in.a AR sound/hda/built-in.a CC [M] sound/hda/hda_bus_type.o AR sound/x86/built-in.a CC [M] net/netfilter/nf_nat_proto.o CC [M] sound/hda/hdac_bus.o CC net/ethtool/phc_vclocks.o CC fs/fat/inode.o CC lib/zstd/compress/zstd_double_fast.o CC fs/fat/misc.o CC fs/fat/nfs.o CC crypto/blake2b_generic.o CC kernel/sysctl.o CC fs/nfs/file.o CC block/genhd.o CC fs/nls/nls_iso8859-1.o AR fs/unicode/built-in.a CC crypto/ecb.o CC [M] drivers/video/fbdev/core/fb_cmdline.o CC fs/proc/thread_self.o CC kernel/time/vsyscall.o CC fs/ntfs/aops.o CC arch/x86/kernel/cpu/zhaoxin.o CC fs/ntfs/attrib.o CC io_uring/kbuf.o CC fs/ntfs/collate.o CC kernel/trace/trace_event_perf.o CC net/core/sock_reuseport.o CC drivers/pci/setup-bus.o CC net/core/fib_notifier.o CC fs/nfs/getroot.o CC fs/nls/nls_utf8.o CC kernel/time/timekeeping_debug.o CC mm/gup.o CC crypto/cbc.o CC crypto/pcbc.o CC kernel/time/namespace.o CC fs/lockd/clntproc.o CC arch/x86/kernel/cpu/perfctr-watchdog.o CC fs/fat/namei_vfat.o CC [M] sound/hda/hdac_device.o CC fs/nfs/inode.o CC fs/nfs/super.o CC fs/proc/proc_sysctl.o CC arch/x86/kernel/cpu/vmware.o CC arch/x86/kernel/apic/x2apic_cluster.o CC arch/x86/kernel/apic/apic_flat_64.o CC kernel/trace/trace_events_filter.o CC net/ethtool/mm.o CC arch/x86/kernel/cpu/hypervisor.o CC fs/ntfs/compress.o AR fs/nls/built-in.a CC [M] sound/hda/hdac_sysfs.o CC mm/mmap_lock.o CC fs/proc/proc_net.o CC [M] drivers/video/fbdev/core/fb_io_fops.o CC crypto/cts.o CC [M] drivers/video/fbdev/core/fb_defio.o CC fs/ext4/fsmap.o CC arch/x86/kernel/cpu/mshyperv.o CC arch/x86/kernel/cpu/capflags.o CC [M] drivers/video/fbdev/core/fb_chrdev.o AR fs/jbd2/built-in.a CC fs/ntfs/debug.o CC [M] drivers/video/fbdev/core/fb_procfs.o CC [M] drivers/video/fbdev/core/fbsysfs.o CC [M] drivers/video/fbdev/core/fbcon.o CC fs/nfs/io.o CC fs/nfs/direct.o CC fs/nfs/pagelist.o CC io_uring/rsrc.o CC net/ipv4/tcp_timer.o CC net/ipv4/tcp_ipv4.o AR kernel/time/built-in.a AR sound/xen/built-in.a CC fs/nfs/read.o CC fs/autofs/init.o CC block/ioprio.o CC arch/x86/kernel/apic/probe_64.o CC fs/autofs/inode.o CC [M] net/netfilter/nf_nat_helper.o CC kernel/trace/trace_events_trigger.o CC io_uring/rw.o CC [M] sound/hda/hdac_regmap.o AR arch/x86/kernel/apic/built-in.a CC io_uring/opdef.o CC io_uring/notif.o CC net/ethtool/module.o CC kernel/trace/trace_eprobe.o CC fs/ext4/fsync.o CC fs/fat/namei_msdos.o CC crypto/lrw.o CC fs/proc/kcore.o CC kernel/capability.o CC net/ipv4/tcp_minisocks.o CC block/badblocks.o CC [M] sound/hda/hdac_controller.o CC net/ethtool/pse-pd.o CC fs/lockd/clntxdr.o AR arch/x86/kernel/cpu/built-in.a CC arch/x86/kernel/idt.o CC [M] arch/x86/kvm/i8259.o CC fs/autofs/root.o CC drivers/pci/vc.o CC fs/ntfs/dir.o CC [M] drivers/video/fbdev/core/bitblit.o CC arch/x86/kernel/irq.o CC [M] drivers/video/fbdev/core/softcursor.o CC fs/proc/kmsg.o CC [M] net/netfilter/nf_nat_redirect.o CC [M] net/netfilter/nf_nat_masquerade.o CC arch/x86/kernel/irq_64.o CC [M] net/netfilter/x_tables.o CC [M] drivers/video/fbdev/simplefb.o CC fs/ext4/hash.o CC crypto/xts.o CC block/blk-rq-qos.o CC fs/ext4/ialloc.o CC fs/autofs/symlink.o CC net/ethtool/plca.o CC io_uring/io-wq.o CC kernel/ptrace.o AR fs/fat/built-in.a CC kernel/user.o CC fs/ext4/indirect.o CC fs/proc/page.o CC sound/sound_core.o AR sound/virtio/built-in.a CC net/core/xdp.o CC sound/last.o CC drivers/pci/mmap.o CC [M] sound/hda/hdac_stream.o CC drivers/pci/setup-irq.o CC mm/highmem.o CC net/ipv4/tcp_cong.o AR fs/hostfs/built-in.a CC arch/x86/kernel/dumpstack_64.o CC net/xfrm/xfrm_policy.o CC net/xfrm/xfrm_state.o CC arch/x86/kernel/time.o CC net/unix/af_unix.o CC kernel/signal.o CC fs/lockd/host.o CC fs/lockd/svc.o CC drivers/pci/proc.o CC arch/x86/kernel/ioport.o CC kernel/trace/trace_kprobe.o CC [M] drivers/video/fbdev/core/tileblit.o CC fs/autofs/waitq.o CC [M] drivers/video/fbdev/core/cfbfillrect.o CC fs/lockd/svclock.o CC fs/lockd/svcshare.o CC block/disk-events.o CC fs/autofs/expire.o CC net/ipv4/tcp_metrics.o CC fs/debugfs/inode.o CC fs/tracefs/inode.o CC fs/ntfs/file.o CC lib/zstd/compress/zstd_fast.o CC crypto/ctr.o CC crypto/gcm.o CC lib/zstd/compress/zstd_lazy.o CC block/blk-ia-ranges.o CC drivers/pci/slot.o CC fs/nfs/symlink.o CC net/unix/garbage.o CC fs/ntfs/index.o CC mm/memory.o CC fs/btrfs/super.o CC fs/ext4/inline.o AR net/ethtool/built-in.a AR fs/proc/built-in.a CC [M] sound/hda/array.o AR net/ipv6/netfilter/built-in.a CC net/ipv6/af_inet6.o CC [M] net/ipv6/netfilter/nf_defrag_ipv6_hooks.o CC [M] arch/x86/kvm/irq.o CC crypto/pcrypt.o CC fs/autofs/dev-ioctl.o CC arch/x86/kernel/dumpstack.o CC arch/x86/kernel/nmi.o CC [M] net/ipv6/netfilter/nf_conntrack_reasm.o CC fs/ext4/inode.o CC kernel/sys.o CC fs/ntfs/inode.o CC drivers/acpi/acpica/dsargs.o CC [M] drivers/video/fbdev/core/cfbcopyarea.o AR fs/tracefs/built-in.a CC drivers/acpi/acpica/dscontrol.o CC fs/debugfs/file.o CC block/bsg.o CC fs/pstore/inode.o CC drivers/pci/pci-acpi.o CC fs/pstore/platform.o CC [M] net/netfilter/xt_tcpudp.o CC [M] sound/hda/hdmi_chmap.o CC arch/x86/kernel/ldt.o CC fs/efivarfs/inode.o CC [M] fs/netfs/buffered_read.o AR io_uring/built-in.a CC [M] fs/fscache/cache.o CC fs/ntfs/mft.o CC fs/efivarfs/file.o CC lib/zstd/compress/zstd_ldm.o CC fs/ntfs/mst.o CC fs/nfs/unlink.o CC fs/nfs/write.o CC fs/ext4/ioctl.o CC drivers/acpi/acpica/dsdebug.o CC crypto/cryptd.o CC net/ipv4/tcp_fastopen.o CC fs/lockd/svcproc.o CC fs/efivarfs/super.o CC [M] arch/x86/kvm/lapic.o AR fs/autofs/built-in.a CC net/ipv4/tcp_rate.o CC arch/x86/kernel/setup.o CC net/core/flow_offload.o CC block/bsg-lib.o CC arch/x86/kernel/x86_init.o CC fs/btrfs/ctree.o CC mm/mincore.o CC drivers/acpi/acpica/dsfield.o CC [M] drivers/video/fbdev/core/cfbimgblt.o CC block/blk-cgroup.o CC fs/pstore/pmsg.o CC fs/btrfs/extent-tree.o CC mm/mlock.o CC net/ipv4/tcp_recovery.o CC [M] arch/x86/kvm/i8254.o CC fs/ntfs/namei.o AR fs/debugfs/built-in.a CC [M] fs/netfs/io.o CC fs/lockd/svcsubs.o CC kernel/trace/error_report-traces.o CC [M] sound/hda/trace.o CC fs/efivarfs/vars.o CC drivers/pci/quirks.o CC [M] fs/fscache/cookie.o CC arch/x86/kernel/i8259.o CC crypto/des_generic.o LD [M] net/ipv6/netfilter/nf_defrag_ipv6.o CC lib/zstd/compress/zstd_opt.o CC crypto/aes_generic.o CC net/ipv6/anycast.o CC drivers/acpi/acpica/dsinit.o CC kernel/trace/power-traces.o AR fs/pstore/built-in.a CC fs/ext4/mballoc.o CC crypto/deflate.o CC [M] net/netfilter/xt_mark.o CC drivers/acpi/acpica/dsmethod.o CC mm/mmap.o CC fs/lockd/mon.o CC net/unix/sysctl_net_unix.o CC [M] fs/netfs/iterator.o CC fs/ntfs/runlist.o CC net/core/gro.o CC [M] drivers/video/fbdev/core/sysfillrect.o CC net/ipv6/ip6_output.o CC block/blk-cgroup-rwstat.o CC drivers/acpi/acpica/dsmthdat.o CC [M] net/netfilter/xt_nat.o CC arch/x86/kernel/irqinit.o CC net/core/netdev-genl.o CC [M] sound/hda/hdac_component.o CC [M] sound/hda/hdac_i915.o AR fs/efivarfs/built-in.a CC fs/ntfs/super.o CC crypto/crc32c_generic.o CC [M] net/netfilter/xt_REDIRECT.o CC mm/mmu_gather.o CC net/ipv4/tcp_ulp.o CC net/ipv4/tcp_offload.o CC [M] fs/netfs/main.o CC net/xfrm/xfrm_hash.o CC arch/x86/kernel/jump_label.o CC drivers/acpi/acpica/dsobject.o CC kernel/trace/rpm-traces.o CC kernel/umh.o CC net/ipv4/tcp_plb.o CC kernel/workqueue.o CC drivers/acpi/acpica/dsopcode.o CC crypto/crct10dif_common.o CC net/xfrm/xfrm_input.o CC fs/nfs/namespace.o CC crypto/crct10dif_generic.o CC net/unix/diag.o CC net/ipv6/ip6_input.o CC [M] drivers/video/fbdev/core/syscopyarea.o CC kernel/trace/trace_dynevent.o CC [M] sound/hda/intel-dsp-config.o CC [M] fs/fscache/io.o CC kernel/trace/trace_probe.o CC fs/lockd/trace.o CC [M] fs/smb/common/cifs_arc4.o CC fs/lockd/xdr.o CC block/blk-throttle.o CC [M] fs/smb/common/cifs_md4.o CC [M] sound/hda/intel-nhlt.o CC arch/x86/kernel/irq_work.o CC [M] net/netfilter/xt_MASQUERADE.o CC [M] net/netfilter/xt_addrtype.o CC [M] net/netfilter/xt_conntrack.o CC [M] net/netfilter/xt_ipvs.o CC crypto/authenc.o CC lib/zstd/zstd_decompress_module.o CC drivers/acpi/acpica/dspkginit.o CC [M] fs/netfs/objects.o CC net/xfrm/xfrm_output.o CC kernel/trace/trace_uprobe.o CC kernel/trace/rethook.o CC drivers/video/aperture.o CC drivers/acpi/acpica/dsutils.o CC crypto/authencesn.o CC [M] fs/smb/client/trace.o CC crypto/lzo.o CC net/ipv4/datagram.o CC [M] fs/smb/client/cifsfs.o CC fs/ntfs/sysctl.o CC fs/ntfs/unistr.o CC drivers/acpi/apei/apei-base.o CC net/core/netdev-genl-gen.o CC [M] sound/hda/intel-sdw-acpi.o CC drivers/pci/ats.o CC drivers/acpi/apei/hest.o CC net/core/net-sysfs.o CC fs/ntfs/upcase.o CC [M] fs/fscache/main.o CC [M] drivers/video/fbdev/core/sysimgblt.o CC drivers/acpi/apei/erst.o CC net/unix/scm.o CC fs/nfs/mount_clnt.o CC arch/x86/kernel/probe_roms.o CC drivers/acpi/acpica/dswexec.o CC fs/lockd/clnt4xdr.o LD [M] fs/netfs/netfs.o CC kernel/pid.o CC [M] fs/fuse/dev.o CC [M] fs/overlayfs/super.o CC [M] fs/fuse/dir.o CC mm/mprotect.o CC net/xfrm/xfrm_sysctl.o CC drivers/acpi/acpica/dswload.o LD [M] sound/hda/snd-hda-core.o CC net/xfrm/xfrm_replay.o LD [M] sound/hda/snd-intel-dspcfg.o CC kernel/task_work.o LD [M] sound/hda/snd-intel-sdw-acpi.o CC crypto/lzo-rle.o CC kernel/extable.o AR sound/built-in.a AR fs/ntfs/built-in.a CC crypto/lz4.o LD [M] net/netfilter/nf_conntrack.o CC [M] drivers/video/fbdev/core/fb_sys_fops.o CC mm/mremap.o CC drivers/acpi/apei/bert.o CC drivers/acpi/acpica/dswload2.o LD [M] net/netfilter/nf_nat.o CC drivers/pci/iov.o CC fs/open.o AR net/netfilter/built-in.a CC arch/x86/kernel/sys_ia32.o CC fs/nfs/nfstrace.o CC block/mq-deadline.o CC drivers/acpi/apei/ghes.o CC net/core/page_pool.o CC mm/msync.o CC fs/lockd/xdr4.o CC fs/ext4/migrate.o CC net/core/net-procfs.o CC net/packet/af_packet.o AR net/unix/built-in.a CC drivers/acpi/acpica/dswscope.o CC net/packet/diag.o CC net/ipv4/raw.o CC arch/x86/kernel/signal_32.o CC mm/page_vma_mapped.o CC crypto/lz4hc.o CC kernel/params.o CC kernel/kthread.o CC mm/pagewalk.o CC net/key/af_key.o CC [M] fs/fscache/volume.o AR net/dsa/built-in.a AR net/bridge/netfilter/built-in.a CC [M] fs/fscache/proc.o CC net/bridge/br.o CC fs/read_write.o LD [M] drivers/video/fbdev/core/fb.o CC [M] fs/overlayfs/namei.o CC drivers/acpi/acpica/dswstate.o AR drivers/video/fbdev/core/built-in.a AR drivers/video/fbdev/built-in.a CC drivers/video/cmdline.o CC net/xfrm/xfrm_device.o CC fs/file_table.o CC [M] net/sunrpc/auth_gss/auth_gss.o CC crypto/xxhash_generic.o CC [M] net/sunrpc/auth_gss/gss_generic_token.o CC mm/pgtable-generic.o CC net/ipv6/addrconf.o AR kernel/trace/built-in.a CC fs/btrfs/print-tree.o CC kernel/sys_ni.o CC [M] fs/overlayfs/util.o CC fs/lockd/svc4proc.o CC drivers/pci/pci-label.o CC [M] fs/smb/client/cifs_debug.o CC fs/lockd/procfs.o CC drivers/video/nomodeset.o CC arch/x86/kernel/sys_x86_64.o CC drivers/acpi/acpica/evevent.o CC net/bridge/br_device.o CC mm/rmap.o CC kernel/nsproxy.o CC drivers/video/hdmi.o CC net/core/netpoll.o CC drivers/acpi/acpica/evgpe.o CC crypto/rng.o CC fs/btrfs/root-tree.o AR drivers/acpi/apei/built-in.a CC [M] fs/overlayfs/inode.o CC [M] net/sunrpc/auth_gss/gss_mech_switch.o CC [M] net/sunrpc/auth_gss/svcauth_gss.o CC block/kyber-iosched.o CC [M] net/sunrpc/auth_gss/gss_rpc_upcall.o CC drivers/acpi/acpica/evgpeblk.o CC kernel/notifier.o CC [M] arch/x86/kvm/ioapic.o CC net/ipv6/addrlabel.o CC net/bridge/br_fdb.o LD [M] fs/fscache/fscache.o CC [M] fs/fuse/file.o CC [M] net/sunrpc/auth_gss/gss_rpc_xdr.o CC crypto/drbg.o CC fs/btrfs/dir-item.o CC [M] arch/x86/kvm/irq_comm.o CC fs/super.o CC [M] fs/fuse/inode.o CC net/bridge/br_forward.o CC kernel/ksysfs.o CC block/bfq-iosched.o CC drivers/pci/pci-stub.o AR drivers/acpi/pmic/built-in.a CC drivers/acpi/dptf/int340x_thermal.o CC drivers/acpi/tables.o CC lib/xz/xz_dec_syms.o CC lib/raid6/algos.o CC arch/x86/kernel/espfix_64.o CC lib/raid6/recov.o CC drivers/acpi/acpica/evgpeinit.o CC net/bridge/br_if.o AR drivers/video/built-in.a CC net/ipv4/udp.o CC net/xfrm/xfrm_algo.o CC drivers/pnp/pnpacpi/core.o CC drivers/pnp/core.o AR fs/lockd/built-in.a CC kernel/cred.o CC drivers/acpi/blacklist.o CC lib/xz/xz_dec_stream.o CC fs/ext4/mmp.o AR drivers/acpi/dptf/built-in.a CC [M] net/sunrpc/auth_gss/trace.o CC drivers/pci/vgaarb.o CC net/xfrm/xfrm_user.o CC fs/btrfs/file-item.o CC [M] fs/overlayfs/file.o CC net/bridge/br_input.o CC drivers/acpi/acpica/evgpeutil.o AR drivers/amba/built-in.a CC drivers/pnp/card.o CC [M] net/sunrpc/auth_gss/gss_krb5_mech.o CC [M] net/sunrpc/auth_gss/gss_krb5_seal.o CC kernel/reboot.o CC net/8021q/vlan_core.o HOSTCC lib/raid6/mktables CC [M] fs/smb/client/connect.o CC [M] net/sunrpc/auth_gss/gss_krb5_unseal.o CC arch/x86/kernel/ksysfs.o UNROLL lib/raid6/int1.c UNROLL lib/raid6/int2.c CC net/ipv4/udplite.o CC [M] arch/x86/kvm/cpuid.o CC drivers/pnp/pnpacpi/rsparser.o CC net/ipv4/udp_offload.o CC [M] arch/x86/kvm/pmu.o CC kernel/async.o AR drivers/clk/actions/built-in.a AR drivers/clk/analogbits/built-in.a UNROLL lib/raid6/int4.c AR drivers/clk/bcm/built-in.a UNROLL lib/raid6/int8.c UNROLL lib/raid6/int16.c AR drivers/clk/imgtec/built-in.a UNROLL lib/raid6/int32.c CC lib/xz/xz_dec_lzma2.o AR drivers/clk/imx/built-in.a CC lib/raid6/recov_ssse3.o AR drivers/clk/ingenic/built-in.a AR drivers/clk/mediatek/built-in.a CC net/ipv6/route.o AR drivers/clk/microchip/built-in.a AR drivers/clk/mstar/built-in.a CC drivers/dma/dw/core.o CC net/core/fib_rules.o AR drivers/clk/mvebu/built-in.a AR drivers/clk/ralink/built-in.a AR drivers/clk/renesas/built-in.a CC arch/x86/kernel/bootflag.o AR drivers/clk/socfpga/built-in.a CC arch/x86/kernel/e820.o AR drivers/clk/sprd/built-in.a AR drivers/clk/starfive/built-in.a AR drivers/clk/sunxi-ng/built-in.a CC crypto/jitterentropy.o AR drivers/clk/ti/built-in.a CC drivers/acpi/acpica/evglock.o AR drivers/soc/apple/built-in.a AR drivers/clk/versatile/built-in.a AR drivers/soc/aspeed/built-in.a CC drivers/clk/x86/clk-lpss-atom.o AR drivers/soc/bcm/bcm63xx/built-in.a AR drivers/soc/bcm/built-in.a AR drivers/soc/fsl/built-in.a CC crypto/jitterentropy-kcapi.o AR drivers/soc/fujitsu/built-in.a AR drivers/soc/imx/built-in.a AR drivers/soc/ixp4xx/built-in.a AR net/key/built-in.a CC drivers/clk/x86/clk-pmc-atom.o AR drivers/soc/loongson/built-in.a AR drivers/soc/mediatek/built-in.a AR drivers/soc/microchip/built-in.a CC [M] net/sunrpc/auth_gss/gss_krb5_seqnum.o AR drivers/soc/nuvoton/built-in.a CC net/dcb/dcbnl.o CC net/dcb/dcbevent.o AR drivers/soc/pxa/built-in.a AR drivers/soc/amlogic/built-in.a AR drivers/soc/qcom/built-in.a AR drivers/soc/renesas/built-in.a AR drivers/soc/rockchip/built-in.a AR drivers/soc/sifive/built-in.a CC fs/ext4/move_extent.o AR drivers/soc/sunxi/built-in.a CC net/sunrpc/clnt.o CC drivers/dma/dw/dw.o AR drivers/soc/ti/built-in.a AR drivers/soc/xilinx/built-in.a AR drivers/soc/built-in.a CC [M] fs/fuse/control.o CC drivers/dma/dw/idma32.o CC net/sunrpc/xprt.o CC lib/raid6/recov_avx2.o CC crypto/ghash-generic.o CC [M] fs/overlayfs/dir.o CC kernel/range.o CC net/bridge/br_ioctl.o CC drivers/acpi/acpica/evhandler.o CC drivers/acpi/acpica/evmisc.o AR drivers/pci/built-in.a CC net/l3mdev/l3mdev.o CC [M] fs/smb/client/dir.o CC [M] net/sunrpc/auth_gss/gss_krb5_wrap.o CC kernel/smpboot.o CC drivers/pnp/driver.o CC drivers/acpi/acpica/evregion.o CC mm/vmalloc.o CC kernel/ucount.o CC lib/xz/xz_dec_bcj.o AR drivers/pnp/pnpacpi/built-in.a CC drivers/pnp/resource.o AR drivers/clk/x86/built-in.a CC net/handshake/genl.o AR drivers/clk/xilinx/built-in.a CC drivers/clk/clk-devres.o CC net/handshake/netlink.o CC net/bridge/br_stp.o AR net/packet/built-in.a CC [M] net/bluetooth/af_bluetooth.o CC crypto/af_alg.o CC [M] net/bluetooth/hci_core.o CC [M] net/8021q/vlan.o CC drivers/dma/dw/acpi.o CC drivers/dma/dw/pci.o CC net/ipv4/arp.o CC drivers/virtio/virtio.o CC crypto/algif_hash.o CC lib/raid6/mmx.o CC drivers/tty/vt/vt_ioctl.o CC lib/raid6/sse1.o CC drivers/virtio/virtio_ring.o CC [M] fs/fuse/xattr.o CC lib/raid6/sse2.o CC arch/x86/kernel/pci-dma.o CC drivers/tty/hvc/hvc_console.o CC drivers/acpi/acpica/evrgnini.o AR lib/xz/built-in.a CC drivers/clk/clk-bulk.o CC fs/btrfs/inode-item.o CC net/ipv4/icmp.o CC drivers/pnp/manager.o CC drivers/dma/hsu/hsu.o CC fs/nfs/export.o CC kernel/regset.o CC fs/ext4/namei.o CC lib/fonts/fonts.o AR drivers/dma/idxd/built-in.a AR drivers/dma/mediatek/built-in.a CC lib/argv_split.o AR net/l3mdev/built-in.a CC lib/fonts/font_8x8.o CC net/bridge/br_stp_bpdu.o AR drivers/dma/qcom/built-in.a AR drivers/dma/ti/built-in.a AR drivers/dma/xilinx/built-in.a CC [M] net/sunrpc/auth_gss/gss_krb5_crypto.o CC [M] drivers/dma/ioat/init.o CC [M] fs/overlayfs/readdir.o CC [M] drivers/dma/ioat/dma.o AR drivers/dma/dw/built-in.a CC drivers/dma/dmaengine.o CC net/core/net-traces.o CC drivers/acpi/acpica/evsci.o CC lib/fonts/font_8x16.o CC kernel/groups.o CC net/core/selftests.o CC drivers/clk/clkdev.o CC net/handshake/request.o CC net/bridge/br_stp_if.o CC drivers/pnp/support.o CC lib/raid6/avx2.o CC [M] fs/fuse/acl.o CC [M] drivers/dma/ioat/prep.o CC [M] arch/x86/kvm/mtrr.o CC arch/x86/kernel/quirks.o CC block/bfq-wf2q.o CC net/handshake/tlshd.o AR lib/fonts/built-in.a CC lib/bug.o AR drivers/tty/hvc/built-in.a CC fs/nfs/sysfs.o CC [M] net/8021q/vlan_dev.o CC drivers/tty/vt/vc_screen.o CC drivers/tty/vt/selection.o CC drivers/acpi/acpica/evxface.o AR drivers/dma/hsu/built-in.a AR net/xfrm/built-in.a CC arch/x86/kernel/topology.o CC net/handshake/trace.o CC net/ipv4/devinet.o AR net/dcb/built-in.a CC crypto/algif_skcipher.o CC drivers/dma/virt-dma.o CC drivers/pnp/interface.o CC drivers/clk/clk.o CC [M] fs/smb/client/file.o CC kernel/vhost_task.o CC [M] fs/fuse/readdir.o CC net/ipv4/af_inet.o CC lib/raid6/avx512.o CC [M] net/bluetooth/hci_conn.o CC net/bridge/br_stp_timer.o CC drivers/dma/acpi-dma.o CC arch/x86/kernel/kdebugfs.o CC drivers/tty/serial/8250/8250_core.o CC [M] net/sunrpc/auth_gss/gss_krb5_keys.o CC fs/btrfs/disk-io.o CC drivers/virtio/virtio_anchor.o CC drivers/tty/serial/serial_core.o CC [M] fs/overlayfs/copy_up.o CC drivers/acpi/acpica/evxfevnt.o CC [M] drivers/dma/ioat/dca.o CC drivers/tty/serial/8250/8250_pnp.o CC arch/x86/kernel/alternative.o CC [M] net/dns_resolver/dns_key.o CC [M] arch/x86/kvm/hyperv.o CC [M] net/dns_resolver/dns_query.o CC [M] fs/smb/client/inode.o CC net/ipv6/ip6_fib.o CC drivers/pnp/quirks.o CC kernel/kcmp.o CC [M] drivers/dma/ioat/sysfs.o CC drivers/tty/vt/keyboard.o CC drivers/pnp/system.o CC net/ipv6/ipv6_sockglue.o CC block/bfq-cgroup.o CC net/devres.o CC mm/page_alloc.o CC fs/nfs/fs_context.o CC net/ipv4/igmp.o CC crypto/xor.o CC drivers/acpi/acpica/evxfgpe.o CC crypto/hash_info.o CC drivers/virtio/virtio_pci_modern_dev.o CC lib/raid6/recov_avx512.o CC crypto/simd.o CC [M] arch/x86/kvm/debugfs.o CC [M] crypto/md4.o CC [M] net/8021q/vlan_netlink.o AR net/handshake/built-in.a CC [M] net/8021q/vlanproc.o CC kernel/freezer.o CC [M] fs/fuse/ioctl.o CC [M] crypto/ccm.o CC mm/init-mm.o CC drivers/tty/serial/8250/8250_port.o LD [M] net/sunrpc/auth_gss/auth_rpcgss.o CC net/ipv4/fib_frontend.o CC [M] fs/smb/client/link.o LD [M] net/dns_resolver/dns_resolver.o LD [M] net/sunrpc/auth_gss/rpcsec_gss_krb5.o CC mm/memblock.o CC net/sunrpc/socklib.o LD [M] drivers/dma/ioat/ioatdma.o AR drivers/dma/built-in.a CC fs/nfs/sysctl.o CC net/bridge/br_netlink.o CC drivers/char/hw_random/core.o AR drivers/pnp/built-in.a CC net/bridge/br_netlink_tunnel.o CC fs/nfs/nfs2super.o CC [M] crypto/arc4.o CC drivers/acpi/acpica/evxfregn.o CC [M] fs/overlayfs/export.o CC drivers/char/hw_random/intel-rng.o TABLE lib/raid6/tables.c CC [M] crypto/ecc.o CC lib/raid6/int1.o CC drivers/char/agp/backend.o CC lib/zstd/decompress/huf_decompress.o CC block/blk-mq-pci.o CC drivers/virtio/virtio_pci_legacy_dev.o CC fs/nfs/proc.o CC [M] net/bluetooth/hci_event.o CC arch/x86/kernel/i8253.o CC net/bridge/br_arp_nd_proxy.o CC net/socket.o CC kernel/stacktrace.o CC drivers/acpi/acpica/exconcat.o LD [M] fs/fuse/fuse.o CC drivers/acpi/osi.o CC drivers/char/agp/generic.o AR net/8021q/built-in.a LD [M] net/8021q/8021q.o CC net/compat.o CC lib/raid6/int2.o CC fs/ext4/page-io.o CC lib/raid6/int4.o AR drivers/char/hw_random/built-in.a CC drivers/acpi/acpica/exconfig.o CC mm/memory_hotplug.o CC [M] fs/smb/client/misc.o CC drivers/tty/vt/consolemap.o LD [M] fs/overlayfs/overlay.o CC fs/nfs/nfs2xdr.o CC net/sunrpc/xprtsock.o CC arch/x86/kernel/hw_breakpoint.o CC arch/x86/kernel/tsc.o CC net/sysctl_net.o CC drivers/char/agp/isoch.o CC block/blk-mq-virtio.o CC fs/nfs/nfs3super.o CC drivers/virtio/virtio_mmio.o CC net/ipv4/fib_semantics.o CC [M] arch/x86/kvm/mmu/mmu.o CC mm/madvise.o CC kernel/dma.o CC kernel/smp.o CC net/bridge/br_sysfs_if.o CC arch/x86/kernel/tsc_msr.o CC drivers/char/tpm/tpm-chip.o CC drivers/acpi/acpica/exconvrt.o CC drivers/char/tpm/tpm-dev-common.o CC [M] arch/x86/kvm/mmu/page_track.o CC kernel/uid16.o CC lib/raid6/int8.o CC arch/x86/kernel/io_delay.o CC arch/x86/kernel/rtc.o CC block/blk-mq-debugfs.o CC [M] net/bluetooth/mgmt.o CC [M] net/bluetooth/hci_sock.o CC drivers/char/tpm/tpm-dev.o CC net/ipv6/ndisc.o CC net/sunrpc/sched.o CC drivers/tty/serial/8250/8250_dma.o CC arch/x86/kernel/resource.o CC fs/ext4/readpage.o CC [M] net/bluetooth/hci_sysfs.o HOSTCC drivers/tty/vt/conmakehash CC drivers/acpi/acpica/excreate.o CC net/ipv4/fib_trie.o CC drivers/char/agp/intel-agp.o CC lib/buildid.o CC drivers/virtio/virtio_pci_modern.o CC lib/cmdline.o CC drivers/char/mem.o AS arch/x86/kernel/irqflags.o CC arch/x86/kernel/static_call.o CC drivers/clk/clk-divider.o CC fs/nfs/nfs3client.o CC fs/nfs/nfs3proc.o CC drivers/tty/vt/vt.o CC lib/cpumask.o CC net/bridge/br_sysfs_br.o CC [M] crypto/essiv.o CC [M] fs/smb/client/netmisc.o CC drivers/clk/clk-fixed-factor.o CC fs/nfs/nfs3xdr.o CC net/ipv4/fib_notifier.o CC arch/x86/kernel/process.o CC lib/raid6/int16.o CC drivers/acpi/acpica/exdebug.o CC [M] arch/x86/kvm/mmu/spte.o CC drivers/char/tpm/tpm-interface.o CC net/core/ptp_classifier.o CC kernel/kallsyms.o CC drivers/clk/clk-fixed-rate.o CC lib/raid6/int32.o CC fs/ext4/resize.o CC net/bridge/br_nf_core.o CC drivers/char/tpm/tpm1-cmd.o CC [M] fs/smb/client/smbencrypt.o CC drivers/acpi/osl.o CC drivers/tty/serial/8250/8250_dwlib.o CC block/blk-pm.o CC drivers/acpi/utils.o CC drivers/virtio/virtio_pci_common.o CC lib/ctype.o CC fs/btrfs/transaction.o CC lib/zstd/decompress/zstd_ddict.o CC drivers/char/agp/intel-gtt.o CC lib/zstd/decompress/zstd_decompress.o AR drivers/iommu/amd/built-in.a CC drivers/acpi/reboot.o CC drivers/iommu/intel/dmar.o CC drivers/acpi/nvs.o CC drivers/acpi/acpica/exdump.o CC net/bridge/br_multicast.o CC fs/ext4/super.o CC fs/ext4/symlink.o AR drivers/tty/ipwireless/built-in.a CC drivers/char/random.o CC drivers/clk/clk-gate.o CC [M] crypto/ecdh.o CC drivers/acpi/wakeup.o CC lib/raid6/tables.o CC net/ipv4/inet_fragment.o CC drivers/tty/serial/earlycon.o CC drivers/acpi/acpica/exfield.o CC drivers/tty/tty_io.o CC block/holder.o AR drivers/gpu/host1x/built-in.a CC drivers/connector/cn_queue.o AR drivers/gpu/drm/tests/built-in.a CC [M] drivers/gpu/drm/tests/drm_kunit_helpers.o CC drivers/tty/serial/8250/8250_pcilib.o CC drivers/char/tpm/tpm2-cmd.o CC drivers/connector/connector.o CC drivers/tty/serial/8250/8250_pci.o CC drivers/acpi/sleep.o CC fs/btrfs/inode.o AR drivers/gpu/vga/built-in.a CC net/core/netprio_cgroup.o CC drivers/acpi/device_sysfs.o CC [M] drivers/gpu/drm/tests/drm_buddy_test.o CC drivers/char/tpm/tpmrm-dev.o CC drivers/clk/clk-multiplier.o CC drivers/acpi/device_pm.o CC [M] crypto/ecdh_helper.o CC drivers/virtio/virtio_pci_legacy.o CC [M] arch/x86/kvm/mmu/tdp_iter.o CC [M] arch/x86/kvm/mmu/tdp_mmu.o CC net/sunrpc/auth.o CC arch/x86/kernel/ptrace.o CC lib/zstd/decompress/zstd_decompress_block.o CC drivers/connector/cn_proc.o CC drivers/acpi/acpica/exfldio.o CC kernel/acct.o AR lib/raid6/built-in.a AR drivers/char/agp/built-in.a CC drivers/acpi/acpica/exmisc.o CC drivers/iommu/intel/iommu.o CC [M] drivers/virtio/virtio_mem.o CC net/bridge/br_mdb.o CC [M] drivers/gpu/drm/tests/drm_cmdline_parser_test.o CC mm/page_io.o CC [M] fs/smb/client/transport.o AR block/built-in.a CC drivers/acpi/acpica/exmutex.o LD [M] crypto/ecdh_generic.o CC drivers/clk/clk-mux.o AR crypto/built-in.a CC kernel/crash_core.o CC lib/dec_and_lock.o AR fs/nfs/built-in.a CC fs/char_dev.o CC drivers/char/misc.o CC net/ipv6/udp.o CC net/ipv6/udplite.o CC net/core/dst_cache.o CC drivers/acpi/acpica/exnames.o COPY drivers/tty/vt/defkeymap.c CC [M] fs/smb/client/cached_dir.o CC drivers/acpi/proc.o CC net/bridge/br_multicast_eht.o CC lib/decompress.o CC net/bridge/br_vlan.o CC lib/decompress_bunzip2.o CC lib/decompress_inflate.o CC mm/swap_state.o CC drivers/char/tpm/tpm2-space.o CC mm/swapfile.o CC drivers/acpi/acpica/exoparg1.o CC drivers/acpi/acpica/exoparg2.o CC [M] fs/smb/client/cifs_unicode.o CC drivers/clk/clk-composite.o CC net/ipv4/ping.o CC drivers/tty/serial/serial_mctrl_gpio.o CC mm/swap_slots.o CC drivers/char/tpm/tpm-sysfs.o CC kernel/compat.o CC arch/x86/kernel/tls.o AR drivers/gpu/drm/arm/built-in.a CC lib/decompress_unlz4.o AR drivers/gpu/drm/display/built-in.a CONMK drivers/tty/vt/consolemap_deftbl.c CC drivers/tty/vt/defkeymap.o CC [M] drivers/gpu/drm/display/drm_display_helper_mod.o CC drivers/tty/serial/8250/8250_exar.o CC drivers/tty/serial/8250/8250_early.o AR drivers/connector/built-in.a CC net/ipv6/raw.o CC mm/dmapool.o CC kernel/utsname.o CC lib/decompress_unlzma.o CC drivers/tty/vt/consolemap_deftbl.o CC drivers/acpi/acpica/exoparg3.o AR drivers/tty/vt/built-in.a AR drivers/virtio/built-in.a CC drivers/char/tpm/eventlog/common.o CC arch/x86/kernel/step.o CC [M] drivers/gpu/drm/tests/drm_connector_test.o CC lib/decompress_unlzo.o CC drivers/tty/n_tty.o CC [M] drivers/gpu/drm/display/drm_dp_dual_mode_helper.o CC kernel/user_namespace.o CC [M] drivers/gpu/drm/display/drm_dp_helper.o CC drivers/clk/clk-fractional-divider.o CC drivers/clk/clk-gpio.o CC net/core/gro_cells.o CC net/core/failover.o CC drivers/char/tpm/eventlog/tpm1.o CC drivers/acpi/bus.o CC drivers/base/power/sysfs.o CC drivers/block/loop.o AR drivers/misc/eeprom/built-in.a CC drivers/acpi/acpica/exoparg6.o AR drivers/misc/cb710/built-in.a CC drivers/base/firmware_loader/builtin/main.o AR drivers/misc/ti-st/built-in.a AR drivers/misc/lis3lv02d/built-in.a AR drivers/nfc/built-in.a CC drivers/mfd/mfd-core.o AR drivers/misc/cardreader/built-in.a CC drivers/base/regmap/regmap.o CC [M] drivers/misc/mei/hdcp/mei_hdcp.o CC [M] drivers/misc/mei/pxp/mei_pxp.o AR drivers/dax/hmem/built-in.a CC drivers/dax/super.o CC drivers/base/regmap/regcache.o CC arch/x86/kernel/i8237.o CC [M] fs/smb/client/nterr.o CC [M] drivers/misc/mei/init.o CC [M] drivers/gpu/drm/tests/drm_damage_helper_test.o CC net/bridge/br_vlan_tunnel.o CC net/ipv6/icmp.o CC [M] fs/smb/client/cifsencrypt.o CC fs/btrfs/file.o CC drivers/tty/serial/8250/8250_dw.o CC [M] fs/smb/client/readdir.o CC arch/x86/kernel/stacktrace.o CC [M] net/bluetooth/l2cap_core.o CC [M] drivers/gpu/drm/display/drm_dp_mst_topology.o AR drivers/misc/built-in.a CC net/bridge/br_vlan_options.o AR drivers/base/firmware_loader/builtin/built-in.a CC drivers/base/firmware_loader/main.o CC net/bridge/br_mst.o AR drivers/clk/built-in.a CC drivers/dma-buf/dma-buf.o CC drivers/acpi/acpica/exprep.o CC drivers/dma-buf/dma-fence.o CC drivers/base/power/generic_ops.o CC drivers/char/tpm/eventlog/tpm2.o CC [M] drivers/misc/mei/hbm.o CC [M] drivers/gpu/drm/tests/drm_dp_mst_helper_test.o CC [M] fs/smb/client/ioctl.o AR net/core/built-in.a CC kernel/pid_namespace.o CC [M] fs/smb/client/sess.o CC lib/decompress_unxz.o CC [M] drivers/misc/mei/interrupt.o CC net/ipv4/ip_tunnel_core.o CC arch/x86/kernel/reboot.o CC [M] drivers/misc/mei/client.o CC drivers/mfd/intel-lpss.o CC drivers/dax/bus.o CC net/ipv6/mcast.o CC drivers/acpi/acpica/exregion.o CC [M] drivers/misc/mei/main.o CC drivers/base/power/common.o CC drivers/base/regmap/regcache-rbtree.o CC drivers/tty/serial/8250/8250_lpss.o CC drivers/char/tpm/tpm_ppi.o CC drivers/char/tpm/eventlog/acpi.o CC drivers/dma-buf/dma-fence-array.o CC [M] fs/smb/client/export.o CC drivers/iommu/intel/pasid.o CC net/ipv6/reassembly.o CC drivers/acpi/acpica/exresnte.o AR drivers/base/firmware_loader/built-in.a CC drivers/acpi/glue.o CC [M] drivers/gpu/drm/tests/drm_format_helper_test.o CC net/ipv4/gre_offload.o CC lib/zstd/zstd_common_module.o CC drivers/base/power/qos.o CC net/ipv4/metrics.o UPD kernel/config_data CC kernel/stop_machine.o AR drivers/base/test/built-in.a CC drivers/mfd/intel-lpss-pci.o CC drivers/dma-buf/dma-fence-chain.o CC drivers/base/component.o CC fs/btrfs/defrag.o CC mm/hugetlb.o CC lib/decompress_unzstd.o CC lib/dump_stack.o CC drivers/block/virtio_blk.o CC drivers/iommu/intel/trace.o CC drivers/base/core.o CC [M] drivers/gpu/drm/tests/drm_format_test.o CC kernel/kprobes.o CC kernel/hung_task.o CC arch/x86/kernel/msr.o CC [M] net/bridge/br_netfilter_hooks.o CC drivers/acpi/acpica/exresolv.o CC drivers/mfd/intel-lpss-acpi.o CC lib/zstd/common/debug.o CC drivers/tty/serial/8250/8250_mid.o CC [M] fs/smb/client/unc.o CC lib/zstd/common/entropy_common.o CC net/ipv4/netlink.o CC drivers/char/tpm/eventlog/efi.o CC [M] fs/smb/client/winucase.o CC [M] drivers/misc/mei/dma-ring.o CC drivers/char/tpm/tpm_crb.o CC [M] net/bluetooth/l2cap_sock.o AR drivers/dax/built-in.a CC [M] drivers/gpu/drm/tests/drm_framebuffer_test.o CC drivers/mfd/intel_soc_pmic_crc.o CC net/ipv6/tcp_ipv6.o CC lib/zstd/common/error_private.o CC drivers/acpi/scan.o CC drivers/dma-buf/dma-fence-unwrap.o AR drivers/cxl/core/built-in.a CC net/ipv4/nexthop.o AR drivers/cxl/built-in.a CC lib/zstd/common/fse_decompress.o CC net/ipv4/udp_tunnel_stub.o CC drivers/base/bus.o CC drivers/acpi/acpica/exresop.o AR drivers/macintosh/built-in.a CC [M] arch/x86/kvm/smm.o CC [M] drivers/gpu/drm/tests/drm_managed_test.o CC drivers/acpi/acpica/exserial.o CC drivers/iommu/intel/cap_audit.o CC [M] drivers/mfd/lpc_sch.o CC [M] drivers/block/nbd.o CC [M] net/bluetooth/smp.o CC arch/x86/kernel/cpuid.o CC drivers/base/power/runtime.o CC drivers/iommu/intel/irq_remapping.o CC drivers/scsi/scsi.o CC drivers/tty/serial/8250/8250_pericom.o CC net/ipv4/sysctl_net_ipv4.o CC drivers/nvme/host/core.o CC net/sunrpc/auth_null.o AR drivers/nvme/target/built-in.a CC [M] drivers/gpu/drm/tests/drm_mm_test.o CC [M] drivers/misc/mei/bus.o CC drivers/base/dd.o CC drivers/dma-buf/dma-resv.o CC drivers/ata/libata-core.o CC drivers/scsi/hosts.o CC drivers/ata/libata-scsi.o CC drivers/acpi/acpica/exstore.o CC drivers/acpi/resource.o CC [M] drivers/mfd/lpc_ich.o CC [M] arch/x86/kvm/vmx/vmx.o CC drivers/nvme/host/ioctl.o CC drivers/base/syscore.o CC drivers/base/regmap/regcache-flat.o AR drivers/char/tpm/built-in.a CC drivers/base/regmap/regcache-maple.o CC drivers/char/virtio_console.o CC [M] fs/smb/client/smb2ops.o CC lib/earlycpio.o CC arch/x86/kernel/early-quirks.o AR drivers/gpu/drm/renesas/rcar-du/built-in.a CC lib/zstd/common/zstd_common.o AR drivers/gpu/drm/renesas/built-in.a AR drivers/gpu/drm/omapdrm/built-in.a CC drivers/base/driver.o AR drivers/gpu/drm/tilcdc/built-in.a CC drivers/base/class.o CC drivers/base/platform.o AR lib/zstd/built-in.a CC lib/extable.o CC kernel/watchdog.o CC drivers/acpi/acpica/exstoren.o AR drivers/tty/serial/8250/built-in.a AR drivers/tty/serial/built-in.a CC drivers/tty/tty_ioctl.o CC drivers/iommu/intel/perfmon.o CC fs/btrfs/extent_map.o CC [M] drivers/gpu/drm/display/drm_dsc_helper.o CC [M] drivers/gpu/drm/display/drm_hdcp_helper.o CC [M] arch/x86/kvm/kvm-asm-offsets.s CC drivers/base/regmap/regmap-debugfs.o CC arch/x86/kernel/smp.o CC kernel/watchdog_hld.o CC fs/btrfs/sysfs.o CC net/sunrpc/auth_unix.o CC drivers/base/regmap/regmap-i2c.o AR drivers/mfd/built-in.a CC lib/flex_proportions.o CC lib/idr.o CC lib/irq_regs.o CC drivers/acpi/acpica/exstorob.o CC drivers/base/power/wakeirq.o CC lib/is_single_threaded.o CC drivers/dma-buf/sync_file.o CC [M] drivers/misc/mei/bus-fixup.o CC [M] net/bluetooth/lib.o CC drivers/acpi/acpica/exsystem.o CC drivers/acpi/acpica/extrace.o CC drivers/scsi/scsi_ioctl.o CC kernel/seccomp.o CC drivers/dma-buf/sw_sync.o CC arch/x86/kernel/smpboot.o CC drivers/nvme/host/trace.o CC fs/ext4/sysfs.o CC net/ipv4/proc.o CC [M] net/bridge/br_netfilter_ipv6.o CC fs/ext4/xattr.o CC drivers/char/hpet.o CC drivers/base/cpu.o CC drivers/base/regmap/regmap-irq.o CC drivers/tty/tty_ldisc.o CC [M] arch/x86/kvm/vmx/pmu_intel.o CC [M] arch/x86/kvm/vmx/vmcs12.o CC [M] drivers/gpu/drm/display/drm_hdmi_helper.o CC drivers/acpi/acpica/exutils.o CC lib/klist.o CC drivers/base/power/main.o CC drivers/tty/tty_buffer.o CC net/ipv4/syncookies.o CC fs/ext4/xattr_hurd.o AR drivers/block/built-in.a CC drivers/nvme/host/fault_inject.o CC arch/x86/kernel/tsc_sync.o CC drivers/acpi/acpica/hwacpi.o CC fs/ext4/xattr_trusted.o CC [M] drivers/gpu/drm/display/drm_scdc_helper.o CC drivers/nvme/host/pci.o CC [M] drivers/misc/mei/debugfs.o CC net/ipv4/esp4.o CC [M] drivers/gpu/drm/tests/drm_modes_test.o CC net/sunrpc/svc.o AR drivers/iommu/intel/built-in.a AR drivers/iommu/arm/arm-smmu/built-in.a AR drivers/iommu/arm/arm-smmu-v3/built-in.a AR drivers/iommu/arm/built-in.a AR drivers/iommu/iommufd/built-in.a CC drivers/iommu/iommu.o CC net/ipv6/ping.o CC lib/kobject.o AR drivers/gpu/drm/imx/built-in.a AR drivers/gpu/drm/i2c/built-in.a AR drivers/gpu/drm/panel/built-in.a AR drivers/gpu/drm/hisilicon/built-in.a AR drivers/gpu/drm/bridge/analogix/built-in.a CC drivers/dma-buf/sync_debug.o AR drivers/gpu/drm/bridge/cadence/built-in.a CC drivers/tty/tty_port.o AR drivers/gpu/drm/bridge/imx/built-in.a CC drivers/tty/tty_mutex.o AR drivers/gpu/drm/bridge/synopsys/built-in.a AR drivers/gpu/drm/bridge/built-in.a CC drivers/acpi/acpica/hwesleep.o CC drivers/scsi/scsicam.o CC drivers/scsi/scsi_error.o CC drivers/scsi/scsi_lib.o CC drivers/scsi/scsi_lib_dma.o CC drivers/acpi/acpica/hwgpe.o CC lib/kobject_uevent.o CC [M] net/bluetooth/ecdh_helper.o CC net/sunrpc/svcsock.o CC drivers/tty/tty_ldsem.o CC [M] drivers/gpu/drm/tests/drm_plane_helper_test.o CC drivers/tty/tty_baudrate.o CC [M] arch/x86/kvm/vmx/hyperv.o CC fs/ext4/xattr_user.o CC [M] arch/x86/kvm/vmx/nested.o CC [M] drivers/misc/mei/mei-trace.o CC drivers/char/nvram.o CC fs/btrfs/accessors.o AR drivers/gpu/drm/mxsfb/built-in.a CC drivers/iommu/iommu-traces.o CC [M] drivers/gpu/drm/display/drm_dp_aux_dev.o CC [M] drivers/gpu/drm/tests/drm_probe_helper_test.o CC arch/x86/kernel/setup_percpu.o CC net/sunrpc/svcauth.o CC [M] drivers/gpu/drm/tests/drm_rect_test.o AR net/bridge/built-in.a LD [M] net/bridge/br_netfilter.o CC [M] drivers/dma-buf/selftest.o CC drivers/tty/tty_jobctrl.o CC [M] drivers/dma-buf/st-dma-fence.o CC drivers/acpi/acpica/hwregs.o CC arch/x86/kernel/ftrace.o AR drivers/base/regmap/built-in.a CC drivers/iommu/iommu-sysfs.o CC net/sunrpc/svcauth_unix.o CC drivers/iommu/dma-iommu.o CC [M] net/bluetooth/hci_request.o CC drivers/iommu/iova.o CC drivers/acpi/acpica/hwsleep.o CC drivers/base/power/wakeup.o CC kernel/relay.o CC fs/btrfs/xattr.o CC drivers/acpi/acpi_processor.o CC drivers/tty/n_null.o CC drivers/iommu/irq_remapping.o CC drivers/tty/pty.o CC drivers/ata/libata-eh.o CC fs/ext4/fast_commit.o CC net/ipv6/exthdrs.o CC fs/ext4/orphan.o CC [M] drivers/dma-buf/st-dma-fence-chain.o CC [M] drivers/misc/mei/pci-me.o CC [M] drivers/misc/mei/hw-me.o AR drivers/char/built-in.a CC drivers/spi/spi.o CC lib/logic_pio.o CC drivers/acpi/acpica/hwvalid.o CC [M] fs/smb/client/smb2maperror.o AR drivers/gpu/drm/tiny/built-in.a CC net/ipv6/datagram.o CC lib/maple_tree.o CC [M] arch/x86/kvm/vmx/posted_intr.o CC drivers/net/phy/mdio-boardinfo.o AR drivers/net/pse-pd/built-in.a CC [M] drivers/dma-buf/st-dma-fence-unwrap.o LD [M] drivers/gpu/drm/display/drm_display_helper.o LD [M] arch/x86/kvm/kvm.o CC drivers/net/mdio/acpi_mdio.o AR drivers/net/pcs/built-in.a CC drivers/tty/sysrq.o AR drivers/gpu/drm/xlnx/built-in.a AR drivers/gpu/drm/gud/built-in.a AS arch/x86/kernel/ftrace_64.o AR drivers/gpu/drm/solomon/built-in.a CC mm/hugetlb_vmemmap.o CC net/ipv4/esp4_offload.o CC [M] drivers/gpu/drm/ttm/ttm_tt.o CC arch/x86/kernel/trace_clock.o CC arch/x86/kernel/trace.o AR drivers/net/ethernet/adi/built-in.a AR drivers/net/ethernet/alacritech/built-in.a UPD arch/x86/kvm/kvm-asm-offsets.h AR drivers/net/ethernet/amazon/built-in.a CC drivers/ata/libata-transport.o AR drivers/net/ethernet/aquantia/built-in.a AR drivers/net/ethernet/asix/built-in.a AR drivers/net/ethernet/cadence/built-in.a CC drivers/base/power/wakeup_stats.o CC net/ipv6/ip6_flowlabel.o CC [M] drivers/dma-buf/st-dma-resv.o AR drivers/net/ethernet/broadcom/built-in.a CC [M] drivers/net/ethernet/broadcom/b44.o CC [M] drivers/net/ethernet/broadcom/bnx2.o CC drivers/acpi/acpica/hwxface.o AS [M] arch/x86/kvm/vmx/vmenter.o CC net/ipv6/inet6_connection_sock.o CC net/ipv4/netfilter.o AR drivers/net/ethernet/cavium/common/built-in.a AR drivers/net/ethernet/cavium/thunder/built-in.a AR drivers/net/ethernet/cavium/liquidio/built-in.a AR drivers/net/ethernet/cortina/built-in.a AR drivers/net/ethernet/engleder/built-in.a AR drivers/net/ethernet/cavium/octeon/built-in.a CC lib/memcat_p.o AR drivers/net/ethernet/ezchip/built-in.a AR drivers/net/ethernet/cavium/built-in.a AR drivers/net/ethernet/fungible/built-in.a AR drivers/net/ethernet/huawei/built-in.a CC lib/nmi_backtrace.o CC net/sunrpc/addr.o CC kernel/utsname_sysctl.o CC [M] drivers/net/ethernet/intel/e1000/e1000_main.o CC [M] drivers/net/ethernet/intel/e1000e/82571.o CC [M] drivers/net/ethernet/intel/igb/igb_main.o CC [M] drivers/net/ethernet/intel/igc/igc_main.o CC drivers/scsi/scsi_scan.o CC net/sunrpc/rpcb_clnt.o CC [M] drivers/net/ethernet/intel/igbvf/vf.o CC arch/x86/kernel/rethook.o AR drivers/iommu/built-in.a CC drivers/net/phy/mdio_devres.o CC drivers/net/phy/phy.o CC fs/btrfs/ordered-data.o CC [M] net/bluetooth/mgmt_util.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_main.o CC drivers/acpi/acpica/hwxfsleep.o CC drivers/net/mdio/fwnode_mdio.o CC drivers/base/power/domain.o AR drivers/net/usb/built-in.a CC [M] drivers/net/usb/pegasus.o AR drivers/nvme/host/built-in.a AR drivers/nvme/built-in.a CC kernel/delayacct.o CC kernel/taskstats.o AR drivers/dma-buf/built-in.a LD [M] drivers/dma-buf/dmabuf_selftests.o CC [M] drivers/net/ipvlan/ipvlan_core.o AR drivers/net/ethernet/i825xx/built-in.a CC kernel/tsacct.o CC [M] drivers/net/ipvlan/ipvlan_main.o CC [M] drivers/gpu/drm/ttm/ttm_bo.o CC mm/sparse.o AR drivers/tty/built-in.a AR drivers/firewire/built-in.a AR drivers/cdrom/built-in.a AR drivers/auxdisplay/built-in.a CC [M] drivers/net/ethernet/broadcom/cnic.o CC drivers/usb/common/common.o CC drivers/usb/common/debug.o CC [M] drivers/net/ethernet/broadcom/tg3.o CC drivers/ata/libata-trace.o CC arch/x86/kernel/crash_core_64.o CC drivers/acpi/acpica/hwpci.o AR drivers/net/ethernet/microsoft/built-in.a CC fs/stat.o CC fs/exec.o CC fs/pipe.o CC fs/btrfs/extent_io.o CC [M] fs/smb/client/smb2transport.o CC net/ipv4/inet_diag.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_common.o CC drivers/usb/core/usb.o CC [M] drivers/misc/mei/gsc-me.o AR drivers/usb/phy/built-in.a CC net/ipv4/tcp_diag.o CC mm/sparse-vmemmap.o CC [M] drivers/net/ethernet/intel/igbvf/mbx.o CC drivers/net/phy/phy-c45.o CC net/sunrpc/timer.o AR drivers/net/mdio/built-in.a CC [M] drivers/net/ethernet/intel/igc/igc_mac.o CC drivers/acpi/acpica/nsaccess.o CC net/ipv6/udp_offload.o CC arch/x86/kernel/module.o CC [M] drivers/net/ethernet/intel/igbvf/ethtool.o CC [M] net/bluetooth/mgmt_config.o CC kernel/tracepoint.o AR fs/ext4/built-in.a AR drivers/usb/common/built-in.a CC fs/btrfs/volumes.o CC fs/btrfs/async-thread.o GEN drivers/scsi/scsi_devinfo_tbl.c CC drivers/scsi/scsi_devinfo.o CC [M] drivers/net/ethernet/intel/e1000e/ich8lan.o CC [M] drivers/net/ethernet/intel/e1000e/80003es2lan.o CC [M] drivers/gpu/drm/ttm/ttm_bo_util.o CC [M] drivers/net/ethernet/intel/e1000e/mac.o CC [M] drivers/net/ethernet/intel/e1000e/manage.o LD [M] drivers/misc/mei/mei.o CC drivers/acpi/acpica/nsalloc.o LD [M] drivers/misc/mei/mei-me.o CC [M] drivers/net/usb/rtl8150.o CC drivers/net/phy/phy-core.o LD [M] drivers/misc/mei/mei-gsc.o CC mm/mmu_notifier.o CC [M] net/bluetooth/hci_codec.o CC net/ipv4/udp_diag.o CC drivers/input/serio/serio.o CC net/ipv4/tcp_cubic.o CC drivers/ata/libata-sata.o CC fs/namei.o CC arch/x86/kernel/early_printk.o CC drivers/base/power/domain_governor.o CC drivers/usb/core/hub.o CC [M] drivers/net/ipvlan/ipvlan_l3s.o CC [M] drivers/net/ethernet/intel/e1000/e1000_hw.o CC net/sunrpc/xdr.o CC net/sunrpc/sunrpc_syms.o CC kernel/latencytop.o CC drivers/input/keyboard/atkbd.o CC drivers/acpi/acpica/nsarguments.o CC drivers/scsi/scsi_sysctl.o CC drivers/acpi/acpica/nsconvert.o CC drivers/scsi/scsi_debugfs.o CC [M] drivers/net/ethernet/intel/igbvf/netdev.o AR drivers/spi/built-in.a CC net/sunrpc/cache.o CC net/ipv4/xfrm4_policy.o CC net/ipv6/seg6.o CC arch/x86/kernel/hpet.o CC drivers/ata/libata-sff.o CC drivers/base/power/clock_ops.o CC [M] drivers/gpu/drm/ttm/ttm_bo_vm.o CC [M] fs/smb/client/smb2misc.o CC fs/btrfs/ioctl.o CC drivers/acpi/acpica/nsdump.o CC drivers/input/serio/i8042.o CC net/ipv6/fib6_notifier.o AR drivers/input/mouse/built-in.a CC drivers/net/phy/phy_device.o CC drivers/input/input.o CC kernel/irq_work.o CC drivers/net/phy/linkmode.o CC mm/ksm.o CC [M] net/bluetooth/eir.o CC [M] drivers/net/ethernet/intel/e1000e/nvm.o CC drivers/acpi/processor_core.o CC drivers/net/phy/mdio_bus.o CC drivers/input/input-compat.o CC drivers/scsi/scsi_trace.o CC [M] drivers/net/usb/r8152.o CC drivers/acpi/acpica/nseval.o CC [M] drivers/net/ethernet/intel/e1000e/phy.o CC [M] net/bluetooth/hci_sync.o CC drivers/base/firmware.o LD [M] drivers/net/ipvlan/ipvlan.o CC drivers/input/serio/libps2.o CC mm/slub.o AR drivers/base/power/built-in.a CC arch/x86/kernel/amd_nb.o AR drivers/input/keyboard/built-in.a CC drivers/input/input-mt.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ethtool.o CC [M] drivers/gpu/drm/ttm/ttm_module.o CC [M] drivers/net/ethernet/intel/igb/igb_ethtool.o CC drivers/acpi/acpica/nsinit.o CC net/ipv4/xfrm4_state.o CC kernel/static_call.o CC [M] net/bluetooth/coredump.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82599.o CC mm/migrate.o CC arch/x86/kernel/kvm.o CC drivers/base/init.o CC arch/x86/kernel/kvmclock.o CC net/ipv6/rpl.o CC drivers/scsi/scsi_logging.o LD [M] arch/x86/kvm/kvm-intel.o CC kernel/static_call_inline.o CC [M] drivers/gpu/drm/ttm/ttm_execbuf_util.o CC [M] net/bluetooth/sco.o CC drivers/acpi/acpica/nsload.o CC [M] net/bluetooth/iso.o CC drivers/input/input-poller.o AR drivers/input/serio/built-in.a CC drivers/base/map.o CC arch/x86/kernel/paravirt.o CC net/ipv4/xfrm4_input.o CC mm/migrate_device.o CC [M] drivers/net/usb/asix_devices.o CC fs/btrfs/locking.o CC [M] fs/smb/client/smb2pdu.o CC arch/x86/kernel/pvclock.o CC [M] drivers/net/vxlan/vxlan_core.o CC drivers/acpi/acpica/nsnames.o CC [M] drivers/net/vxlan/vxlan_multicast.o CC [M] drivers/net/ethernet/intel/igc/igc_i225.o CC kernel/user-return-notifier.o CC fs/fcntl.o LD [M] drivers/net/ethernet/intel/igbvf/igbvf.o CC drivers/base/devres.o CC [M] drivers/net/ethernet/intel/ixgbevf/vf.o CC net/sunrpc/rpc_pipe.o CC drivers/scsi/scsi_pm.o CC drivers/input/ff-core.o CC lib/plist.o CC [M] drivers/gpu/drm/ttm/ttm_range_manager.o CC [M] drivers/net/ethernet/intel/e1000/e1000_ethtool.o CC drivers/ata/libata-pmp.o CC drivers/input/touchscreen.o CC net/ipv6/ioam6.o CC kernel/padata.o CC net/sunrpc/sysfs.o CC drivers/net/phy/mdio_device.o CC [M] drivers/net/ethernet/intel/e1000/e1000_param.o CC kernel/jump_label.o CC mm/huge_memory.o CC net/sunrpc/svc_xprt.o CC drivers/acpi/acpica/nsobject.o CC arch/x86/kernel/pcspeaker.o CC [M] net/bluetooth/a2mp.o CC [M] drivers/net/ethernet/intel/e1000e/param.o CC lib/radix-tree.o CC net/ipv4/xfrm4_output.o CC lib/ratelimit.o CC drivers/input/ff-memless.o CC drivers/input/vivaldi-fmap.o CC drivers/scsi/scsi_bsg.o CC [M] drivers/gpu/drm/ttm/ttm_resource.o CC [M] drivers/net/ethernet/intel/igb/e1000_82575.o CC drivers/acpi/acpica/nsparse.o CC arch/x86/kernel/check.o CC drivers/base/attribute_container.o CC [M] drivers/net/ethernet/intel/igc/igc_base.o CC drivers/usb/core/hcd.o CC [M] drivers/net/usb/asix_common.o CC drivers/net/phy/swphy.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_82598.o CC arch/x86/kernel/uprobes.o CC drivers/acpi/acpica/nspredef.o CC [M] drivers/net/ethernet/intel/igc/igc_nvm.o CC [M] drivers/net/usb/ax88172a.o CC [M] drivers/net/ethernet/intel/ixgbevf/mbx.o CC kernel/context_tracking.o CC [M] drivers/net/ethernet/intel/ixgbevf/ethtool.o CC fs/ioctl.o CC [M] drivers/net/ethernet/intel/e1000e/ethtool.o CC drivers/ata/libata-acpi.o CC net/sunrpc/xprtmultipath.o CC arch/x86/kernel/perf_regs.o CC arch/x86/kernel/tracepoint.o CC drivers/base/transport_class.o CC [M] drivers/net/ethernet/intel/e1000e/netdev.o CC net/ipv4/xfrm4_protocol.o CC drivers/scsi/scsi_common.o CC mm/khugepaged.o CC kernel/iomem.o CC fs/btrfs/orphan.o CC net/ipv6/sysctl_net_ipv6.o CC [M] net/bluetooth/amp.o CC drivers/acpi/acpica/nsprepkg.o CC drivers/acpi/acpica/nsrepair.o CC drivers/base/topology.o CC drivers/input/input-leds.o CC drivers/net/phy/fixed_phy.o CC lib/rbtree.o CC [M] drivers/gpu/drm/ttm/ttm_pool.o CC [M] net/bluetooth/hci_debugfs.o CC drivers/net/loopback.o CC [M] drivers/gpu/drm/ttm/ttm_device.o CC net/ipv6/xfrm6_policy.o CC drivers/ata/libata-pata-timings.o CC drivers/acpi/acpica/nsrepair2.o CC [M] drivers/net/ethernet/intel/igc/igc_phy.o CC drivers/scsi/sd.o CC [M] drivers/net/ethernet/intel/e1000e/ptp.o CC lib/seq_buf.o CC arch/x86/kernel/itmt.o CC [M] drivers/net/vxlan/vxlan_vnifilter.o LD [M] drivers/net/ethernet/intel/e1000/e1000.o AR drivers/net/ethernet/intel/built-in.a CC net/ipv6/xfrm6_state.o CC net/ipv6/xfrm6_input.o CC [M] drivers/net/usb/ax88179_178a.o CC lib/show_mem.o CC kernel/rseq.o CC [M] drivers/net/ethernet/intel/igc/igc_diag.o CC [M] drivers/net/ethernet/intel/igc/igc_ethtool.o CC drivers/base/container.o CC net/sunrpc/stats.o CC [M] drivers/net/usb/cdc_ether.o CC net/ipv6/xfrm6_output.o CC net/ipv6/xfrm6_protocol.o CC drivers/input/mousedev.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_phy.o CC drivers/ata/ahci.o CC [M] fs/smb/client/smb2inode.o CC drivers/acpi/acpica/nssearch.o CC net/ipv6/netfilter.o CC [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf_main.o CC [M] net/ipv4/ip_tunnel.o CC drivers/base/property.o CC fs/btrfs/export.o CC drivers/usb/core/urb.o CC [M] drivers/net/ethernet/intel/ixgbevf/ipsec.o CC [M] fs/smb/client/smb2file.o CC drivers/acpi/acpica/nsutils.o CC drivers/base/cacheinfo.o CC arch/x86/kernel/umip.o CC [M] drivers/net/ethernet/intel/igb/e1000_mac.o CC lib/siphash.o CC [M] drivers/gpu/drm/ttm/ttm_sys_manager.o CC arch/x86/kernel/unwind_orc.o CC [M] drivers/net/phy/phylink.o CC net/sunrpc/sysctl.o CC [M] drivers/net/ethernet/intel/igc/igc_ptp.o CC [M] fs/smb/client/cifsacl.o CC [M] drivers/net/ethernet/intel/igc/igc_dump.o CC [M] fs/smb/client/fs_context.o CC fs/btrfs/tree-log.o CC fs/readdir.o CC fs/select.o GZIP kernel/config_data.gz CC drivers/input/evdev.o CC kernel/configs.o CC lib/string.o CC drivers/acpi/acpica/nswalk.o CC lib/timerqueue.o AR drivers/net/ethernet/litex/built-in.a AR drivers/net/ethernet/microchip/built-in.a CC [M] drivers/net/usb/cdc_eem.o CC fs/dcache.o CC [M] drivers/gpu/drm/ttm/ttm_agp_backend.o CC net/ipv6/fib6_rules.o CC [M] drivers/net/ethernet/intel/igc/igc_tsn.o LD [M] net/bluetooth/bluetooth.o CC lib/vsprintf.o CC [M] net/ipv4/udp_tunnel_core.o CC net/ipv6/proc.o CC arch/x86/kernel/callthunks.o CC arch/x86/kernel/mmconf-fam10h_64.o CC drivers/usb/core/message.o CC lib/win_minmax.o CC drivers/ata/libahci.o AR kernel/built-in.a CC arch/x86/kernel/vsmp_64.o CC [M] net/ipv4/udp_tunnel_nic.o CC drivers/acpi/acpica/nsxfeval.o CC drivers/base/swnode.o CC [M] fs/smb/client/dns_resolve.o CC [M] drivers/gpu/drm/scheduler/sched_main.o CC drivers/base/auxiliary.o CC lib/xarray.o CC [M] drivers/net/phy/aquantia_main.o CC drivers/rtc/lib.o CC [M] drivers/gpu/drm/scheduler/sched_fence.o AR net/sunrpc/built-in.a CC [M] drivers/gpu/drm/scheduler/sched_entity.o CC [M] drivers/net/phy/aquantia_hwmon.o LD [M] drivers/gpu/drm/ttm/ttm.o CC drivers/rtc/class.o CC drivers/ata/ata_piix.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_drv.o CC [M] drivers/net/phy/ax88796b.o CC [M] drivers/net/ethernet/intel/igb/e1000_nvm.o CC [M] drivers/net/phy/bcm7xxx.o CC fs/inode.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sriov.o CC drivers/base/devtmpfs.o CC fs/btrfs/free-space-cache.o CC [M] drivers/net/ethernet/intel/igc/igc_xdp.o CC [M] drivers/net/usb/smsc75xx.o AR drivers/input/built-in.a CC drivers/acpi/acpica/nsxfname.o AR drivers/i2c/algos/built-in.a CC [M] drivers/net/vxlan/vxlan_mdb.o CC [M] drivers/i2c/algos/i2c-algo-bit.o CC drivers/i2c/busses/i2c-designware-common.o AR arch/x86/kernel/built-in.a CC drivers/scsi/sg.o CC drivers/i2c/busses/i2c-designware-master.o CC drivers/base/memory.o AR arch/x86/built-in.a CC drivers/base/module.o CC drivers/acpi/acpica/nsxfobj.o CC fs/btrfs/zlib.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_mbx.o CC net/ipv6/syncookies.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x540.o CC drivers/rtc/interface.o CC [M] drivers/gpu/drm/amd/amdxcp/amdgpu_xcp_drv.o CC drivers/acpi/acpica/psargs.o CC net/ipv6/mip6.o CC [M] drivers/gpu/drm/i915/i915_driver.o CC mm/page_counter.o CC [M] drivers/gpu/drm/i915/i915_drm_client.o CC drivers/acpi/acpica/psloop.o CC [M] drivers/gpu/drm/i915/i915_config.o CC mm/memcontrol.o CC [M] drivers/gpu/drm/i915/i915_getparam.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_x550.o CC drivers/rtc/nvmem.o ASN.1 fs/smb/client/cifs_spnego_negtokeninit.asn1.[ch] CC [M] fs/smb/client/smb1ops.o CC net/ipv6/addrconf_core.o CC drivers/net/netconsole.o CC [M] drivers/net/phy/bcm87xx.o CC [M] drivers/gpu/drm/i915/i915_ioctl.o CC drivers/usb/core/driver.o LD [M] drivers/gpu/drm/amd/amdxcp/amdxcp.o CC fs/attr.o CC [M] drivers/net/ethernet/intel/igb/e1000_phy.o CC [M] drivers/gpu/drm/vgem/vgem_drv.o CC drivers/base/pinctrl.o LD [M] drivers/gpu/drm/scheduler/gpu-sched.o CC drivers/usb/core/config.o AR net/ipv4/built-in.a CC [M] drivers/gpu/drm/xe/tests/xe_bo_test.o LD [M] drivers/net/ethernet/intel/igc/igc.o LD [M] net/ipv4/udp_tunnel.o CC drivers/usb/core/file.o CC [M] drivers/gpu/drm/xe/tests/xe_dma_buf_test.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_lib.o CC [M] drivers/gpu/drm/i915/i915_irq.o CC [M] drivers/gpu/drm/nouveau/nvif/object.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ptp.o CC drivers/i2c/busses/i2c-designware-platdrv.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_device.o CC [M] drivers/gpu/drm/vgem/vgem_fence.o CC drivers/acpi/acpica/psobject.o AR drivers/i2c/muxes/built-in.a CC [M] drivers/i2c/muxes/i2c-mux-gpio.o CC drivers/rtc/dev.o CC drivers/rtc/proc.o CC lib/lockref.o CC drivers/rtc/sysfs.o AR drivers/ata/built-in.a CC drivers/usb/core/buffer.o CC [M] drivers/gpu/drm/xe/tests/xe_migrate_test.o CC drivers/i2c/i2c-boardinfo.o CC [M] drivers/gpu/drm/xe/tests/xe_pci_test.o CC drivers/base/devcoredump.o CC [M] fs/smb/client/cifssmb.o CC [M] drivers/net/phy/bcm-phy-lib.o CC fs/bad_inode.o CC [M] drivers/gpu/drm/i915/i915_mitigations.o CC [M] drivers/gpu/drm/i915/i915_module.o LD [M] drivers/net/ethernet/intel/ixgbevf/ixgbevf.o CC drivers/acpi/acpica/psopcode.o CC drivers/acpi/processor_pdc.o CC drivers/usb/core/sysfs.o CC drivers/acpi/acpica/psopinfo.o CC drivers/rtc/rtc-mc146818-lib.o CC drivers/i2c/busses/i2c-designware-baytrail.o CC [M] drivers/net/usb/smsc95xx.o CC drivers/acpi/acpica/psparse.o CC drivers/scsi/scsi_sysfs.o LD [M] drivers/gpu/drm/vgem/vgem.o CC lib/bcd.o CC [M] drivers/gpu/drm/i915/i915_params.o CC net/ipv6/exthdrs_core.o CC net/ipv6/ip6_checksum.o CC [M] drivers/gpu/drm/xe/tests/xe_rtp_test.o CC drivers/usb/host/pci-quirks.o CC lib/sort.o CC drivers/usb/host/ehci-hcd.o CC drivers/usb/host/ehci-pci.o LD [M] drivers/net/ethernet/intel/e1000e/e1000e.o CC drivers/usb/core/endpoint.o CC drivers/usb/host/ohci-hcd.o CC drivers/usb/host/ohci-pci.o CC drivers/net/virtio_net.o CC lib/parser.o CC [M] drivers/gpu/drm/nouveau/nvif/client.o CC drivers/usb/storage/scsiglue.o CC drivers/rtc/rtc-cmos.o CC drivers/i2c/i2c-core-base.o CC drivers/usb/storage/protocol.o CC lib/debug_locks.o CC fs/file.o CC drivers/i2c/i2c-core-smbus.o CC drivers/base/platform-msi.o LD [M] drivers/net/vxlan/vxlan.o CC drivers/base/physical_location.o CC [M] drivers/gpu/drm/i915/i915_pci.o CC drivers/usb/core/devio.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_xsk.o CC [M] drivers/gpu/drm/i915/i915_scatterlist.o CC drivers/acpi/acpica/psscope.o CC [M] drivers/i2c/busses/i2c-scmi.o CC drivers/acpi/ec.o CC drivers/usb/core/notify.o CC [M] drivers/gpu/drm/nouveau/nvif/conn.o CC lib/random32.o CC fs/btrfs/lzo.o CC drivers/i2c/i2c-core-acpi.o CC [M] drivers/net/ethernet/intel/igb/e1000_mbx.o CC drivers/usb/host/uhci-hcd.o CC drivers/usb/core/generic.o CC drivers/net/net_failover.o CC drivers/usb/host/xhci.o CC [M] drivers/gpu/drm/xe/tests/xe_wa_test.o CC [M] drivers/net/dummy.o CC [M] drivers/net/ethernet/intel/igb/e1000_i210.o CC [M] drivers/net/ethernet/intel/e100.o CC [M] drivers/gpu/drm/nouveau/nvif/device.o CC drivers/base/trace.o CC [M] drivers/net/phy/broadcom.o CC drivers/acpi/acpica/pstree.o CC [M] drivers/gpu/drm/i915/i915_suspend.o CC drivers/usb/core/quirks.o CC [M] drivers/net/macvlan.o CC drivers/usb/storage/transport.o CC [M] drivers/gpu/drm/nouveau/nvif/disp.o CC lib/bust_spinlocks.o CC lib/kasprintf.o CC drivers/usb/storage/usb.o CC drivers/usb/host/xhci-mem.o CC drivers/usb/host/xhci-ext-caps.o CC net/ipv6/ip6_icmp.o CC [M] fs/smb/client/cifs_spnego_negtokeninit.asn1.o AR drivers/net/ethernet/mscc/built-in.a CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb.o CC [M] drivers/net/usb/mcs7830.o AR drivers/rtc/built-in.a AR drivers/i3c/built-in.a AR drivers/media/i2c/built-in.a AR drivers/ptp/built-in.a CC [M] drivers/ptp/ptp_clock.o AR drivers/media/tuners/built-in.a AR drivers/media/rc/keymaps/built-in.a AR drivers/media/rc/built-in.a CC [M] drivers/i2c/busses/i2c-ccgx-ucsi.o CC drivers/acpi/acpica/psutils.o AR drivers/media/common/b2c2/built-in.a CC lib/bitmap.o AR drivers/media/common/saa7146/built-in.a AR drivers/media/common/siano/built-in.a AR drivers/scsi/built-in.a CC lib/scatterlist.o CC fs/btrfs/zstd.o AR drivers/media/common/v4l2-tpg/built-in.a AR drivers/media/common/videobuf2/built-in.a AR drivers/media/common/built-in.a AR drivers/power/reset/built-in.a AR drivers/media/platform/allegro-dvt/built-in.a CC drivers/power/supply/power_supply_core.o AR drivers/media/platform/amlogic/meson-ge2d/built-in.a AR drivers/media/platform/amlogic/built-in.a AR drivers/media/platform/amphion/built-in.a AR drivers/media/platform/aspeed/built-in.a AR drivers/media/platform/atmel/built-in.a AR drivers/media/platform/cadence/built-in.a AR drivers/media/pci/ttpci/built-in.a AR drivers/media/usb/b2c2/built-in.a AR drivers/media/pci/b2c2/built-in.a AR drivers/media/platform/chips-media/built-in.a AR drivers/media/platform/intel/built-in.a AR drivers/media/usb/dvb-usb/built-in.a CC [M] drivers/net/mii.o AR drivers/media/pci/pluto2/built-in.a CC lib/list_sort.o AR drivers/media/usb/dvb-usb-v2/built-in.a AR drivers/media/platform/marvell/built-in.a AR drivers/media/pci/dm1105/built-in.a AR drivers/media/usb/s2255/built-in.a AR drivers/media/platform/mediatek/jpeg/built-in.a AR drivers/media/pci/pt1/built-in.a AR drivers/media/usb/siano/built-in.a AR drivers/base/built-in.a AR drivers/media/platform/mediatek/mdp/built-in.a CC [M] drivers/gpu/drm/xe/xe_bb.o AR drivers/media/pci/pt3/built-in.a AR drivers/media/usb/ttusb-budget/built-in.a CC [M] drivers/net/mdio.o AR drivers/media/usb/ttusb-dec/built-in.a AR drivers/media/platform/mediatek/vcodec/built-in.a AR drivers/media/pci/mantis/built-in.a AR drivers/media/usb/built-in.a AR drivers/media/pci/ngene/built-in.a CC [M] drivers/gpu/drm/xe/xe_bo.o AR drivers/media/platform/mediatek/vpu/built-in.a AR drivers/media/pci/ddbridge/built-in.a CC [M] drivers/net/usb/usbnet.o CC [M] drivers/net/usb/cdc_ncm.o CC lib/uuid.o AR drivers/media/platform/mediatek/mdp3/built-in.a AR drivers/media/pci/saa7146/built-in.a AR drivers/media/platform/mediatek/built-in.a AR drivers/media/pci/smipcie/built-in.a AR drivers/media/platform/microchip/built-in.a AR drivers/media/pci/netup_unidvb/built-in.a CC [M] drivers/gpu/drm/nouveau/nvif/driver.o CC lib/iov_iter.o AR drivers/media/platform/nvidia/tegra-vde/built-in.a AR drivers/media/platform/nvidia/built-in.a AR drivers/media/platform/nxp/dw100/built-in.a AR drivers/media/pci/intel/ipu3/built-in.a AR drivers/media/pci/intel/built-in.a AR drivers/media/platform/nxp/imx-jpeg/built-in.a AR drivers/media/platform/nxp/imx8-isi/built-in.a AR drivers/media/pci/built-in.a AR drivers/media/platform/nxp/built-in.a AR drivers/net/ethernet/neterion/built-in.a AR drivers/net/ethernet/netronome/built-in.a CC drivers/i2c/i2c-core-slave.o CC net/ipv6/output_core.o CC [M] drivers/net/ethernet/intel/igb/igb_ptp.o AR drivers/media/platform/qcom/camss/built-in.a CC [M] drivers/gpu/drm/nouveau/nvif/event.o AR drivers/media/platform/qcom/venus/built-in.a AR drivers/media/platform/qcom/built-in.a CC drivers/acpi/acpica/pswalk.o CC [M] drivers/gpu/drm/nouveau/nvif/fifo.o AR drivers/media/platform/renesas/rcar-vin/built-in.a AR drivers/media/platform/renesas/rzg2l-cru/built-in.a CC [M] drivers/net/ethernet/intel/igb/igb_hwmon.o AR drivers/media/platform/renesas/vsp1/built-in.a AR drivers/media/platform/renesas/built-in.a CC [M] drivers/gpu/drm/nouveau/nvif/head.o AR drivers/media/platform/rockchip/rga/built-in.a CC [M] drivers/net/phy/lxt.o AR drivers/media/platform/rockchip/rkisp1/built-in.a AR drivers/media/platform/rockchip/built-in.a CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_kms.o AR drivers/media/platform/samsung/exynos-gsc/built-in.a CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82598.o CC drivers/power/supply/power_supply_sysfs.o AR drivers/media/platform/samsung/exynos4-is/built-in.a AR drivers/media/platform/samsung/s3c-camif/built-in.a AR drivers/media/platform/samsung/s5p-g2d/built-in.a AR drivers/media/platform/samsung/s5p-jpeg/built-in.a AR drivers/media/platform/samsung/s5p-mfc/built-in.a CC drivers/usb/serial/usb-serial.o AR drivers/media/platform/samsung/built-in.a CC drivers/usb/storage/initializers.o AR drivers/media/platform/st/sti/bdisp/built-in.a CC drivers/usb/storage/sierra_ms.o AR drivers/media/platform/st/sti/c8sectpfe/built-in.a CC [M] drivers/gpu/drm/i915/i915_switcheroo.o AR drivers/media/platform/st/sti/delta/built-in.a CC [M] drivers/i2c/busses/i2c-i801.o AR drivers/media/platform/st/sti/hva/built-in.a CC [M] drivers/gpu/drm/i915/i915_sysfs.o AR drivers/media/platform/st/stm32/built-in.a AR drivers/media/platform/st/built-in.a AR drivers/net/ethernet/ni/built-in.a AR drivers/net/ethernet/packetengines/built-in.a CC drivers/usb/host/xhci-ring.o AR drivers/net/ethernet/realtek/built-in.a CC [M] drivers/net/ethernet/realtek/8139cp.o CC [M] drivers/net/usb/r8153_ecm.o AR drivers/media/platform/sunxi/sun4i-csi/built-in.a AR drivers/media/platform/sunxi/sun6i-csi/built-in.a AR drivers/media/platform/sunxi/sun6i-mipi-csi2/built-in.a AR drivers/media/platform/sunxi/sun8i-a83t-mipi-csi2/built-in.a AR drivers/media/platform/sunxi/sun8i-di/built-in.a AR drivers/media/platform/sunxi/sun8i-rotate/built-in.a AR drivers/media/platform/sunxi/built-in.a CC drivers/acpi/acpica/psxface.o AR drivers/media/platform/ti/am437x/built-in.a CC [M] drivers/net/ethernet/realtek/8139too.o AR drivers/media/platform/ti/cal/built-in.a AR drivers/media/platform/ti/vpe/built-in.a CC [M] drivers/ptp/ptp_chardev.o AR drivers/media/platform/ti/davinci/built-in.a AR drivers/media/platform/ti/omap/built-in.a AR drivers/media/platform/ti/omap3isp/built-in.a AR drivers/media/platform/ti/built-in.a AR drivers/media/platform/verisilicon/built-in.a AR drivers/media/platform/via/built-in.a AR drivers/media/platform/xilinx/built-in.a AR drivers/media/platform/built-in.a CC lib/clz_ctz.o CC [M] drivers/gpu/drm/xe/xe_bo_evict.o AR drivers/media/mmc/siano/built-in.a AR drivers/media/mmc/built-in.a CC lib/bsearch.o AR drivers/media/firewire/built-in.a AR drivers/media/spi/built-in.a CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atombios.o CC [M] drivers/net/tun.o AR drivers/media/test-drivers/built-in.a AR drivers/media/built-in.a CC [M] drivers/i2c/busses/i2c-isch.o CC drivers/hwmon/hwmon.o CC [M] drivers/hwmon/acpi_power_meter.o CC drivers/power/supply/power_supply_leds.o CC [M] drivers/ptp/ptp_sysfs.o AR drivers/net/ethernet/renesas/built-in.a CC [M] fs/smb/client/asn1.o CC drivers/usb/core/devices.o CC fs/btrfs/compression.o CC [M] drivers/gpu/drm/nouveau/nvif/mem.o CC drivers/watchdog/watchdog_core.o CC drivers/acpi/acpica/rsaddr.o AR drivers/thermal/broadcom/built-in.a AR drivers/thermal/samsung/built-in.a CC drivers/acpi/acpica/rscalc.o CC drivers/thermal/intel/intel_tcc.o CC drivers/usb/storage/option_ms.o CC drivers/watchdog/watchdog_dev.o CC [M] drivers/net/phy/realtek.o CC drivers/acpi/dock.o CC drivers/acpi/acpica/rscreate.o CC drivers/power/supply/power_supply_hwmon.o CC drivers/thermal/intel/therm_throt.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_82599.o CC net/ipv6/protocol.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_dcb_nl.o CC [M] drivers/thermal/intel/x86_pkg_temp_thermal.o CC fs/btrfs/delayed-ref.o CC fs/btrfs/relocation.o AR drivers/net/ethernet/sfc/built-in.a CC drivers/usb/host/xhci-hub.o CC drivers/usb/serial/generic.o CC drivers/acpi/acpica/rsdumpinfo.o CC [M] drivers/gpu/drm/i915/i915_utils.o CC net/ipv6/ip6_offload.o CC [M] drivers/net/veth.o LD [M] drivers/net/usb/asix.o CC [M] drivers/gpu/drm/i915/intel_clock_gating.o CC net/ipv6/tcpv6_offload.o LD [M] drivers/net/ethernet/intel/igb/igb.o CC drivers/acpi/acpica/rsinfo.o CC [M] drivers/i2c/busses/i2c-ismt.o CC [M] drivers/hwmon/coretemp.o CC [M] drivers/gpu/drm/xe/xe_debugfs.o CC drivers/usb/storage/usual-tables.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_sysfs.o CC drivers/usb/core/phy.o CC [M] drivers/ptp/ptp_vclock.o CC [M] drivers/gpu/drm/i915/intel_device_info.o AR drivers/power/supply/built-in.a AR drivers/power/built-in.a CC [M] drivers/ptp/ptp_kvm_x86.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_debugfs.o CC [M] drivers/gpu/drm/nouveau/nvif/mmu.o CC drivers/acpi/acpica/rsio.o CC net/ipv6/exthdrs_offload.o AR drivers/net/ethernet/smsc/built-in.a CC [M] drivers/net/ethernet/smsc/smsc9420.o AR drivers/net/ethernet/socionext/built-in.a AR drivers/net/ethernet/vertexcom/built-in.a AR drivers/net/ethernet/wangxun/built-in.a CC [M] drivers/gpu/drm/amd/amdgpu/atombios_crtc.o CC [M] drivers/i2c/busses/i2c-piix4.o CC [M] drivers/gpu/drm/xe/xe_devcoredump.o CC net/ipv6/inet6_hashtables.o CC [M] drivers/md/persistent-data/dm-array.o LD [M] fs/smb/client/cifs.o CC [M] drivers/md/persistent-data/dm-bitset.o CC drivers/watchdog/softdog.o CC [M] drivers/i2c/busses/i2c-designware-pcidrv.o CC [M] drivers/net/phy/smsc.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_connectors.o CC [M] drivers/ptp/ptp_kvm_common.o CC mm/vmpressure.o CC [M] drivers/net/ethernet/intel/ixgbe/ixgbe_ipsec.o CC drivers/acpi/acpica/rsirq.o AR drivers/thermal/intel/built-in.a AR drivers/thermal/st/built-in.a AR drivers/thermal/qcom/built-in.a AR drivers/usb/storage/built-in.a AR drivers/thermal/tegra/built-in.a CC [M] drivers/net/ethernet/realtek/r8169_main.o AR drivers/thermal/mediatek/built-in.a CC drivers/acpi/acpica/rslist.o CC drivers/thermal/thermal_core.o CC drivers/usb/serial/bus.o CC net/ipv6/mcast_snoop.o CC fs/filesystems.o CC drivers/acpi/acpica/rsmemory.o CC drivers/thermal/thermal_sysfs.o CC [M] net/ipv6/ip6_udp_tunnel.o CC [M] drivers/gpu/drm/i915/intel_memory_region.o CC drivers/usb/core/port.o LD [M] drivers/ptp/ptp.o AR drivers/i2c/busses/built-in.a CC [M] drivers/gpu/drm/amd/amdgpu/atom.o CC drivers/acpi/acpica/rsmisc.o CC [M] drivers/gpu/drm/i915/intel_pcode.o AR drivers/watchdog/built-in.a CC drivers/opp/core.o AR drivers/hwmon/built-in.a CC [M] drivers/gpu/drm/i915/intel_region_ttm.o CC drivers/thermal/thermal_trip.o CC [M] drivers/gpu/drm/xe/xe_device.o CC drivers/thermal/thermal_helpers.o CC lib/find_bit.o CC [M] drivers/gpu/drm/nouveau/nvif/outp.o CC drivers/opp/cpu.o CC drivers/opp/debugfs.o CC drivers/usb/serial/console.o CC [M] drivers/gpu/drm/nouveau/nvif/timer.o CC [M] drivers/gpu/drm/nouveau/nvif/vmm.o CC drivers/acpi/acpica/rsserial.o CC drivers/thermal/thermal_hwmon.o CC drivers/usb/host/xhci-dbg.o CC [M] drivers/gpu/drm/ast/ast_drv.o LD [M] drivers/ptp/ptp_kvm.o CC drivers/gpu/drm/drm_mipi_dsi.o CC drivers/acpi/acpica/rsutils.o CC mm/swap_cgroup.o CC mm/hugetlb_cgroup.o CC [M] drivers/md/persistent-data/dm-block-manager.o CC [M] drivers/gpu/drm/ast/ast_i2c.o CC lib/llist.o CC drivers/acpi/acpica/rsxface.o CC mm/kmemleak.o LD [M] drivers/net/phy/aquantia.o AR drivers/net/phy/built-in.a AR drivers/net/ethernet/xilinx/built-in.a CC drivers/thermal/gov_fair_share.o CC lib/memweight.o AR drivers/net/ethernet/synopsys/built-in.a CC [M] drivers/gpu/drm/ast/ast_main.o CC fs/btrfs/delayed-inode.o LD [M] drivers/i2c/busses/i2c-designware-pci.o CC drivers/i2c/i2c-dev.o CC drivers/acpi/acpica/tbdata.o CC drivers/thermal/gov_step_wise.o CC fs/btrfs/scrub.o CC lib/kfifo.o CC fs/btrfs/backref.o CC drivers/usb/serial/ftdi_sio.o CC lib/percpu-refcount.o CC mm/page_isolation.o CC drivers/cpufreq/cpufreq.o CC drivers/usb/core/hcd-pci.o CC drivers/cpufreq/freq_table.o CC drivers/thermal/gov_user_space.o CC drivers/cpuidle/governors/menu.o CC drivers/mmc/core/core.o CC drivers/mmc/core/bus.o CC drivers/cpuidle/cpuidle.o CC drivers/mmc/core/host.o CC drivers/cpuidle/driver.o AR net/ipv6/built-in.a CC drivers/cpuidle/governor.o AR net/built-in.a CC drivers/acpi/pci_root.o AR drivers/net/ethernet/pensando/built-in.a CC drivers/mmc/host/sdhci.o CC [M] drivers/gpu/drm/i915/intel_runtime_pm.o CC [M] drivers/gpu/drm/drm_aperture.o CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o CC [M] drivers/md/persistent-data/dm-space-map-common.o CC [M] drivers/gpu/drm/nouveau/nvif/user.o CC drivers/cpuidle/sysfs.o CC drivers/mmc/host/sdhci-pci-core.o CC [M] drivers/gpu/drm/nouveau/nvif/userc361.o CC drivers/usb/host/xhci-trace.o CC [M] drivers/gpu/drm/drm_atomic.o CC [M] drivers/md/persistent-data/dm-space-map-disk.o CC [M] drivers/gpu/drm/i915/intel_sbi.o CC drivers/acpi/acpica/tbfadt.o CC [M] drivers/gpu/drm/i915/intel_step.o LD [M] drivers/net/ethernet/intel/ixgbe/ixgbe.o AR drivers/ufs/built-in.a AR drivers/thermal/built-in.a AR drivers/leds/trigger/built-in.a CC [M] drivers/leds/trigger/ledtrig-audio.o AR drivers/leds/blink/built-in.a CC drivers/cpufreq/cpufreq_performance.o AR drivers/leds/simple/built-in.a CC [M] drivers/gpu/drm/drm_atomic_uapi.o AR drivers/usb/misc/built-in.a CC drivers/cpuidle/governors/haltpoll.o CC drivers/cpufreq/cpufreq_ondemand.o CC drivers/usb/gadget/udc/core.o CC drivers/cpuidle/poll_state.o CC drivers/mmc/core/mmc.o AR drivers/usb/gadget/function/built-in.a CC lib/rhashtable.o AR drivers/usb/gadget/legacy/built-in.a CC lib/base64.o CC drivers/usb/gadget/usbstring.o CC [M] drivers/gpu/drm/ast/ast_mm.o CC drivers/leds/led-core.o CC [M] drivers/gpu/drm/i915/intel_uncore.o AR drivers/opp/built-in.a CC [M] drivers/gpu/drm/xe/xe_dma_buf.o CC drivers/usb/gadget/udc/trace.o CC [M] drivers/i2c/i2c-smbus.o CC drivers/mmc/core/mmc_ops.o CC drivers/usb/core/usb-acpi.o CC drivers/mmc/host/sdhci-pci-o2micro.o CC drivers/cpufreq/cpufreq_governor.o CC [M] drivers/i2c/i2c-mux.o CC [M] drivers/gpu/drm/ast/ast_mode.o CC drivers/acpi/acpica/tbfind.o CC [M] drivers/net/ethernet/realtek/r8169_firmware.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/client.o CC [M] drivers/net/ethernet/realtek/r8169_phy_config.o CC drivers/usb/gadget/config.o CC mm/early_ioremap.o CC [M] drivers/gpu/drm/i915/intel_wakeref.o CC drivers/usb/serial/pl2303.o CC drivers/cpufreq/cpufreq_governor_attr_set.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fence.o CC drivers/leds/led-class.o CC [M] drivers/gpu/drm/i915/vlv_sideband.o CC [M] drivers/gpu/drm/i915/vlv_suspend.o CC drivers/usb/gadget/epautoconf.o CC drivers/usb/gadget/composite.o CC [M] drivers/md/persistent-data/dm-space-map-metadata.o CC drivers/leds/led-triggers.o CC drivers/acpi/acpica/tbinstal.o AR drivers/cpuidle/governors/built-in.a CC drivers/cpuidle/cpuidle-haltpoll.o CC fs/namespace.o CC drivers/acpi/acpica/tbprint.o CC drivers/mmc/core/sd.o CC drivers/mmc/host/sdhci-pci-arasan.o CC drivers/md/md.o CC [M] drivers/gpu/drm/i915/soc/intel_dram.o CC [M] drivers/md/persistent-data/dm-transaction-manager.o CC [M] drivers/md/persistent-data/dm-btree.o AR drivers/usb/core/built-in.a CC [M] drivers/gpu/drm/nouveau/nvkm/core/engine.o CC [M] drivers/usb/class/usbtmc.o CC [M] drivers/gpu/drm/ast/ast_post.o CC [M] drivers/gpu/drm/xe/xe_exec.o CC drivers/usb/gadget/functions.o CC [M] drivers/gpu/drm/i915/soc/intel_gmch.o CC mm/cma.o CC drivers/md/md-bitmap.o CC drivers/mmc/host/sdhci-pci-dwc-mshc.o CC [M] drivers/gpu/drm/xe/xe_execlist.o CC fs/seq_file.o AR drivers/i2c/built-in.a CC [M] drivers/gpu/drm/nouveau/nvkm/core/enum.o AR drivers/cpuidle/built-in.a CC [M] drivers/gpu/drm/i915/soc/intel_pch.o CC mm/secretmem.o CC mm/userfaultfd.o CC drivers/acpi/acpica/tbutils.o AR drivers/firmware/arm_ffa/built-in.a AR drivers/firmware/arm_scmi/built-in.a AR drivers/crypto/stm32/built-in.a AR drivers/firmware/broadcom/built-in.a AR drivers/crypto/xilinx/built-in.a CC drivers/cpufreq/acpi-cpufreq.o AR drivers/firmware/cirrus/built-in.a CC drivers/mmc/host/sdhci-pci-gli.o AR drivers/firmware/meson/built-in.a AR drivers/crypto/intel/keembay/built-in.a AR drivers/crypto/hisilicon/trng/built-in.a AR drivers/crypto/hisilicon/built-in.a AR drivers/crypto/intel/ixp4xx/built-in.a LD [M] drivers/net/ethernet/realtek/r8169.o AR drivers/crypto/intel/built-in.a CC drivers/firmware/efi/efi-bgrt.o AR drivers/crypto/built-in.a CC drivers/firmware/efi/efi.o CC drivers/acpi/acpica/tbxface.o AR drivers/net/ethernet/built-in.a CC drivers/firmware/efi/libstub/efi-stub-helper.o AR drivers/net/built-in.a CC drivers/firmware/efi/vars.o CC lib/once.o AR drivers/usb/serial/built-in.a AR drivers/usb/gadget/udc/built-in.a CC drivers/firmware/efi/libstub/gop.o CC drivers/mmc/host/sdhci-acpi.o CC lib/refcount.o AR drivers/leds/built-in.a CC fs/xattr.o CC fs/libfs.o CC drivers/usb/host/xhci-debugfs.o CC fs/btrfs/ulist.o CC [M] drivers/md/persistent-data/dm-btree-remove.o CC drivers/mmc/core/sd_ops.o CC drivers/usb/gadget/configfs.o CC lib/rcuref.o CC mm/memremap.o AR drivers/firmware/imx/built-in.a CC mm/hmm.o CC mm/memfd.o CC [M] drivers/gpu/drm/drm_auth.o CC drivers/mmc/core/sdio.o CC drivers/acpi/acpica/tbxfload.o CC fs/fs-writeback.o CC drivers/clocksource/acpi_pm.o CC lib/usercopy.o CC drivers/clocksource/i8253.o CC fs/btrfs/qgroup.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ttm.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_object.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/event.o CC fs/pnode.o CC [M] drivers/gpu/drm/xe/xe_exec_queue.o AR drivers/firmware/psci/built-in.a CC drivers/firmware/efi/reboot.o CC mm/bootmem_info.o CC drivers/md/md-autodetect.o CC drivers/mmc/core/sdio_ops.o CC drivers/mmc/core/sdio_bus.o CC drivers/acpi/acpica/tbxfroot.o CC drivers/hid/usbhid/hid-core.o CC drivers/firmware/efi/libstub/secureboot.o CC drivers/hid/usbhid/hiddev.o CC lib/errseq.o CC drivers/cpufreq/intel_pstate.o CC lib/bucket_locks.o CC fs/btrfs/send.o CC drivers/mmc/core/sdio_cis.o CC fs/splice.o CC [M] drivers/md/persistent-data/dm-btree-spine.o CC lib/generic-radix-tree.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/firmware.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/gpuobj.o CC [M] drivers/gpu/drm/i915/i915_memcpy.o CC [M] drivers/gpu/drm/ast/ast_dp501.o AR drivers/clocksource/built-in.a CC [M] drivers/gpu/drm/ast/ast_dp.o CC fs/sync.o CC [M] drivers/gpu/drm/xe/xe_force_wake.o CC [M] drivers/gpu/drm/xe/xe_ggtt.o AR drivers/firmware/smccc/built-in.a CC drivers/acpi/acpica/utaddress.o CC drivers/firmware/efi/memattr.o CC drivers/usb/host/xhci-pci.o CC drivers/firmware/efi/libstub/tpm.o CC drivers/hid/hid-core.o CC drivers/md/dm-uevent.o CC fs/utimes.o CC [M] drivers/gpu/drm/i915/i915_mm.o CC fs/btrfs/dev-replace.o CC fs/d_path.o CC fs/btrfs/raid56.o CC fs/stack.o CC fs/fs_struct.o AR mm/built-in.a CC drivers/hid/hid-input.o CC drivers/md/dm.o CC drivers/acpi/acpica/utalloc.o CC drivers/firmware/efi/tpm.o CC drivers/md/dm-table.o CC drivers/md/dm-target.o CC lib/string_helpers.o CC lib/hexdump.o CC drivers/mmc/host/cqhci-core.o CC [M] drivers/mmc/host/sdhci-pltfm.o CC drivers/mmc/core/sdio_io.o CC drivers/acpi/acpica/utascii.o LD [M] drivers/md/persistent-data/dm-persistent-data.o AR drivers/staging/media/built-in.a AR drivers/staging/built-in.a CC drivers/mmc/core/sdio_irq.o CC drivers/md/dm-linear.o AR drivers/platform/x86/amd/built-in.a CC drivers/platform/x86/intel/pmc/core.o CC drivers/usb/gadget/u_f.o AR drivers/platform/surface/built-in.a CC [M] drivers/gpu/drm/nouveau/nvkm/core/intr.o CC lib/kstrtox.o CC fs/statfs.o CC [M] drivers/platform/x86/intel/pmt/class.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/ioctl.o CC [M] drivers/platform/x86/intel/pmt/telemetry.o CC drivers/firmware/efi/libstub/file.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/memory.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/mm.o CC drivers/mmc/core/slot-gpio.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/object.o CC drivers/md/dm-stripe.o CC drivers/md/dm-ioctl.o CC fs/fs_pin.o LD [M] drivers/gpu/drm/ast/ast.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/oproxy.o CC drivers/platform/x86/p2sb.o CC [M] drivers/gpu/drm/xe/xe_gt.o CC drivers/acpi/acpica/utbuffer.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gart.o CC drivers/acpi/pci_link.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_encoders.o CC drivers/firmware/efi/libstub/mem.o CC drivers/acpi/pci_irq.o CC drivers/platform/x86/pmc_atom.o AR drivers/usb/gadget/built-in.a CC drivers/firmware/efi/memmap.o CC [M] drivers/gpu/drm/i915/i915_sw_fence.o AR drivers/hid/usbhid/built-in.a CC lib/debug_info.o AR drivers/firmware/tegra/built-in.a CC drivers/hid/hid-quirks.o CC drivers/md/dm-io.o CC drivers/hid/hid-debug.o CC drivers/firmware/efi/esrt.o CC drivers/mmc/core/regulator.o CC drivers/acpi/acpica/utcksum.o AR drivers/usb/host/built-in.a AR drivers/usb/built-in.a CC fs/nsfs.o CC [M] drivers/platform/x86/wmi.o CC [M] drivers/platform/x86/wmi-bmof.o CC drivers/mailbox/mailbox.o CC [M] drivers/platform/x86/intel/pmt/crashlog.o LD [M] drivers/platform/x86/intel/pmt/pmt_class.o CC drivers/firmware/efi/efi-pstore.o CC drivers/md/dm-kcopyd.o CC drivers/hid/hidraw.o CC drivers/firmware/efi/cper.o CC drivers/devfreq/devfreq.o CC fs/fs_types.o CC [M] drivers/devfreq/governor_simpleondemand.o AR drivers/mmc/host/built-in.a CC drivers/mmc/core/debugfs.o CC drivers/hid/hid-generic.o CC drivers/firmware/efi/libstub/random.o CC drivers/md/dm-sysfs.o CC drivers/firmware/efi/libstub/randomalloc.o CC drivers/hid/hid-a4tech.o AR drivers/cpufreq/built-in.a CC drivers/firmware/efi/libstub/pci.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/option.o AR drivers/firmware/xilinx/built-in.a CC drivers/firmware/efi/libstub/skip_spaces.o CC drivers/acpi/acpica/utcopy.o CC [M] drivers/platform/x86/mxm-wmi.o CC drivers/platform/x86/intel/pmc/spt.o CC [M] drivers/platform/x86/intel_ips.o CC drivers/firmware/dmi_scan.o CC drivers/acpi/acpi_lpss.o CC drivers/powercap/powercap_sys.o CC drivers/acpi/acpi_apd.o CC drivers/powercap/intel_rapl_common.o CC [M] drivers/gpu/drm/xe/xe_gt_clock.o CC drivers/powercap/intel_rapl_msr.o CC drivers/acpi/acpi_platform.o CC [M] drivers/devfreq/governor_performance.o CC drivers/hid/hid-apple.o CC drivers/hid/hid-belkin.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_display.o CC fs/fs_context.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_i2c.o AR drivers/perf/built-in.a CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gem.o CC drivers/mailbox/pcc.o CC drivers/firmware/dmi-sysfs.o LD [M] drivers/platform/x86/intel/pmt/pmt_telemetry.o LD [M] drivers/platform/x86/intel/pmt/pmt_crashlog.o CC [M] drivers/gpu/drm/i915/i915_sw_fence_work.o CC drivers/platform/x86/intel/turbo_max_3.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring.o CC drivers/hid/hid-cherry.o CC drivers/md/dm-stats.o CC drivers/md/dm-rq.o CC drivers/acpi/acpica/utexcep.o CC drivers/mmc/core/block.o CC lib/iomap.o CC drivers/acpi/acpica/utdebug.o CC drivers/platform/x86/intel/pmc/cnp.o CC lib/pci_iomap.o CC drivers/firmware/dmi-id.o CC [M] drivers/gpu/drm/i915/i915_syncmap.o CC drivers/ras/ras.o CC drivers/hid/hid-chicony.o CC drivers/ras/debugfs.o CC drivers/firmware/efi/cper_cxl.o CC drivers/firmware/efi/libstub/lib-cmdline.o CC drivers/hid/hid-cypress.o CC drivers/md/dm-io-rewind.o CC drivers/hid/hid-ezkey.o CC drivers/acpi/acpica/utdecode.o CC drivers/firmware/efi/libstub/lib-ctype.o CC drivers/md/dm-builtin.o CC drivers/firmware/efi/libstub/alignedmem.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/ramht.o CC drivers/firmware/efi/libstub/relocate.o CC drivers/acpi/acpica/utdelete.o CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o CC drivers/firmware/efi/runtime-wrappers.o CC drivers/platform/x86/intel/pmc/icl.o CC drivers/acpi/acpi_pnp.o CC drivers/platform/x86/intel/pmc/tgl.o CC drivers/platform/x86/intel/pmc/adl.o CC drivers/hid/hid-kensington.o CC [M] drivers/gpu/drm/xe/xe_gt_idle_sysfs.o CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o AR drivers/mailbox/built-in.a CC fs/btrfs/uuid-tree.o CC drivers/acpi/power.o CC drivers/mmc/core/queue.o CC drivers/platform/x86/intel/pmc/mtl.o CC drivers/hid/hid-lg.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cs.o CC fs/btrfs/props.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/subdev.o CC fs/fs_parser.o CC [M] drivers/md/dm-bufio.o CC [M] drivers/gpu/drm/nouveau/nvkm/core/uevent.o CC fs/btrfs/free-space-tree.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bios.o CC lib/iomap_copy.o CC drivers/firmware/memmap.o CC drivers/firmware/efi/libstub/printk.o AR drivers/powercap/built-in.a AR drivers/hwtracing/intel_th/built-in.a CC drivers/android/binderfs.o CC drivers/acpi/acpica/uterror.o CC [M] drivers/md/dm-bio-prison-v1.o AR drivers/devfreq/built-in.a CC drivers/acpi/acpica/uteval.o CC lib/devres.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_benchmark.o CC drivers/android/binder.o CC drivers/platform/x86/intel/pmc/pltdrv.o CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/fw.o CC drivers/acpi/event.o CC drivers/hid/hid-lg-g15.o CC drivers/acpi/evged.o CC lib/check_signature.o CC lib/interval_tree.o CC lib/assoc_array.o CC drivers/firmware/efi/libstub/vsprintf.o CC [M] drivers/md/dm-bio-prison-v2.o CC drivers/android/binder_alloc.o CC drivers/hid/hid-microsoft.o CC drivers/acpi/sysfs.o CC drivers/hid/hid-monterey.o CC [M] drivers/md/dm-crypt.o CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/hs.o CC [M] drivers/md/dm-thin.o AR drivers/ras/built-in.a CC drivers/acpi/property.o CC [M] drivers/gpu/drm/i915/i915_user_extensions.o AR drivers/nvmem/layouts/built-in.a CC drivers/nvmem/core.o CC drivers/acpi/acpi_cmos_rtc.o CC lib/list_debug.o CC [M] drivers/gpu/drm/i915/i915_ioc32.o CC [M] drivers/platform/x86/intel/vsec.o CC drivers/acpi/acpica/utglobal.o CC drivers/acpi/acpica/uthex.o CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/ls.o CC fs/btrfs/tree-checker.o CC drivers/firmware/efi/libstub/x86-stub.o CC drivers/acpi/x86/apple.o CC [M] drivers/gpu/drm/i915/i915_debugfs.o AR drivers/platform/x86/intel/pmc/built-in.a CC [M] drivers/gpu/drm/drm_blend.o CC [M] drivers/gpu/drm/drm_bridge.o CC [M] drivers/gpu/drm/drm_cache.o CC fs/fsopen.o CC drivers/acpi/x86/utils.o CC drivers/firmware/efi/dev-path-parser.o CC lib/debugobjects.o STUBCPY drivers/firmware/efi/libstub/alignedmem.stub.o STUBCPY drivers/firmware/efi/libstub/efi-stub-helper.stub.o STUBCPY drivers/firmware/efi/libstub/file.stub.o STUBCPY drivers/firmware/efi/libstub/gop.stub.o STUBCPY drivers/firmware/efi/libstub/lib-cmdline.stub.o CC fs/init.o CC drivers/firmware/efi/apple-properties.o CC [M] drivers/md/dm-thin-metadata.o CC fs/btrfs/space-info.o CC lib/bitrev.o CC lib/crc16.o CC drivers/acpi/x86/s2idle.o STUBCPY drivers/firmware/efi/libstub/lib-ctype.stub.o CC drivers/acpi/debugfs.o CC drivers/acpi/acpi_lpat.o CC drivers/acpi/acpica/utids.o LD [M] drivers/md/dm-bio-prison.o STUBCPY drivers/firmware/efi/libstub/mem.stub.o CC [M] drivers/gpu/drm/drm_client.o STUBCPY drivers/firmware/efi/libstub/pci.stub.o CC drivers/acpi/acpica/utinit.o CC drivers/acpi/acpi_lpit.o STUBCPY drivers/firmware/efi/libstub/printk.stub.o CC drivers/acpi/acpica/utlock.o CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/acr.o CC [M] drivers/gpu/drm/nouveau/nvkm/nvfw/flcn.o CC drivers/acpi/prmt.o CC [M] drivers/mtd/chips/chipreg.o CC [M] drivers/uio/uio.o AR drivers/hid/built-in.a CC [M] drivers/vfio/pci/vfio_pci_core.o AR drivers/mmc/core/built-in.a CC [M] drivers/pps/pps.o AR drivers/mmc/built-in.a CC [M] drivers/bluetooth/btusb.o CC [M] drivers/vfio/vfio_main.o CC [M] drivers/bluetooth/btintel.o CC [M] drivers/platform/x86/intel/rst.o CC [M] drivers/dca/dca-core.o CC [M] drivers/dca/dca-sysfs.o CC [M] drivers/ssb/main.o STUBCPY drivers/firmware/efi/libstub/random.stub.o CC [M] drivers/pps/kapi.o CC [M] drivers/ssb/scan.o CC fs/kernel_read_file.o STUBCPY drivers/firmware/efi/libstub/randomalloc.stub.o CC fs/btrfs/block-rsv.o STUBCPY drivers/firmware/efi/libstub/relocate.stub.o STUBCPY drivers/firmware/efi/libstub/secureboot.stub.o STUBCPY drivers/firmware/efi/libstub/skip_spaces.stub.o CC [M] drivers/bluetooth/btbcm.o CC drivers/acpi/acpica/utmath.o STUBCPY drivers/firmware/efi/libstub/tpm.stub.o STUBCPY drivers/firmware/efi/libstub/vsprintf.stub.o STUBCPY drivers/firmware/efi/libstub/x86-stub.stub.o CC [M] drivers/gpu/drm/drm_client_modeset.o CC [M] drivers/pps/sysfs.o AR drivers/firmware/efi/libstub/lib.a CC [M] drivers/bluetooth/btrtl.o CC [M] drivers/ssb/sprom.o CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o CC lib/crc-t10dif.o CC drivers/firmware/efi/earlycon.o AR drivers/nvmem/built-in.a CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o LD [M] drivers/platform/x86/intel/intel_vsec.o CC [M] drivers/gpu/drm/i915/i915_debugfs_params.o CC [M] drivers/vfio/group.o CC drivers/acpi/acpica/utmisc.o CC [M] drivers/gpu/drm/drm_color_mgmt.o CC [M] drivers/ssb/pci.o CC [M] drivers/vhost/net.o CC fs/mnt_idmapping.o CC [M] drivers/mtd/mtdcore.o AR drivers/platform/x86/intel/built-in.a LD [M] drivers/platform/x86/intel/intel-rst.o AR drivers/platform/x86/built-in.a AR drivers/platform/built-in.a CC fs/btrfs/delalloc-space.o CC [M] drivers/gpu/drm/xe/xe_gt_topology.o CC drivers/acpi/acpi_pcc.o CC [M] drivers/gpu/drm/amd/amdgpu/atombios_dp.o CC drivers/acpi/ac.o CC fs/btrfs/block-group.o CC fs/remap_range.o HOSTCC lib/gen_crc32table HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob CC [M] drivers/mtd/mtdsuper.o CC [M] drivers/mtd/mtdconcat.o LD [M] drivers/pps/pps_core.o CC fs/buffer.o CC fs/mpage.o CC [M] drivers/mtd/mtdpart.o CC [M] drivers/mtd/mtdchar.o CC fs/proc_namespace.o CC drivers/acpi/acpica/utmutex.o CC lib/libcrc32c.o LD [M] drivers/dca/dca.o CC fs/direct-io.o CC [M] drivers/ssb/pcihost_wrapper.o CC fs/btrfs/discard.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/cmdq.o CC [M] drivers/vfio/pci/vfio_pci_intrs.o CC [M] drivers/ssb/driver_chipcommon.o CC [M] drivers/vhost/vhost.o CC [M] drivers/vfio/pci/vfio_pci_rdwr.o CC [M] drivers/vfio/iova_bitmap.o CC drivers/firmware/efi/cper-x86.o CC drivers/acpi/button.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_afmt.o CC [M] drivers/ssb/driver_chipcommon_pmu.o AR drivers/md/built-in.a CC drivers/acpi/fan_core.o CC drivers/acpi/acpica/utnonansi.o CC [M] drivers/gpu/drm/xe/xe_guc_ads.o CC drivers/acpi/fan_attr.o CC lib/xxhash.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_trace_points.o CC [M] drivers/gpu/drm/xe/xe_guc_ct.o CC [M] drivers/gpu/drm/i915/display/intel_display_debugfs.o CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o CC [M] drivers/gpu/drm/xe/xe_guc_log.o CC fs/eventpoll.o CC [M] drivers/gpu/drm/amd/amdgpu/atombios_encoders.o CC drivers/acpi/processor_driver.o CC [M] drivers/vfio/container.o CC [M] drivers/vfio/pci/vfio_pci_config.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/fw.o CC [M] drivers/gpu/drm/xe/xe_guc_pc.o CC fs/anon_inodes.o CC [M] drivers/ssb/driver_pcicore.o CC [M] drivers/vfio/virqfd.o CC drivers/acpi/acpica/utobject.o CC drivers/acpi/processor_thermal.o CC drivers/acpi/processor_idle.o AR drivers/firmware/efi/built-in.a AR drivers/firmware/built-in.a CC fs/btrfs/reflink.o CC [M] drivers/vhost/iotlb.o CC fs/signalfd.o CC lib/genalloc.o CC fs/timerfd.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/msgq.o LD [M] drivers/md/dm-thin-pool.o CC drivers/acpi/acpica/utosi.o CC drivers/acpi/acpica/utownerid.o CC [M] drivers/gpu/drm/i915/display/intel_pipe_crc.o CC lib/percpu_counter.o CC lib/fault-inject.o CC [M] drivers/gpu/drm/xe/xe_guc_submit.o CC [M] drivers/vfio/pci/vfio_pci.o CC fs/eventfd.o CC drivers/acpi/processor_throttling.o CC fs/userfaultfd.o CC fs/btrfs/subpage.o LD [M] drivers/mtd/mtd.o CC fs/btrfs/tree-mod-log.o CC [M] drivers/gpu/drm/xe/xe_hw_engine.o CC drivers/acpi/processor_perflib.o CC [M] drivers/vfio/vfio_iommu_type1.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sa.o CC fs/aio.o CC [M] drivers/gpu/drm/drm_connector.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/qmgr.o CC fs/locks.o CC [M] drivers/gpu/drm/xe/xe_hw_fence.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/v1.o CC lib/syscall.o CC drivers/acpi/acpica/utpredef.o CC [M] drivers/gpu/drm/i915/i915_pmu.o CC [M] drivers/gpu/drm/i915/gt/gen2_engine_cs.o CC [M] drivers/gpu/drm/i915/gt/gen6_engine_cs.o CC [M] drivers/gpu/drm/i915/gt/gen6_ppgtt.o LD [M] drivers/vfio/vfio.o LD [M] drivers/ssb/ssb.o CC [M] drivers/gpu/drm/i915/gt/gen7_renderclear.o CC fs/binfmt_script.o CC [M] drivers/gpu/drm/drm_crtc.o CC [M] drivers/gpu/drm/xe/xe_huc.o CC lib/dynamic_debug.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gm200.o LD [M] drivers/vfio/pci/vfio-pci.o CC lib/errname.o LD [M] drivers/vhost/vhost_net.o LD [M] drivers/vhost/vhost_iotlb.o CC lib/nlattr.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/gp102.o CC fs/binfmt_elf.o CC fs/btrfs/extent-io-tree.o CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o CC drivers/acpi/acpica/utresdecode.o CC drivers/acpi/acpica/utresrc.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga100.o CC [M] drivers/gpu/drm/i915/gt/gen8_engine_cs.o CC fs/compat_binfmt_elf.o CC [M] drivers/gpu/drm/xe/xe_irq.o CC [M] drivers/gpu/drm/amd/amdgpu/atombios_i2c.o LD [M] drivers/vfio/pci/vfio-pci-core.o CC fs/btrfs/fs.o CC drivers/acpi/acpica/utstate.o CC fs/mbcache.o CC [M] drivers/gpu/drm/i915/gt/gen8_ppgtt.o CC [M] drivers/gpu/drm/drm_displayid.o CC drivers/acpi/container.o CC [M] drivers/gpu/drm/xe/xe_lrc.o CC drivers/acpi/acpica/utstring.o CC drivers/acpi/acpica/utstrsuppt.o CC [M] drivers/gpu/drm/nouveau/nvkm/falcon/ga102.o CC [M] drivers/gpu/drm/xe/xe_migrate.o CC lib/checksum.o CC drivers/acpi/thermal.o CC fs/posix_acl.o CC fs/coredump.o CC fs/drop_caches.o CC [M] drivers/gpu/drm/i915/gt/intel_breadcrumbs.o CC fs/sysctls.o CC fs/fhandle.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_dma_buf.o CC [M] drivers/gpu/drm/xe/xe_mmio.o CC fs/btrfs/messages.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/lsfw.o CC drivers/acpi/acpi_memhotplug.o CC lib/cpu_rmap.o CC [M] drivers/gpu/drm/i915/gt/intel_context.o CC [M] drivers/gpu/drm/drm_drv.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm200.o CC drivers/acpi/acpica/utstrtoul64.o CC drivers/acpi/ioapic.o CC [M] drivers/gpu/drm/i915/gt/intel_context_sseu.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm.o CC [M] drivers/gpu/drm/drm_dumb_buffers.o CC lib/dynamic_queue_limits.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gm20b.o CC lib/glob.o CC [M] drivers/gpu/drm/xe/xe_mocs.o CC [M] drivers/gpu/drm/i915/gt/intel_engine_cs.o CC [M] drivers/gpu/drm/drm_edid.o AR drivers/android/built-in.a CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_pt.o CC [M] drivers/gpu/drm/i915/gt/intel_engine_heartbeat.o CC fs/btrfs/bio.o CC drivers/acpi/battery.o CC [M] drivers/gpu/drm/i915/gt/intel_engine_pm.o CC fs/btrfs/lru_cache.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ib.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pll.o CC [M] drivers/gpu/drm/xe/xe_module.o CC fs/btrfs/acl.o CC drivers/acpi/acpica/utxface.o CC drivers/acpi/hed.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp102.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp108.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ucode.o CC lib/strncpy_from_user.o CC [M] drivers/gpu/drm/i915/gt/intel_engine_user.o CC [M] drivers/gpu/drm/xe/xe_pat.o CC drivers/acpi/bgrt.o CC drivers/acpi/cppc_acpi.o CC drivers/acpi/spcr.o CC [M] drivers/gpu/drm/drm_encoder.o CC [M] drivers/gpu/drm/drm_file.o CC [M] drivers/gpu/drm/drm_fourcc.o CC [M] drivers/gpu/drm/drm_framebuffer.o CC [M] drivers/gpu/drm/xe/xe_pci.o CC [M] drivers/gpu/drm/xe/xe_pcode.o CC [M] drivers/gpu/drm/xe/xe_pm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gv100.o CC drivers/acpi/acpi_pad.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/gp10b.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/tu102.o CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga100.o CC [M] drivers/gpu/drm/xe/xe_pt.o CC drivers/acpi/acpica/utxfinit.o CC [M] drivers/gpu/drm/i915/gt/intel_execlists_submission.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/acr/ga102.o CC [M] drivers/gpu/drm/drm_gem.o CC lib/strnlen_user.o CC lib/net_utils.o CC [M] drivers/gpu/drm/i915/gt/intel_ggtt.o CC [M] drivers/gpu/drm/drm_ioctl.o CC lib/sg_pool.o CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_fencing.o CC [M] drivers/gpu/drm/i915/gt/intel_gt.o CC [M] drivers/acpi/acpi_video.o CC [M] drivers/acpi/video_detect.o CC lib/stackdepot.o CC [M] drivers/gpu/drm/drm_lease.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/base.o CC [M] drivers/gpu/drm/xe/xe_pt_walk.o CC [M] drivers/gpu/drm/xe/xe_query.o CC drivers/acpi/acpica/utxferror.o CC drivers/acpi/acpica/utxfmutex.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_bo_list.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ctx.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/nv50.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/g84.o CC [M] drivers/gpu/drm/drm_managed.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sync.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gtt_mgr.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gf100.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_preempt_mgr.o CC [M] drivers/gpu/drm/drm_mm.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vram_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_virt.o CC [M] drivers/gpu/drm/xe/xe_range_fence.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gk20a.o AR fs/btrfs/built-in.a CC [M] drivers/gpu/drm/drm_mode_config.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_clock_utils.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_debugfs.o AR fs/built-in.a CC [M] drivers/gpu/drm/xe/xe_reg_sr.o CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o CC lib/ucs2_string.o CC [M] drivers/gpu/drm/xe/xe_rtp.o GEN xe_wa_oob.c xe_wa_oob.h AR drivers/acpi/acpica/built-in.a GEN xe_wa_oob.c xe_wa_oob.h CC [M] drivers/gpu/drm/xe/xe_sa.o CC [M] drivers/gpu/drm/xe/xe_sched_job.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm107.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_atomfirmware.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.o CC lib/sbitmap.o CC [M] drivers/gpu/drm/drm_mode_object.o AR drivers/acpi/built-in.a CC [M] drivers/gpu/drm/drm_modes.o CC [M] drivers/gpu/drm/xe/xe_step.o CC [M] drivers/gpu/drm/drm_modeset_lock.o CC [M] drivers/gpu/drm/drm_plane.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_irq.o CC lib/group_cpus.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/gm20b.o CC [M] drivers/gpu/drm/drm_prime.o CC [M] drivers/gpu/drm/drm_print.o CC [M] lib/asn1_decoder.o CC [M] drivers/gpu/drm/xe/xe_sync.o CC [M] drivers/gpu/drm/drm_property.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bar/tu102.o CC [M] drivers/gpu/drm/xe/xe_tile.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/bit.o CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/boost.o GEN lib/oid_registry_data.c CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vf_error.o CC [M] lib/oid_registry.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sched.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_mcr.o CC [M] drivers/gpu/drm/xe/xe_trace.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.o CC [M] drivers/gpu/drm/drm_syncobj.o CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/conn.o CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o LD [M] drivers/acpi/video.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ids.o CC [M] drivers/gpu/drm/drm_sysfs.o CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.o CC [M] drivers/gpu/drm/drm_trace_points.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_pm_irq.o CC [M] drivers/gpu/drm/drm_vblank.o CC [M] drivers/gpu/drm/drm_vblank_work.o CC [M] drivers/gpu/drm/drm_vma_manager.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_requests.o CC [M] drivers/gpu/drm/drm_gpuva_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gmc.o CC [M] drivers/gpu/drm/xe/xe_tuning.o AR lib/lib.a CC [M] drivers/gpu/drm/drm_writeback.o GEN lib/crc32table.h CC lib/crc32.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/cstep.o CC [M] drivers/gpu/drm/lib/drm_random.o CC [M] drivers/gpu/drm/xe/xe_uc.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mmhub.o CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o CC [M] drivers/gpu/drm/xe/xe_uc_fw.o CC [M] drivers/gpu/drm/xe/xe_vm.o CC [M] drivers/gpu/drm/xe/xe_vm_madvise.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hdp.o CC [M] drivers/gpu/drm/drm_ioc32.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs.o CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o CC [M] drivers/gpu/drm/xe/xe_wa.o CC [M] drivers/gpu/drm/drm_panel.o CC [M] drivers/gpu/drm/drm_pci.o CC [M] drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dcb.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/disp.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/dp.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/extdev.o CC [M] drivers/gpu/drm/xe/xe_wopcm.o CC [M] drivers/gpu/drm/drm_debugfs.o CC [M] drivers/gpu/drm/xe/xe_display.o AR lib/built-in.a CC [M] drivers/gpu/drm/drm_debugfs_crc.o CC [M] drivers/gpu/drm/drm_edid_load.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/fan.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/gpio.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_xgmi.o CC [M] drivers/gpu/drm/drm_panel_orientation_quirks.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/i2c.o CC [M] drivers/gpu/drm/drm_buddy.o CC [M] drivers/gpu/drm/i915/gt/intel_gtt.o CC [M] drivers/gpu/drm/xe/display/xe_fb_pin.o CC [M] drivers/gpu/drm/drm_gem_shmem_helper.o CC [M] drivers/gpu/drm/drm_suballoc.o CC [M] drivers/gpu/drm/xe/display/xe_hdcp_gsc.o CC [M] drivers/gpu/drm/xe/display/xe_plane_initial.o CC [M] drivers/gpu/drm/xe/display/xe_display_rps.o CC [M] drivers/gpu/drm/xe/display/ext/i915_irq.o CC [M] drivers/gpu/drm/i915/gt/intel_llc.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_csa.o CC [M] drivers/gpu/drm/i915/gt/intel_lrc.o CC [M] drivers/gpu/drm/drm_gem_ttm_helper.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/iccsense.o CC [M] drivers/gpu/drm/xe/display/ext/intel_clock_gating.o CC [M] drivers/gpu/drm/xe/display/ext/intel_device_info.o CC [M] drivers/gpu/drm/i915/gt/intel_migrate.o CC [M] drivers/gpu/drm/i915/gt/intel_mocs.o CC [M] drivers/gpu/drm/drm_atomic_helper.o CC [M] drivers/gpu/drm/xe/i915-soc/intel_dram.o CC [M] drivers/gpu/drm/i915/gt/intel_ppgtt.o CC [M] drivers/gpu/drm/xe/i915-soc/intel_pch.o CC [M] drivers/gpu/drm/xe/i915-display/icl_dsi.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_cpu.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vm_sdma.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/image.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.o CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic.o CC [M] drivers/gpu/drm/drm_atomic_state_helper.o CC [M] drivers/gpu/drm/drm_bridge_connector.o CC [M] drivers/gpu/drm/xe/i915-display/intel_atomic_plane.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ras_eeprom.o CC [M] drivers/gpu/drm/i915/gt/intel_rc6.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/init.o CC [M] drivers/gpu/drm/i915/gt/intel_region_lmem.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/mxm.o CC [M] drivers/gpu/drm/drm_crtc_helper.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/npde.o CC [M] drivers/gpu/drm/drm_damage_helper.o CC [M] drivers/gpu/drm/drm_encoder_slave.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pcir.o CC [M] drivers/gpu/drm/xe/i915-display/intel_audio.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/perf.o CC [M] drivers/gpu/drm/drm_flip_work.o CC [M] drivers/gpu/drm/drm_format_helper.o CC [M] drivers/gpu/drm/xe/i915-display/intel_backlight.o CC [M] drivers/gpu/drm/drm_gem_atomic_helper.o CC [M] drivers/gpu/drm/i915/gt/intel_renderstate.o CC [M] drivers/gpu/drm/i915/gt/intel_reset.o CC [M] drivers/gpu/drm/drm_gem_framebuffer_helper.o CC [M] drivers/gpu/drm/xe/i915-display/intel_bios.o CC [M] drivers/gpu/drm/xe/i915-display/intel_bw.o CC [M] drivers/gpu/drm/i915/gt/intel_ring.o CC [M] drivers/gpu/drm/xe/i915-display/intel_cdclk.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pll.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/pmu.o CC [M] drivers/gpu/drm/i915/gt/intel_ring_submission.o CC [M] drivers/gpu/drm/drm_kms_helper_common.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_nbio.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_umc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_color.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/power_budget.o CC [M] drivers/gpu/drm/xe/i915-display/intel_combo_phy.o CC [M] drivers/gpu/drm/drm_modeset_helper.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/ramcfg.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/rammap.o CC [M] drivers/gpu/drm/i915/gt/intel_rps.o CC [M] drivers/gpu/drm/xe/i915-display/intel_connector.o CC [M] drivers/gpu/drm/drm_plane_helper.o CC [M] drivers/gpu/drm/drm_probe_helper.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadow.o CC [M] drivers/gpu/drm/i915/gt/intel_sa_media.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowacpi.o CC [M] drivers/gpu/drm/i915/gt/intel_sseu.o CC [M] drivers/gpu/drm/i915/gt/intel_sseu_debugfs.o CC [M] drivers/gpu/drm/amd/amdgpu/smu_v11_0_i2c.o CC [M] drivers/gpu/drm/i915/gt/intel_timeline.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowof.o CC [M] drivers/gpu/drm/drm_rect.o CC [M] drivers/gpu/drm/drm_self_refresh_helper.o CC [M] drivers/gpu/drm/drm_simple_kms_helper.o CC [M] drivers/gpu/drm/bridge/panel.o CC [M] drivers/gpu/drm/i915/gt/intel_wopcm.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fru_eeprom.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rap.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowpci.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowramin.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fw_attestation.o CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_crtc_state_dump.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/shadowrom.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/timing.o CC [M] drivers/gpu/drm/i915/gt/intel_workarounds.o CC [M] drivers/gpu/drm/drm_fbdev_generic.o CC [M] drivers/gpu/drm/xe/i915-display/intel_cursor.o CC [M] drivers/gpu/drm/i915/gt/shmem_utils.o CC [M] drivers/gpu/drm/drm_fb_helper.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_securedisplay.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/therm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vmap.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/volt.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_eeprom.o LD [M] drivers/gpu/drm/drm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/vpstate.o CC [M] drivers/gpu/drm/xe/i915-display/intel_cx0_phy.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/xpio.o LD [M] drivers/gpu/drm/drm_shmem_helper.o LD [M] drivers/gpu/drm/drm_suballoc_helper.o LD [M] drivers/gpu/drm/drm_ttm_helper.o AR drivers/gpu/drm/built-in.a CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mca.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp_ta.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_lsdma.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ring_mux.o CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0203.o CC [M] drivers/gpu/drm/xe/i915-display/intel_ddi_buf_trans.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_xcp.o CC [M] drivers/gpu/drm/i915/gt/sysfs_engines.o CC [M] drivers/gpu/drm/i915/gt/intel_ggtt_gmch.o CC [M] drivers/gpu/drm/i915/gt/gen6_renderstate.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_fdinfo.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0205.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_pmu.o CC [M] drivers/gpu/drm/amd/amdgpu/cik.o CC [M] drivers/gpu/drm/i915/gt/gen7_renderstate.o CC [M] drivers/gpu/drm/amd/amdgpu/cik_ih.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/M0209.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bios/P0260.o CC [M] drivers/gpu/drm/amd/amdgpu/dce_v8_0.o CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v7_0.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_debugfs.o CC [M] drivers/gpu/drm/i915/gt/gen8_renderstate.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/base.o CC [M] drivers/gpu/drm/amd/amdgpu/cik_sdma.o CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v4_2.o CC [M] drivers/gpu/drm/i915/gt/gen9_renderstate.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/hwsq.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv04.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv31.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_device.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/nv50.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_busy.o CC [M] drivers/gpu/drm/amd/amdgpu/vce_v2_0.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_clflush.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/g94.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_driver.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_irq.o CC [M] drivers/gpu/drm/amd/amdgpu/si.o CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v6_0.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_context.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_create.o CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v6_0.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/bus/gf100.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_dmabuf.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_domain.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_map.o CC [M] drivers/gpu/drm/amd/amdgpu/si_ih.o CC [M] drivers/gpu/drm/amd/amdgpu/si_dma.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_execbuffer.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_internal.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/base.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_power_well.o CC [M] drivers/gpu/drm/amd/amdgpu/dce_v6_0.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv04.o LD [M] drivers/gpu/drm/drm_kms_helper.o CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v3_1.o CC [M] drivers/gpu/drm/amd/amdgpu/vi.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv40.o CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_vi.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/nv50.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/g84.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gt215.o CC [M] drivers/gpu/drm/xe/i915-display/intel_display_trace.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/mcp77.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gf100.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_object.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_lmem.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_mman.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk104.o CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v6_1.o CC [M] drivers/gpu/drm/amd/amdgpu/soc15.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_pages.o CC [M] drivers/gpu/drm/amd/amdgpu/emu_soc.o CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_ai.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dkl_phy.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gk20a.o CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_0.o CC [M] drivers/gpu/drm/amd/amdgpu/vega10_reg_init.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_phys.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dmc.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_pm.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_region.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/gm20b.o CC [M] drivers/gpu/drm/amd/amdgpu/vega20_reg_init.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllnv04.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_aux_backlight.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_hdcp.o CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_4.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_shmem.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/clk/pllgt215.o CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v2_3.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/base.o CC [M] drivers/gpu/drm/amd/amdgpu/nv.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_shrinker.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_stolen.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_throttle.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_tiling.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_link_training.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dp_mst.o CC [M] drivers/gpu/drm/amd/amdgpu/arct_reg_init.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv04.o CC [M] drivers/gpu/drm/amd/amdgpu/mxgpu_nv.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dpll_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_2.o CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v4_0.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv05.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dpt.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv10.o CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_0.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_move.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv1a.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.o CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran_reg_init.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_userptr.o CC [M] drivers/gpu/drm/amd/amdgpu/aldebaran.o CC [M] drivers/gpu/drm/amd/amdgpu/soc21.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv20.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv50.o CC [M] drivers/gpu/drm/xe/i915-display/intel_drrs.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsb.o CC [M] drivers/gpu/drm/amd/amdgpu/sienna_cichlid.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_dcs_backlight.o CC [M] drivers/gpu/drm/amd/amdgpu/smu_v13_0_10.o CC [M] drivers/gpu/drm/xe/i915-display/intel_dsi_vbt.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fb.o CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v4_3.o CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v6_0.o CC [M] drivers/gpu/drm/i915/gem/i915_gem_wait.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g84.o CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_7.o CC [M] drivers/gpu/drm/amd/amdgpu/hdp_v5_2.o CC [M] drivers/gpu/drm/i915/gem/i915_gemfs.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/g98.o CC [M] drivers/gpu/drm/i915/i915_active.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gt215.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/mcp89.o CC [M] drivers/gpu/drm/i915/i915_cmd_parser.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gf100.o CC [M] drivers/gpu/drm/amd/amdgpu/lsdma_v6_0.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm107.o CC [M] drivers/gpu/drm/amd/amdgpu/nbio_v7_9.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gm200.o CC [M] drivers/gpu/drm/i915/i915_deps.o CC [M] drivers/gpu/drm/amd/amdgpu/aqua_vanjaram_reg_init.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/gv100.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/tu102.o CC [M] drivers/gpu/drm/amd/amdgpu/df_v1_7.o CC [M] drivers/gpu/drm/amd/amdgpu/df_v3_6.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fbc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fdi.o CC [M] drivers/gpu/drm/amd/amdgpu/df_v4_3.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fifo_underrun.o CC [M] drivers/gpu/drm/xe/i915-display/intel_frontbuffer.o CC [M] drivers/gpu/drm/i915/i915_gem_evict.o CC [M] drivers/gpu/drm/xe/i915-display/intel_global_state.o CC [M] drivers/gpu/drm/i915/i915_gem_gtt.o CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v7_0.o CC [M] drivers/gpu/drm/i915/i915_gem_ww.o CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v8_0.o CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_0.o CC [M] drivers/gpu/drm/xe/i915-display/intel_gmbus.o CC [M] drivers/gpu/drm/i915/i915_gem.o CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_0.o CC [M] drivers/gpu/drm/i915/i915_query.o CC [M] drivers/gpu/drm/i915/i915_request.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/devinit/ga100.o CC [M] drivers/gpu/drm/i915/i915_scheduler.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/base.o CC [M] drivers/gpu/drm/i915/i915_trace_points.o CC [M] drivers/gpu/drm/i915/i915_ttm_buddy_manager.o CC [M] drivers/gpu/drm/i915/i915_vma.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/user.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hdcp.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hdmi.o CC [M] drivers/gpu/drm/i915/i915_vma_resource.o CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v9_0.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp100.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gp10b.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.o CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_1.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/gv100.o CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v9_4.o CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_0.o CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_0.o CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v10_0.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.o CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v2_1.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fault/tu102.o CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v2_3.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ads.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug.o CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_7.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hotplug_irq.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/base.o CC [M] drivers/gpu/drm/xe/i915-display/intel_hti.o CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0.o CC [M] drivers/gpu/drm/xe/i915-display/intel_lspcon.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_capture.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_ct.o CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.o CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_lock.o CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_setup.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.o CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_2.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_fw.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv04.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv10.o CC [M] drivers/gpu/drm/amd/amdgpu/gmc_v11_0.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv1a.o CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v3_0_1.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_hwconfig.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_rc.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_guc_submission.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv20.o CC [M] drivers/gpu/drm/xe/i915-display/intel_modeset_verify.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv25.o CC [M] drivers/gpu/drm/xe/i915-display/intel_panel.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_huc_fw.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_pipe_crc.o CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v3_0_3.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv30.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv35.o CC [M] drivers/gpu/drm/xe/i915-display/intel_pmdemand.o CC [M] drivers/gpu/drm/amd/amdgpu/gfxhub_v1_2.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.o CC [M] drivers/gpu/drm/i915/gt/uc/intel_uc_fw.o CC [M] drivers/gpu/drm/i915/gt/intel_gsc.o CC [M] drivers/gpu/drm/i915/i915_hwmon.o CC [M] drivers/gpu/drm/xe/i915-display/intel_pps.o CC [M] drivers/gpu/drm/amd/amdgpu/mmhub_v1_8.o CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_0.o CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_1.o CC [M] drivers/gpu/drm/xe/i915-display/intel_psr.o CC [M] drivers/gpu/drm/xe/i915-display/intel_qp_tables.o CC [M] drivers/gpu/drm/i915/display/hsw_ips.o CC [M] drivers/gpu/drm/amd/amdgpu/umc_v6_7.o CC [M] drivers/gpu/drm/i915/display/intel_atomic.o CC [M] drivers/gpu/drm/xe/i915-display/intel_quirks.o CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_7.o CC [M] drivers/gpu/drm/amd/amdgpu/umc_v8_10.o CC [M] drivers/gpu/drm/i915/display/intel_atomic_plane.o CC [M] drivers/gpu/drm/i915/display/intel_audio.o CC [M] drivers/gpu/drm/xe/i915-display/intel_snps_phy.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv36.o CC [M] drivers/gpu/drm/i915/display/intel_bios.o CC [M] drivers/gpu/drm/i915/display/intel_bw.o CC [M] drivers/gpu/drm/i915/display/intel_cdclk.o CC [M] drivers/gpu/drm/i915/display/intel_color.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv40.o CC [M] drivers/gpu/drm/xe/i915-display/intel_tc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vblank.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vdsc.o CC [M] drivers/gpu/drm/i915/display/intel_combo_phy.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vga.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_irq.o CC [M] drivers/gpu/drm/i915/display/intel_connector.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ih.o CC [M] drivers/gpu/drm/i915/display/intel_crtc.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv41.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv44.o CC [M] drivers/gpu/drm/i915/display/intel_crtc_state_dump.o CC [M] drivers/gpu/drm/xe/i915-display/intel_vrr.o CC [M] drivers/gpu/drm/i915/display/intel_cursor.o CC [M] drivers/gpu/drm/i915/display/intel_display.o CC [M] drivers/gpu/drm/xe/i915-display/intel_wm.o CC [M] drivers/gpu/drm/amd/amdgpu/iceland_ih.o CC [M] drivers/gpu/drm/xe/i915-display/skl_scaler.o CC [M] drivers/gpu/drm/amd/amdgpu/tonga_ih.o CC [M] drivers/gpu/drm/i915/display/intel_display_driver.o CC [M] drivers/gpu/drm/i915/display/intel_display_irq.o CC [M] drivers/gpu/drm/xe/i915-display/skl_universal_plane.o CC [M] drivers/gpu/drm/xe/i915-display/skl_watermark.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv46.o CC [M] drivers/gpu/drm/amd/amdgpu/cz_ih.o CC [M] drivers/gpu/drm/i915/display/intel_display_power.o CC [M] drivers/gpu/drm/amd/amdgpu/vega10_ih.o CC [M] drivers/gpu/drm/amd/amdgpu/vega20_ih.o CC [M] drivers/gpu/drm/xe/i915-display/intel_acpi.o CC [M] drivers/gpu/drm/xe/i915-display/intel_opregion.o CC [M] drivers/gpu/drm/i915/display/intel_display_power_map.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv47.o CC [M] drivers/gpu/drm/i915/display/intel_display_power_well.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv49.o CC [M] drivers/gpu/drm/i915/display/intel_display_reset.o CC [M] drivers/gpu/drm/i915/display/intel_display_rps.o CC [M] drivers/gpu/drm/i915/display/intel_dmc.o CC [M] drivers/gpu/drm/xe/i915-display/intel_fbdev.o CC [M] drivers/gpu/drm/amd/amdgpu/navi10_ih.o CC [M] drivers/gpu/drm/amd/amdgpu/ih_v6_0.o CC [M] drivers/gpu/drm/i915/display/intel_dpio_phy.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_psp.o CC [M] drivers/gpu/drm/i915/display/intel_dpll.o CC [M] drivers/gpu/drm/i915/display/intel_dpll_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/psp_v3_1.o CC [M] drivers/gpu/drm/xe/xe_guc.o CC [M] drivers/gpu/drm/amd/amdgpu/psp_v10_0.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv4e.o CC [M] drivers/gpu/drm/i915/display/intel_dpt.o CC [M] drivers/gpu/drm/i915/display/intel_drrs.o CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0.o CC [M] drivers/gpu/drm/i915/display/intel_dsb.o CC [M] drivers/gpu/drm/amd/amdgpu/psp_v11_0_8.o CC [M] drivers/gpu/drm/i915/display/intel_fb.o CC [M] drivers/gpu/drm/amd/amdgpu/psp_v12_0.o CC [M] drivers/gpu/drm/i915/display/intel_fb_pin.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/g84.o CC [M] drivers/gpu/drm/xe/xe_ring_ops.o CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0.o HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h CC [M] drivers/gpu/drm/i915/display/intel_fbc.o HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h CC [M] drivers/gpu/drm/i915/display/intel_fdi.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma_types.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband_reg.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_wakeref.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pcode.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_drv.h CC [M] drivers/gpu/drm/amd/amdgpu/psp_v13_0_4.o CC [M] drivers/gpu/drm/i915/display/intel_fifo_underrun.o CC [M] drivers/gpu/drm/amd/amdgpu/dce_v10_0.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gt215.o CC [M] drivers/gpu/drm/i915/display/intel_frontbuffer.o CC [M] drivers/gpu/drm/i915/display/intel_global_state.o CC [M] drivers/gpu/drm/i915/display/intel_hdcp.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp77.o CC [M] drivers/gpu/drm/amd/amdgpu/dce_v11_0.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg_defs.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_trace.h CC [M] drivers/gpu/drm/i915/display/intel_hdcp_gsc.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_reg.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vkms.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_active_types.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_utils.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/mcp89.o CC [M] drivers/gpu/drm/i915/display/intel_hotplug.o CC [M] drivers/gpu/drm/i915/display/intel_hotplug_irq.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf100.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_config.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_rlc.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vma.h CC [M] drivers/gpu/drm/i915/display/intel_hti.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/vlv_sideband.h CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v8_0.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_mchbar_regs.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_debugfs.h CC [M] drivers/gpu/drm/i915/display/intel_load_detect.o CC [M] drivers/gpu/drm/i915/display/intel_lpe_audio.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_pch.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_dram.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/soc/intel_gmch.h CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_0.o CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4.o CC [M] drivers/gpu/drm/i915/display/intel_modeset_lock.o CC [M] drivers/gpu/drm/i915/display/intel_modeset_verify.o CC [M] drivers/gpu/drm/i915/display/intel_modeset_setup.o CC [M] drivers/gpu/drm/i915/display/intel_overlay.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gf108.o CC [M] drivers/gpu/drm/i915/display/intel_pch_display.o CC [M] drivers/gpu/drm/i915/display/intel_pch_refclk.o CC [M] drivers/gpu/drm/i915/display/intel_plane_initial.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk104.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_vgpu.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk110.o CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4_2.o CC [M] drivers/gpu/drm/i915/display/intel_pmdemand.o CC [M] drivers/gpu/drm/i915/display/intel_psr.o CC [M] drivers/gpu/drm/i915/display/intel_quirks.o CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v9_4_3.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/i915_fixed.h CC [M] drivers/gpu/drm/i915/display/intel_sprite.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gk20a.o CC [M] drivers/gpu/drm/i915/display/intel_sprite_uapi.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm107.o CC [M] drivers/gpu/drm/i915/display/intel_tc.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm200.o CC [M] drivers/gpu/drm/i915/display/intel_vblank.o CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v10_0.o CC [M] drivers/gpu/drm/i915/display/intel_vga.o CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0.o CC [M] drivers/gpu/drm/i915/display/intel_wm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gm20b.o CC [M] drivers/gpu/drm/i915/display/i9xx_plane.o CC [M] drivers/gpu/drm/i915/display/i9xx_wm.o CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0.o CC [M] drivers/gpu/drm/i915/display/skl_scaler.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp100.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp102.o CC [M] drivers/gpu/drm/i915/display/skl_universal_plane.o CC [M] drivers/gpu/drm/i915/display/skl_watermark.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gp10b.o CC [M] drivers/gpu/drm/i915/display/intel_acpi.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gv100.o CC [M] drivers/gpu/drm/amd/amdgpu/gfx_v11_0_3.o CC [M] drivers/gpu/drm/i915/display/intel_opregion.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_runtime_pm.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pm_types.h CC [M] drivers/gpu/drm/amd/amdgpu/imu_v11_0_3.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_sdma.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_uncore.h CC [M] drivers/gpu/drm/i915/display/intel_fbdev.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/tu102.o CC [M] drivers/gpu/drm/i915/display/dvo_ch7017.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga100.o CC [M] drivers/gpu/drm/i915/display/dvo_ch7xxx.o CC [M] drivers/gpu/drm/i915/display/dvo_ivch.o CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v2_4.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ga102.o CC [M] drivers/gpu/drm/i915/display/dvo_ns2501.o CC [M] drivers/gpu/drm/i915/display/dvo_sil164.o CC [M] drivers/gpu/drm/i915/display/dvo_tfp410.o CC [M] drivers/gpu/drm/i915/display/g4x_dp.o CC [M] drivers/gpu/drm/i915/display/g4x_hdmi.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ram.o CC [M] drivers/gpu/drm/i915/display/icl_dsi.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv04.o CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v3_0.o CC [M] drivers/gpu/drm/i915/display/intel_backlight.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv10.o CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_0.o CC [M] drivers/gpu/drm/i915/display/intel_crt.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_pci_config.h HDRTEST drivers/gpu/drm/xe/compat-i915-headers/gt/intel_rps.h CC [M] drivers/gpu/drm/i915/display/intel_cx0_phy.o HDRTEST drivers/gpu/drm/xe/compat-i915-headers/intel_clock_gating.h CC [M] drivers/gpu/drm/i915/display/intel_ddi.o HDRTEST drivers/gpu/drm/xe/display/ext/i915_irq.h CC [M] drivers/gpu/drm/i915/display/intel_ddi_buf_trans.o HDRTEST drivers/gpu/drm/xe/display/ext/intel_device_info.h CC [M] drivers/gpu/drm/i915/display/intel_display_device.o CC [M] drivers/gpu/drm/i915/display/intel_display_trace.o CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv1a.o CC [M] drivers/gpu/drm/i915/display/intel_dkl_phy.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv20.o CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v4_4_2.o CC [M] drivers/gpu/drm/i915/display/intel_dp.o CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_0.o CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v5_2.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv40.o CC [M] drivers/gpu/drm/i915/display/intel_dp_aux.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv41.o CC [M] drivers/gpu/drm/i915/display/intel_dp_aux_backlight.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv44.o CC [M] drivers/gpu/drm/i915/display/intel_dp_hdcp.o CC [M] drivers/gpu/drm/i915/display/intel_dp_link_training.o HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv49.o HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv4e.o CC [M] drivers/gpu/drm/i915/display/intel_dp_mst.o CC [M] drivers/gpu/drm/i915/display/intel_dsi.o HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h CC [M] drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.o HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h CC [M] drivers/gpu/drm/i915/display/intel_dsi_vbt.o HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h HDRTEST drivers/gpu/drm/xe/tests/xe_test.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramnv50.o CC [M] drivers/gpu/drm/i915/display/intel_dvo.o HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h CC [M] drivers/gpu/drm/i915/display/intel_gmbus.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgt215.o CC [M] drivers/gpu/drm/amd/amdgpu/sdma_v6_0.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_mes.o CC [M] drivers/gpu/drm/i915/display/intel_hdmi.o CC [M] drivers/gpu/drm/i915/display/intel_lspcon.o HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/rammcp77.o HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h CC [M] drivers/gpu/drm/i915/display/intel_lvds.o HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h HDRTEST drivers/gpu/drm/xe/xe_bb.h HDRTEST drivers/gpu/drm/xe/xe_bb_types.h HDRTEST drivers/gpu/drm/xe/xe_bo.h HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf100.o HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h HDRTEST drivers/gpu/drm/xe/xe_bo_types.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgf108.o CC [M] drivers/gpu/drm/i915/display/intel_panel.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgk104.o CC [M] drivers/gpu/drm/i915/display/intel_pps.o CC [M] drivers/gpu/drm/amd/amdgpu/mes_v10_1.o CC [M] drivers/gpu/drm/i915/display/intel_qp_tables.o CC [M] drivers/gpu/drm/i915/display/intel_sdvo.o CC [M] drivers/gpu/drm/i915/display/intel_snps_phy.o CC [M] drivers/gpu/drm/amd/amdgpu/mes_v11_0.o CC [M] drivers/gpu/drm/i915/display/intel_tv.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.o CC [M] drivers/gpu/drm/i915/display/intel_vdsc.o CC [M] drivers/gpu/drm/i915/display/intel_vrr.o CC [M] drivers/gpu/drm/i915/display/vlv_dsi.o HDRTEST drivers/gpu/drm/xe/xe_debugfs.h HDRTEST drivers/gpu/drm/xe/xe_devcoredump.h HDRTEST drivers/gpu/drm/xe/xe_devcoredump_types.h CC [M] drivers/gpu/drm/i915/display/vlv_dsi_pll.o HDRTEST drivers/gpu/drm/xe/xe_device.h HDRTEST drivers/gpu/drm/xe/xe_device_sysfs.h HDRTEST drivers/gpu/drm/xe/xe_device_types.h HDRTEST drivers/gpu/drm/xe/xe_display.h CC [M] drivers/gpu/drm/i915/i915_perf.o HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm107.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgm200.o CC [M] drivers/gpu/drm/i915/pxp/intel_pxp.o CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_tee.o CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_huc.o HDRTEST drivers/gpu/drm/xe/xe_drv.h CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_cmd.o CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.o CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v5_0.o CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.o CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_irq.o CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_pm.o HDRTEST drivers/gpu/drm/xe/xe_exec.h HDRTEST drivers/gpu/drm/xe/xe_exec_queue.h CC [M] drivers/gpu/drm/i915/pxp/intel_pxp_session.o HDRTEST drivers/gpu/drm/xe/xe_exec_queue_types.h CC [M] drivers/gpu/drm/i915/i915_gpu_error.o HDRTEST drivers/gpu/drm/xe/xe_execlist.h HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h HDRTEST drivers/gpu/drm/xe/xe_force_wake.h CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v6_0.o CC [M] drivers/gpu/drm/amd/amdgpu/uvd_v7_0.o CC [M] drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.o CC [M] drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.o HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h CC [M] drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramgp100.o CC [M] drivers/gpu/drm/i915/selftests/i915_random.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/ramga102.o HDRTEST drivers/gpu/drm/xe/xe_ggtt.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr2.o HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h CC [M] drivers/gpu/drm/i915/selftests/i915_selftest.o HDRTEST drivers/gpu/drm/xe/xe_gt.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vce.o HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs.h HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs_types.h HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h HDRTEST drivers/gpu/drm/xe/xe_gt_printk.h CC [M] drivers/gpu/drm/amd/amdgpu/vce_v3_0.o HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h CC [M] drivers/gpu/drm/i915/selftests/igt_atomic.o CC [M] drivers/gpu/drm/i915/selftests/igt_flush_test.o CC [M] drivers/gpu/drm/amd/amdgpu/vce_v4_0.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.o CC [M] drivers/gpu/drm/i915/selftests/igt_live_test.o CC [M] drivers/gpu/drm/i915/selftests/igt_mmap.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/sddr3.o CC [M] drivers/gpu/drm/amd/amdgpu/vcn_sw_ring.o HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h CC [M] drivers/gpu/drm/i915/selftests/igt_reset.o CC [M] drivers/gpu/drm/i915/selftests/igt_spinner.o CC [M] drivers/gpu/drm/i915/selftests/librapl.o HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h CC [M] drivers/gpu/drm/i915/i915_vgpu.o CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v1_0.o HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_crtc_state_dump.h HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h HDRTEST drivers/gpu/drm/i915/display/hsw_ips.h HDRTEST drivers/gpu/drm/i915/display/g4x_hdmi.h HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_regs.h HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h HDRTEST drivers/gpu/drm/i915/display/intel_overlay.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr3.o HDRTEST drivers/gpu/drm/i915/display/intel_display.h CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_0.o HDRTEST drivers/gpu/drm/i915/display/skl_watermark_regs.h CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v2_5.o HDRTEST drivers/gpu/drm/i915/display/intel_dmc.h HDRTEST drivers/gpu/drm/xe/xe_gt_types.h CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v3_0.o HDRTEST drivers/gpu/drm/i915/display/intel_vga.h HDRTEST drivers/gpu/drm/i915/display/intel_audio.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fb/gddr5.o HDRTEST drivers/gpu/drm/xe/xe_guc.h HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h HDRTEST drivers/gpu/drm/i915/display/intel_lvds.h HDRTEST drivers/gpu/drm/i915/display/intel_modeset_setup.h HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h HDRTEST drivers/gpu/drm/i915/display/intel_cdclk.h HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v4_0.o HDRTEST drivers/gpu/drm/i915/display/intel_display_limits.h HDRTEST drivers/gpu/drm/i915/display/intel_hotplug.h HDRTEST drivers/gpu/drm/i915/display/intel_dkl_phy.h HDRTEST drivers/gpu/drm/i915/display/intel_atomic.h HDRTEST drivers/gpu/drm/i915/display/intel_display_driver.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/base.o HDRTEST drivers/gpu/drm/i915/display/intel_dpll.h HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_dp_mst.h HDRTEST drivers/gpu/drm/i915/display/intel_fdi_regs.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/nv50.o HDRTEST drivers/gpu/drm/i915/display/g4x_dp.h HDRTEST drivers/gpu/drm/i915/display/intel_tc.h HDRTEST drivers/gpu/drm/i915/display/intel_frontbuffer.h HDRTEST drivers/gpu/drm/i915/display/intel_dsi_vbt.h HDRTEST drivers/gpu/drm/i915/display/intel_psr.h HDRTEST drivers/gpu/drm/i915/display/intel_crt.h HDRTEST drivers/gpu/drm/i915/display/intel_opregion.h HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy_regs.h HDRTEST drivers/gpu/drm/i915/display/i9xx_wm.h HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_global_state.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gf100.o HDRTEST drivers/gpu/drm/i915/display/intel_lpe_audio.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/fuse/gm107.o HDRTEST drivers/gpu/drm/i915/display/intel_drrs.h HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h HDRTEST drivers/gpu/drm/i915/display/intel_display_rps.h HDRTEST drivers/gpu/drm/xe/xe_guc_exec_queue_types.h HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h CC [M] drivers/gpu/drm/amd/amdgpu/vcn_v4_0_3.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/base.o HDRTEST drivers/gpu/drm/i915/display/intel_fbdev.h HDRTEST drivers/gpu/drm/i915/display/intel_pps_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_hdmi.h HDRTEST drivers/gpu/drm/i915/display/intel_fdi.h HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h HDRTEST drivers/gpu/drm/xe/xe_guc_log.h HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv10.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_jpeg.o HDRTEST drivers/gpu/drm/i915/display/intel_fb.h HDRTEST drivers/gpu/drm/i915/display/intel_qp_tables.h HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h HDRTEST drivers/gpu/drm/i915/display/intel_dsb_regs.h CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v1_0.o HDRTEST drivers/gpu/drm/i915/display/intel_vdsc.h HDRTEST drivers/gpu/drm/i915/display/intel_snps_phy.h HDRTEST drivers/gpu/drm/i915/display/intel_display_core.h HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_pll.h HDRTEST drivers/gpu/drm/i915/display/intel_dvo_dev.h HDRTEST drivers/gpu/drm/i915/display/intel_hdcp.h HDRTEST drivers/gpu/drm/i915/display/intel_sdvo_regs.h CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_0.o HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v2_5.o HDRTEST drivers/gpu/drm/i915/display/intel_pch_refclk.h CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v3_0.o HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h HDRTEST drivers/gpu/drm/xe/xe_guc_submit_types.h CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v4_0.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/nv50.o HDRTEST drivers/gpu/drm/i915/display/intel_modeset_lock.h HDRTEST drivers/gpu/drm/xe/xe_guc_types.h HDRTEST drivers/gpu/drm/i915/display/intel_display_trace.h CC [M] drivers/gpu/drm/amd/amdgpu/jpeg_v4_0_3.o HDRTEST drivers/gpu/drm/xe/xe_huc.h HDRTEST drivers/gpu/drm/i915/display/intel_display_power.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/g94.o HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_regs.h HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h HDRTEST drivers/gpu/drm/i915/display/i9xx_plane.h HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux_backlight.h HDRTEST drivers/gpu/drm/i915/display/intel_dpll_mgr.h CC [M] drivers/gpu/drm/amd/amdgpu/athub_v1_0.o CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_0.o HDRTEST drivers/gpu/drm/xe/xe_huc_types.h CC [M] drivers/gpu/drm/amd/amdgpu/athub_v2_1.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gf119.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/gk104.o HDRTEST drivers/gpu/drm/i915/display/vlv_dsi.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gpio/ga102.o HDRTEST drivers/gpu/drm/i915/display/intel_plane_initial.h HDRTEST drivers/gpu/drm/i915/display/intel_display_device.h CC [M] drivers/gpu/drm/amd/amdgpu/athub_v3_0.o HDRTEST drivers/gpu/drm/i915/display/intel_fifo_underrun.h HDRTEST drivers/gpu/drm/i915/display/intel_cursor.h CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v9_0.o HDRTEST drivers/gpu/drm/i915/display/vlv_dsi_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_cx0_phy.h HDRTEST drivers/gpu/drm/i915/display/skl_scaler.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/base.o HDRTEST drivers/gpu/drm/i915/display/intel_hti.h HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h HDRTEST drivers/gpu/drm/i915/display/icl_dsi_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_atomic_plane.h HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h HDRTEST drivers/gpu/drm/i915/display/skl_watermark.h HDRTEST drivers/gpu/drm/i915/display/intel_fbc.h HDRTEST drivers/gpu/drm/i915/display/intel_display_reg_defs.h HDRTEST drivers/gpu/drm/i915/display/intel_acpi.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/gv100.o HDRTEST drivers/gpu/drm/i915/display/intel_connector.h HDRTEST drivers/gpu/drm/i915/display/intel_dpt.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/gsp/ga102.o HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h HDRTEST drivers/gpu/drm/i915/display/intel_quirks.h HDRTEST drivers/gpu/drm/i915/display/intel_dp_link_training.h HDRTEST drivers/gpu/drm/i915/display/intel_color.h HDRTEST drivers/gpu/drm/xe/xe_irq.h HDRTEST drivers/gpu/drm/i915/display/intel_crtc.h HDRTEST drivers/gpu/drm/xe/xe_lrc.h HDRTEST drivers/gpu/drm/i915/display/intel_display_debugfs.h HDRTEST drivers/gpu/drm/i915/display/intel_modeset_verify.h HDRTEST drivers/gpu/drm/i915/display/intel_display_power_well.h HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/base.o HDRTEST drivers/gpu/drm/i915/display/intel_psr_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_wm.h CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0.o HDRTEST drivers/gpu/drm/i915/display/intel_pipe_crc.h HDRTEST drivers/gpu/drm/i915/display/intel_audio_regs.h HDRTEST drivers/gpu/drm/xe/xe_macros.h CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v11_0_6.o HDRTEST drivers/gpu/drm/i915/display/intel_panel.h CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv04.o HDRTEST drivers/gpu/drm/xe/xe_map.h HDRTEST drivers/gpu/drm/i915/display/intel_sprite.h HDRTEST drivers/gpu/drm/xe/xe_migrate.h HDRTEST drivers/gpu/drm/i915/display/intel_wm_types.h HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h HDRTEST drivers/gpu/drm/xe/xe_mmio.h HDRTEST drivers/gpu/drm/i915/display/intel_tv.h HDRTEST drivers/gpu/drm/i915/display/intel_hti_regs.h HDRTEST drivers/gpu/drm/xe/xe_mocs.h HDRTEST drivers/gpu/drm/xe/xe_module.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv4e.o HDRTEST drivers/gpu/drm/i915/display/intel_vrr.h HDRTEST drivers/gpu/drm/xe/xe_pat.h HDRTEST drivers/gpu/drm/xe/xe_pci.h HDRTEST drivers/gpu/drm/i915/display/intel_load_detect.h HDRTEST drivers/gpu/drm/i915/display/skl_universal_plane.h HDRTEST drivers/gpu/drm/xe/xe_pci_types.h CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0_3.o HDRTEST drivers/gpu/drm/i915/display/intel_mg_phy_regs.h CC [M] drivers/gpu/drm/amd/amdgpu/smuio_v13_0_6.o HDRTEST drivers/gpu/drm/i915/display/intel_bw.h HDRTEST drivers/gpu/drm/i915/display/intel_display_irq.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/nv50.o HDRTEST drivers/gpu/drm/i915/display/intel_de.h HDRTEST drivers/gpu/drm/xe/xe_pcode.h HDRTEST drivers/gpu/drm/i915/display/intel_lvds_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_gmbus_regs.h HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_reset.o HDRTEST drivers/gpu/drm/xe/xe_platform_types.h HDRTEST drivers/gpu/drm/i915/display/intel_dsi_dcs_backlight.h HDRTEST drivers/gpu/drm/xe/xe_pm.h HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/g94.o HDRTEST drivers/gpu/drm/i915/display/intel_dvo.h HDRTEST drivers/gpu/drm/i915/display/intel_sdvo.h CC [M] drivers/gpu/drm/amd/amdgpu/mca_v3_0.o HDRTEST drivers/gpu/drm/i915/display/intel_dp_aux.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd.o HDRTEST drivers/gpu/drm/i915/display/intel_vdsc_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy.h HDRTEST drivers/gpu/drm/i915/display/intel_dvo_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_gmbus.h HDRTEST drivers/gpu/drm/i915/display/intel_hdcp_gsc.h HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h HDRTEST drivers/gpu/drm/i915/display/intel_dsi.h HDRTEST drivers/gpu/drm/i915/display/intel_dmc_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_ddi.h HDRTEST drivers/gpu/drm/i915/display/intel_hotplug_irq.h HDRTEST drivers/gpu/drm/i915/display/intel_tv_regs.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf117.o HDRTEST drivers/gpu/drm/i915/display/intel_dsb.h HDRTEST drivers/gpu/drm/xe/xe_pt.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gf119.o HDRTEST drivers/gpu/drm/i915/display/intel_bios.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk104.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_module.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gk110.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/gm200.o HDRTEST drivers/gpu/drm/xe/xe_pt_types.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_chardev.o HDRTEST drivers/gpu/drm/i915/display/intel_pch_display.h HDRTEST drivers/gpu/drm/i915/display/intel_display_types.h HDRTEST drivers/gpu/drm/i915/display/intel_backlight.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_topology.o HDRTEST drivers/gpu/drm/i915/display/intel_vblank.h HDRTEST drivers/gpu/drm/i915/display/intel_dp.h HDRTEST drivers/gpu/drm/xe/xe_pt_walk.h HDRTEST drivers/gpu/drm/i915/display/intel_pmdemand.h HDRTEST drivers/gpu/drm/xe/xe_query.h HDRTEST drivers/gpu/drm/xe/xe_range_fence.h HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h HDRTEST drivers/gpu/drm/i915/display/intel_backlight_regs.h HDRTEST drivers/gpu/drm/i915/display/intel_combo_phy_regs.h HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h HDRTEST drivers/gpu/drm/i915/display/intel_display_reset.h HDRTEST drivers/gpu/drm/i915/display/intel_display_power_map.h HDRTEST drivers/gpu/drm/i915/display/intel_ddi_buf_trans.h HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/pad.o HDRTEST drivers/gpu/drm/i915/display/icl_dsi.h HDRTEST drivers/gpu/drm/i915/display/intel_lspcon.h HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h HDRTEST drivers/gpu/drm/i915/display/intel_dpio_phy.h HDRTEST drivers/gpu/drm/i915/display/intel_dp_hdcp.h HDRTEST drivers/gpu/drm/i915/display/intel_fb_pin.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_pasid.o HDRTEST drivers/gpu/drm/i915/display/intel_pps.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv04.o HDRTEST drivers/gpu/drm/i915/display/intel_sprite_uapi.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv4e.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padnv50.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padg94.o HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_doorbell.o HDRTEST drivers/gpu/drm/i915/gem/i915_gem_region.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context_types.h HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_lmem.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_flat_memory.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgf119.o HDRTEST drivers/gpu/drm/xe/xe_rtp.h HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/padgm200.o HDRTEST drivers/gpu/drm/i915/gem/i915_gem_mman.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_queue.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager.o HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object_types.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bus.o HDRTEST drivers/gpu/drm/i915/gem/i915_gem_context.h HDRTEST drivers/gpu/drm/xe/xe_sa.h HDRTEST drivers/gpu/drm/xe/xe_sa_types.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_clflush.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_cik.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_vi.o HDRTEST drivers/gpu/drm/xe/xe_sched_job.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_tiling.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv04.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv4e.o HDRTEST drivers/gpu/drm/i915/gem/i915_gem_stolen.h HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h HDRTEST drivers/gpu/drm/xe/xe_step.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_pm.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_create.h HDRTEST drivers/gpu/drm/xe/xe_step_types.h HDRTEST drivers/gpu/drm/xe/xe_sync.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ttm_move.h HDRTEST drivers/gpu/drm/xe/xe_sync_types.h HDRTEST drivers/gpu/drm/xe/xe_tile.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_ioctls.h HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_domain.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_internal.h HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs_types.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v9.o HDRTEST drivers/gpu/drm/i915/gem/i915_gem_dmabuf.h HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_context.h HDRTEST drivers/gpu/drm/i915/gem/selftests/huge_gem_object.h HDRTEST drivers/gpu/drm/xe/xe_trace.h HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_gem_object.h HDRTEST drivers/gpu/drm/i915/gem/selftests/mock_dmabuf.h HDRTEST drivers/gpu/drm/i915/gem/selftests/igt_gem_utils.h HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busnv50.o HDRTEST drivers/gpu/drm/i915/gem/i915_gem_userptr.h HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v10.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/busgf119.o HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_pm.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/bit.o HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h HDRTEST drivers/gpu/drm/xe/xe_tuning.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/aux.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxg94.o HDRTEST drivers/gpu/drm/i915/gem/i915_gem_shrinker.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgf119.o HDRTEST drivers/gpu/drm/xe/xe_uc.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/auxgm200.o HDRTEST drivers/gpu/drm/i915/gem/i915_gemfs.h HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h HDRTEST drivers/gpu/drm/i915/gem/i915_gem_object.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/i2c/anx9805.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_mqd_manager_v11.o HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h HDRTEST drivers/gpu/drm/i915/gt/intel_timeline_types.h HDRTEST drivers/gpu/drm/xe/xe_uc_types.h HDRTEST drivers/gpu/drm/i915/gt/selftest_engine.h HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs.h HDRTEST drivers/gpu/drm/xe/xe_vm.h HDRTEST drivers/gpu/drm/i915/gt/intel_engine_heartbeat.h HDRTEST drivers/gpu/drm/i915/gt/intel_context_types.h HDRTEST drivers/gpu/drm/i915/gt/intel_execlists_submission.h HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_kernel_queue.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager.o HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_vi.o HDRTEST drivers/gpu/drm/xe/xe_vm_types.h HDRTEST drivers/gpu/drm/xe/xe_wa.h HDRTEST drivers/gpu/drm/i915/gt/selftest_rc6.h HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h HDRTEST drivers/gpu/drm/i915/gt/intel_llc_types.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/base.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_packet_manager_v9.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/iccsense/gf100.o HDRTEST drivers/gpu/drm/i915/gt/intel_gt.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_process_queue_manager.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager.o HDRTEST drivers/gpu/drm/xe/xe_wopcm.h HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h HDRTEST drivers/gpu/drm/i915/gt/intel_region_lmem.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_cik.o HDRTEST drivers/gpu/drm/i915/gt/intel_gt_requests.h HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_gmch.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/base.o LD [M] drivers/gpu/drm/xe/xe.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv04.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_vi.o HDRTEST drivers/gpu/drm/i915/gt/intel_gt_print.h HDRTEST drivers/gpu/drm/i915/gt/gen8_ppgtt.h HDRTEST drivers/gpu/drm/i915/gt/intel_gt_mcr.h HDRTEST drivers/gpu/drm/i915/gt/intel_timeline.h HDRTEST drivers/gpu/drm/i915/gt/gen6_engine_cs.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v9.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v10.o HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_debugfs.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_device_queue_manager_v11.o HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds_types.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv40.o HDRTEST drivers/gpu/drm/i915/gt/selftest_rps.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_interrupt.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_events.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/nv50.o HDRTEST drivers/gpu/drm/i915/gt/intel_sa_media.h HDRTEST drivers/gpu/drm/i915/gt/intel_gt_debugfs.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/instmem/gk20a.o HDRTEST drivers/gpu/drm/i915/gt/intel_gt_clock_utils.h HDRTEST drivers/gpu/drm/i915/gt/intel_rps_types.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/cik_event_interrupt.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v9.o HDRTEST drivers/gpu/drm/i915/gt/selftest_engine_heartbeat.h HDRTEST drivers/gpu/drm/i915/gt/sysfs_engines.h HDRTEST drivers/gpu/drm/i915/gt/gen7_renderclear.h HDRTEST drivers/gpu/drm/i915/gt/intel_context.h HDRTEST drivers/gpu/drm/i915/gt/intel_wopcm.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/base.o HDRTEST drivers/gpu/drm/i915/gt/intel_mocs.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gf100.o HDRTEST drivers/gpu/drm/i915/gt/intel_engine_pm.h HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs.h HDRTEST drivers/gpu/drm/i915/gt/intel_rc6.h HDRTEST drivers/gpu/drm/i915/gt/intel_ring_types.h HDRTEST drivers/gpu/drm/i915/gt/intel_workarounds.h HDRTEST drivers/gpu/drm/i915/gt/intel_engine_regs.h HDRTEST drivers/gpu/drm/i915/gt/intel_gt_pm_irq.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v10.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gk104.o HDRTEST drivers/gpu/drm/i915/gt/shmem_utils.h HDRTEST drivers/gpu/drm/i915/gt/intel_engine.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_int_process_v11.o HDRTEST drivers/gpu/drm/i915/gt/intel_reset_types.h HDRTEST drivers/gpu/drm/i915/gt/intel_gt_regs.h HDRTEST drivers/gpu/drm/i915/gt/intel_reset.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_fw.h HDRTEST drivers/gpu/drm/i915/gt/uc/guc_capture_fwif.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_smi_events.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_crat.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm107.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debug.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw_abi.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_debugfs.o CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_svm.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_print.h CC [M] drivers/gpu/drm/amd/amdgpu/../amdkfd/kfd_migrate.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fw.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_debugfs.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_fence.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gpuvm.o HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_klvs_abi.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v8.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v9.o HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_errors_abi.h HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_slpc_abi.h HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_mmio_abi.h HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_actions_abi.h HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_communication_ctb_abi.h HDRTEST drivers/gpu/drm/i915/gt/uc/abi/guc_messages_abi.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_arcturus.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_debugfs.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc_heci_cmd_submit.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_reg.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_uc.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gm200.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp100.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_binary_headers.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_aldebaran.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_print.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_fw.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_fwif.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gc_9_4_3.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_capture.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log_debugfs.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_gsc_proxy.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_submission.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v10_3.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v11.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp102.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_log.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/gp10b.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_amdkfd_gfx_v7.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_cgs.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/ltc/ga102.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv04.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ct.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_job.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv11.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acp.o HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_fw.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_ads.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_uc_debugfs.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_guc_rc.h HDRTEST drivers/gpu/drm/i915/gt/uc/intel_huc_debugfs.h HDRTEST drivers/gpu/drm/i915/gt/intel_hwconfig.h CC [M] drivers/gpu/drm/amd/amdgpu/../acp/acp_hw.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv17.o CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_ioc32.o HDRTEST drivers/gpu/drm/i915/gt/intel_llc.h HDRTEST drivers/gpu/drm/i915/gt/gen8_engine_cs.h HDRTEST drivers/gpu/drm/i915/gt/intel_sseu_debugfs.h HDRTEST drivers/gpu/drm/i915/gt/intel_rc6_types.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_acpi.o HDRTEST drivers/gpu/drm/i915/gt/intel_context_param.h CC [M] drivers/gpu/drm/amd/amdgpu/amdgpu_hmm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv44.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/arcturus_ppt.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv50.o HDRTEST drivers/gpu/drm/i915/gt/intel_gpu_commands.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/navi10_ppt.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g84.o HDRTEST drivers/gpu/drm/i915/gt/intel_engine_user.h HDRTEST drivers/gpu/drm/i915/gt/intel_gt_irq.h HDRTEST drivers/gpu/drm/i915/gt/intel_gsc.h HDRTEST drivers/gpu/drm/i915/gt/intel_rps.h HDRTEST drivers/gpu/drm/i915/gt/selftest_llc.h HDRTEST drivers/gpu/drm/i915/gt/gen6_ppgtt.h HDRTEST drivers/gpu/drm/i915/gt/intel_ggtt_fencing.h HDRTEST drivers/gpu/drm/i915/gt/intel_migrate_types.h HDRTEST drivers/gpu/drm/i915/gt/selftests/mock_timeline.h HDRTEST drivers/gpu/drm/i915/gt/intel_lrc.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/g98.o HDRTEST drivers/gpu/drm/i915/gt/intel_lrc_reg.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/sienna_cichlid_ppt.o HDRTEST drivers/gpu/drm/i915/gt/intel_migrate.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/vangogh_ppt.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gt215.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/cyan_skillfish_ppt.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gf100.o HDRTEST drivers/gpu/drm/i915/gt/intel_gt_sysfs_pm.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk104.o HDRTEST drivers/gpu/drm/i915/gt/intel_breadcrumbs_types.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu11/smu_v11_0.o HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool.h HDRTEST drivers/gpu/drm/i915/gt/mock_engine.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/renoir_ppt.o HDRTEST drivers/gpu/drm/i915/gt/intel_engine_stats.h HDRTEST drivers/gpu/drm/i915/gt/intel_gtt.h HDRTEST drivers/gpu/drm/i915/gt/intel_gt_buffer_pool_types.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu12/smu_v12_0.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0.o HDRTEST drivers/gpu/drm/i915/gt/intel_ring.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gk20a.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp100.o HDRTEST drivers/gpu/drm/i915/gt/intel_gt_types.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/gp10b.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/aldebaran_ppt.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/yellow_carp_ppt.o HDRTEST drivers/gpu/drm/i915/gt/intel_renderstate.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_0_ppt.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_4_ppt.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_5_ppt.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mc/ga100.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_7_ppt.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/base.o HDRTEST drivers/gpu/drm/i915/gt/intel_sseu.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu13/smu_v13_0_6_ppt.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv04.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/amdgpu_smu.o HDRTEST drivers/gpu/drm/i915/gt/intel_engine_types.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/swsmu/smu_cmn.o HDRTEST drivers/gpu/drm/i915/gt/intel_gt_engines_debugfs.h HDRTEST drivers/gpu/drm/i915/gt/gen2_engine_cs.h HDRTEST drivers/gpu/drm/i915/gvt/gvt.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smumgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv41.o HDRTEST drivers/gpu/drm/i915/gvt/trace.h HDRTEST drivers/gpu/drm/i915/gvt/debug.h HDRTEST drivers/gpu/drm/i915/gvt/edid.h HDRTEST drivers/gpu/drm/i915/gvt/page_track.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv44.o HDRTEST drivers/gpu/drm/i915/gvt/mmio.h HDRTEST drivers/gpu/drm/i915/gvt/sched_policy.h HDRTEST drivers/gpu/drm/i915/gvt/fb_decoder.h HDRTEST drivers/gpu/drm/i915/gvt/cmd_parser.h HDRTEST drivers/gpu/drm/i915/gvt/dmabuf.h HDRTEST drivers/gpu/drm/i915/gvt/mmio_context.h HDRTEST drivers/gpu/drm/i915/gvt/display.h HDRTEST drivers/gpu/drm/i915/gvt/gtt.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.o HDRTEST drivers/gpu/drm/i915/gvt/scheduler.h HDRTEST drivers/gpu/drm/i915/gvt/reg.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu8_smumgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/g84.o HDRTEST drivers/gpu/drm/i915/gvt/execlist.h HDRTEST drivers/gpu/drm/i915/gvt/interrupt.h HDRTEST drivers/gpu/drm/i915/i915_active.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mcp77.o HDRTEST drivers/gpu/drm/i915/i915_active_types.h HDRTEST drivers/gpu/drm/i915/i915_cmd_parser.h HDRTEST drivers/gpu/drm/i915/i915_config.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gf100.o HDRTEST drivers/gpu/drm/i915/i915_debugfs.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk104.o HDRTEST drivers/gpu/drm/i915/i915_debugfs_params.h HDRTEST drivers/gpu/drm/i915/i915_deps.h HDRTEST drivers/gpu/drm/i915/i915_driver.h HDRTEST drivers/gpu/drm/i915/i915_drm_client.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/tonga_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_drv.h HDRTEST drivers/gpu/drm/i915/i915_file_private.h HDRTEST drivers/gpu/drm/i915/i915_fixed.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/fiji_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_gem.h HDRTEST drivers/gpu/drm/i915/i915_gem_evict.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gk20a.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm200.o HDRTEST drivers/gpu/drm/i915/i915_gem_gtt.h HDRTEST drivers/gpu/drm/i915/i915_gem_ww.h HDRTEST drivers/gpu/drm/i915/i915_getparam.h HDRTEST drivers/gpu/drm/i915/i915_gpu_error.h HDRTEST drivers/gpu/drm/i915/i915_hwmon.h HDRTEST drivers/gpu/drm/i915/i915_ioc32.h HDRTEST drivers/gpu/drm/i915/i915_ioctl.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gm20b.o HDRTEST drivers/gpu/drm/i915/i915_iosf_mbi.h HDRTEST drivers/gpu/drm/i915/i915_irq.h HDRTEST drivers/gpu/drm/i915/i915_memcpy.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/polaris10_smumgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/iceland_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_mitigations.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp100.o HDRTEST drivers/gpu/drm/i915/i915_mm.h HDRTEST drivers/gpu/drm/i915/i915_params.h HDRTEST drivers/gpu/drm/i915/i915_pci.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gp10b.o HDRTEST drivers/gpu/drm/i915/i915_perf.h HDRTEST drivers/gpu/drm/i915/i915_perf_oa_regs.h HDRTEST drivers/gpu/drm/i915/i915_perf_types.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu7_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_pmu.h HDRTEST drivers/gpu/drm/i915/i915_priolist_types.h HDRTEST drivers/gpu/drm/i915/i915_pvinfo.h HDRTEST drivers/gpu/drm/i915/i915_query.h HDRTEST drivers/gpu/drm/i915/i915_reg.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega10_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_reg_defs.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu10_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_request.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/gv100.o HDRTEST drivers/gpu/drm/i915/i915_scatterlist.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/tu102.o HDRTEST drivers/gpu/drm/i915/i915_scheduler.h HDRTEST drivers/gpu/drm/i915/i915_scheduler_types.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/mem.o HDRTEST drivers/gpu/drm/i915/i915_selftest.h HDRTEST drivers/gpu/drm/i915/i915_suspend.h HDRTEST drivers/gpu/drm/i915/i915_sw_fence.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/ci_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_sw_fence_work.h HDRTEST drivers/gpu/drm/i915/i915_switcheroo.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv04.o HDRTEST drivers/gpu/drm/i915/i915_syncmap.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memnv50.o HDRTEST drivers/gpu/drm/i915/i915_sysfs.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega12_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_tasklet.h HDRTEST drivers/gpu/drm/i915/i915_trace.h HDRTEST drivers/gpu/drm/i915/i915_ttm_buddy_manager.h HDRTEST drivers/gpu/drm/i915/i915_user_extensions.h HDRTEST drivers/gpu/drm/i915/i915_utils.h HDRTEST drivers/gpu/drm/i915/i915_vgpu.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vegam_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_vma.h HDRTEST drivers/gpu/drm/i915/i915_vma_resource.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/smu9_smumgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/smumgr/vega20_smumgr.o HDRTEST drivers/gpu/drm/i915/i915_vma_types.h HDRTEST drivers/gpu/drm/i915/intel_clock_gating.h HDRTEST drivers/gpu/drm/i915/intel_device_info.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hwmgr.o HDRTEST drivers/gpu/drm/i915/intel_gvt.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/memgf100.o HDRTEST drivers/gpu/drm/i915/intel_mchbar_regs.h HDRTEST drivers/gpu/drm/i915/intel_memory_region.h HDRTEST drivers/gpu/drm/i915/intel_pci_config.h HDRTEST drivers/gpu/drm/i915/intel_pcode.h HDRTEST drivers/gpu/drm/i915/intel_region_ttm.h HDRTEST drivers/gpu/drm/i915/intel_runtime_pm.h HDRTEST drivers/gpu/drm/i915/intel_sbi.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/processpptables.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/hardwaremanager.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmm.o HDRTEST drivers/gpu/drm/i915/intel_step.h HDRTEST drivers/gpu/drm/i915/intel_uncore.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu8_hwmgr.o HDRTEST drivers/gpu/drm/i915/intel_wakeref.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pppcielanes.o HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_tee.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_irq.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/process_pptables_v1_0.o HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_session.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv04.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomctrl.o HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_43.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ppatomfwctrl.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_hwmgr.o HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_gsccs.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv41.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv44.o HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_types.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_debugfs.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_powertune.o HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_cmn.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_thermal.o HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_huc.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_pm.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_cmd_interface_42.h HDRTEST drivers/gpu/drm/i915/pxp/intel_pxp_regs.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmnv50.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmmcp77.o HDRTEST drivers/gpu/drm/i915/selftests/igt_live_test.h HDRTEST drivers/gpu/drm/i915/selftests/igt_atomic.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgf100.o HDRTEST drivers/gpu/drm/i915/selftests/mock_gem_device.h HDRTEST drivers/gpu/drm/i915/selftests/mock_drm.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_clockpowergating.o HDRTEST drivers/gpu/drm/i915/selftests/igt_reset.h HDRTEST drivers/gpu/drm/i915/selftests/intel_scheduler_helpers.h HDRTEST drivers/gpu/drm/i915/selftests/lib_sw_fence.h HDRTEST drivers/gpu/drm/i915/selftests/i915_perf_selftests.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_processpptables.o HDRTEST drivers/gpu/drm/i915/selftests/mock_uncore.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_hwmgr.o HDRTEST drivers/gpu/drm/i915/selftests/mock_gtt.h HDRTEST drivers/gpu/drm/i915/selftests/i915_mock_selftests.h HDRTEST drivers/gpu/drm/i915/selftests/mock_request.h HDRTEST drivers/gpu/drm/i915/selftests/i915_random.h HDRTEST drivers/gpu/drm/i915/selftests/igt_spinner.h HDRTEST drivers/gpu/drm/i915/selftests/librapl.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_powertune.o HDRTEST drivers/gpu/drm/i915/selftests/mock_region.h HDRTEST drivers/gpu/drm/i915/selftests/i915_live_selftests.h HDRTEST drivers/gpu/drm/i915/selftests/igt_mmap.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk104.o HDRTEST drivers/gpu/drm/i915/selftests/igt_flush_test.h HDRTEST drivers/gpu/drm/i915/soc/intel_pch.h HDRTEST drivers/gpu/drm/i915/soc/intel_dram.h HDRTEST drivers/gpu/drm/i915/soc/intel_gmch.h HDRTEST drivers/gpu/drm/i915/vlv_sideband.h HDRTEST drivers/gpu/drm/i915/vlv_sideband_reg.h CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgk20a.o HDRTEST drivers/gpu/drm/i915/vlv_suspend.h CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_thermal.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm200.o LD [M] drivers/gpu/drm/i915/i915.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu10_hwmgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_psm.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_processpptables.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_hwmgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgm20b.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp100.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_thermal.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/pp_overdriver.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgp10b.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmgv100.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu_helper.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_processpptables.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_hwmgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_powertune.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/vmmtu102.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_thermal.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/common_baco.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega10_baco.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega20_baco.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/vega12_baco.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu9_baco.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/tonga_baco.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/polaris_baco.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/fiji_baco.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/umem.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/ummu.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/ci_baco.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/hwmgr/smu7_baco.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mmu/uvmm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/mxms.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/powerplay/amd_powerplay.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/legacy_dpm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/mxm/nv50.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_dpm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/agp.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/base.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/kv_smc.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_dpm.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/pcie.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/legacy-dpm/si_smc.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_pm.o CC [M] drivers/gpu/drm/amd/amdgpu/../pm/amdgpu_dpm_internal.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_plane.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv04.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv40.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crtc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_irq.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv46.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/nv4c.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_mst_types.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_color.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g84.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/dc_fpu.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g92.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_services.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_helpers.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/g94.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_pp_smu.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_psr.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gf106.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gk104.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_hdcp.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pci/gp100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_crc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/amdgpu_dm/amdgpu_dm_debugfs.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/base.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/conversion.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/memx.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/fixpt31_32.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/vector.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gt215.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/basics/dc_common.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf100.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gf119.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_interface.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_helper.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk104.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk110.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser_common.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table2.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk208.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/command_table_helper2.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gk20a.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm107.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm200.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gm20b.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/bios_parser2.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp102.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/pmu/gp10b.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce60/command_table_helper_dce60.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce80/command_table_helper_dce80.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce110/command_table_helper_dce110.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gf117.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk104.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper_dce112.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/bios/dce112/command_table_helper2_dce112.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gk20a.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dce_calcs.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gm200.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/privring/gp10b.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/custom_float.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/bw_fixed.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fan.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_lib.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fannil.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_rq_dlg_helpers.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dml1_display_rq_dlg_calc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn10/dcn10_fpu.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/dcn20_fpu.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/display_mode_vba.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fanpwm.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_rq_dlg_calc_20v2.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn20/display_mode_vba_20v2.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/fantog.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_rq_dlg_calc_21.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/ic.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn21/display_mode_vba_21.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/temp.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv40.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/nv50.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/dcn30_fpu.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/g84.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_mode_vba_30.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gt215.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf100.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gf119.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn30/display_rq_dlg_calc_30.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_mode_vba_31.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/display_rq_dlg_calc_31.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_mode_vba_314.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gk104.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/display_rq_dlg_calc_314.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm107.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gm200.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_32.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/therm/gp100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_rq_dlg_calc_32.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/display_mode_vba_util_32.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn31/dcn31_fpu.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv04.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn32/dcn32_fpu.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv40.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn321/dcn321_fpu.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/nv41.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn301/dcn301_fpu.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn302/dcn302_fpu.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn303/dcn303_fpu.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dcn314/dcn314_fpu.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/timer/gk20a.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/dsc/rc_calc_fpu.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/gk104.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calcs.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/top/ga100.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/uvfn.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/gv100.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/tu102.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/vfn/ga100.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gpio.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/nv40.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_math.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dml/calcs/dcn_calc_auto.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gf117.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk104.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gk20a.o CC [M] drivers/gpu/drm/nouveau/nvkm/subdev/volt/gm20b.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/falcon.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/xtensa.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce60/dce60_clk_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce100/dce_clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/bsp/g84.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce110/dce110_clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gt215.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gf100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce112/dce112_clk_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dce120/dce120_clk_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gk104.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm107.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gm200.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv1_clk_mgr_vbios_smu.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn10/rv2_clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gp102.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn20/dcn20_clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/gv100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn201/dcn201_clk_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn21/rn_clk_mgr_vbios_smu.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/tu102.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/ce/ga102.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/cipher/g84.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/acpi.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn30/dcn30_clk_mgr_smu_msg.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/vg_clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/ctrl.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/pci.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn301/dcn301_smu.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/tegra.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/device/user.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/base.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_smu.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/chan.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/conn.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/dp.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/hdmi.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/head.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ior.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn31/dcn31_clk_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_smu.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/outp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn314/dcn314_clk_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_smu.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/vga.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn315/dcn315_clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv04.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/nv50.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_smu.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn316/dcn316_clk_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g84.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/clk_mgr/dcn32/dcn32_clk_mgr_smu_msg.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_audio.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/g94.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt200.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_stream_encoder.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_link_encoder.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_hwseq.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_mem_input.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_clock_source.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp77.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_scl_filters.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_transform.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_opp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_dmcu.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gt215.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/mcp89.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gf119.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_abm.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk104.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gk110.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_ipp.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm107.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gm200.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_aux.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_hw.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp100.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gp102.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/gv100.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/tu102.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_i2c_sw.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_psr.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/ga102.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_abm_lcd.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dce_panel_cntl.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_hw_lock_mgr.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/dce/dmub_outbox.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/udisp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_base.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/gpio_service.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uconn.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uoutp.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/disp/uhead.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/base.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv04.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_factory.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_gpio.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_hpd.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/nv50.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_ddc.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_generic.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gf119.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/gv100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/hw_translate.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_translate_dce60.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/user.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv04.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usernv50.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf100.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergf119.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/dma/usergv100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce60/hw_factory_dce60.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/base.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_translate_dce80.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce80/hw_factory_dce80.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_translate_dce110.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce110/hw_factory_dce110.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/cgrp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_translate_dce120.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chan.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dce120/hw_factory_dce120.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_translate_dcn10.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn10/hw_factory_dcn10.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/chid.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runl.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_translate_dcn20.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/runq.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn20/hw_factory_dcn20.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv04.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv10.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv17.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_translate_dcn21.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv40.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv50.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/g84.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/g98.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn21/hw_factory_dcn21.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gf100.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk104.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn30/hw_translate_dcn30.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk110.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn30/hw_factory_dcn30.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk208.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gk20a.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm107.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gm200.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn315/hw_translate_dcn315.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gp100.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/gv100.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/tu102.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn315/hw_factory_dcn315.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn32/hw_translate_dcn32.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/gpio/dcn32/hw_factory_dcn32.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/irq_service.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce60/irq_service_dce60.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce80/irq_service_dce80.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce110/irq_service_dce110.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga100.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dce120/irq_service_dce120.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/ga102.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/ucgrp.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn10/irq_service_dcn10.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn20/irq_service_dcn20.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn21/irq_service_dcn21.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn201/irq_service_dcn201.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/fifo/uchan.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/base.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn30/irq_service_dcn30.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn302/irq_service_dcn302.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv04.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv10.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn303/irq_service_dcn303.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv15.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn31/irq_service_dcn31.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv17.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv20.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv25.o CC [M] drivers/gpu/drm/nouveau/nvkm/engine/gr/nv2a.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn314/irq_service_dcn314.o CC [M] drivers/gpu/drm/amd/amdgpu/../display/dc/irq/dcn315/irq_service_dcn315.o CC ^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-xe] ✗ CI.Hooks: failure for Rename engine to exec_queue 2023-07-31 16:08 [Intel-xe] [RFC PATCH 0/1] Rename engine to exec_queue Francois Dugast ` (4 preceding siblings ...) 2023-07-31 16:17 ` [Intel-xe] ✓ CI.Build: " Patchwork @ 2023-07-31 16:18 ` Patchwork 5 siblings, 0 replies; 9+ messages in thread From: Patchwork @ 2023-07-31 16:18 UTC (permalink / raw) To: Francois Dugast; +Cc: intel-xe == Series Details == Series: Rename engine to exec_queue URL : https://patchwork.freedesktop.org/series/121627/ State : failure == Summary == run-parts: executing /workspace/ci/hooks/00-showenv /workspace + pwd + ls -la total 720 drwxrwxr-x 10 1003 1003 4096 Jul 31 16:17 . drwxr-xr-x 1 root root 4096 Jul 31 16:17 .. -rw-rw-r-- 1 1003 1003 389647 Jul 31 16:17 build.log -rw-rw-r-- 1 1003 1003 2864 Jul 31 16:12 checkpatch.log drwxrwxr-x 5 1003 1003 4096 Jul 31 16:10 ci drwxrwxr-x 9 1003 1003 4096 Jul 31 16:10 docker drwxrwxr-x 8 1003 1003 4096 Jul 31 16:10 .git -rw-rw-r-- 1 1003 1003 228 Jul 31 16:12 git_apply.log drwxrwxr-x 3 1003 1003 4096 Jul 31 16:10 .github -rw-rw-r-- 1 1003 1003 233 Jul 31 16:10 .groovylintrc.json -rw-rw-r-- 1 1003 1003 78 Jul 31 16:17 hooks.log drwxrwxr-x 31 1003 1003 4096 Jul 31 16:17 kernel -rw-rw-r-- 1 1003 1003 247219 Jul 31 16:12 kernel.mbox -rw-rw-r-- 1 1003 1003 26091 Jul 31 16:13 kunit.log -rw-rw-r-- 1 1003 1003 48 Jul 31 16:12 parent.tag drwxrwxr-x 45 1003 1003 4096 Jul 31 16:10 pipelines -rw-rw-r-- 1 1003 1003 793 Jul 31 16:10 README.adoc drwxrwxr-x 3 1003 1003 4096 Jul 31 16:10 scripts drwxrwxr-x 2 1003 1003 4096 Jul 31 16:10 .vscode + uname -a Linux a2f8982dadc4 5.4.0-149-generic #166-Ubuntu SMP Tue Apr 18 16:51:45 UTC 2023 x86_64 x86_64 x86_64 GNU/Linux + export + grep -Ei '(^|\W)CI_' declare -x CI_KERNEL_BUILD_DIR="/workspace/kernel/build64" declare -x CI_KERNEL_IMAGES_DIR="/workspace/kernel/archive/boot" declare -x CI_KERNEL_MODULES_DIR="/workspace/kernel/archive" declare -x CI_KERNEL_SRC_DIR="/workspace/kernel" declare -x CI_SRC_DIR="/workspace/kernel" declare -x CI_TOOLS_SRC_DIR="/workspace/ci" declare -x CI_WORKSPACE_DIR="/workspace" + '[' -n /workspace ']' + git_args='-C /workspace/kernel' + git_log_args= + git --no-pager -C /workspace/kernel log --format=oneline --abbrev-commit f8ca940e0 drm/xe: Rename engine to exec_queue d74e8f840 drm/xe: Prefer WARN() over BUG() to avoid crashing the kernel run-parts: executing /workspace/ci/hooks/10-build-W1 + SRC_DIR=/workspace/kernel + RESTORE_DISPLAY_CONFIG=0 + '[' -n /workspace/kernel/build64 ']' + BUILD_DIR=/workspace/kernel/build64 + cd /workspace/kernel + grep -q -e '^CONFIG_DRM_XE_DISPLAY=[yY]' /workspace/kernel/build64/.config + RESTORE_DISPLAY_CONFIG=1 + trap cleanup EXIT + ./scripts/config --file /workspace/kernel/build64/.config --disable CONFIG_DRM_XE_DISPLAY ++ nproc + make -j48 O=/workspace/kernel/build64 modules_prepare make[1]: Entering directory '/workspace/kernel/build64' SYNC include/config/auto.conf.cmd GEN Makefile GEN Makefile UPD include/generated/compile.h UPD include/config/kernel.release UPD include/generated/utsrelease.h DESCEND objtool CALL ../scripts/checksyscalls.sh HOSTCC /workspace/kernel/build64/tools/objtool/fixdep.o HOSTLD /workspace/kernel/build64/tools/objtool/fixdep-in.o LINK /workspace/kernel/build64/tools/objtool/fixdep INSTALL libsubcmd_headers CC /workspace/kernel/build64/tools/objtool/libsubcmd/exec-cmd.o CC /workspace/kernel/build64/tools/objtool/libsubcmd/help.o CC /workspace/kernel/build64/tools/objtool/libsubcmd/pager.o CC /workspace/kernel/build64/tools/objtool/libsubcmd/parse-options.o CC /workspace/kernel/build64/tools/objtool/libsubcmd/run-command.o CC /workspace/kernel/build64/tools/objtool/libsubcmd/sigchain.o CC /workspace/kernel/build64/tools/objtool/libsubcmd/subcmd-config.o LD /workspace/kernel/build64/tools/objtool/libsubcmd/libsubcmd-in.o AR /workspace/kernel/build64/tools/objtool/libsubcmd/libsubcmd.a CC /workspace/kernel/build64/tools/objtool/weak.o CC /workspace/kernel/build64/tools/objtool/check.o CC /workspace/kernel/build64/tools/objtool/special.o CC /workspace/kernel/build64/tools/objtool/builtin-check.o CC /workspace/kernel/build64/tools/objtool/elf.o CC /workspace/kernel/build64/tools/objtool/objtool.o CC /workspace/kernel/build64/tools/objtool/orc_gen.o CC /workspace/kernel/build64/tools/objtool/orc_dump.o CC /workspace/kernel/build64/tools/objtool/libstring.o CC /workspace/kernel/build64/tools/objtool/libctype.o CC /workspace/kernel/build64/tools/objtool/str_error_r.o CC /workspace/kernel/build64/tools/objtool/librbtree.o CC /workspace/kernel/build64/tools/objtool/arch/x86/special.o CC /workspace/kernel/build64/tools/objtool/arch/x86/decode.o LD /workspace/kernel/build64/tools/objtool/arch/x86/objtool-in.o LD /workspace/kernel/build64/tools/objtool/objtool-in.o LINK /workspace/kernel/build64/tools/objtool/objtool make[1]: Leaving directory '/workspace/kernel/build64' ++ nproc + make -j48 O=/workspace/kernel/build64 M=drivers/gpu/drm/xe W=1 make[1]: Entering directory '/workspace/kernel/build64' CC [M] drivers/gpu/drm/xe/xe_bb.o CC [M] drivers/gpu/drm/xe/xe_bo.o CC [M] drivers/gpu/drm/xe/xe_bo_evict.o CC [M] drivers/gpu/drm/xe/xe_debugfs.o CC [M] drivers/gpu/drm/xe/xe_devcoredump.o CC [M] drivers/gpu/drm/xe/xe_device.o CC [M] drivers/gpu/drm/xe/xe_device_sysfs.o CC [M] drivers/gpu/drm/xe/xe_dma_buf.o CC [M] drivers/gpu/drm/xe/xe_exec.o CC [M] drivers/gpu/drm/xe/xe_execlist.o CC [M] drivers/gpu/drm/xe/xe_exec_queue.o CC [M] drivers/gpu/drm/xe/xe_force_wake.o CC [M] drivers/gpu/drm/xe/xe_ggtt.o CC [M] drivers/gpu/drm/xe/xe_gt.o CC [M] drivers/gpu/drm/xe/xe_gt_clock.o CC [M] drivers/gpu/drm/xe/xe_gt_debugfs.o CC [M] drivers/gpu/drm/xe/xe_gt_idle_sysfs.o CC [M] drivers/gpu/drm/xe/xe_gt_mcr.o CC [M] drivers/gpu/drm/xe/xe_gt_pagefault.o CC [M] drivers/gpu/drm/xe/xe_gt_sysfs.o CC [M] drivers/gpu/drm/xe/xe_gt_tlb_invalidation.o CC [M] drivers/gpu/drm/xe/xe_gt_topology.o HOSTCC drivers/gpu/drm/xe/xe_gen_wa_oob CC [M] drivers/gpu/drm/xe/xe_guc_ads.o CC [M] drivers/gpu/drm/xe/xe_guc_ct.o CC [M] drivers/gpu/drm/xe/xe_guc_debugfs.o CC [M] drivers/gpu/drm/xe/xe_guc_hwconfig.o CC [M] drivers/gpu/drm/xe/xe_guc_log.o CC [M] drivers/gpu/drm/xe/xe_guc_pc.o CC [M] drivers/gpu/drm/xe/xe_guc_submit.o CC [M] drivers/gpu/drm/xe/xe_hw_engine.o CC [M] drivers/gpu/drm/xe/xe_hw_fence.o CC [M] drivers/gpu/drm/xe/xe_huc.o CC [M] drivers/gpu/drm/xe/xe_huc_debugfs.o CC [M] drivers/gpu/drm/xe/xe_irq.o CC [M] drivers/gpu/drm/xe/xe_lrc.o CC [M] drivers/gpu/drm/xe/xe_migrate.o CC [M] drivers/gpu/drm/xe/xe_mmio.o CC [M] drivers/gpu/drm/xe/xe_mocs.o CC [M] drivers/gpu/drm/xe/xe_module.o CC [M] drivers/gpu/drm/xe/xe_pat.o CC [M] drivers/gpu/drm/xe/xe_pci.o CC [M] drivers/gpu/drm/xe/xe_pcode.o CC [M] drivers/gpu/drm/xe/xe_pm.o CC [M] drivers/gpu/drm/xe/xe_preempt_fence.o CC [M] drivers/gpu/drm/xe/xe_pt.o CC [M] drivers/gpu/drm/xe/xe_pt_walk.o CC [M] drivers/gpu/drm/xe/xe_query.o CC [M] drivers/gpu/drm/xe/xe_range_fence.o CC [M] drivers/gpu/drm/xe/xe_reg_sr.o CC [M] drivers/gpu/drm/xe/xe_reg_whitelist.o CC [M] drivers/gpu/drm/xe/xe_rtp.o CC [M] drivers/gpu/drm/xe/xe_sa.o CC [M] drivers/gpu/drm/xe/xe_sched_job.o CC [M] drivers/gpu/drm/xe/xe_step.o CC [M] drivers/gpu/drm/xe/xe_sync.o CC [M] drivers/gpu/drm/xe/xe_tile.o CC [M] drivers/gpu/drm/xe/xe_tile_sysfs.o CC [M] drivers/gpu/drm/xe/xe_trace.o CC [M] drivers/gpu/drm/xe/xe_ttm_sys_mgr.o CC [M] drivers/gpu/drm/xe/xe_ttm_stolen_mgr.o CC [M] drivers/gpu/drm/xe/xe_ttm_vram_mgr.o CC [M] drivers/gpu/drm/xe/xe_tuning.o CC [M] drivers/gpu/drm/xe/xe_uc.o CC [M] drivers/gpu/drm/xe/xe_uc_debugfs.o CC [M] drivers/gpu/drm/xe/xe_uc_fw.o CC [M] drivers/gpu/drm/xe/xe_vm.o CC [M] drivers/gpu/drm/xe/xe_vm_madvise.o CC [M] drivers/gpu/drm/xe/xe_wait_user_fence.o ../drivers/gpu/drm/xe/xe_preempt_fence.c:120: warning: Function parameter or member 'q' not described in 'xe_preempt_fence_arm' ../drivers/gpu/drm/xe/xe_preempt_fence.c:120: warning: Excess function parameter 'e' description in 'xe_preempt_fence_arm' ../drivers/gpu/drm/xe/xe_preempt_fence.c:145: warning: Function parameter or member 'q' not described in 'xe_preempt_fence_create' ../drivers/gpu/drm/xe/xe_preempt_fence.c:145: warning: Excess function parameter 'e' description in 'xe_preempt_fence_create' CC [M] drivers/gpu/drm/xe/xe_wopcm.o HDRTEST drivers/gpu/drm/xe/abi/guc_klvs_abi.h HDRTEST drivers/gpu/drm/xe/abi/guc_errors_abi.h CC [M] drivers/gpu/drm/xe/tests/xe_bo_test.o CC [M] drivers/gpu/drm/xe/tests/xe_dma_buf_test.o HDRTEST drivers/gpu/drm/xe/abi/guc_actions_slpc_abi.h HDRTEST drivers/gpu/drm/xe/abi/guc_communication_mmio_abi.h CC [M] drivers/gpu/drm/xe/tests/xe_migrate_test.o HDRTEST drivers/gpu/drm/xe/abi/guc_actions_abi.h CC [M] drivers/gpu/drm/xe/tests/xe_pci_test.o HDRTEST drivers/gpu/drm/xe/abi/guc_communication_ctb_abi.h CC [M] drivers/gpu/drm/xe/tests/xe_rtp_test.o HDRTEST drivers/gpu/drm/xe/abi/guc_messages_abi.h HDRTEST drivers/gpu/drm/xe/regs/xe_reg_defs.h HDRTEST drivers/gpu/drm/xe/regs/xe_guc_regs.h CC [M] drivers/gpu/drm/xe/tests/xe_wa_test.o HDRTEST drivers/gpu/drm/xe/regs/xe_gt_regs.h HDRTEST drivers/gpu/drm/xe/regs/xe_regs.h HDRTEST drivers/gpu/drm/xe/regs/xe_gpu_commands.h HDRTEST drivers/gpu/drm/xe/regs/xe_lrc_layout.h HDRTEST drivers/gpu/drm/xe/regs/xe_engine_regs.h HDRTEST drivers/gpu/drm/xe/tests/xe_test.h HDRTEST drivers/gpu/drm/xe/tests/xe_pci_test.h HDRTEST drivers/gpu/drm/xe/tests/xe_migrate_test.h HDRTEST drivers/gpu/drm/xe/tests/xe_dma_buf_test.h HDRTEST drivers/gpu/drm/xe/tests/xe_bo_test.h HDRTEST drivers/gpu/drm/xe/xe_bb.h HDRTEST drivers/gpu/drm/xe/xe_bb_types.h HDRTEST drivers/gpu/drm/xe/xe_bo.h HDRTEST drivers/gpu/drm/xe/xe_bo_doc.h HDRTEST drivers/gpu/drm/xe/xe_bo_evict.h HDRTEST drivers/gpu/drm/xe/xe_bo_types.h HDRTEST drivers/gpu/drm/xe/xe_debugfs.h HDRTEST drivers/gpu/drm/xe/xe_devcoredump.h HDRTEST drivers/gpu/drm/xe/xe_devcoredump_types.h HDRTEST drivers/gpu/drm/xe/xe_device.h HDRTEST drivers/gpu/drm/xe/xe_device_types.h HDRTEST drivers/gpu/drm/xe/xe_device_sysfs.h HDRTEST drivers/gpu/drm/xe/xe_dma_buf.h HDRTEST drivers/gpu/drm/xe/xe_drv.h HDRTEST drivers/gpu/drm/xe/xe_exec.h HDRTEST drivers/gpu/drm/xe/xe_exec_queue.h HDRTEST drivers/gpu/drm/xe/xe_exec_queue_types.h HDRTEST drivers/gpu/drm/xe/xe_execlist.h HDRTEST drivers/gpu/drm/xe/xe_execlist_types.h HDRTEST drivers/gpu/drm/xe/xe_force_wake.h HDRTEST drivers/gpu/drm/xe/xe_force_wake_types.h HDRTEST drivers/gpu/drm/xe/xe_ggtt.h HDRTEST drivers/gpu/drm/xe/xe_ggtt_types.h HDRTEST drivers/gpu/drm/xe/xe_gt.h HDRTEST drivers/gpu/drm/xe/xe_gt_clock.h HDRTEST drivers/gpu/drm/xe/xe_gt_debugfs.h HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs.h HDRTEST drivers/gpu/drm/xe/xe_gt_idle_sysfs_types.h HDRTEST drivers/gpu/drm/xe/xe_gt_mcr.h HDRTEST drivers/gpu/drm/xe/xe_gt_pagefault.h HDRTEST drivers/gpu/drm/xe/xe_gt_printk.h HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs.h HDRTEST drivers/gpu/drm/xe/xe_gt_sysfs_types.h HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation.h HDRTEST drivers/gpu/drm/xe/xe_gt_tlb_invalidation_types.h HDRTEST drivers/gpu/drm/xe/xe_gt_topology.h HDRTEST drivers/gpu/drm/xe/xe_gt_types.h HDRTEST drivers/gpu/drm/xe/xe_guc.h HDRTEST drivers/gpu/drm/xe/xe_guc_ads.h HDRTEST drivers/gpu/drm/xe/xe_guc_ads_types.h HDRTEST drivers/gpu/drm/xe/xe_guc_ct.h HDRTEST drivers/gpu/drm/xe/xe_guc_ct_types.h HDRTEST drivers/gpu/drm/xe/xe_guc_debugfs.h HDRTEST drivers/gpu/drm/xe/xe_guc_exec_queue_types.h HDRTEST drivers/gpu/drm/xe/xe_guc_fwif.h HDRTEST drivers/gpu/drm/xe/xe_guc_hwconfig.h HDRTEST drivers/gpu/drm/xe/xe_guc_log.h HDRTEST drivers/gpu/drm/xe/xe_guc_log_types.h HDRTEST drivers/gpu/drm/xe/xe_guc_pc.h HDRTEST drivers/gpu/drm/xe/xe_guc_pc_types.h HDRTEST drivers/gpu/drm/xe/xe_guc_submit.h HDRTEST drivers/gpu/drm/xe/xe_guc_submit_types.h HDRTEST drivers/gpu/drm/xe/xe_guc_types.h HDRTEST drivers/gpu/drm/xe/xe_huc.h HDRTEST drivers/gpu/drm/xe/xe_huc_debugfs.h HDRTEST drivers/gpu/drm/xe/xe_huc_types.h HDRTEST drivers/gpu/drm/xe/xe_hw_engine.h HDRTEST drivers/gpu/drm/xe/xe_hw_engine_types.h HDRTEST drivers/gpu/drm/xe/xe_hw_fence.h HDRTEST drivers/gpu/drm/xe/xe_hw_fence_types.h HDRTEST drivers/gpu/drm/xe/xe_irq.h HDRTEST drivers/gpu/drm/xe/xe_lrc.h HDRTEST drivers/gpu/drm/xe/xe_lrc_types.h HDRTEST drivers/gpu/drm/xe/xe_macros.h HDRTEST drivers/gpu/drm/xe/xe_map.h HDRTEST drivers/gpu/drm/xe/xe_migrate.h HDRTEST drivers/gpu/drm/xe/xe_migrate_doc.h HDRTEST drivers/gpu/drm/xe/xe_mmio.h HDRTEST drivers/gpu/drm/xe/xe_mocs.h HDRTEST drivers/gpu/drm/xe/xe_module.h HDRTEST drivers/gpu/drm/xe/xe_pat.h HDRTEST drivers/gpu/drm/xe/xe_pci.h HDRTEST drivers/gpu/drm/xe/xe_pci_types.h HDRTEST drivers/gpu/drm/xe/xe_pcode.h HDRTEST drivers/gpu/drm/xe/xe_pcode_api.h HDRTEST drivers/gpu/drm/xe/xe_platform_types.h HDRTEST drivers/gpu/drm/xe/xe_pm.h HDRTEST drivers/gpu/drm/xe/xe_preempt_fence.h HDRTEST drivers/gpu/drm/xe/xe_preempt_fence_types.h HDRTEST drivers/gpu/drm/xe/xe_pt.h HDRTEST drivers/gpu/drm/xe/xe_pt_types.h HDRTEST drivers/gpu/drm/xe/xe_pt_walk.h HDRTEST drivers/gpu/drm/xe/xe_query.h HDRTEST drivers/gpu/drm/xe/xe_range_fence.h HDRTEST drivers/gpu/drm/xe/xe_reg_sr.h HDRTEST drivers/gpu/drm/xe/xe_reg_sr_types.h HDRTEST drivers/gpu/drm/xe/xe_reg_whitelist.h HDRTEST drivers/gpu/drm/xe/xe_res_cursor.h HDRTEST drivers/gpu/drm/xe/xe_ring_ops.h HDRTEST drivers/gpu/drm/xe/xe_ring_ops_types.h HDRTEST drivers/gpu/drm/xe/xe_rtp.h HDRTEST drivers/gpu/drm/xe/xe_rtp_types.h HDRTEST drivers/gpu/drm/xe/xe_sa.h HDRTEST drivers/gpu/drm/xe/xe_sa_types.h HDRTEST drivers/gpu/drm/xe/xe_sched_job.h HDRTEST drivers/gpu/drm/xe/xe_sched_job_types.h HDRTEST drivers/gpu/drm/xe/xe_step.h HDRTEST drivers/gpu/drm/xe/xe_sync.h HDRTEST drivers/gpu/drm/xe/xe_step_types.h HDRTEST drivers/gpu/drm/xe/xe_sync_types.h HDRTEST drivers/gpu/drm/xe/xe_tile.h HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs.h HDRTEST drivers/gpu/drm/xe/xe_tile_sysfs_types.h HDRTEST drivers/gpu/drm/xe/xe_trace.h HDRTEST drivers/gpu/drm/xe/xe_ttm_stolen_mgr.h HDRTEST drivers/gpu/drm/xe/xe_ttm_sys_mgr.h HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr.h HDRTEST drivers/gpu/drm/xe/xe_tuning.h HDRTEST drivers/gpu/drm/xe/xe_ttm_vram_mgr_types.h HDRTEST drivers/gpu/drm/xe/xe_uc.h HDRTEST drivers/gpu/drm/xe/xe_uc_fw.h HDRTEST drivers/gpu/drm/xe/xe_uc_debugfs.h HDRTEST drivers/gpu/drm/xe/xe_uc_fw_abi.h HDRTEST drivers/gpu/drm/xe/xe_uc_fw_types.h HDRTEST drivers/gpu/drm/xe/xe_uc_types.h HDRTEST drivers/gpu/drm/xe/xe_vm.h HDRTEST drivers/gpu/drm/xe/xe_vm_doc.h HDRTEST drivers/gpu/drm/xe/xe_vm_madvise.h HDRTEST drivers/gpu/drm/xe/xe_vm_types.h HDRTEST drivers/gpu/drm/xe/xe_wa.h HDRTEST drivers/gpu/drm/xe/xe_wait_user_fence.h HDRTEST drivers/gpu/drm/xe/xe_wopcm.h HDRTEST drivers/gpu/drm/xe/xe_wopcm_types.h GEN xe_wa_oob.c xe_wa_oob.h GEN xe_wa_oob.c xe_wa_oob.h CC [M] drivers/gpu/drm/xe/xe_guc.o CC [M] drivers/gpu/drm/xe/xe_ring_ops.o CC [M] drivers/gpu/drm/xe/xe_wa.o ../drivers/gpu/drm/xe/xe_guc_submit.c:1730: warning: Function parameter or member 'q' not described in 'xe_guc_exec_queue_snapshot_capture' ../drivers/gpu/drm/xe/xe_guc_submit.c:1730: warning: Excess function parameter 'e' description in 'xe_guc_exec_queue_snapshot_capture' ../drivers/gpu/drm/xe/xe_migrate.c:65: warning: Function parameter or member 'q' not described in 'xe_migrate' ../drivers/gpu/drm/xe/xe_migrate.c:1140: warning: Function parameter or member 'q' not described in 'xe_migrate_update_pgtables' ../drivers/gpu/drm/xe/xe_migrate.c:1140: warning: Excess function parameter 'eng' description in 'xe_migrate_update_pgtables' LD [M] drivers/gpu/drm/xe/xe.o MODPOST drivers/gpu/drm/xe/Module.symvers CC [M] drivers/gpu/drm/xe/xe.mod.o CC [M] drivers/gpu/drm/xe/tests/xe_bo_test.mod.o CC [M] drivers/gpu/drm/xe/tests/xe_dma_buf_test.mod.o CC [M] drivers/gpu/drm/xe/tests/xe_migrate_test.mod.o CC [M] drivers/gpu/drm/xe/tests/xe_pci_test.mod.o CC [M] drivers/gpu/drm/xe/tests/xe_rtp_test.mod.o CC [M] drivers/gpu/drm/xe/tests/xe_wa_test.mod.o LD [M] drivers/gpu/drm/xe/tests/xe_rtp_test.ko LD [M] drivers/gpu/drm/xe/xe.ko LD [M] drivers/gpu/drm/xe/tests/xe_wa_test.ko LD [M] drivers/gpu/drm/xe/tests/xe_pci_test.ko LD [M] drivers/gpu/drm/xe/tests/xe_migrate_test.ko LD [M] drivers/gpu/drm/xe/tests/xe_bo_test.ko LD [M] drivers/gpu/drm/xe/tests/xe_dma_buf_test.ko make[1]: Leaving directory '/workspace/kernel/build64' + cleanup + '[' 1 -eq 1 ']' + ./scripts/config --file /workspace/kernel/build64/.config --enable CONFIG_DRM_XE_DISPLAY run-parts: executing /workspace/ci/hooks/20-kernel-doc + SRC_DIR=/workspace/kernel + cd /workspace/kernel + find drivers/gpu/drm/xe/ -name '*.[ch]' -not -path 'drivers/gpu/drm/xe/display/*' + xargs ./scripts/kernel-doc -Werror -none include/uapi/drm/xe_drm.h drivers/gpu/drm/xe/xe_sched_job_types.h:45: warning: Function parameter or member 'q' not described in 'xe_sched_job' drivers/gpu/drm/xe/xe_device_types.h:499: warning: Function parameter or member 'exec_queue' not described in 'xe_file' drivers/gpu/drm/xe/xe_preempt_fence.c:121: warning: Function parameter or member 'q' not described in 'xe_preempt_fence_arm' drivers/gpu/drm/xe/xe_preempt_fence.c:121: warning: Excess function parameter 'e' description in 'xe_preempt_fence_arm' drivers/gpu/drm/xe/xe_preempt_fence.c:146: warning: Function parameter or member 'q' not described in 'xe_preempt_fence_create' drivers/gpu/drm/xe/xe_preempt_fence.c:146: warning: Excess function parameter 'e' description in 'xe_preempt_fence_create' drivers/gpu/drm/xe/xe_migrate.c:66: warning: Function parameter or member 'q' not described in 'xe_migrate' drivers/gpu/drm/xe/xe_migrate.c:1141: warning: Function parameter or member 'q' not described in 'xe_migrate_update_pgtables' drivers/gpu/drm/xe/xe_migrate.c:1141: warning: Excess function parameter 'eng' description in 'xe_migrate_update_pgtables' drivers/gpu/drm/xe/xe_guc_submit.c:1731: warning: Function parameter or member 'q' not described in 'xe_guc_exec_queue_snapshot_capture' drivers/gpu/drm/xe/xe_guc_submit.c:1731: warning: Excess function parameter 'e' description in 'xe_guc_exec_queue_snapshot_capture' drivers/gpu/drm/xe/xe_preempt_fence_types.h:31: warning: Function parameter or member 'q' not described in 'xe_preempt_fence' drivers/gpu/drm/xe/xe_guc_exec_queue_types.h:53: warning: Function parameter or member 'q' not described in 'xe_guc_exec_queue' 13 warnings as Errors run-parts: /workspace/ci/hooks/20-kernel-doc exited with return code 123 ^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-07-31 19:20 UTC | newest] Thread overview: 9+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2023-07-31 16:08 [Intel-xe] [RFC PATCH 0/1] Rename engine to exec_queue Francois Dugast 2023-07-31 16:08 ` [Intel-xe] [RFC PATCH 1/1] drm/xe: " Francois Dugast 2023-07-31 18:03 ` Rodrigo Vivi 2023-07-31 19:19 ` Francois Dugast 2023-07-31 16:12 ` [Intel-xe] ✓ CI.Patch_applied: success for " Patchwork 2023-07-31 16:12 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork 2023-07-31 16:14 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork 2023-07-31 16:17 ` [Intel-xe] ✓ CI.Build: " Patchwork 2023-07-31 16:18 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
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