Re: [PATCH 2/3] riscv: kprobes: simulate c.jr and c.jalr instructions

[Charlie Jenkins <charlie@rivosinc.com>]

On Sun, Jul 30, 2023 at 10:27:08AM +0200, Nam Cao wrote:
> kprobes currently rejects c.jr and c.jalr instructions. Implement them.
> 
> Signed-off-by: Nam Cao <namcaov@gmail.com>
> ---
>  arch/riscv/kernel/probes/decode-insn.c   |  4 +--
>  arch/riscv/kernel/probes/simulate-insn.c | 37 ++++++++++++++++++++++++
>  arch/riscv/kernel/probes/simulate-insn.h |  2 ++
>  3 files changed, 41 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/riscv/kernel/probes/decode-insn.c b/arch/riscv/kernel/probes/decode-insn.c
> index 39adb07a342d..6dba23a55ac7 100644
> --- a/arch/riscv/kernel/probes/decode-insn.c
> +++ b/arch/riscv/kernel/probes/decode-insn.c
> @@ -29,14 +29,14 @@ riscv_probe_decode_insn(probe_opcode_t *addr, struct arch_probe_insn *api)
>  	 * TODO: the REJECTED ones below need to be implemented
>  	 */
>  #ifdef CONFIG_RISCV_ISA_C
> -	RISCV_INSN_REJECTED(c_jr,		insn);
>  	RISCV_INSN_REJECTED(c_jal,		insn);
> -	RISCV_INSN_REJECTED(c_jalr,		insn);
>  	RISCV_INSN_REJECTED(c_beqz,		insn);
>  	RISCV_INSN_REJECTED(c_bnez,		insn);
>  	RISCV_INSN_REJECTED(c_ebreak,		insn);
>  
>  	RISCV_INSN_SET_SIMULATE(c_j,		insn);
> +	RISCV_INSN_SET_SIMULATE(c_jr,		insn);
> +	RISCV_INSN_SET_SIMULATE(c_jalr,		insn);
>  #endif
>  
>  	RISCV_INSN_SET_SIMULATE(jal,		insn);
> diff --git a/arch/riscv/kernel/probes/simulate-insn.c b/arch/riscv/kernel/probes/simulate-insn.c
> index 3ba45c612cd8..1ead6f4951f9 100644
> --- a/arch/riscv/kernel/probes/simulate-insn.c
> +++ b/arch/riscv/kernel/probes/simulate-insn.c
> @@ -212,3 +212,40 @@ bool __kprobes simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs
>  
>  	return true;
>  }
> +
> +static bool __kprobes simulate_c_jr_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs,
> +					 bool is_jalr)
> +{
> +	/*
> +	 *  15    12 11  7 6   2 1  0
> +	 * | funct4 | rs1 | rs2 | op |
> +	 *     4       5     5    2
> +	 */
> +
> +	unsigned long jump_addr;
> +
> +	u32 rs1 = (opcode >> 7) & 0x1f;
> +
> +	if (rs1 == 0) /* C.JR is only valid when rs1 != x0 */
> +		return false;
> +
> +	if (!rv_insn_reg_get_val(regs, rs1, &jump_addr))
> +		return false;
> +
> +	if (is_jalr && !rv_insn_reg_set_val(regs, 1, addr + 2))
> +		return false;
> +
> +	instruction_pointer_set(regs, jump_addr);
> +
> +	return true;
> +}
> +
> +bool __kprobes simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs)
> +{
> +	return simulate_c_jr_jalr(opcode, addr, regs, false);
> +}
> +
> +bool __kprobes simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs)
> +{
> +	return simulate_c_jr_jalr(opcode, addr, regs, true);
> +}
> diff --git a/arch/riscv/kernel/probes/simulate-insn.h b/arch/riscv/kernel/probes/simulate-insn.h
> index 4bd6c266e7d3..472a1948ec4f 100644
> --- a/arch/riscv/kernel/probes/simulate-insn.h
> +++ b/arch/riscv/kernel/probes/simulate-insn.h
> @@ -25,5 +25,7 @@ bool simulate_branch(u32 opcode, unsigned long addr, struct pt_regs *regs);
>  bool simulate_jal(u32 opcode, unsigned long addr, struct pt_regs *regs);
>  bool simulate_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
>  bool simulate_c_j(u32 opcode, unsigned long addr, struct pt_regs *regs);
> +bool simulate_c_jr(u32 opcode, unsigned long addr, struct pt_regs *regs);
> +bool simulate_c_jalr(u32 opcode, unsigned long addr, struct pt_regs *regs);
>  
>  #endif /* _RISCV_KERNEL_PROBES_SIMULATE_INSN_H */
> -- 
> 2.34.1
> 
> 
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Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>

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