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From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: <ajones@ventanamicro.com>, <heiko@sntech.de>,
	<samuel@sholland.org>, <geert+renesas@glider.be>,
	<n.shubin@yadro.com>, <dminus@andestech.com>,
	<ycliang@andestech.com>, <tim609@andestech.com>,
	<locus84@andestech.com>, <dylan@andestech.com>,
	<linux-riscv@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<conor.dooley@microchip.com>, <atishp@atishpatra.org>,
	<anup@brainfault.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 3/4] riscv: errata: Add Andes PMU errata
Date: Mon, 11 Sep 2023 10:38:56 +0800	[thread overview]
Message-ID: <ZP59wF5Knq3G7On_@APC323> (raw)
In-Reply-To: <82a82449-3af0-4756-881a-b31b6b187e6c@sifive.com>

Hi Samuel,

On Wed, Sep 06, 2023 at 09:48:35PM -0500, Samuel Holland wrote:
> If the code here needs to be different, then it must check that it is actually
> running on an Andes core, not just that the errata Kconfig option is enabled.

Thank you for catching this, will fix in PATCH v2.

> However, I suggest setting riscv_pmu_irq_num to the real IRQ number:
>   riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMU;
> and then adding a new variable for the mask:
>   riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG);
> which handles the large IRQ number somewhat more generically, and reduces the
> number of bit operations needed elsewhere in the driver.

I will make changes according to your suggestions. Thank you!

> Or we could use IRQ chip operations here instead of direct CSR acccess. But
> maybe the direct CSR access is needed for performance?
> 
> Regards,
> Samuel

Best regards,
Peter Lin

WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: <ajones@ventanamicro.com>, <heiko@sntech.de>,
	<samuel@sholland.org>, <geert+renesas@glider.be>,
	<n.shubin@yadro.com>, <dminus@andestech.com>,
	<ycliang@andestech.com>, <tim609@andestech.com>,
	<locus84@andestech.com>, <dylan@andestech.com>,
	<linux-riscv@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<conor.dooley@microchip.com>, <atishp@atishpatra.org>,
	<anup@brainfault.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 3/4] riscv: errata: Add Andes PMU errata
Date: Mon, 11 Sep 2023 10:38:56 +0800	[thread overview]
Message-ID: <ZP59wF5Knq3G7On_@APC323> (raw)
In-Reply-To: <82a82449-3af0-4756-881a-b31b6b187e6c@sifive.com>

Hi Samuel,

On Wed, Sep 06, 2023 at 09:48:35PM -0500, Samuel Holland wrote:
> If the code here needs to be different, then it must check that it is actually
> running on an Andes core, not just that the errata Kconfig option is enabled.

Thank you for catching this, will fix in PATCH v2.

> However, I suggest setting riscv_pmu_irq_num to the real IRQ number:
>   riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMU;
> and then adding a new variable for the mask:
>   riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG);
> which handles the large IRQ number somewhat more generically, and reduces the
> number of bit operations needed elsewhere in the driver.

I will make changes according to your suggestions. Thank you!

> Or we could use IRQ chip operations here instead of direct CSR acccess. But
> maybe the direct CSR access is needed for performance?
> 
> Regards,
> Samuel

Best regards,
Peter Lin

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Samuel Holland <samuel.holland@sifive.com>
Cc: <ajones@ventanamicro.com>, <heiko@sntech.de>,
	<samuel@sholland.org>, <geert+renesas@glider.be>,
	<n.shubin@yadro.com>, <dminus@andestech.com>,
	<ycliang@andestech.com>, <tim609@andestech.com>,
	<locus84@andestech.com>, <dylan@andestech.com>,
	<linux-riscv@lists.infradead.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>,
	<linux-perf-users@vger.kernel.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>,
	<conor.dooley@microchip.com>, <atishp@atishpatra.org>,
	<anup@brainfault.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH 3/4] riscv: errata: Add Andes PMU errata
Date: Mon, 11 Sep 2023 10:38:56 +0800	[thread overview]
Message-ID: <ZP59wF5Knq3G7On_@APC323> (raw)
In-Reply-To: <82a82449-3af0-4756-881a-b31b6b187e6c@sifive.com>

Hi Samuel,

On Wed, Sep 06, 2023 at 09:48:35PM -0500, Samuel Holland wrote:
> If the code here needs to be different, then it must check that it is actually
> running on an Andes core, not just that the errata Kconfig option is enabled.

Thank you for catching this, will fix in PATCH v2.

> However, I suggest setting riscv_pmu_irq_num to the real IRQ number:
>   riscv_pmu_irq_num = ANDES_SLI_CAUSE_BASE + ANDES_RV_IRQ_PMU;
> and then adding a new variable for the mask:
>   riscv_pmu_irq_mask = BIT(riscv_pmu_irq_num % BITS_PER_LONG);
> which handles the large IRQ number somewhat more generically, and reduces the
> number of bit operations needed elsewhere in the driver.

I will make changes according to your suggestions. Thank you!

> Or we could use IRQ chip operations here instead of direct CSR acccess. But
> maybe the direct CSR access is needed for performance?
> 
> Regards,
> Samuel

Best regards,
Peter Lin

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

  reply	other threads:[~2023-09-11  2:40 UTC|newest]

Thread overview: 45+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-07  2:16 [PATCH 0/4] Support Andes PMU extension Yu Chien Peter Lin
2023-09-07  2:16 ` Yu Chien Peter Lin
2023-09-07  2:16 ` Yu Chien Peter Lin
2023-09-07  2:16 ` [PATCH 1/4] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2023-09-07  2:16   ` Yu Chien Peter Lin
2023-09-07  2:16   ` Yu Chien Peter Lin
2023-09-07  2:16 ` [RFC PATCH 2/4] irqchip/riscv-intc: Support large non-standard hwirq number Yu Chien Peter Lin
2023-09-07  2:16   ` Yu Chien Peter Lin
2023-09-07  2:16   ` Yu Chien Peter Lin
2023-09-07 10:22   ` Clément Léger
2023-09-07 10:22     ` Clément Léger
2023-09-07 10:22     ` Clément Léger
2023-09-11  8:04     ` Yu-Chien Peter Lin
2023-09-11  8:04       ` Yu-Chien Peter Lin
2023-09-11  8:04       ` Yu-Chien Peter Lin
2023-09-07 13:06   ` Anup Patel
2023-09-07 13:06     ` Anup Patel
2023-09-07 13:06     ` Anup Patel
2023-09-11  8:12     ` Yu-Chien Peter Lin
2023-09-11  8:12       ` Yu-Chien Peter Lin
2023-09-11  8:12       ` Yu-Chien Peter Lin
2023-09-07  2:16 ` [PATCH 3/4] riscv: errata: Add Andes PMU errata Yu Chien Peter Lin
2023-09-07  2:16   ` Yu Chien Peter Lin
2023-09-07  2:16   ` Yu Chien Peter Lin
2023-09-07  2:48   ` Samuel Holland
2023-09-07  2:48     ` Samuel Holland
2023-09-07  2:48     ` Samuel Holland
2023-09-11  2:38     ` Yu-Chien Peter Lin [this message]
2023-09-11  2:38       ` Yu-Chien Peter Lin
2023-09-11  2:38       ` Yu-Chien Peter Lin
2023-09-07  9:27   ` Conor Dooley
2023-09-07  9:27     ` Conor Dooley
2023-09-07  9:27     ` Conor Dooley
2023-09-07 11:02     ` Conor Dooley
2023-09-07 11:02       ` Conor Dooley
2023-09-07 11:02       ` Conor Dooley
2023-09-11  2:48       ` Yu-Chien Peter Lin
2023-09-11  2:48         ` Yu-Chien Peter Lin
2023-09-11  2:48         ` Yu-Chien Peter Lin
2023-09-11 12:35         ` Conor Dooley
2023-09-11 12:35           ` Conor Dooley
2023-09-11 12:35           ` Conor Dooley
2023-09-07  2:16 ` [PATCH 4/4] riscv: andes: Support symbolic FW and HW raw events Yu Chien Peter Lin
2023-09-07  2:16   ` Yu Chien Peter Lin
2023-09-07  2:16   ` Yu Chien Peter Lin

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