* [Intel-gfx] [PATCH v2 01/22] drm/i915/dp: Factor out helpers to compute the link limits
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-24 8:04 ` Imre Deak
2023-09-04 3:19 ` Ville Syrjälä
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (25 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:04 UTC (permalink / raw)
To: intel-gfx
Factor out helpers that DP / DP_MST encoders can use to compute the link
rate/lane count and bpp limits. A follow-up patch will call these to
recalculate the limits if DSC compression is required.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 61 +++++++++++++--------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 ++++++++++--------
2 files changed, 68 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 7067ee3a4bd36..53697f361f950 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2187,29 +2187,25 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return 0;
}
-static int
-intel_dp_compute_link_config(struct intel_encoder *encoder,
- struct intel_crtc_state *pipe_config,
- struct drm_connector_state *conn_state,
- bool respect_downstream_limits)
+static void
+intel_dp_compute_config_limits(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ bool respect_downstream_limits,
+ struct link_config_limits *limits)
{
- struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
const struct drm_display_mode *adjusted_mode =
- &pipe_config->hw.adjusted_mode;
- struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
- struct link_config_limits limits;
- bool joiner_needs_dsc = false;
- int ret;
+ &crtc_state->hw.adjusted_mode;
- limits.min_rate = intel_dp_common_rate(intel_dp, 0);
- limits.max_rate = intel_dp_max_link_rate(intel_dp);
+ limits->min_rate = intel_dp_common_rate(intel_dp, 0);
+ limits->max_rate = intel_dp_max_link_rate(intel_dp);
- limits.min_lane_count = 1;
- limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
+ limits->min_lane_count = 1;
+ limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
- limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
- limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
+ limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
+ respect_downstream_limits);
if (intel_dp->use_max_params) {
/*
@@ -2220,16 +2216,35 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
* configuration, and typically on older panels these
* values correspond to the native resolution of the panel.
*/
- limits.min_lane_count = limits.max_lane_count;
- limits.min_rate = limits.max_rate;
+ limits->min_lane_count = limits->max_lane_count;
+ limits->min_rate = limits->max_rate;
}
- intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
+ intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
"max rate %d max bpp %d pixel clock %iKHz\n",
- limits.max_lane_count, limits.max_rate,
- limits.max_bpp, adjusted_mode->crtc_clock);
+ limits->max_lane_count, limits->max_rate,
+ limits->max_bpp, adjusted_mode->crtc_clock);
+}
+
+static int
+intel_dp_compute_link_config(struct intel_encoder *encoder,
+ struct intel_crtc_state *pipe_config,
+ struct drm_connector_state *conn_state,
+ bool respect_downstream_limits)
+{
+ struct drm_i915_private *i915 = to_i915(encoder->base.dev);
+ struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
+ const struct drm_display_mode *adjusted_mode =
+ &pipe_config->hw.adjusted_mode;
+ struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
+ struct link_config_limits limits;
+ bool joiner_needs_dsc = false;
+ int ret;
+
+ intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits, &limits);
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3eb085fbc7c82..218c2dfd57adc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -306,6 +306,35 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}
+static void
+intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ struct link_config_limits *limits)
+{
+ /*
+ * for MST we always configure max link bw - the spec doesn't
+ * seem to suggest we should do otherwise.
+ */
+ limits->min_rate = limits->max_rate =
+ intel_dp_max_link_rate(intel_dp);
+
+ limits->min_lane_count = limits->max_lane_count =
+ intel_dp_max_lane_count(intel_dp);
+
+ limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ /*
+ * FIXME: If all the streams can't fit into the link with
+ * their current pipe_bpp we should reduce pipe_bpp across
+ * the board until things start to fit. Until then we
+ * limit to <= 8bpc since that's what was hardcoded for all
+ * MST streams previously. This hack should be removed once
+ * we have the proper retry logic in place.
+ */
+ limits->max_bpp = min(crtc_state->pipe_bpp, 24);
+
+ intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
+}
+
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -329,28 +358,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_dp_mst_has_audio(conn_state) &&
intel_audio_compute_config(encoder, pipe_config, conn_state);
- /*
- * for MST we always configure max link bw - the spec doesn't
- * seem to suggest we should do otherwise.
- */
- limits.min_rate =
- limits.max_rate = intel_dp_max_link_rate(intel_dp);
-
- limits.min_lane_count =
- limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
-
- limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
- /*
- * FIXME: If all the streams can't fit into the link with
- * their current pipe_bpp we should reduce pipe_bpp across
- * the board until things start to fit. Until then we
- * limit to <= 8bpc since that's what was hardcoded for all
- * MST streams previously. This hack should be removed once
- * we have the proper retry logic in place.
- */
- limits.max_bpp = min(pipe_config->pipe_bpp, 24);
-
- intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
+ intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
conn_state, &limits);
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 01/22] drm/i915/dp: Factor out helpers to compute the link limits
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/dp: Factor out helpers to compute the link limits Imre Deak
@ 2023-09-04 3:19 ` Ville Syrjälä
2023-09-04 10:25 ` Imre Deak
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2023-09-04 3:19 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:04:56AM +0300, Imre Deak wrote:
> Factor out helpers that DP / DP_MST encoders can use to compute the link
> rate/lane count and bpp limits. A follow-up patch will call these to
> recalculate the limits if DSC compression is required.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 61 +++++++++++++--------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 ++++++++++--------
> 2 files changed, 68 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 7067ee3a4bd36..53697f361f950 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2187,29 +2187,25 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> return 0;
> }
>
> -static int
> -intel_dp_compute_link_config(struct intel_encoder *encoder,
> - struct intel_crtc_state *pipe_config,
> - struct drm_connector_state *conn_state,
> - bool respect_downstream_limits)
> +static void
> +intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state,
> + bool respect_downstream_limits,
> + struct link_config_limits *limits)
> {
> - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> const struct drm_display_mode *adjusted_mode =
> - &pipe_config->hw.adjusted_mode;
> - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> - struct link_config_limits limits;
> - bool joiner_needs_dsc = false;
> - int ret;
> + &crtc_state->hw.adjusted_mode;
>
> - limits.min_rate = intel_dp_common_rate(intel_dp, 0);
> - limits.max_rate = intel_dp_max_link_rate(intel_dp);
> + limits->min_rate = intel_dp_common_rate(intel_dp, 0);
> + limits->max_rate = intel_dp_max_link_rate(intel_dp);
>
> - limits.min_lane_count = 1;
> - limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> + limits->min_lane_count = 1;
> + limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
>
> - limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
> - limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
> + limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> + limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
> + respect_downstream_limits);
>
> if (intel_dp->use_max_params) {
> /*
> @@ -2220,16 +2216,35 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> * configuration, and typically on older panels these
> * values correspond to the native resolution of the panel.
> */
> - limits.min_lane_count = limits.max_lane_count;
> - limits.min_rate = limits.max_rate;
> + limits->min_lane_count = limits->max_lane_count;
> + limits->min_rate = limits->max_rate;
> }
>
> - intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
> + intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
Annoying little bugger that mutates the crtc_state. Would be nice
to relocate that small part somewhere else so that we could constify
things more...
Anyways
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
> "max rate %d max bpp %d pixel clock %iKHz\n",
> - limits.max_lane_count, limits.max_rate,
> - limits.max_bpp, adjusted_mode->crtc_clock);
> + limits->max_lane_count, limits->max_rate,
> + limits->max_bpp, adjusted_mode->crtc_clock);
> +}
> +
> +static int
> +intel_dp_compute_link_config(struct intel_encoder *encoder,
> + struct intel_crtc_state *pipe_config,
> + struct drm_connector_state *conn_state,
> + bool respect_downstream_limits)
> +{
> + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> + const struct drm_display_mode *adjusted_mode =
> + &pipe_config->hw.adjusted_mode;
> + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> + struct link_config_limits limits;
> + bool joiner_needs_dsc = false;
> + int ret;
> +
> + intel_dp_compute_config_limits(intel_dp, pipe_config,
> + respect_downstream_limits, &limits);
>
> if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
> adjusted_mode->crtc_clock))
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 3eb085fbc7c82..218c2dfd57adc 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -306,6 +306,35 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
> return intel_conn_state->force_audio == HDMI_AUDIO_ON;
> }
>
> +static void
> +intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> + struct intel_crtc_state *crtc_state,
> + struct link_config_limits *limits)
> +{
> + /*
> + * for MST we always configure max link bw - the spec doesn't
> + * seem to suggest we should do otherwise.
> + */
> + limits->min_rate = limits->max_rate =
> + intel_dp_max_link_rate(intel_dp);
> +
> + limits->min_lane_count = limits->max_lane_count =
> + intel_dp_max_lane_count(intel_dp);
> +
> + limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> + /*
> + * FIXME: If all the streams can't fit into the link with
> + * their current pipe_bpp we should reduce pipe_bpp across
> + * the board until things start to fit. Until then we
> + * limit to <= 8bpc since that's what was hardcoded for all
> + * MST streams previously. This hack should be removed once
> + * we have the proper retry logic in place.
> + */
> + limits->max_bpp = min(crtc_state->pipe_bpp, 24);
> +
> + intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> +}
> +
> static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> struct intel_crtc_state *pipe_config,
> struct drm_connector_state *conn_state)
> @@ -329,28 +358,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> intel_dp_mst_has_audio(conn_state) &&
> intel_audio_compute_config(encoder, pipe_config, conn_state);
>
> - /*
> - * for MST we always configure max link bw - the spec doesn't
> - * seem to suggest we should do otherwise.
> - */
> - limits.min_rate =
> - limits.max_rate = intel_dp_max_link_rate(intel_dp);
> -
> - limits.min_lane_count =
> - limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> -
> - limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
> - /*
> - * FIXME: If all the streams can't fit into the link with
> - * their current pipe_bpp we should reduce pipe_bpp across
> - * the board until things start to fit. Until then we
> - * limit to <= 8bpc since that's what was hardcoded for all
> - * MST streams previously. This hack should be removed once
> - * we have the proper retry logic in place.
> - */
> - limits.max_bpp = min(pipe_config->pipe_bpp, 24);
> -
> - intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
> + intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
>
> ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
> conn_state, &limits);
> --
> 2.37.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 01/22] drm/i915/dp: Factor out helpers to compute the link limits
2023-09-04 3:19 ` Ville Syrjälä
@ 2023-09-04 10:25 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-09-04 10:25 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Sep 04, 2023 at 06:19:04AM +0300, Ville Syrjälä wrote:
> On Thu, Aug 24, 2023 at 11:04:56AM +0300, Imre Deak wrote:
> > Factor out helpers that DP / DP_MST encoders can use to compute the link
> > rate/lane count and bpp limits. A follow-up patch will call these to
> > recalculate the limits if DSC compression is required.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp.c | 61 +++++++++++++--------
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 52 ++++++++++--------
> > 2 files changed, 68 insertions(+), 45 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 7067ee3a4bd36..53697f361f950 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2187,29 +2187,25 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > return 0;
> > }
> >
> > -static int
> > -intel_dp_compute_link_config(struct intel_encoder *encoder,
> > - struct intel_crtc_state *pipe_config,
> > - struct drm_connector_state *conn_state,
> > - bool respect_downstream_limits)
> > +static void
> > +intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state,
> > + bool respect_downstream_limits,
> > + struct link_config_limits *limits)
> > {
> > - struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > - struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > const struct drm_display_mode *adjusted_mode =
> > - &pipe_config->hw.adjusted_mode;
> > - struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > - struct link_config_limits limits;
> > - bool joiner_needs_dsc = false;
> > - int ret;
> > + &crtc_state->hw.adjusted_mode;
> >
> > - limits.min_rate = intel_dp_common_rate(intel_dp, 0);
> > - limits.max_rate = intel_dp_max_link_rate(intel_dp);
> > + limits->min_rate = intel_dp_common_rate(intel_dp, 0);
> > + limits->max_rate = intel_dp_max_link_rate(intel_dp);
> >
> > - limits.min_lane_count = 1;
> > - limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> > + limits->min_lane_count = 1;
> > + limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
> >
> > - limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
> > - limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config, respect_downstream_limits);
> > + limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> > + limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
> > + respect_downstream_limits);
> >
> > if (intel_dp->use_max_params) {
> > /*
> > @@ -2220,16 +2216,35 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> > * configuration, and typically on older panels these
> > * values correspond to the native resolution of the panel.
> > */
> > - limits.min_lane_count = limits.max_lane_count;
> > - limits.min_rate = limits.max_rate;
> > + limits->min_lane_count = limits->max_lane_count;
> > + limits->min_rate = limits->max_rate;
> > }
> >
> > - intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
> > + intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
>
> Annoying little bugger that mutates the crtc_state. Would be nice
> to relocate that small part somewhere else so that we could constify
> things more...
Yes, it could set dither_force_disable later separately.
> Anyways
> Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
>
> >
> > drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
> > "max rate %d max bpp %d pixel clock %iKHz\n",
> > - limits.max_lane_count, limits.max_rate,
> > - limits.max_bpp, adjusted_mode->crtc_clock);
> > + limits->max_lane_count, limits->max_rate,
> > + limits->max_bpp, adjusted_mode->crtc_clock);
> > +}
> > +
> > +static int
> > +intel_dp_compute_link_config(struct intel_encoder *encoder,
> > + struct intel_crtc_state *pipe_config,
> > + struct drm_connector_state *conn_state,
> > + bool respect_downstream_limits)
> > +{
> > + struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> > + struct intel_crtc *crtc = to_intel_crtc(pipe_config->uapi.crtc);
> > + const struct drm_display_mode *adjusted_mode =
> > + &pipe_config->hw.adjusted_mode;
> > + struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> > + struct link_config_limits limits;
> > + bool joiner_needs_dsc = false;
> > + int ret;
> > +
> > + intel_dp_compute_config_limits(intel_dp, pipe_config,
> > + respect_downstream_limits, &limits);
> >
> > if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
> > adjusted_mode->crtc_clock))
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index 3eb085fbc7c82..218c2dfd57adc 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -306,6 +306,35 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
> > return intel_conn_state->force_audio == HDMI_AUDIO_ON;
> > }
> >
> > +static void
> > +intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> > + struct intel_crtc_state *crtc_state,
> > + struct link_config_limits *limits)
> > +{
> > + /*
> > + * for MST we always configure max link bw - the spec doesn't
> > + * seem to suggest we should do otherwise.
> > + */
> > + limits->min_rate = limits->max_rate =
> > + intel_dp_max_link_rate(intel_dp);
> > +
> > + limits->min_lane_count = limits->max_lane_count =
> > + intel_dp_max_lane_count(intel_dp);
> > +
> > + limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
> > + /*
> > + * FIXME: If all the streams can't fit into the link with
> > + * their current pipe_bpp we should reduce pipe_bpp across
> > + * the board until things start to fit. Until then we
> > + * limit to <= 8bpc since that's what was hardcoded for all
> > + * MST streams previously. This hack should be removed once
> > + * we have the proper retry logic in place.
> > + */
> > + limits->max_bpp = min(crtc_state->pipe_bpp, 24);
> > +
> > + intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> > +}
> > +
> > static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> > struct intel_crtc_state *pipe_config,
> > struct drm_connector_state *conn_state)
> > @@ -329,28 +358,7 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> > intel_dp_mst_has_audio(conn_state) &&
> > intel_audio_compute_config(encoder, pipe_config, conn_state);
> >
> > - /*
> > - * for MST we always configure max link bw - the spec doesn't
> > - * seem to suggest we should do otherwise.
> > - */
> > - limits.min_rate =
> > - limits.max_rate = intel_dp_max_link_rate(intel_dp);
> > -
> > - limits.min_lane_count =
> > - limits.max_lane_count = intel_dp_max_lane_count(intel_dp);
> > -
> > - limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format);
> > - /*
> > - * FIXME: If all the streams can't fit into the link with
> > - * their current pipe_bpp we should reduce pipe_bpp across
> > - * the board until things start to fit. Until then we
> > - * limit to <= 8bpc since that's what was hardcoded for all
> > - * MST streams previously. This hack should be removed once
> > - * we have the proper retry logic in place.
> > - */
> > - limits.max_bpp = min(pipe_config->pipe_bpp, 24);
> > -
> > - intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits);
> > + intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
> >
> > ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
> > conn_state, &limits);
> > --
> > 2.37.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/dp: Factor out helpers to compute the link limits Imre Deak
@ 2023-08-24 8:04 ` Imre Deak
2023-09-14 9:33 ` Luca Coelho
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed Imre Deak
` (24 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:04 UTC (permalink / raw)
To: intel-gfx
A follow-up patch will need to limit the output link bpp both in the
non-DSC and DSC configuration, so track the pipe and link bpp limits
separately in the link_config_limits struct.
Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
in DSC mode and for now keep this limit matching the pipe bpp limit.
v2: (Jani)
- Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
- Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 10 ++++++++
drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++-
drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 ++++++++-----
4 files changed, 44 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 731f2ec04d5cd..5875eff5012ce 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2108,4 +2108,14 @@ to_intel_frontbuffer(struct drm_framebuffer *fb)
return fb ? to_intel_framebuffer(fb)->frontbuffer : NULL;
}
+static inline int to_bpp_int(int bpp_x16)
+{
+ return bpp_x16 >> 4;
+}
+
+static inline int to_bpp_x16(int bpp)
+{
+ return bpp << 4;
+}
+
#endif /* __INTEL_DISPLAY_TYPES_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 53697f361f950..cf29562795f75 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1470,7 +1470,7 @@ intel_dp_adjust_compliance_config(struct intel_dp *intel_dp,
if (intel_dp->compliance.test_data.bpc != 0) {
int bpp = 3 * intel_dp->compliance.test_data.bpc;
- limits->min_bpp = limits->max_bpp = bpp;
+ limits->pipe.min_bpp = limits->pipe.max_bpp = bpp;
pipe_config->dither_force_disable = bpp == 6 * 3;
drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp);
@@ -1532,7 +1532,9 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp,
int bpp, i, lane_count, clock = intel_dp_mode_clock(pipe_config, conn_state);
int mode_rate, link_rate, link_avail;
- for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) {
+ for (bpp = to_bpp_int(limits->link.max_bpp_x16);
+ bpp >= to_bpp_int(limits->link.min_bpp_x16);
+ bpp -= 2 * 3) {
int link_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp);
mode_rate = intel_dp_link_required(clock, link_bpp);
@@ -1958,8 +1960,8 @@ bool is_dsc_pipe_bpp_sufficient(struct drm_i915_private *i915,
dsc_max_bpc = min(intel_dp_dsc_max_src_input_bpc(i915), conn_state->max_requested_bpc);
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
- dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
- dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+ dsc_max_pipe_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
+ dsc_min_pipe_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
return pipe_bpp >= dsc_min_pipe_bpp &&
pipe_bpp <= dsc_max_pipe_bpp;
@@ -2019,10 +2021,10 @@ static int intel_dp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
return -EINVAL;
dsc_max_bpc = min_t(u8, dsc_max_bpc, max_req_bpc);
- dsc_max_bpp = min(dsc_max_bpc * 3, limits->max_bpp);
+ dsc_max_bpp = min(dsc_max_bpc * 3, limits->pipe.max_bpp);
dsc_min_bpc = intel_dp_dsc_min_src_input_bpc(i915);
- dsc_min_bpp = max(dsc_min_bpc * 3, limits->min_bpp);
+ dsc_min_bpp = max(dsc_min_bpc * 3, limits->pipe.min_bpp);
/*
* Get the maximum DSC bpc that will be supported by any valid
@@ -2203,9 +2205,9 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
limits->min_lane_count = 1;
limits->max_lane_count = intel_dp_max_lane_count(intel_dp);
- limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
- limits->max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
- respect_downstream_limits);
+ limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ limits->pipe.max_bpp = intel_dp_max_bpp(intel_dp, crtc_state,
+ respect_downstream_limits);
if (intel_dp->use_max_params) {
/*
@@ -2222,10 +2224,13 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
+ limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
+ limits->link.max_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
+
drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
"max rate %d max bpp %d pixel clock %iKHz\n",
limits->max_lane_count, limits->max_rate,
- limits->max_bpp, adjusted_mode->crtc_clock);
+ to_bpp_int(limits->link.max_bpp_x16), adjusted_mode->crtc_clock);
}
static int
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 788a577ebe16e..ebc7f4e60c777 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -26,7 +26,14 @@ struct intel_encoder;
struct link_config_limits {
int min_rate, max_rate;
int min_lane_count, max_lane_count;
- int min_bpp, max_bpp;
+ struct {
+ /* Uncompressed DSC input or link output bpp in 1 bpp units */
+ int min_bpp, max_bpp;
+ } pipe;
+ struct {
+ /* Compressed or uncompressed link output bpp in 1/16 bpp units */
+ int min_bpp_x16, max_bpp_x16;
+ } link;
};
void intel_edp_fixup_vbt_bpp(struct intel_encoder *encoder, int pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 218c2dfd57adc..6c1c996c74e62 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -157,8 +157,10 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder,
int slots = -EINVAL;
int link_bpp;
- slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp,
- limits->min_bpp, limits,
+ slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state,
+ to_bpp_int(limits->link.max_bpp_x16),
+ to_bpp_int(limits->link.min_bpp_x16),
+ limits,
conn_state, 2 * 3, false);
if (slots < 0)
@@ -203,8 +205,8 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
else
dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc);
- max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp);
- min_bpp = limits->min_bpp;
+ max_bpp = min_t(u8, dsc_max_bpc * 3, limits->pipe.max_bpp);
+ min_bpp = limits->pipe.min_bpp;
num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd,
dsc_bpc);
@@ -321,7 +323,7 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
limits->min_lane_count = limits->max_lane_count =
intel_dp_max_lane_count(intel_dp);
- limits->min_bpp = intel_dp_min_bpp(crtc_state->output_format);
+ limits->pipe.min_bpp = intel_dp_min_bpp(crtc_state->output_format);
/*
* FIXME: If all the streams can't fit into the link with
* their current pipe_bpp we should reduce pipe_bpp across
@@ -330,9 +332,12 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
* MST streams previously. This hack should be removed once
* we have the proper retry logic in place.
*/
- limits->max_bpp = min(crtc_state->pipe_bpp, 24);
+ limits->pipe.max_bpp = min(crtc_state->pipe_bpp, 24);
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
+
+ limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
+ limits->link.max_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
}
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
@ 2023-09-14 9:33 ` Luca Coelho
2023-09-14 9:55 ` Imre Deak
0 siblings, 1 reply; 60+ messages in thread
From: Luca Coelho @ 2023-09-14 9:33 UTC (permalink / raw)
To: Imre Deak, intel-gfx
On Thu, 2023-08-24 at 11:04 +0300, Imre Deak wrote:
> A follow-up patch will need to limit the output link bpp both in the
> non-DSC and DSC configuration, so track the pipe and link bpp limits
> separately in the link_config_limits struct.
>
> Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> in DSC mode and for now keep this limit matching the pipe bpp limit.
>
> v2: (Jani)
> - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
> - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 10 ++++++++
> drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
> drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++-
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 ++++++++-----
> 4 files changed, 44 insertions(+), 17 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 731f2ec04d5cd..5875eff5012ce 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
[...]
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index 788a577ebe16e..ebc7f4e60c777 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -26,7 +26,14 @@ struct intel_encoder;
> struct link_config_limits {
> int min_rate, max_rate;
> int min_lane_count, max_lane_count;
> - int min_bpp, max_bpp;
> + struct {
> + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> + int min_bpp, max_bpp;
> + } pipe;
> + struct {
> + /* Compressed or uncompressed link output bpp in 1/16 bpp units */
> + int min_bpp_x16, max_bpp_x16;
> + } link;
> };
It's not clear to me from the commit message (nor from the code, for
that matter) why you need to store the values in both formats. Can you
clarify?
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
2023-09-14 9:33 ` Luca Coelho
@ 2023-09-14 9:55 ` Imre Deak
2023-09-14 10:51 ` Luca Coelho
0 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-09-14 9:55 UTC (permalink / raw)
To: Luca Coelho; +Cc: intel-gfx
On Thu, Sep 14, 2023 at 12:33:59PM +0300, Luca Coelho wrote:
> On Thu, 2023-08-24 at 11:04 +0300, Imre Deak wrote:
> > A follow-up patch will need to limit the output link bpp both in the
> > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > separately in the link_config_limits struct.
> >
> > Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> > in DSC mode and for now keep this limit matching the pipe bpp limit.
> >
> > v2: (Jani)
> > - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
> > - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
> >
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 10 ++++++++
> > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
> > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++-
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 ++++++++-----
> > 4 files changed, 44 insertions(+), 17 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 731f2ec04d5cd..5875eff5012ce 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
>
> [...]
>
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index 788a577ebe16e..ebc7f4e60c777 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -26,7 +26,14 @@ struct intel_encoder;
> > struct link_config_limits {
> > int min_rate, max_rate;
> > int min_lane_count, max_lane_count;
> > - int min_bpp, max_bpp;
> > + struct {
> > + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> > + int min_bpp, max_bpp;
> > + } pipe;
> > + struct {
> > + /* Compressed or uncompressed link output bpp in 1/16 bpp units */
> > + int min_bpp_x16, max_bpp_x16;
> > + } link;
> > };
>
> It's not clear to me from the commit message (nor from the code, for
> that matter) why you need to store the values in both formats. Can you
> clarify?
For DSC configuration two separate limits need to be considered:
One is the bpp value which is a property of the pixel format input to
the DSC engine, for this the DSC state computation should use the
pipe.min/max_bpp limits and this functionality of the DSC HW block can
be configured in 1 bits per pixel granularity.
The other one is the bpp value which is the format of pixels output from
the DSC engine (and is the actual pixel format on the link), for which
the DSC state computation should use link.min/max_bpp_x16. The DSC HW
block can be configure this pixel format in 1/16 bits per granularity.
For instance pipe.min/max_bpp will be 16 .. 30 bpp range (in 1 bpp
units), link.min/max_bpp_x16 in the 8 .. 27 bpp range (in 1/16 bpp
units).
>
> --
> Cheers,
> Luca.
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
2023-09-14 9:55 ` Imre Deak
@ 2023-09-14 10:51 ` Luca Coelho
2023-09-14 11:08 ` Imre Deak
0 siblings, 1 reply; 60+ messages in thread
From: Luca Coelho @ 2023-09-14 10:51 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
On Thu, 2023-09-14 at 12:55 +0300, Imre Deak wrote:
> On Thu, Sep 14, 2023 at 12:33:59PM +0300, Luca Coelho wrote:
> > On Thu, 2023-08-24 at 11:04 +0300, Imre Deak wrote:
> > > A follow-up patch will need to limit the output link bpp both in the
> > > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > > separately in the link_config_limits struct.
> > >
> > > Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> > > in DSC mode and for now keep this limit matching the pipe bpp limit.
> > >
> > > v2: (Jani)
> > > - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
> > > - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
> > >
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 10 ++++++++
> > > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
> > > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++-
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 ++++++++-----
> > > 4 files changed, 44 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 731f2ec04d5cd..5875eff5012ce 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> >
> > [...]
> >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > > index 788a577ebe16e..ebc7f4e60c777 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > @@ -26,7 +26,14 @@ struct intel_encoder;
> > > struct link_config_limits {
> > > int min_rate, max_rate;
> > > int min_lane_count, max_lane_count;
> > > - int min_bpp, max_bpp;
> > > + struct {
> > > + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> > > + int min_bpp, max_bpp;
> > > + } pipe;
> > > + struct {
> > > + /* Compressed or uncompressed link output bpp in 1/16 bpp units */
> > > + int min_bpp_x16, max_bpp_x16;
> > > + } link;
> > > };
> >
> > It's not clear to me from the commit message (nor from the code, for
> > that matter) why you need to store the values in both formats. Can you
> > clarify?
>
> For DSC configuration two separate limits need to be considered:
>
> One is the bpp value which is a property of the pixel format input to
> the DSC engine, for this the DSC state computation should use the
> pipe.min/max_bpp limits and this functionality of the DSC HW block can
> be configured in 1 bits per pixel granularity.
>
> The other one is the bpp value which is the format of pixels output from
> the DSC engine (and is the actual pixel format on the link), for which
> the DSC state computation should use link.min/max_bpp_x16. The DSC HW
> block can be configure this pixel format in 1/16 bits per granularity.
>
> For instance pipe.min/max_bpp will be 16 .. 30 bpp range (in 1 bpp
> units), link.min/max_bpp_x16 in the 8 .. 27 bpp range (in 1/16 bpp
> units).
Okay, but you're storing these two limits in the link structure. So
the important difference between them is not x16 vs non-x16. If it
were, you wouldn't have to store both, because you can easily convert
them with your new to_*() functions.
So, isn't there a better name for these? Maybe input_max/min_bpp and
output_max/min_bpp? You could keep the _x16 in the relevant one, but I
think the main difference between the two should be reflected in the
symbol names.
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
2023-09-14 10:51 ` Luca Coelho
@ 2023-09-14 11:08 ` Imre Deak
2023-09-14 12:08 ` Luca Coelho
0 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-09-14 11:08 UTC (permalink / raw)
To: Luca Coelho; +Cc: intel-gfx
On Thu, Sep 14, 2023 at 01:51:16PM +0300, Luca Coelho wrote:
> On Thu, 2023-09-14 at 12:55 +0300, Imre Deak wrote:
> > On Thu, Sep 14, 2023 at 12:33:59PM +0300, Luca Coelho wrote:
> > > On Thu, 2023-08-24 at 11:04 +0300, Imre Deak wrote:
> > > > A follow-up patch will need to limit the output link bpp both in the
> > > > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > > > separately in the link_config_limits struct.
> > > >
> > > > Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> > > > in DSC mode and for now keep this limit matching the pipe bpp limit.
> > > >
> > > > v2: (Jani)
> > > > - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
> > > > - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
> > > >
> > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > .../drm/i915/display/intel_display_types.h | 10 ++++++++
> > > > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
> > > > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++-
> > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 ++++++++-----
> > > > 4 files changed, 44 insertions(+), 17 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > index 731f2ec04d5cd..5875eff5012ce 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > >
> > > [...]
> > >
> > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > index 788a577ebe16e..ebc7f4e60c777 100644
> > > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > @@ -26,7 +26,14 @@ struct intel_encoder;
> > > > struct link_config_limits {
> > > > int min_rate, max_rate;
> > > > int min_lane_count, max_lane_count;
> > > > - int min_bpp, max_bpp;
> > > > + struct {
> > > > + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> > > > + int min_bpp, max_bpp;
> > > > + } pipe;
> > > > + struct {
> > > > + /* Compressed or uncompressed link output bpp in 1/16 bpp units */
> > > > + int min_bpp_x16, max_bpp_x16;
> > > > + } link;
> > > > };
> > >
> > > It's not clear to me from the commit message (nor from the code, for
> > > that matter) why you need to store the values in both formats. Can you
> > > clarify?
> >
> > For DSC configuration two separate limits need to be considered:
> >
> > One is the bpp value which is a property of the pixel format input to
> > the DSC engine, for this the DSC state computation should use the
> > pipe.min/max_bpp limits and this functionality of the DSC HW block can
> > be configured in 1 bits per pixel granularity.
> >
> > The other one is the bpp value which is the format of pixels output from
> > the DSC engine (and is the actual pixel format on the link), for which
> > the DSC state computation should use link.min/max_bpp_x16. The DSC HW
> > block can be configure this pixel format in 1/16 bits per granularity.
> >
> > For instance pipe.min/max_bpp will be 16 .. 30 bpp range (in 1 bpp
> > units), link.min/max_bpp_x16 in the 8 .. 27 bpp range (in 1/16 bpp
> > units).
>
> Okay, but you're storing these two limits in the link structure. So
> the important difference between them is not x16 vs non-x16. If it
> were, you wouldn't have to store both, because you can easily convert
> them with your new to_*() functions.
>
> So, isn't there a better name for these? Maybe input_max/min_bpp and
> output_max/min_bpp? You could keep the _x16 in the relevant one, but I
> think the main difference between the two should be reflected in the
> symbol names.
They are part of a pipe/link sub-structure, so the names are in effect
pipe.min/max_bpp and link.min/max_bpp_x16. pipe and link in turn are the
terms used for these same types of bpps elsewhere in DSC and non-DSC
code, hence I used them here as well for clarity. Maybe the comments
in the struct could be improved how the limits are used?
> --
> Cheers,
> Luca.
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately
2023-09-14 11:08 ` Imre Deak
@ 2023-09-14 12:08 ` Luca Coelho
0 siblings, 0 replies; 60+ messages in thread
From: Luca Coelho @ 2023-09-14 12:08 UTC (permalink / raw)
To: imre.deak; +Cc: intel-gfx
On Thu, 2023-09-14 at 14:08 +0300, Imre Deak wrote:
> On Thu, Sep 14, 2023 at 01:51:16PM +0300, Luca Coelho wrote:
> > On Thu, 2023-09-14 at 12:55 +0300, Imre Deak wrote:
> > > On Thu, Sep 14, 2023 at 12:33:59PM +0300, Luca Coelho wrote:
> > > > On Thu, 2023-08-24 at 11:04 +0300, Imre Deak wrote:
> > > > > A follow-up patch will need to limit the output link bpp both in the
> > > > > non-DSC and DSC configuration, so track the pipe and link bpp limits
> > > > > separately in the link_config_limits struct.
> > > > >
> > > > > Use .4 fixed point format for link bpp matching the 1/16 bpp granularity
> > > > > in DSC mode and for now keep this limit matching the pipe bpp limit.
> > > > >
> > > > > v2: (Jani)
> > > > > - Add to_bpp_int(), to_bpp_x16() helpers instead of opencoding them.
> > > > > - Rename link_config_limits::link.min/max_bpp to min/max_bpp_x16.
> > > > >
> > > > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > > ---
> > > > > .../drm/i915/display/intel_display_types.h | 10 ++++++++
> > > > > drivers/gpu/drm/i915/display/intel_dp.c | 25 +++++++++++--------
> > > > > drivers/gpu/drm/i915/display/intel_dp.h | 9 ++++++-
> > > > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 17 ++++++++-----
> > > > > 4 files changed, 44 insertions(+), 17 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > index 731f2ec04d5cd..5875eff5012ce 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > >
> > > > [...]
> > > >
> > > > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > index 788a577ebe16e..ebc7f4e60c777 100644
> > > > > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > > > > @@ -26,7 +26,14 @@ struct intel_encoder;
> > > > > struct link_config_limits {
> > > > > int min_rate, max_rate;
> > > > > int min_lane_count, max_lane_count;
> > > > > - int min_bpp, max_bpp;
> > > > > + struct {
> > > > > + /* Uncompressed DSC input or link output bpp in 1 bpp units */
> > > > > + int min_bpp, max_bpp;
> > > > > + } pipe;
> > > > > + struct {
> > > > > + /* Compressed or uncompressed link output bpp in 1/16 bpp units */
> > > > > + int min_bpp_x16, max_bpp_x16;
> > > > > + } link;
> > > > > };
> > > >
> > > > It's not clear to me from the commit message (nor from the code, for
> > > > that matter) why you need to store the values in both formats. Can you
> > > > clarify?
> > >
> > > For DSC configuration two separate limits need to be considered:
> > >
> > > One is the bpp value which is a property of the pixel format input to
> > > the DSC engine, for this the DSC state computation should use the
> > > pipe.min/max_bpp limits and this functionality of the DSC HW block can
> > > be configured in 1 bits per pixel granularity.
> > >
> > > The other one is the bpp value which is the format of pixels output from
> > > the DSC engine (and is the actual pixel format on the link), for which
> > > the DSC state computation should use link.min/max_bpp_x16. The DSC HW
> > > block can be configure this pixel format in 1/16 bits per granularity.
> > >
> > > For instance pipe.min/max_bpp will be 16 .. 30 bpp range (in 1 bpp
> > > units), link.min/max_bpp_x16 in the 8 .. 27 bpp range (in 1/16 bpp
> > > units).
> >
> > Okay, but you're storing these two limits in the link structure. So
> > the important difference between them is not x16 vs non-x16. If it
> > were, you wouldn't have to store both, because you can easily convert
> > them with your new to_*() functions.
> >
> > So, isn't there a better name for these? Maybe input_max/min_bpp and
> > output_max/min_bpp? You could keep the _x16 in the relevant one, but I
> > think the main difference between the two should be reflected in the
> > symbol names.
>
> They are part of a pipe/link sub-structure, so the names are in effect
> pipe.min/max_bpp and link.min/max_bpp_x16. pipe and link in turn are the
> terms used for these same types of bpps elsewhere in DSC and non-DSC
> code, hence I used them here as well for clarity. Maybe the comments
> in the struct could be improved how the limits are used?
Oh, of course. Sorry, I missed that.
Reviewed-by: Luca Coelho <luciano.coelho@intel.com>
--
Cheers,
Luca.
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 03/22] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 01/22] drm/i915/dp: Factor out helpers to compute the link limits Imre Deak
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
@ 2023-08-24 8:04 ` Imre Deak
2023-09-04 3:24 ` Ville Syrjälä
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode Imre Deak
` (23 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:04 UTC (permalink / raw)
To: intel-gfx
Computing the non-DSC mode link config is redundant once it's determined
that DSC will be needed, so skip computing it. In a follow-up patch this
simplifies setting the link limits which are dependent on the DSC vs.
non-DSC mode.
While at it sanitize the debug print about the MST DSC fallback path,
making it similar to the SST DSC one.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++------
drivers/gpu/drm/i915/display/intel_dp_mst.c | 25 +++++++++++++++------
2 files changed, 33 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index cf29562795f75..c580472c06b85 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2246,7 +2246,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
struct link_config_limits limits;
bool joiner_needs_dsc = false;
- int ret;
+ bool dsc_needed;
+ int ret = 0;
intel_dp_compute_config_limits(intel_dp, pipe_config,
respect_downstream_limits, &limits);
@@ -2262,13 +2263,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
*/
joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
- /*
- * Optimize for slow and wide for everything, because there are some
- * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
- */
- ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
+ dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en;
+
+ if (!dsc_needed) {
+ /*
+ * Optimize for slow and wide for everything, because there are some
+ * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
+ */
+ ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
+ conn_state, &limits);
+ if (ret)
+ dsc_needed = true;
+ }
- if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
+ if (dsc_needed) {
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
str_yes_no(intel_dp->force_dsc_en));
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 6c1c996c74e62..c077b999ccb74 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -350,7 +350,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
const struct drm_display_mode *adjusted_mode =
&pipe_config->hw.adjusted_mode;
struct link_config_limits limits;
- int ret;
+ bool dsc_needed;
+ int ret = 0;
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
@@ -365,15 +366,25 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
- ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
- conn_state, &limits);
+ dsc_needed = intel_dp->force_dsc_en;
- if (ret == -EDEADLK)
- return ret;
+ if (!dsc_needed) {
+ ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
+ conn_state, &limits);
+
+ if (ret == -EDEADLK)
+ return ret;
+
+ if (ret)
+ dsc_needed = true;
+ }
/* enable compression if the mode doesn't fit available BW */
- drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
- if (ret || intel_dp->force_dsc_en) {
+ if (dsc_needed) {
+ drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, force=%s)\n",
+ str_yes_no(ret),
+ str_yes_no(intel_dp->force_dsc_en));
+
/*
* FIXME: As bpc is hardcoded to 8, as mentioned above,
* WARN and ignore the debug flag force_dsc_bpc for now.
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 03/22] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed Imre Deak
@ 2023-09-04 3:24 ` Ville Syrjälä
0 siblings, 0 replies; 60+ messages in thread
From: Ville Syrjälä @ 2023-09-04 3:24 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:04:58AM +0300, Imre Deak wrote:
> Computing the non-DSC mode link config is redundant once it's determined
> that DSC will be needed, so skip computing it. In a follow-up patch this
> simplifies setting the link limits which are dependent on the DSC vs.
> non-DSC mode.
>
> While at it sanitize the debug print about the MST DSC fallback path,
> making it similar to the SST DSC one.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 22 ++++++++++++------
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 25 +++++++++++++++------
> 2 files changed, 33 insertions(+), 14 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index cf29562795f75..c580472c06b85 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2246,7 +2246,8 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
> struct link_config_limits limits;
> bool joiner_needs_dsc = false;
> - int ret;
> + bool dsc_needed;
> + int ret = 0;
>
> intel_dp_compute_config_limits(intel_dp, pipe_config,
> respect_downstream_limits, &limits);
> @@ -2262,13 +2263,20 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> */
> joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
>
> - /*
> - * Optimize for slow and wide for everything, because there are some
> - * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
> - */
> - ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, conn_state, &limits);
> + dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en;
> +
> + if (!dsc_needed) {
> + /*
> + * Optimize for slow and wide for everything, because there are some
> + * eDP 1.3 and 1.4 panels don't work well with fast and narrow.
> + */
> + ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config,
> + conn_state, &limits);
> + if (ret)
> + dsc_needed = true;
> + }
>
> - if (ret || joiner_needs_dsc || intel_dp->force_dsc_en) {
> + if (dsc_needed) {
> drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
> str_yes_no(ret), str_yes_no(joiner_needs_dsc),
> str_yes_no(intel_dp->force_dsc_en));
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 6c1c996c74e62..c077b999ccb74 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -350,7 +350,8 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> const struct drm_display_mode *adjusted_mode =
> &pipe_config->hw.adjusted_mode;
> struct link_config_limits limits;
> - int ret;
> + bool dsc_needed;
> + int ret = 0;
>
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
> @@ -365,15 +366,25 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
>
> intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
>
> - ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
> - conn_state, &limits);
> + dsc_needed = intel_dp->force_dsc_en;
>
> - if (ret == -EDEADLK)
> - return ret;
> + if (!dsc_needed) {
> + ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
> + conn_state, &limits);
> +
> + if (ret == -EDEADLK)
> + return ret;
> +
> + if (ret)
> + dsc_needed = true;
> + }
>
> /* enable compression if the mode doesn't fit available BW */
> - drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en);
> - if (ret || intel_dp->force_dsc_en) {
> + if (dsc_needed) {
> + drm_dbg_kms(&dev_priv->drm, "Try DSC (fallback=%s, force=%s)\n",
> + str_yes_no(ret),
> + str_yes_no(intel_dp->force_dsc_en));
> +
> /*
> * FIXME: As bpc is hardcoded to 8, as mentioned above,
> * WARN and ignore the debug flag force_dsc_bpc for now.
> --
> 2.37.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (2 preceding siblings ...)
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 03/22] drm/i915/dp: Skip computing a non-DSC link config if DSC is needed Imre Deak
@ 2023-08-24 8:04 ` Imre Deak
2023-09-04 3:48 ` Ville Syrjälä
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/dp: Limit the output link bpp in " Imre Deak
` (22 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:04 UTC (permalink / raw)
To: intel-gfx
In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
range, while in DSC mode it can be set in 1/16 bpp steps to any value
up to the maximum pipe bpp. Update the limits accordingly in both modes
to prepare for a follow-up patch which may need to reduce the max link
bpp value and starts to check the link bpp limits in DSC mode as well.
While at it add more detail to the link limit debug print and print it
also for DSC mode.
v2:
- Add to_bpp_frac_dec() instead of open coding it. (Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_types.h | 5 ++
drivers/gpu/drm/i915/display/intel_dp.c | 89 +++++++++++++++----
drivers/gpu/drm/i915/display/intel_dp.h | 6 ++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++--
4 files changed, 101 insertions(+), 22 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 5875eff5012ce..a0a404967b5d2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2113,6 +2113,11 @@ static inline int to_bpp_int(int bpp_x16)
return bpp_x16 >> 4;
}
+static inline int to_bpp_frac_dec(int bpp_x16)
+{
+ return (bpp_x16 & 0xf) * 625;
+}
+
static inline int to_bpp_x16(int bpp)
{
return bpp << 4;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index c580472c06b85..9ce861a7fd418 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2189,16 +2189,68 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
return 0;
}
-static void
+/**
+ * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
+ * @intel_dp: intel DP
+ * @crtc_state: crtc state
+ * @dsc: DSC compression mode
+ * @limits: link configuration limits
+ *
+ * Calculates the output link min, max bpp values in @limits based on the
+ * pipe bpp range, @crtc_state and @dsc mode.
+ *
+ * Returns %true in case of success.
+ */
+bool
+intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ bool dsc,
+ struct link_config_limits *limits)
+{
+ struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
+ const struct drm_display_mode *adjusted_mode =
+ &crtc_state->hw.adjusted_mode;
+ const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
+ const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
+ int max_link_bpp_x16;
+
+ max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
+
+ if (!dsc) {
+ max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
+
+ if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
+ return false;
+
+ limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
+ } else {
+ limits->link.min_bpp_x16 = 0;
+ }
+
+ limits->link.max_bpp_x16 = max_link_bpp_x16;
+
+ drm_dbg_kms(&i915->drm,
+ "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp %d.%04d\n",
+ encoder->base.base.id, encoder->base.name,
+ crtc->base.base.id, crtc->base.name,
+ adjusted_mode->crtc_clock,
+ dsc ? "on" : "off",
+ limits->max_lane_count,
+ limits->max_rate,
+ limits->pipe.max_bpp,
+ to_bpp_int(limits->link.max_bpp_x16),
+ to_bpp_frac_dec(limits->link.max_bpp_x16));
+
+ return true;
+}
+
+static bool
intel_dp_compute_config_limits(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
bool respect_downstream_limits,
+ bool dsc,
struct link_config_limits *limits)
{
- struct drm_i915_private *i915 = dp_to_i915(intel_dp);
- const struct drm_display_mode *adjusted_mode =
- &crtc_state->hw.adjusted_mode;
-
limits->min_rate = intel_dp_common_rate(intel_dp, 0);
limits->max_rate = intel_dp_max_link_rate(intel_dp);
@@ -2224,13 +2276,10 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
- limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
- limits->link.max_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
-
- drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
- "max rate %d max bpp %d pixel clock %iKHz\n",
- limits->max_lane_count, limits->max_rate,
- to_bpp_int(limits->link.max_bpp_x16), adjusted_mode->crtc_clock);
+ return intel_dp_compute_config_link_bpp_limits(intel_dp,
+ crtc_state,
+ dsc,
+ limits);
}
static int
@@ -2249,9 +2298,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
- intel_dp_compute_config_limits(intel_dp, pipe_config,
- respect_downstream_limits, &limits);
-
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
@@ -2263,7 +2309,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
*/
joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
- dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en;
+ dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
+ !intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits,
+ false,
+ &limits);
if (!dsc_needed) {
/*
@@ -2280,6 +2330,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
str_yes_no(ret), str_yes_no(joiner_needs_dsc),
str_yes_no(intel_dp->force_dsc_en));
+
+ if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
+ respect_downstream_limits,
+ true,
+ &limits))
+ return -EINVAL;
+
ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
conn_state, &limits, 64, true);
if (ret < 0)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index ebc7f4e60c777..0b8a4bbef8f7d 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -153,4 +153,10 @@ void intel_dp_phy_test(struct intel_encoder *encoder);
void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
+bool
+intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *crtc_state,
+ bool dsc,
+ struct link_config_limits *limits);
+
#endif /* __INTEL_DP_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index c077b999ccb74..2b78a3a8966f3 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -308,9 +308,10 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
return intel_conn_state->force_audio == HDMI_AUDIO_ON;
}
-static void
+static bool
intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
struct intel_crtc_state *crtc_state,
+ bool dsc,
struct link_config_limits *limits)
{
/*
@@ -336,8 +337,10 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
- limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
- limits->link.max_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
+ return intel_dp_compute_config_link_bpp_limits(intel_dp,
+ crtc_state,
+ dsc,
+ limits);
}
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
@@ -364,9 +367,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
intel_dp_mst_has_audio(conn_state) &&
intel_audio_compute_config(encoder, pipe_config, conn_state);
- intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
-
- dsc_needed = intel_dp->force_dsc_en;
+ dsc_needed = intel_dp->force_dsc_en ||
+ !intel_dp_mst_compute_config_limits(intel_dp,
+ pipe_config,
+ false,
+ &limits);
if (!dsc_needed) {
ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
@@ -385,6 +390,12 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
str_yes_no(ret),
str_yes_no(intel_dp->force_dsc_en));
+ if (!intel_dp_mst_compute_config_limits(intel_dp,
+ pipe_config,
+ true,
+ &limits))
+ return -EINVAL;
+
/*
* FIXME: As bpc is hardcoded to 8, as mentioned above,
* WARN and ignore the debug flag force_dsc_bpc for now.
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode Imre Deak
@ 2023-09-04 3:48 ` Ville Syrjälä
2023-09-04 11:08 ` Imre Deak
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2023-09-04 3:48 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:04:59AM +0300, Imre Deak wrote:
> In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
> range, while in DSC mode it can be set in 1/16 bpp steps to any value
> up to the maximum pipe bpp. Update the limits accordingly in both modes
> to prepare for a follow-up patch which may need to reduce the max link
> bpp value and starts to check the link bpp limits in DSC mode as well.
>
> While at it add more detail to the link limit debug print and print it
> also for DSC mode.
>
> v2:
> - Add to_bpp_frac_dec() instead of open coding it. (Jani)
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_types.h | 5 ++
> drivers/gpu/drm/i915/display/intel_dp.c | 89 +++++++++++++++----
> drivers/gpu/drm/i915/display/intel_dp.h | 6 ++
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++--
> 4 files changed, 101 insertions(+), 22 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index 5875eff5012ce..a0a404967b5d2 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -2113,6 +2113,11 @@ static inline int to_bpp_int(int bpp_x16)
> return bpp_x16 >> 4;
> }
>
> +static inline int to_bpp_frac_dec(int bpp_x16)
> +{
> + return (bpp_x16 & 0xf) * 625;
> +}
This gives me the impression that this would be somehow
generally useful, but I presume we only use it for the printk?
So maybe should just have some printk FMT+ARG macros for
this stuff?
> +
> static inline int to_bpp_x16(int bpp)
> {
> return bpp << 4;
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index c580472c06b85..9ce861a7fd418 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2189,16 +2189,68 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> return 0;
> }
>
> -static void
> +/**
> + * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
> + * @intel_dp: intel DP
> + * @crtc_state: crtc state
> + * @dsc: DSC compression mode
> + * @limits: link configuration limits
> + *
> + * Calculates the output link min, max bpp values in @limits based on the
> + * pipe bpp range, @crtc_state and @dsc mode.
> + *
> + * Returns %true in case of success.
> + */
> +bool
> +intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + bool dsc,
> + struct link_config_limits *limits)
> +{
> + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> + const struct drm_display_mode *adjusted_mode =
> + &crtc_state->hw.adjusted_mode;
> + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> + const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> + int max_link_bpp_x16;
> +
> + max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> +
> + if (!dsc) {
> + max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
> +
> + if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
> + return false;
Quite a few to_bpp_x16()'s in there. Seems like it would a bit simpler
to just do that once at the end.
> +
> + limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
> + } else {
> + limits->link.min_bpp_x16 = 0;
Why is that zero? Don't we now have some helpers to fill
this stuff correctly?
> + }
> +
> + limits->link.max_bpp_x16 = max_link_bpp_x16;
> +
> + drm_dbg_kms(&i915->drm,
> + "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp %d.%04d\n",
> + encoder->base.base.id, encoder->base.name,
> + crtc->base.base.id, crtc->base.name,
> + adjusted_mode->crtc_clock,
> + dsc ? "on" : "off",
> + limits->max_lane_count,
> + limits->max_rate,
> + limits->pipe.max_bpp,
> + to_bpp_int(limits->link.max_bpp_x16),
> + to_bpp_frac_dec(limits->link.max_bpp_x16));
> +
> + return true;
> +}
> +
> +static bool
> intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> bool respect_downstream_limits,
> + bool dsc,
> struct link_config_limits *limits)
> {
> - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> - const struct drm_display_mode *adjusted_mode =
> - &crtc_state->hw.adjusted_mode;
> -
> limits->min_rate = intel_dp_common_rate(intel_dp, 0);
> limits->max_rate = intel_dp_max_link_rate(intel_dp);
>
> @@ -2224,13 +2276,10 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
>
> intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
>
> - limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
> - limits->link.max_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> -
> - drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
> - "max rate %d max bpp %d pixel clock %iKHz\n",
> - limits->max_lane_count, limits->max_rate,
> - to_bpp_int(limits->link.max_bpp_x16), adjusted_mode->crtc_clock);
> + return intel_dp_compute_config_link_bpp_limits(intel_dp,
> + crtc_state,
> + dsc,
> + limits);
> }
>
> static int
> @@ -2249,9 +2298,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> bool dsc_needed;
> int ret = 0;
>
> - intel_dp_compute_config_limits(intel_dp, pipe_config,
> - respect_downstream_limits, &limits);
> -
> if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
> adjusted_mode->crtc_clock))
> pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
> @@ -2263,7 +2309,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> */
> joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
>
> - dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en;
> + dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
> + !intel_dp_compute_config_limits(intel_dp, pipe_config,
> + respect_downstream_limits,
> + false,
> + &limits);
>
> if (!dsc_needed) {
> /*
> @@ -2280,6 +2330,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
> str_yes_no(ret), str_yes_no(joiner_needs_dsc),
> str_yes_no(intel_dp->force_dsc_en));
> +
> + if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
> + respect_downstream_limits,
> + true,
> + &limits))
> + return -EINVAL;
> +
> ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
> conn_state, &limits, 64, true);
> if (ret < 0)
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> index ebc7f4e60c777..0b8a4bbef8f7d 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.h
> +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> @@ -153,4 +153,10 @@ void intel_dp_phy_test(struct intel_encoder *encoder);
> void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
> int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
>
> +bool
> +intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> + const struct intel_crtc_state *crtc_state,
> + bool dsc,
> + struct link_config_limits *limits);
> +
> #endif /* __INTEL_DP_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index c077b999ccb74..2b78a3a8966f3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -308,9 +308,10 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
> return intel_conn_state->force_audio == HDMI_AUDIO_ON;
> }
>
> -static void
> +static bool
> intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> struct intel_crtc_state *crtc_state,
> + bool dsc,
> struct link_config_limits *limits)
> {
> /*
> @@ -336,8 +337,10 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
>
> intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
>
> - limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
> - limits->link.max_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> + return intel_dp_compute_config_link_bpp_limits(intel_dp,
> + crtc_state,
> + dsc,
> + limits);
> }
>
> static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> @@ -364,9 +367,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> intel_dp_mst_has_audio(conn_state) &&
> intel_audio_compute_config(encoder, pipe_config, conn_state);
>
> - intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
> -
> - dsc_needed = intel_dp->force_dsc_en;
> + dsc_needed = intel_dp->force_dsc_en ||
> + !intel_dp_mst_compute_config_limits(intel_dp,
> + pipe_config,
> + false,
> + &limits);
>
> if (!dsc_needed) {
> ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
> @@ -385,6 +390,12 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> str_yes_no(ret),
> str_yes_no(intel_dp->force_dsc_en));
>
> + if (!intel_dp_mst_compute_config_limits(intel_dp,
> + pipe_config,
> + true,
> + &limits))
> + return -EINVAL;
> +
> /*
> * FIXME: As bpc is hardcoded to 8, as mentioned above,
> * WARN and ignore the debug flag force_dsc_bpc for now.
> --
> 2.37.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode
2023-09-04 3:48 ` Ville Syrjälä
@ 2023-09-04 11:08 ` Imre Deak
2023-09-05 5:25 ` Ville Syrjälä
0 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-09-04 11:08 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Sep 04, 2023 at 06:48:25AM +0300, Ville Syrjälä wrote:
> On Thu, Aug 24, 2023 at 11:04:59AM +0300, Imre Deak wrote:
> > In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
> > range, while in DSC mode it can be set in 1/16 bpp steps to any value
> > up to the maximum pipe bpp. Update the limits accordingly in both modes
> > to prepare for a follow-up patch which may need to reduce the max link
> > bpp value and starts to check the link bpp limits in DSC mode as well.
> >
> > While at it add more detail to the link limit debug print and print it
> > also for DSC mode.
> >
> > v2:
> > - Add to_bpp_frac_dec() instead of open coding it. (Jani)
> >
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > .../drm/i915/display/intel_display_types.h | 5 ++
> > drivers/gpu/drm/i915/display/intel_dp.c | 89 +++++++++++++++----
> > drivers/gpu/drm/i915/display/intel_dp.h | 6 ++
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++--
> > 4 files changed, 101 insertions(+), 22 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index 5875eff5012ce..a0a404967b5d2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -2113,6 +2113,11 @@ static inline int to_bpp_int(int bpp_x16)
> > return bpp_x16 >> 4;
> > }
> >
> > +static inline int to_bpp_frac_dec(int bpp_x16)
> > +{
> > + return (bpp_x16 & 0xf) * 625;
> > +}
>
> This gives me the impression that this would be somehow
> generally useful, but I presume we only use it for the printk?
> So maybe should just have some printk FMT+ARG macros for
> this stuff?
Yes, only used by printks. Make sense to define the FMT+ARG helpers at
one place, can add these here.
>
> > +
> > static inline int to_bpp_x16(int bpp)
> > {
> > return bpp << 4;
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index c580472c06b85..9ce861a7fd418 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2189,16 +2189,68 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > return 0;
> > }
> >
> > -static void
> > +/**
> > + * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
> > + * @intel_dp: intel DP
> > + * @crtc_state: crtc state
> > + * @dsc: DSC compression mode
> > + * @limits: link configuration limits
> > + *
> > + * Calculates the output link min, max bpp values in @limits based on the
> > + * pipe bpp range, @crtc_state and @dsc mode.
> > + *
> > + * Returns %true in case of success.
> > + */
> > +bool
> > +intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state,
> > + bool dsc,
> > + struct link_config_limits *limits)
> > +{
> > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> > + const struct drm_display_mode *adjusted_mode =
> > + &crtc_state->hw.adjusted_mode;
> > + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > + const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > + int max_link_bpp_x16;
> > +
> > + max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> > +
> > + if (!dsc) {
> > + max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
> > +
> > + if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
> > + return false;
>
> Quite a few to_bpp_x16()'s in there. Seems like it would a bit simpler
> to just do that once at the end.
At the moment yes, but in a later patch max_link_bpp_x16 starts out as
crtc_state->max_link_bpp_x16 limited value (with a non-zero fractional
part).
>
> > +
> > + limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
> > + } else {
> > + limits->link.min_bpp_x16 = 0;
>
> Why is that zero? Don't we now have some helpers to fill
> this stuff correctly?
At the moment it's calculated only later in
intel_edp_dsc_compute_pipe_bpp() / intel_dp_dsc_compute_pipe_bpp().
It should be inited already here, but I wanted to do that only as a
follow-up, since there's been other DSC changes from Ankit still under
review. Is that ok, adding a TODO: here?
>
> > + }
> > +
> > + limits->link.max_bpp_x16 = max_link_bpp_x16;
> > +
> > + drm_dbg_kms(&i915->drm,
> > + "[ENCODER:%d:%s][CRTC:%d:%s] DP link limits: pixel clock %d kHz DSC %s max lanes %d max rate %d max pipe_bpp %d max link_bpp %d.%04d\n",
> > + encoder->base.base.id, encoder->base.name,
> > + crtc->base.base.id, crtc->base.name,
> > + adjusted_mode->crtc_clock,
> > + dsc ? "on" : "off",
> > + limits->max_lane_count,
> > + limits->max_rate,
> > + limits->pipe.max_bpp,
> > + to_bpp_int(limits->link.max_bpp_x16),
> > + to_bpp_frac_dec(limits->link.max_bpp_x16));
> > +
> > + return true;
> > +}
> > +
> > +static bool
> > intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > bool respect_downstream_limits,
> > + bool dsc,
> > struct link_config_limits *limits)
> > {
> > - struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> > - const struct drm_display_mode *adjusted_mode =
> > - &crtc_state->hw.adjusted_mode;
> > -
> > limits->min_rate = intel_dp_common_rate(intel_dp, 0);
> > limits->max_rate = intel_dp_max_link_rate(intel_dp);
> >
> > @@ -2224,13 +2276,10 @@ intel_dp_compute_config_limits(struct intel_dp *intel_dp,
> >
> > intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> >
> > - limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
> > - limits->link.max_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> > -
> > - drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i "
> > - "max rate %d max bpp %d pixel clock %iKHz\n",
> > - limits->max_lane_count, limits->max_rate,
> > - to_bpp_int(limits->link.max_bpp_x16), adjusted_mode->crtc_clock);
> > + return intel_dp_compute_config_link_bpp_limits(intel_dp,
> > + crtc_state,
> > + dsc,
> > + limits);
> > }
> >
> > static int
> > @@ -2249,9 +2298,6 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> > bool dsc_needed;
> > int ret = 0;
> >
> > - intel_dp_compute_config_limits(intel_dp, pipe_config,
> > - respect_downstream_limits, &limits);
> > -
> > if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
> > adjusted_mode->crtc_clock))
> > pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
> > @@ -2263,7 +2309,11 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> > */
> > joiner_needs_dsc = DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes;
> >
> > - dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en;
> > + dsc_needed = joiner_needs_dsc || intel_dp->force_dsc_en ||
> > + !intel_dp_compute_config_limits(intel_dp, pipe_config,
> > + respect_downstream_limits,
> > + false,
> > + &limits);
> >
> > if (!dsc_needed) {
> > /*
> > @@ -2280,6 +2330,13 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
> > drm_dbg_kms(&i915->drm, "Try DSC (fallback=%s, joiner=%s, force=%s)\n",
> > str_yes_no(ret), str_yes_no(joiner_needs_dsc),
> > str_yes_no(intel_dp->force_dsc_en));
> > +
> > + if (!intel_dp_compute_config_limits(intel_dp, pipe_config,
> > + respect_downstream_limits,
> > + true,
> > + &limits))
> > + return -EINVAL;
> > +
> > ret = intel_dp_dsc_compute_config(intel_dp, pipe_config,
> > conn_state, &limits, 64, true);
> > if (ret < 0)
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
> > index ebc7f4e60c777..0b8a4bbef8f7d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.h
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.h
> > @@ -153,4 +153,10 @@ void intel_dp_phy_test(struct intel_encoder *encoder);
> > void intel_dp_wait_source_oui(struct intel_dp *intel_dp);
> > int intel_dp_output_bpp(enum intel_output_format output_format, int bpp);
> >
> > +bool
> > +intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> > + const struct intel_crtc_state *crtc_state,
> > + bool dsc,
> > + struct link_config_limits *limits);
> > +
> > #endif /* __INTEL_DP_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index c077b999ccb74..2b78a3a8966f3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -308,9 +308,10 @@ static bool intel_dp_mst_has_audio(const struct drm_connector_state *conn_state)
> > return intel_conn_state->force_audio == HDMI_AUDIO_ON;
> > }
> >
> > -static void
> > +static bool
> > intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> > struct intel_crtc_state *crtc_state,
> > + bool dsc,
> > struct link_config_limits *limits)
> > {
> > /*
> > @@ -336,8 +337,10 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
> >
> > intel_dp_adjust_compliance_config(intel_dp, crtc_state, limits);
> >
> > - limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
> > - limits->link.max_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> > + return intel_dp_compute_config_link_bpp_limits(intel_dp,
> > + crtc_state,
> > + dsc,
> > + limits);
> > }
> >
> > static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> > @@ -364,9 +367,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> > intel_dp_mst_has_audio(conn_state) &&
> > intel_audio_compute_config(encoder, pipe_config, conn_state);
> >
> > - intel_dp_mst_compute_config_limits(intel_dp, pipe_config, &limits);
> > -
> > - dsc_needed = intel_dp->force_dsc_en;
> > + dsc_needed = intel_dp->force_dsc_en ||
> > + !intel_dp_mst_compute_config_limits(intel_dp,
> > + pipe_config,
> > + false,
> > + &limits);
> >
> > if (!dsc_needed) {
> > ret = intel_dp_mst_compute_link_config(encoder, pipe_config,
> > @@ -385,6 +390,12 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
> > str_yes_no(ret),
> > str_yes_no(intel_dp->force_dsc_en));
> >
> > + if (!intel_dp_mst_compute_config_limits(intel_dp,
> > + pipe_config,
> > + true,
> > + &limits))
> > + return -EINVAL;
> > +
> > /*
> > * FIXME: As bpc is hardcoded to 8, as mentioned above,
> > * WARN and ignore the debug flag force_dsc_bpc for now.
> > --
> > 2.37.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode
2023-09-04 11:08 ` Imre Deak
@ 2023-09-05 5:25 ` Ville Syrjälä
0 siblings, 0 replies; 60+ messages in thread
From: Ville Syrjälä @ 2023-09-05 5:25 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Mon, Sep 04, 2023 at 02:08:38PM +0300, Imre Deak wrote:
> On Mon, Sep 04, 2023 at 06:48:25AM +0300, Ville Syrjälä wrote:
> > On Thu, Aug 24, 2023 at 11:04:59AM +0300, Imre Deak wrote:
> > > In non-DSC mode the link bpp can be set in 2*3 bpp steps in the pipe bpp
> > > range, while in DSC mode it can be set in 1/16 bpp steps to any value
> > > up to the maximum pipe bpp. Update the limits accordingly in both modes
> > > to prepare for a follow-up patch which may need to reduce the max link
> > > bpp value and starts to check the link bpp limits in DSC mode as well.
> > >
> > > While at it add more detail to the link limit debug print and print it
> > > also for DSC mode.
> > >
> > > v2:
> > > - Add to_bpp_frac_dec() instead of open coding it. (Jani)
> > >
> > > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > .../drm/i915/display/intel_display_types.h | 5 ++
> > > drivers/gpu/drm/i915/display/intel_dp.c | 89 +++++++++++++++----
> > > drivers/gpu/drm/i915/display/intel_dp.h | 6 ++
> > > drivers/gpu/drm/i915/display/intel_dp_mst.c | 23 +++--
> > > 4 files changed, 101 insertions(+), 22 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > index 5875eff5012ce..a0a404967b5d2 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > > @@ -2113,6 +2113,11 @@ static inline int to_bpp_int(int bpp_x16)
> > > return bpp_x16 >> 4;
> > > }
> > >
> > > +static inline int to_bpp_frac_dec(int bpp_x16)
> > > +{
> > > + return (bpp_x16 & 0xf) * 625;
> > > +}
> >
> > This gives me the impression that this would be somehow
> > generally useful, but I presume we only use it for the printk?
> > So maybe should just have some printk FMT+ARG macros for
> > this stuff?
>
> Yes, only used by printks. Make sense to define the FMT+ARG helpers at
> one place, can add these here.
>
> >
> > > +
> > > static inline int to_bpp_x16(int bpp)
> > > {
> > > return bpp << 4;
> > > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > > index c580472c06b85..9ce861a7fd418 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > > @@ -2189,16 +2189,68 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
> > > return 0;
> > > }
> > >
> > > -static void
> > > +/**
> > > + * intel_dp_compute_config_link_bpp_limits - compute output link bpp limits
> > > + * @intel_dp: intel DP
> > > + * @crtc_state: crtc state
> > > + * @dsc: DSC compression mode
> > > + * @limits: link configuration limits
> > > + *
> > > + * Calculates the output link min, max bpp values in @limits based on the
> > > + * pipe bpp range, @crtc_state and @dsc mode.
> > > + *
> > > + * Returns %true in case of success.
> > > + */
> > > +bool
> > > +intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> > > + const struct intel_crtc_state *crtc_state,
> > > + bool dsc,
> > > + struct link_config_limits *limits)
> > > +{
> > > + struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
> > > + const struct drm_display_mode *adjusted_mode =
> > > + &crtc_state->hw.adjusted_mode;
> > > + const struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > > + const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > > + int max_link_bpp_x16;
> > > +
> > > + max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> > > +
> > > + if (!dsc) {
> > > + max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
> > > +
> > > + if (max_link_bpp_x16 < to_bpp_x16(limits->pipe.min_bpp))
> > > + return false;
> >
> > Quite a few to_bpp_x16()'s in there. Seems like it would a bit simpler
> > to just do that once at the end.
>
> At the moment yes, but in a later patch max_link_bpp_x16 starts out as
> crtc_state->max_link_bpp_x16 limited value (with a non-zero fractional
> part).
>
> >
> > > +
> > > + limits->link.min_bpp_x16 = to_bpp_x16(limits->pipe.min_bpp);
> > > + } else {
> > > + limits->link.min_bpp_x16 = 0;
> >
> > Why is that zero? Don't we now have some helpers to fill
> > this stuff correctly?
>
> At the moment it's calculated only later in
> intel_edp_dsc_compute_pipe_bpp() / intel_dp_dsc_compute_pipe_bpp().
>
> It should be inited already here, but I wanted to do that only as a
> follow-up, since there's been other DSC changes from Ankit still under
> review. Is that ok, adding a TODO: here?
Sure.
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 05/22] drm/i915/dp: Limit the output link bpp in DSC mode
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (3 preceding siblings ...)
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 04/22] drm/i915/dp: Update the link bpp limits for DSC mode Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 06/22] drm/i915: Add helper to modeset a set of pipes Imre Deak
` (21 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
Limit the output link bpp in DSC mode to the link_config_limits
link.min_bpp_x16 .. max_bpp_x16 range the same way it's done in non-DSC
mode. Atm this doesn't make a difference, the link bpp range being
0 .. max pipe bpp, but a follow-up patch will need a way to reduce max
link bpp below its current value.
v2:
- Add to_bpp_int_roundup() instead of open coding it. (Jani)
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display_types.h | 5 +++++
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++++
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 +++
3 files changed, 12 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index a0a404967b5d2..b143085b399eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -2113,6 +2113,11 @@ static inline int to_bpp_int(int bpp_x16)
return bpp_x16 >> 4;
}
+static inline int to_bpp_int_roundup(int bpp_x16)
+{
+ return (bpp_x16 + 0xf) >> 4;
+}
+
static inline int to_bpp_frac_dec(int bpp_x16)
{
return (bpp_x16 & 0xf) * 625;
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 9ce861a7fd418..6637bd4768bf7 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1925,6 +1925,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+ dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
@@ -1934,6 +1935,7 @@ static int dsc_compute_compressed_bpp(struct intel_dp *intel_dp,
adjusted_mode->hdisplay,
pipe_config->bigjoiner_pipes);
dsc_max_bpp = min(dsc_max_bpp, dsc_joiner_max_bpp);
+ dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
if (DISPLAY_VER(i915) >= 13)
return xelpd_dsc_compute_link_config(intel_dp, pipe_config, limits,
@@ -2078,10 +2080,12 @@ static int intel_edp_dsc_compute_pipe_bpp(struct intel_dp *intel_dp,
dsc_src_min_bpp = dsc_src_min_compressed_bpp();
dsc_sink_min_bpp = dsc_sink_min_compressed_bpp(pipe_config);
dsc_min_bpp = max(dsc_src_min_bpp, dsc_sink_min_bpp);
+ dsc_min_bpp = max(dsc_min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
dsc_src_max_bpp = dsc_src_max_compressed_bpp(intel_dp);
dsc_sink_max_bpp = dsc_sink_max_compressed_bpp(intel_dp, pipe_config, pipe_bpp / 3);
dsc_max_bpp = dsc_sink_max_bpp ? min(dsc_sink_max_bpp, dsc_src_max_bpp) : dsc_src_max_bpp;
+ dsc_max_bpp = min(dsc_max_bpp, to_bpp_int(limits->link.max_bpp_x16));
/* Compressed BPP should be less than the Input DSC bpp */
dsc_max_bpp = min(dsc_max_bpp, pipe_bpp - 1);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 2b78a3a8966f3..525766206fce5 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -233,6 +233,9 @@ static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder,
if (max_bpp > sink_max_bpp)
max_bpp = sink_max_bpp;
+ min_bpp = max(min_bpp, to_bpp_int_roundup(limits->link.min_bpp_x16));
+ max_bpp = min(max_bpp, to_bpp_int(limits->link.max_bpp_x16));
+
slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp,
min_bpp, limits,
conn_state, 2 * 3, true);
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Intel-gfx] [PATCH v2 06/22] drm/i915: Add helper to modeset a set of pipes
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (4 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 05/22] drm/i915/dp: Limit the output link bpp in " Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-09-08 19:25 ` Ville Syrjälä
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 07/22] drm/i915: Factor out a helper to check/compute all the CRTC states Imre Deak
` (20 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
Add intel_modeset_pipes_in_mask() to modeset a provided set of pipes,
used in a follow-up patch.
While at it add DocBook descriptions for the exported functions.
v2:
- Add a flag controlling if active planes are force updated as well.
- Add DockBook descriptions.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 43 ++++++++++++++++++--
drivers/gpu/drm/i915/display/intel_display.h | 3 ++
2 files changed, 42 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index db3c26e013e3b..a1956b89fd75d 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -5420,8 +5420,24 @@ intel_verify_planes(struct intel_atomic_state *state)
plane_state->uapi.visible);
}
-int intel_modeset_all_pipes(struct intel_atomic_state *state,
- const char *reason)
+/**
+ * intel_modeset_pipes_in_mask - force a full modeset on a set of pipes
+ * @state: intel atomic state
+ * @reason: the reason for the full modeset
+ * @mask: mask of pipes to modeset
+ * @update_active_planes: force updating all active planes
+ *
+ * Force a full modeset on CRTCs in @mask due to the description in @reason.
+ * Also force updating all active planes in each modeset CRTC if
+ * @update_active_planes is %true. This flag must be set to %true if the
+ * function is called after new plane states are computed already and
+ * set to %false otherwise.
+ *
+ * Returns 0 in case of success, negative error code otherwise.
+ */
+int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
+ const char *reason, u8 mask,
+ bool update_active_planes)
{
struct drm_i915_private *dev_priv = to_i915(state->base.dev);
struct intel_crtc *crtc;
@@ -5430,7 +5446,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
* Add all pipes to the state, and force
* a modeset on all the active ones.
*/
- for_each_intel_crtc(&dev_priv->drm, crtc) {
+ for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, mask) {
struct intel_crtc_state *crtc_state;
int ret;
@@ -5461,7 +5477,9 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
if (ret)
return ret;
- crtc_state->update_planes |= crtc_state->active_planes;
+ if (update_active_planes)
+ crtc_state->update_planes |= crtc_state->active_planes;
+
crtc_state->async_flip_planes = 0;
crtc_state->do_async_flip = false;
}
@@ -5469,6 +5487,23 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
return 0;
}
+/**
+ * intel_modeset_all_pipes - force a full modeset on all pipes
+ * @state: intel atomic state
+ * @reason: the reason for the full modeset
+ *
+ * Force a full modeset on all CRTCs due to the description in @reason.
+ * This function can be called only after new plane states are computed
+ * already.
+ *
+ * Returns 0 in case of success, negative error code otherwise.
+ */
+int intel_modeset_all_pipes(struct intel_atomic_state *state,
+ const char *reason)
+{
+ return intel_modeset_pipes_in_mask(state, reason, -1, true);
+}
+
/*
* This implements the workaround described in the "notes" section of the mode
* set sequence documentation. When going from no pipes or single pipe to
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 49ac8473b988b..d9a54610d9d5e 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -515,6 +515,9 @@ void intel_update_watermarks(struct drm_i915_private *i915);
/* modesetting */
int intel_modeset_all_pipes(struct intel_atomic_state *state,
const char *reason);
+int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
+ const char *reason, u8 pipe_mask,
+ bool update_active_planes);
void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
struct intel_power_domain_mask *old_domains);
void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 06/22] drm/i915: Add helper to modeset a set of pipes
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 06/22] drm/i915: Add helper to modeset a set of pipes Imre Deak
@ 2023-09-08 19:25 ` Ville Syrjälä
2023-09-08 20:08 ` Imre Deak
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2023-09-08 19:25 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:05:01AM +0300, Imre Deak wrote:
> Add intel_modeset_pipes_in_mask() to modeset a provided set of pipes,
> used in a follow-up patch.
>
> While at it add DocBook descriptions for the exported functions.
>
> v2:
> - Add a flag controlling if active planes are force updated as well.
> - Add DockBook descriptions.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 43 ++++++++++++++++++--
> drivers/gpu/drm/i915/display/intel_display.h | 3 ++
> 2 files changed, 42 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index db3c26e013e3b..a1956b89fd75d 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -5420,8 +5420,24 @@ intel_verify_planes(struct intel_atomic_state *state)
> plane_state->uapi.visible);
> }
>
> -int intel_modeset_all_pipes(struct intel_atomic_state *state,
> - const char *reason)
> +/**
> + * intel_modeset_pipes_in_mask - force a full modeset on a set of pipes
> + * @state: intel atomic state
> + * @reason: the reason for the full modeset
> + * @mask: mask of pipes to modeset
> + * @update_active_planes: force updating all active planes
> + *
> + * Force a full modeset on CRTCs in @mask due to the description in @reason.
> + * Also force updating all active planes in each modeset CRTC if
> + * @update_active_planes is %true. This flag must be set to %true if the
> + * function is called after new plane states are computed already and
> + * set to %false otherwise.
> + *
> + * Returns 0 in case of success, negative error code otherwise.
> + */
> +int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
> + const char *reason, u8 mask,
> + bool update_active_planes)
Not really a fan of this parametrized behaviour. Also pretty sure we
have several other places that trigger modesets early in the atomic
check and all those just hand roll currently. So if we want a helper
then it might make more sense to try to combine all those early cases
into a new function. We could rename the current thing _late() or
something to make it clearer when it should be used.
> {
> struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> struct intel_crtc *crtc;
> @@ -5430,7 +5446,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> * Add all pipes to the state, and force
> * a modeset on all the active ones.
> */
> - for_each_intel_crtc(&dev_priv->drm, crtc) {
> + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, mask) {
> struct intel_crtc_state *crtc_state;
> int ret;
>
> @@ -5461,7 +5477,9 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> - crtc_state->update_planes |= crtc_state->active_planes;
> + if (update_active_planes)
> + crtc_state->update_planes |= crtc_state->active_planes;
> +
> crtc_state->async_flip_planes = 0;
> crtc_state->do_async_flip = false;
> }
> @@ -5469,6 +5487,23 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> return 0;
> }
>
> +/**
> + * intel_modeset_all_pipes - force a full modeset on all pipes
> + * @state: intel atomic state
> + * @reason: the reason for the full modeset
> + *
> + * Force a full modeset on all CRTCs due to the description in @reason.
> + * This function can be called only after new plane states are computed
> + * already.
> + *
> + * Returns 0 in case of success, negative error code otherwise.
> + */
> +int intel_modeset_all_pipes(struct intel_atomic_state *state,
> + const char *reason)
> +{
> + return intel_modeset_pipes_in_mask(state, reason, -1, true);
> +}
> +
> /*
> * This implements the workaround described in the "notes" section of the mode
> * set sequence documentation. When going from no pipes or single pipe to
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index 49ac8473b988b..d9a54610d9d5e 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -515,6 +515,9 @@ void intel_update_watermarks(struct drm_i915_private *i915);
> /* modesetting */
> int intel_modeset_all_pipes(struct intel_atomic_state *state,
> const char *reason);
> +int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
> + const char *reason, u8 pipe_mask,
> + bool update_active_planes);
> void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> struct intel_power_domain_mask *old_domains);
> void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
> --
> 2.37.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 06/22] drm/i915: Add helper to modeset a set of pipes
2023-09-08 19:25 ` Ville Syrjälä
@ 2023-09-08 20:08 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-09-08 20:08 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Fri, Sep 08, 2023 at 10:25:59PM +0300, Ville Syrjälä wrote:
> On Thu, Aug 24, 2023 at 11:05:01AM +0300, Imre Deak wrote:
> > Add intel_modeset_pipes_in_mask() to modeset a provided set of pipes,
> > used in a follow-up patch.
> >
> > While at it add DocBook descriptions for the exported functions.
> >
> > v2:
> > - Add a flag controlling if active planes are force updated as well.
> > - Add DockBook descriptions.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_display.c | 43 ++++++++++++++++++--
> > drivers/gpu/drm/i915/display/intel_display.h | 3 ++
> > 2 files changed, 42 insertions(+), 4 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index db3c26e013e3b..a1956b89fd75d 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -5420,8 +5420,24 @@ intel_verify_planes(struct intel_atomic_state *state)
> > plane_state->uapi.visible);
> > }
> >
> > -int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > - const char *reason)
> > +/**
> > + * intel_modeset_pipes_in_mask - force a full modeset on a set of pipes
> > + * @state: intel atomic state
> > + * @reason: the reason for the full modeset
> > + * @mask: mask of pipes to modeset
> > + * @update_active_planes: force updating all active planes
> > + *
> > + * Force a full modeset on CRTCs in @mask due to the description in @reason.
> > + * Also force updating all active planes in each modeset CRTC if
> > + * @update_active_planes is %true. This flag must be set to %true if the
> > + * function is called after new plane states are computed already and
> > + * set to %false otherwise.
> > + *
> > + * Returns 0 in case of success, negative error code otherwise.
> > + */
> > +int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
> > + const char *reason, u8 mask,
> > + bool update_active_planes)
>
> Not really a fan of this parametrized behaviour. Also pretty sure we
> have several other places that trigger modesets early in the atomic
> check and all those just hand roll currently. So if we want a helper
> then it might make more sense to try to combine all those early cases
> into a new function. We could rename the current thing _late() or
> something to make it clearer when it should be used.
Ok, so the exported functions would be
intel_modeset_pipes_in_mask_early() / intel_modeset_all_pipes_late().
Yes, noticed the other early users as well, I suppose it's ok to
refactor those as a follow-up (iiuc I have even some patches for that).
>
> > {
> > struct drm_i915_private *dev_priv = to_i915(state->base.dev);
> > struct intel_crtc *crtc;
> > @@ -5430,7 +5446,7 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > * Add all pipes to the state, and force
> > * a modeset on all the active ones.
> > */
> > - for_each_intel_crtc(&dev_priv->drm, crtc) {
> > + for_each_intel_crtc_in_pipe_mask(&dev_priv->drm, crtc, mask) {
> > struct intel_crtc_state *crtc_state;
> > int ret;
> >
> > @@ -5461,7 +5477,9 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > if (ret)
> > return ret;
> >
> > - crtc_state->update_planes |= crtc_state->active_planes;
> > + if (update_active_planes)
> > + crtc_state->update_planes |= crtc_state->active_planes;
> > +
> > crtc_state->async_flip_planes = 0;
> > crtc_state->do_async_flip = false;
> > }
> > @@ -5469,6 +5487,23 @@ int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > return 0;
> > }
> >
> > +/**
> > + * intel_modeset_all_pipes - force a full modeset on all pipes
> > + * @state: intel atomic state
> > + * @reason: the reason for the full modeset
> > + *
> > + * Force a full modeset on all CRTCs due to the description in @reason.
> > + * This function can be called only after new plane states are computed
> > + * already.
> > + *
> > + * Returns 0 in case of success, negative error code otherwise.
> > + */
> > +int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > + const char *reason)
> > +{
> > + return intel_modeset_pipes_in_mask(state, reason, -1, true);
> > +}
> > +
> > /*
> > * This implements the workaround described in the "notes" section of the mode
> > * set sequence documentation. When going from no pipes or single pipe to
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > index 49ac8473b988b..d9a54610d9d5e 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -515,6 +515,9 @@ void intel_update_watermarks(struct drm_i915_private *i915);
> > /* modesetting */
> > int intel_modeset_all_pipes(struct intel_atomic_state *state,
> > const char *reason);
> > +int intel_modeset_pipes_in_mask(struct intel_atomic_state *state,
> > + const char *reason, u8 pipe_mask,
> > + bool update_active_planes);
> > void intel_modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
> > struct intel_power_domain_mask *old_domains);
> > void intel_modeset_put_crtc_power_domains(struct intel_crtc *crtc,
> > --
> > 2.37.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 07/22] drm/i915: Factor out a helper to check/compute all the CRTC states
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (5 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 06/22] drm/i915: Add helper to modeset a set of pipes Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-09-08 19:31 ` Ville Syrjälä
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/fdi: Improve FDI BW sharing between pipe B and C Imre Deak
` (19 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
Factor out intel_atomic_check_config() to check and compute all the CRTC
states. This will be used by a follow up patch to recompute/check the
state until required by BW limitations between CRTCs.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 78 ++++++++++++--------
1 file changed, 46 insertions(+), 32 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index a1956b89fd75d..dbf109a2e738f 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -6206,6 +6206,51 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
return 0;
}
+static int intel_atomic_check_config(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+ int ret;
+ int i;
+
+ ret = intel_bigjoiner_add_affected_crtcs(state);
+ if (ret)
+ return ret;
+
+ for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
+ if (!intel_crtc_needs_modeset(new_crtc_state)) {
+ if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
+ copy_bigjoiner_crtc_state_nomodeset(state, crtc);
+ else
+ intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
+ continue;
+ }
+
+ if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
+ drm_WARN_ON(&i915->drm, new_crtc_state->uapi.enable);
+ continue;
+ }
+
+ ret = intel_crtc_prepare_cleared_state(state, crtc);
+ if (ret)
+ break;
+
+ if (!new_crtc_state->hw.enable)
+ continue;
+
+ ret = intel_modeset_pipe_config(state, crtc);
+ if (ret)
+ break;
+
+ ret = intel_atomic_check_bigjoiner(state, crtc);
+ if (ret)
+ break;
+ }
+
+ return ret;
+}
+
/**
* intel_atomic_check - validate state object
* @dev: drm device
@@ -6250,41 +6295,10 @@ int intel_atomic_check(struct drm_device *dev,
return ret;
}
- ret = intel_bigjoiner_add_affected_crtcs(state);
+ ret = intel_atomic_check_config(state);
if (ret)
goto fail;
- for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
- new_crtc_state, i) {
- if (!intel_crtc_needs_modeset(new_crtc_state)) {
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
- copy_bigjoiner_crtc_state_nomodeset(state, crtc);
- else
- intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
- continue;
- }
-
- if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
- drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
- continue;
- }
-
- ret = intel_crtc_prepare_cleared_state(state, crtc);
- if (ret)
- goto fail;
-
- if (!new_crtc_state->hw.enable)
- continue;
-
- ret = intel_modeset_pipe_config(state, crtc);
- if (ret)
- goto fail;
-
- ret = intel_atomic_check_bigjoiner(state, crtc);
- if (ret)
- goto fail;
- }
-
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
new_crtc_state, i) {
if (!intel_crtc_needs_modeset(new_crtc_state))
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 07/22] drm/i915: Factor out a helper to check/compute all the CRTC states
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 07/22] drm/i915: Factor out a helper to check/compute all the CRTC states Imre Deak
@ 2023-09-08 19:31 ` Ville Syrjälä
0 siblings, 0 replies; 60+ messages in thread
From: Ville Syrjälä @ 2023-09-08 19:31 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:05:02AM +0300, Imre Deak wrote:
> Factor out intel_atomic_check_config() to check and compute all the CRTC
> states. This will be used by a follow up patch to recompute/check the
> state until required by BW limitations between CRTCs.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_display.c | 78 ++++++++++++--------
> 1 file changed, 46 insertions(+), 32 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index a1956b89fd75d..dbf109a2e738f 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -6206,6 +6206,51 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
> return 0;
> }
>
> +static int intel_atomic_check_config(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc *crtc;
> + int ret;
> + int i;
> +
> + ret = intel_bigjoiner_add_affected_crtcs(state);
> + if (ret)
> + return ret;
> +
> + for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> + if (!intel_crtc_needs_modeset(new_crtc_state)) {
> + if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> + copy_bigjoiner_crtc_state_nomodeset(state, crtc);
> + else
> + intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
> + continue;
> + }
> +
> + if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
> + drm_WARN_ON(&i915->drm, new_crtc_state->uapi.enable);
> + continue;
> + }
> +
> + ret = intel_crtc_prepare_cleared_state(state, crtc);
> + if (ret)
> + break;
> +
> + if (!new_crtc_state->hw.enable)
> + continue;
> +
> + ret = intel_modeset_pipe_config(state, crtc);
> + if (ret)
> + break;
> +
> + ret = intel_atomic_check_bigjoiner(state, crtc);
> + if (ret)
> + break;
> + }
> +
> + return ret;
> +}
> +
> /**
> * intel_atomic_check - validate state object
> * @dev: drm device
> @@ -6250,41 +6295,10 @@ int intel_atomic_check(struct drm_device *dev,
> return ret;
> }
>
> - ret = intel_bigjoiner_add_affected_crtcs(state);
> + ret = intel_atomic_check_config(state);
> if (ret)
> goto fail;
>
> - for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> - new_crtc_state, i) {
> - if (!intel_crtc_needs_modeset(new_crtc_state)) {
> - if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> - copy_bigjoiner_crtc_state_nomodeset(state, crtc);
> - else
> - intel_crtc_copy_uapi_to_hw_state_nomodeset(state, crtc);
> - continue;
> - }
> -
> - if (intel_crtc_is_bigjoiner_slave(new_crtc_state)) {
> - drm_WARN_ON(&dev_priv->drm, new_crtc_state->uapi.enable);
> - continue;
> - }
> -
> - ret = intel_crtc_prepare_cleared_state(state, crtc);
> - if (ret)
> - goto fail;
> -
> - if (!new_crtc_state->hw.enable)
> - continue;
> -
> - ret = intel_modeset_pipe_config(state, crtc);
> - if (ret)
> - goto fail;
> -
> - ret = intel_atomic_check_bigjoiner(state, crtc);
> - if (ret)
> - goto fail;
> - }
> -
> for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state,
> new_crtc_state, i) {
> if (!intel_crtc_needs_modeset(new_crtc_state))
> --
> 2.37.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 08/22] drm/i915/fdi: Improve FDI BW sharing between pipe B and C
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (6 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 07/22] drm/i915: Factor out a helper to check/compute all the CRTC states Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-09-11 18:59 ` Ville Syrjälä
2023-08-24 8:05 ` Imre Deak
` (18 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
link bpp in this case, until pipe B uses only up to 2 FDI lanes.
For this instead of the encoder compute config retry loop - which
reduced link bpp only for the encoder's pipe - check the overall BW
limits after all CRTC states have been computed and if the check fails
reduce the maximum link bpp for a selected pipe (for FDI pipe B or C as
required) and recompute all the CRTC states. Retry this sequence until
either the overall BW limit check passes, or further bpp reduction is
not possible (because all pipes/encoders sharing the link BW reached
their minimum link bpp).
This change also prepares for an upcoming patch resolving BW limits in
a similar way on MST links as well.
v2:
- Rename intel_crtc_state::max_link_bpp to max_link_bpp_x16 and
intel_link_bw_limits::max_bpp to max_bpp_x16. (Jani)
- Increase back pipe B's link bpp if earlier it was limited due to
pipe C and pipe C gets later disabled.
- Don't assume that a CRTC is already in the atomic state, while
reducing its link bpp.
- Add DocBook description to intel_fdi_atomic_check_link().
Cc: Jani Nikula <jani.nikula@linux.intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/g4x_hdmi.c | 5 +-
drivers/gpu/drm/i915/display/intel_atomic.c | 207 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_atomic.h | 8 +
drivers/gpu/drm/i915/display/intel_crt.c | 7 +
drivers/gpu/drm/i915/display/intel_crtc.c | 1 +
drivers/gpu/drm/i915/display/intel_display.c | 44 ++--
drivers/gpu/drm/i915/display/intel_display.h | 4 +
.../drm/i915/display/intel_display_types.h | 9 +-
drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
drivers/gpu/drm/i915/display/intel_fdi.c | 137 ++++++++++--
drivers/gpu/drm/i915/display/intel_fdi.h | 5 +
drivers/gpu/drm/i915/display/intel_lvds.c | 9 +-
drivers/gpu/drm/i915/display/intel_sdvo.c | 9 +-
13 files changed, 404 insertions(+), 44 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 634b14116d9dd..ebbceddc13259 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -133,8 +133,11 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *i915 = to_i915(encoder->base.dev);
- if (HAS_PCH_SPLIT(i915))
+ if (HAS_PCH_SPLIT(i915)) {
crtc_state->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(crtc_state))
+ return -EINVAL;
+ }
if (IS_G4X(i915))
crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index 7cf51dd8c0567..ee4cbf80ddb55 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -38,6 +38,7 @@
#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_fdi.h"
#include "intel_global_state.h"
#include "intel_hdcp.h"
#include "intel_psr.h"
@@ -358,3 +359,209 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
return to_intel_crtc_state(crtc_state);
}
+
+/**
+ * intel_atomic_compute_pipe_bpp - compute pipe bpp limited by max link bpp
+ * @crtc_state: the crtc state
+ *
+ * Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can
+ * call this function during state computation in the simple case where the
+ * link bpp will always match the pipe bpp. This is the case for all non-DP
+ * encoders, while DP encoders will use a link bpp lower than pipe bpp in case
+ * of DSC compression.
+ *
+ * Returns %true in case of success, %false if pipe bpp would need to be
+ * reduced below its valid range.
+ */
+bool intel_atomic_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
+{
+ int pipe_bpp = min(crtc_state->pipe_bpp,
+ to_bpp_int(crtc_state->max_link_bpp_x16));
+
+ pipe_bpp = rounddown(pipe_bpp, 2 * 3);
+
+ if (pipe_bpp < 6 * 3)
+ return false;
+
+ crtc_state->pipe_bpp = pipe_bpp;
+
+ return true;
+}
+
+/**
+ * intel_atomic_reduce_link_bpp - reduce maximum link bpp for a selected pipe
+ * @state: atomic state
+ * @limits: link BW limits
+ * @pipe_mask: mask of pipes to select from
+ * @reason: explanation of why bpp reduction is needed
+ *
+ * Select the pipe from @pipe_mask with the biggest link bpp value and set the
+ * maximum of link bpp in @limits below this value. Modeset the selected pipe,
+ * so that its state will get recomputed.
+ *
+ * This function can be called to resolve a link's BW overallocation by reducing
+ * the link bpp of one pipe on the link and hence reducing the total link BW.
+ *
+ * Returns
+ * - 0 in case of success
+ * - %-EINVAL if no pipe can further reduce its link bpp
+ * - Other negative error, if modesetting the selected pipe failed
+ */
+int intel_atomic_reduce_link_bpp(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits,
+ u8 pipe_mask,
+ const char *reason)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ enum pipe max_bpp_pipe = INVALID_PIPE;
+ struct intel_crtc *crtc;
+ int max_bpp = 0;
+
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
+ struct intel_crtc_state *crtc_state;
+ int pipe_bpp;
+
+ if (limits->min_bpp_pipes & BIT(crtc->pipe))
+ continue;
+
+ crtc_state = intel_atomic_get_crtc_state(&state->base,
+ crtc);
+ if (IS_ERR(crtc_state))
+ return PTR_ERR(crtc_state);
+
+ if (crtc_state->dsc.compression_enable)
+ pipe_bpp = crtc_state->dsc.compressed_bpp;
+ else
+ pipe_bpp = crtc_state->pipe_bpp;
+
+ if (pipe_bpp > max_bpp) {
+ max_bpp = pipe_bpp;
+ max_bpp_pipe = crtc->pipe;
+ }
+ }
+
+ if (max_bpp_pipe == INVALID_PIPE)
+ return -EINVAL;
+
+ limits->max_bpp_x16[max_bpp_pipe] = to_bpp_x16(max_bpp) - 1;
+
+ return intel_modeset_pipes_in_mask(state, reason,
+ BIT(max_bpp_pipe), false);
+}
+
+static int intel_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
+{
+ int ret;
+
+ ret = intel_fdi_atomic_check_link(state, limits);
+ if (ret)
+ return ret;
+
+ return 0;
+}
+
+static bool
+assert_link_limit_change_valid(struct drm_i915_private *i915,
+ const struct intel_link_bw_limits *old_limits,
+ const struct intel_link_bw_limits *new_limits)
+{
+ bool bpps_changed = false;
+ enum pipe pipe;
+
+ for_each_pipe(i915, pipe) {
+ /* The bpp limit can only decrease. */
+ if (drm_WARN_ON(&i915->drm,
+ new_limits->max_bpp_x16[pipe] >
+ old_limits->max_bpp_x16[pipe]))
+ return false;
+
+ if (new_limits->max_bpp_x16[pipe] <
+ old_limits->max_bpp_x16[pipe])
+ bpps_changed = true;
+ }
+
+ if (drm_WARN_ON(&i915->drm,
+ !bpps_changed))
+ return false;
+
+ return true;
+}
+
+static bool
+reset_link_bpp_limit_to_min(struct intel_atomic_state *state,
+ const struct intel_link_bw_limits *old_limits,
+ struct intel_link_bw_limits *new_limits,
+ enum pipe failed_pipe)
+{
+ if (failed_pipe == INVALID_PIPE)
+ return false;
+
+ if (new_limits->min_bpp_pipes & BIT(failed_pipe))
+ return false;
+
+ if (new_limits->max_bpp_x16[failed_pipe] ==
+ old_limits->max_bpp_x16[failed_pipe])
+ return false;
+
+ new_limits->max_bpp_x16[failed_pipe] =
+ old_limits->max_bpp_x16[failed_pipe];
+ new_limits->min_bpp_pipes |= BIT(failed_pipe);
+
+ return true;
+}
+
+/**
+ * intel_atomic_check_config_and_link - compute CRTC configs, resolving any BW limits
+ * @state: atomic state
+ *
+ * Compute the configuration of all CRTCs in @state and resolve any BW
+ * limitations on links shared by these CRTCs.
+ *
+ * Return 0 in case of success, or a negative error code otherwise.
+ */
+int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_link_bw_limits new_limits = {};
+ struct intel_link_bw_limits old_limits;
+ enum pipe pipe;
+ int ret;
+
+ for_each_pipe(i915, pipe)
+ new_limits.max_bpp_x16[pipe] = INT_MAX;
+
+ old_limits = new_limits;
+
+ while (true) {
+ enum pipe failed_pipe;
+
+ ret = intel_atomic_check_config(state, &new_limits,
+ &failed_pipe);
+ if (ret) {
+ if (ret == -EINVAL &&
+ reset_link_bpp_limit_to_min(state,
+ &old_limits,
+ &new_limits,
+ failed_pipe))
+ continue;
+
+ break;
+ }
+
+ old_limits = new_limits;
+
+ ret = intel_atomic_check_link(state, &new_limits);
+ if (ret != -EAGAIN)
+ break;
+
+ if (!assert_link_limit_change_valid(i915,
+ &old_limits,
+ &new_limits)) {
+ ret = -EINVAL;
+ break;
+ }
+ }
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
index e506f6a873447..bbf3595d52c41 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.h
+++ b/drivers/gpu/drm/i915/display/intel_atomic.h
@@ -20,6 +20,7 @@ struct intel_atomic_state;
struct intel_connector;
struct intel_crtc;
struct intel_crtc_state;
+struct intel_link_bw_limits;
int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
const struct drm_connector_state *state,
@@ -52,4 +53,11 @@ struct intel_crtc_state *
intel_atomic_get_crtc_state(struct drm_atomic_state *state,
struct intel_crtc *crtc);
+int intel_atomic_reduce_link_bpp(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits,
+ u8 pipe_mask,
+ const char *reason);
+bool intel_atomic_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
+int intel_atomic_check_config_and_link(struct intel_atomic_state *state);
+
#endif /* __INTEL_ATOMIC_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
index f66340b4caf0f..3322080a574e8 100644
--- a/drivers/gpu/drm/i915/display/intel_crt.c
+++ b/drivers/gpu/drm/i915/display/intel_crt.c
@@ -36,6 +36,7 @@
#include "i915_drv.h"
#include "i915_irq.h"
#include "i915_reg.h"
+#include "intel_atomic.h"
#include "intel_connector.h"
#include "intel_crt.h"
#include "intel_crtc.h"
@@ -413,6 +414,9 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
return -EINVAL;
pipe_config->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(pipe_config))
+ return -EINVAL;
+
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
return 0;
@@ -435,6 +439,9 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
return -EINVAL;
pipe_config->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(pipe_config))
+ return -EINVAL;
+
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
/* LPT FDI RX only supports 8bpc. */
diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
index 182c6dd64f47c..1eda6a9f19aa8 100644
--- a/drivers/gpu/drm/i915/display/intel_crtc.c
+++ b/drivers/gpu/drm/i915/display/intel_crtc.c
@@ -175,6 +175,7 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
crtc_state->hsw_workaround_pipe = INVALID_PIPE;
crtc_state->scaler_state.scaler_id = -1;
crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
+ crtc_state->max_link_bpp_x16 = INT_MAX;
}
static struct intel_crtc *intel_crtc_alloc(void)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index dbf109a2e738f..32778bd01bb05 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4641,7 +4641,8 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
static int
intel_modeset_pipe_config(struct intel_atomic_state *state,
- struct intel_crtc *crtc)
+ struct intel_crtc *crtc,
+ const struct intel_link_bw_limits *limits)
{
struct drm_i915_private *i915 = to_i915(crtc->base.dev);
struct intel_crtc_state *crtc_state =
@@ -4650,7 +4651,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
struct drm_connector_state *connector_state;
int pipe_src_w, pipe_src_h;
int base_bpp, ret, i;
- bool retry = true;
crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
@@ -4673,6 +4673,17 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
if (ret)
return ret;
+ crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
+
+ if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s] Link bpp limited to %d.%04d\n",
+ crtc->base.base.id, crtc->base.name,
+ to_bpp_int(crtc_state->max_link_bpp_x16),
+ to_bpp_frac_dec(crtc_state->max_link_bpp_x16));
+ crtc_state->bw_constrained = true;
+ }
+
base_bpp = crtc_state->pipe_bpp;
/*
@@ -4714,7 +4725,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
crtc_state->output_types |= BIT(encoder->type);
}
-encoder_retry:
/* Ensure the port clock defaults are reset when retrying. */
crtc_state->port_clock = 0;
crtc_state->pixel_multiplier = 1;
@@ -4754,17 +4764,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
ret = intel_crtc_compute_config(state, crtc);
if (ret == -EDEADLK)
return ret;
- if (ret == -EAGAIN) {
- if (drm_WARN(&i915->drm, !retry,
- "[CRTC:%d:%s] loop in pipe configuration computation\n",
- crtc->base.base.id, crtc->base.name))
- return -EINVAL;
-
- drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
- crtc->base.base.id, crtc->base.name);
- retry = false;
- goto encoder_retry;
- }
if (ret < 0) {
drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
crtc->base.base.id, crtc->base.name, ret);
@@ -6206,7 +6205,9 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
return 0;
}
-static int intel_atomic_check_config(struct intel_atomic_state *state)
+int intel_atomic_check_config(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits,
+ enum pipe *failed_pipe)
{
struct drm_i915_private *i915 = to_i915(state->base.dev);
struct intel_crtc_state *new_crtc_state;
@@ -6214,10 +6215,16 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
int ret;
int i;
+ *failed_pipe = INVALID_PIPE;
+
ret = intel_bigjoiner_add_affected_crtcs(state);
if (ret)
return ret;
+ ret = intel_fdi_add_affected_crtcs(state);
+ if (ret)
+ return ret;
+
for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
if (!intel_crtc_needs_modeset(new_crtc_state)) {
if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
@@ -6239,7 +6246,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
if (!new_crtc_state->hw.enable)
continue;
- ret = intel_modeset_pipe_config(state, crtc);
+ ret = intel_modeset_pipe_config(state, crtc, limits);
if (ret)
break;
@@ -6248,6 +6255,9 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
break;
}
+ if (ret)
+ *failed_pipe = crtc->pipe;
+
return ret;
}
@@ -6295,7 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
return ret;
}
- ret = intel_atomic_check_config(state);
+ ret = intel_atomic_check_config_and_link(state);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index d9a54610d9d5e..2e0535739bd70 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -55,6 +55,7 @@ struct intel_digital_port;
struct intel_dp;
struct intel_encoder;
struct intel_initial_plane_config;
+struct intel_link_bw_limits;
struct intel_link_m_n;
struct intel_plane;
struct intel_plane_state;
@@ -391,6 +392,9 @@ enum phy_fia {
(new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
+int intel_atomic_check_config(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits,
+ enum pipe *failed_pipe);
int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
struct intel_crtc *crtc);
u8 intel_calc_active_pipes(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index b143085b399eb..6f4f46658df22 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -66,6 +66,12 @@ struct intel_tc_port;
* Display related stuff
*/
+struct intel_link_bw_limits {
+ u8 min_bpp_pipes;
+ /* in 1/16 bpp units */
+ int max_bpp_x16[I915_MAX_PIPES];
+};
+
/* these are outputs from the chip - integrated only
external chips are via DVO or SDVO output */
enum intel_output_type {
@@ -1189,7 +1195,8 @@ struct intel_crtc_state {
u32 ctrl, div;
} dsi_pll;
- int pipe_bpp;
+ int max_link_bpp_x16; /* in 1/16 bpp units */
+ int pipe_bpp; /* in 1 bpp units */
struct intel_link_m_n dp_m_n;
/* m2_n2 for eDP downclock */
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 6637bd4768bf7..48f005932ad8b 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2218,7 +2218,8 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
int max_link_bpp_x16;
- max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
+ max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
+ to_bpp_x16(limits->pipe.max_bpp));
if (!dsc) {
max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
index e12b46a84fa11..123ba67f68791 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.c
+++ b/drivers/gpu/drm/i915/display/intel_fdi.c
@@ -119,6 +119,59 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
}
+/**
+ * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs
+ * @state: intel atomic state
+ *
+ * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is
+ * known to affect the available FDI BW for the former CRTC. In practice this
+ * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by
+ * CRTC C) and CRTC C is getting disabled.
+ *
+ * Returns 0 in case of success, or a negative error code otherwise.
+ */
+int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc_state *old_crtc_state;
+ struct intel_crtc_state *new_crtc_state;
+ struct intel_crtc *crtc;
+
+ if (!IS_IVYBRIDGE(i915))
+ return 0;
+
+ crtc = intel_crtc_for_pipe(i915, PIPE_C);
+ new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (!new_crtc_state)
+ return 0;
+
+ old_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
+
+ if (!old_crtc_state->fdi_lanes)
+ return 0;
+
+ if (!intel_crtc_needs_modeset(new_crtc_state))
+ return 0;
+
+ if (new_crtc_state->uapi.enable)
+ return 0;
+
+ crtc = intel_crtc_for_pipe(i915, PIPE_B);
+ new_crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
+
+ if (IS_ERR(new_crtc_state))
+ return PTR_ERR(old_crtc_state);
+
+ old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
+ if (!old_crtc_state->fdi_lanes)
+ return 0;
+
+ return intel_modeset_pipes_in_mask(state,
+ "FDI link BW decrease on pipe C",
+ BIT(PIPE_B), false);
+}
+
/* units of 100MHz */
static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
{
@@ -129,13 +182,16 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
}
static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
- struct intel_crtc_state *pipe_config)
+ struct intel_crtc_state *pipe_config,
+ enum pipe *pipe_to_reduce)
{
struct drm_i915_private *dev_priv = to_i915(dev);
struct drm_atomic_state *state = pipe_config->uapi.state;
struct intel_crtc *other_crtc;
struct intel_crtc_state *other_crtc_state;
+ *pipe_to_reduce = pipe;
+
drm_dbg_kms(&dev_priv->drm,
"checking fdi config on pipe %c, lanes %i\n",
pipe_name(pipe), pipe_config->fdi_lanes);
@@ -198,6 +254,9 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
drm_dbg_kms(&dev_priv->drm,
"fdi link B uses too many lanes to enable link C\n");
+
+ *pipe_to_reduce = PIPE_B;
+
return -EINVAL;
}
return 0;
@@ -238,10 +297,8 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *i915 = to_i915(dev);
const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
- int lane, link_bw, fdi_dotclock, ret;
- bool needs_recompute = false;
+ int lane, link_bw, fdi_dotclock;
-retry:
/* FDI is a binary signal running at ~2.7GHz, encoding
* each output octet as 10 bits. The actual frequency
* is stored as a divider into a 100MHz clock, and the
@@ -261,25 +318,69 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
link_bw, &pipe_config->fdi_m_n, false);
- ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
- if (ret == -EDEADLK)
+ return 0;
+}
+
+static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state,
+ struct intel_crtc *crtc,
+ struct intel_crtc_state *pipe_config,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_i915_private *i915 = to_i915(crtc->base.dev);
+ enum pipe pipe_to_reduce;
+ int ret;
+
+ ret = ilk_check_fdi_lanes(&i915->drm, crtc->pipe, pipe_config,
+ &pipe_to_reduce);
+ if (ret != -EINVAL)
return ret;
- if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
- pipe_config->pipe_bpp -= 2*3;
- drm_dbg_kms(&i915->drm,
- "fdi link bw constraint, reducing pipe bpp to %i\n",
- pipe_config->pipe_bpp);
- needs_recompute = true;
- pipe_config->bw_constrained = true;
+ ret = intel_atomic_reduce_link_bpp(state, limits,
+ BIT(pipe_to_reduce),
+ "FDI link BW");
- goto retry;
- }
+ return ret ? : -EAGAIN;
+}
- if (needs_recompute)
- return -EAGAIN;
+/**
+ * intel_fdi_atomic_check_link - check all modeset FDI link configuration
+ * @state: intel atomic state
+ * @limits: link BW limits
+ *
+ * Check the link configuration for all modeset FDI outputs. If the
+ * configuration is invalid @limits will be updated if possible to
+ * reduce the total BW, after which the configuration for all CRTCs in
+ * @state must be recomputed with the updated @limits.
+ *
+ * Returns:
+ * - 0 if the confugration is valid
+ * - %-EAGAIN, if the configuration is invalid and @limits got updated
+ * with fallback values with which the configuration of all CRTCs
+ * in @state must be recomputed
+ * - Other negative error, if the configuration is invalid without a
+ * fallback possibility, or the check failed for another reason
+ */
+int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
+{
+ struct intel_crtc *crtc;
+ struct intel_crtc_state *crtc_state;
+ int i;
+
+ for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
+ int ret;
- return ret;
+ if (!crtc_state->has_pch_encoder ||
+ !intel_crtc_needs_modeset(crtc_state) ||
+ !crtc_state->hw.enable)
+ continue;
+
+ ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
}
static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
index 1cdb86172702f..eb02b967bb440 100644
--- a/drivers/gpu/drm/i915/display/intel_fdi.h
+++ b/drivers/gpu/drm/i915/display/intel_fdi.h
@@ -8,14 +8,19 @@
enum pipe;
struct drm_i915_private;
+struct intel_atomic_state;
struct intel_crtc;
struct intel_crtc_state;
struct intel_encoder;
+struct intel_link_bw_limits;
+int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state);
int intel_fdi_link_freq(struct drm_i915_private *i915,
const struct intel_crtc_state *pipe_config);
int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
struct intel_crtc_state *pipe_config);
+int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits);
void intel_fdi_normal_train(struct intel_crtc *crtc);
void ilk_fdi_disable(struct intel_crtc *crtc);
void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc);
diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
index 3ace56979b70e..08dcc2d10a2c1 100644
--- a/drivers/gpu/drm/i915/display/intel_lvds.c
+++ b/drivers/gpu/drm/i915/display/intel_lvds.c
@@ -425,6 +425,12 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
return -EINVAL;
}
+ if (HAS_PCH_SPLIT(i915)) {
+ crtc_state->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(crtc_state))
+ return -EINVAL;
+ }
+
if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
lvds_bpp = 8*3;
else
@@ -453,9 +459,6 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
- if (HAS_PCH_SPLIT(i915))
- crtc_state->has_pch_encoder = true;
-
ret = intel_panel_fitting(crtc_state, conn_state);
if (ret)
return ret;
diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
index 7d25a64698e2f..1c6330151f4d6 100644
--- a/drivers/gpu/drm/i915/display/intel_sdvo.c
+++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
@@ -1352,14 +1352,17 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
struct drm_display_mode *mode = &pipe_config->hw.mode;
+ if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
+ pipe_config->has_pch_encoder = true;
+ if (!intel_atomic_compute_pipe_bpp(pipe_config))
+ return -EINVAL;
+ }
+
DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
pipe_config->pipe_bpp = 8*3;
pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
- if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
- pipe_config->has_pch_encoder = true;
-
/*
* We need to construct preferred input timings based on our
* output timings. To do that, we have to set the output
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 08/22] drm/i915/fdi: Improve FDI BW sharing between pipe B and C
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 08/22] drm/i915/fdi: Improve FDI BW sharing between pipe B and C Imre Deak
@ 2023-09-11 18:59 ` Ville Syrjälä
2023-09-11 20:42 ` Imre Deak
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2023-09-11 18:59 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:05:03AM +0300, Imre Deak wrote:
> At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
> lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
> link bpp in this case, until pipe B uses only up to 2 FDI lanes.
>
> For this instead of the encoder compute config retry loop - which
> reduced link bpp only for the encoder's pipe - check the overall BW
> limits after all CRTC states have been computed and if the check fails
> reduce the maximum link bpp for a selected pipe (for FDI pipe B or C as
> required) and recompute all the CRTC states. Retry this sequence until
> either the overall BW limit check passes, or further bpp reduction is
> not possible (because all pipes/encoders sharing the link BW reached
> their minimum link bpp).
>
> This change also prepares for an upcoming patch resolving BW limits in
> a similar way on MST links as well.
>
> v2:
> - Rename intel_crtc_state::max_link_bpp to max_link_bpp_x16 and
> intel_link_bw_limits::max_bpp to max_bpp_x16. (Jani)
> - Increase back pipe B's link bpp if earlier it was limited due to
> pipe C and pipe C gets later disabled.
> - Don't assume that a CRTC is already in the atomic state, while
> reducing its link bpp.
> - Add DocBook description to intel_fdi_atomic_check_link().
>
> Cc: Jani Nikula <jani.nikula@linux.intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/g4x_hdmi.c | 5 +-
> drivers/gpu/drm/i915/display/intel_atomic.c | 207 ++++++++++++++++++
> drivers/gpu/drm/i915/display/intel_atomic.h | 8 +
> drivers/gpu/drm/i915/display/intel_crt.c | 7 +
> drivers/gpu/drm/i915/display/intel_crtc.c | 1 +
> drivers/gpu/drm/i915/display/intel_display.c | 44 ++--
> drivers/gpu/drm/i915/display/intel_display.h | 4 +
> .../drm/i915/display/intel_display_types.h | 9 +-
> drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
> drivers/gpu/drm/i915/display/intel_fdi.c | 137 ++++++++++--
> drivers/gpu/drm/i915/display/intel_fdi.h | 5 +
> drivers/gpu/drm/i915/display/intel_lvds.c | 9 +-
> drivers/gpu/drm/i915/display/intel_sdvo.c | 9 +-
> 13 files changed, 404 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> index 634b14116d9dd..ebbceddc13259 100644
> --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> @@ -133,8 +133,11 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
> struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> struct drm_i915_private *i915 = to_i915(encoder->base.dev);
>
> - if (HAS_PCH_SPLIT(i915))
> + if (HAS_PCH_SPLIT(i915)) {
> crtc_state->has_pch_encoder = true;
> + if (!intel_atomic_compute_pipe_bpp(crtc_state))
> + return -EINVAL;
> + }
>
> if (IS_G4X(i915))
> crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> index 7cf51dd8c0567..ee4cbf80ddb55 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
Not convinced we should put anything there. I think I mostly managed to
move a bunch or semi-random stuff out now, so all it more or less has is
the struct intel_atomic_state alloc/free stuff.
You have intel_atomic_check() in intel_display.c and the lower level
intel_atomic_check_config() is also there, but now the middle man
intel_atomic_check_config_and_link() ended up in intel_atomic.c for
whatever reason. I'd just shove all of it into intel_display.c.
The patch is also rather massive. Can we try to chunk it up to
eg. something like:
1) add the new infrastructure
2) convert the fdi retry stuff to use the new infrastructure
3) add intel_fdi_add_affected_crtcs() (which seems more or less
independent from the rest of the fdi conversion?)
?
> @@ -38,6 +38,7 @@
> #include "intel_atomic.h"
> #include "intel_cdclk.h"
> #include "intel_display_types.h"
> +#include "intel_fdi.h"
> #include "intel_global_state.h"
> #include "intel_hdcp.h"
> #include "intel_psr.h"
> @@ -358,3 +359,209 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
>
> return to_intel_crtc_state(crtc_state);
> }
> +
> +/**
> + * intel_atomic_compute_pipe_bpp - compute pipe bpp limited by max link bpp
> + * @crtc_state: the crtc state
> + *
> + * Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can
> + * call this function during state computation in the simple case where the
> + * link bpp will always match the pipe bpp. This is the case for all non-DP
> + * encoders, while DP encoders will use a link bpp lower than pipe bpp in case
> + * of DSC compression.
> + *
> + * Returns %true in case of success, %false if pipe bpp would need to be
> + * reduced below its valid range.
> + */
> +bool intel_atomic_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
> +{
> + int pipe_bpp = min(crtc_state->pipe_bpp,
> + to_bpp_int(crtc_state->max_link_bpp_x16));
> +
> + pipe_bpp = rounddown(pipe_bpp, 2 * 3);
> +
> + if (pipe_bpp < 6 * 3)
> + return false;
> +
> + crtc_state->pipe_bpp = pipe_bpp;
> +
> + return true;
> +}
> +
> +/**
> + * intel_atomic_reduce_link_bpp - reduce maximum link bpp for a selected pipe
> + * @state: atomic state
> + * @limits: link BW limits
> + * @pipe_mask: mask of pipes to select from
> + * @reason: explanation of why bpp reduction is needed
> + *
> + * Select the pipe from @pipe_mask with the biggest link bpp value and set the
> + * maximum of link bpp in @limits below this value. Modeset the selected pipe,
> + * so that its state will get recomputed.
> + *
> + * This function can be called to resolve a link's BW overallocation by reducing
> + * the link bpp of one pipe on the link and hence reducing the total link BW.
> + *
> + * Returns
> + * - 0 in case of success
> + * - %-EINVAL if no pipe can further reduce its link bpp
> + * - Other negative error, if modesetting the selected pipe failed
> + */
> +int intel_atomic_reduce_link_bpp(struct intel_atomic_state *state,
> + struct intel_link_bw_limits *limits,
> + u8 pipe_mask,
> + const char *reason)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + enum pipe max_bpp_pipe = INVALID_PIPE;
> + struct intel_crtc *crtc;
> + int max_bpp = 0;
> +
> + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
> + struct intel_crtc_state *crtc_state;
> + int pipe_bpp;
> +
> + if (limits->min_bpp_pipes & BIT(crtc->pipe))
> + continue;
> +
> + crtc_state = intel_atomic_get_crtc_state(&state->base,
> + crtc);
> + if (IS_ERR(crtc_state))
> + return PTR_ERR(crtc_state);
> +
> + if (crtc_state->dsc.compression_enable)
> + pipe_bpp = crtc_state->dsc.compressed_bpp;
> + else
> + pipe_bpp = crtc_state->pipe_bpp;
> +
> + if (pipe_bpp > max_bpp) {
> + max_bpp = pipe_bpp;
> + max_bpp_pipe = crtc->pipe;
> + }
> + }
> +
> + if (max_bpp_pipe == INVALID_PIPE)
> + return -EINVAL;
> +
> + limits->max_bpp_x16[max_bpp_pipe] = to_bpp_x16(max_bpp) - 1;
> +
> + return intel_modeset_pipes_in_mask(state, reason,
> + BIT(max_bpp_pipe), false);
> +}
> +
> +static int intel_atomic_check_link(struct intel_atomic_state *state,
> + struct intel_link_bw_limits *limits)
> +{
> + int ret;
> +
> + ret = intel_fdi_atomic_check_link(state, limits);
> + if (ret)
> + return ret;
> +
> + return 0;
> +}
> +
> +static bool
> +assert_link_limit_change_valid(struct drm_i915_private *i915,
> + const struct intel_link_bw_limits *old_limits,
> + const struct intel_link_bw_limits *new_limits)
> +{
> + bool bpps_changed = false;
> + enum pipe pipe;
> +
> + for_each_pipe(i915, pipe) {
> + /* The bpp limit can only decrease. */
> + if (drm_WARN_ON(&i915->drm,
> + new_limits->max_bpp_x16[pipe] >
> + old_limits->max_bpp_x16[pipe]))
> + return false;
> +
> + if (new_limits->max_bpp_x16[pipe] <
> + old_limits->max_bpp_x16[pipe])
> + bpps_changed = true;
> + }
> +
> + if (drm_WARN_ON(&i915->drm,
> + !bpps_changed))
> + return false;
> +
> + return true;
> +}
> +
> +static bool
> +reset_link_bpp_limit_to_min(struct intel_atomic_state *state,
> + const struct intel_link_bw_limits *old_limits,
> + struct intel_link_bw_limits *new_limits,
> + enum pipe failed_pipe)
> +{
> + if (failed_pipe == INVALID_PIPE)
> + return false;
> +
> + if (new_limits->min_bpp_pipes & BIT(failed_pipe))
> + return false;
> +
> + if (new_limits->max_bpp_x16[failed_pipe] ==
> + old_limits->max_bpp_x16[failed_pipe])
> + return false;
> +
> + new_limits->max_bpp_x16[failed_pipe] =
> + old_limits->max_bpp_x16[failed_pipe];
> + new_limits->min_bpp_pipes |= BIT(failed_pipe);
> +
> + return true;
> +}
> +
> +/**
> + * intel_atomic_check_config_and_link - compute CRTC configs, resolving any BW limits
> + * @state: atomic state
> + *
> + * Compute the configuration of all CRTCs in @state and resolve any BW
> + * limitations on links shared by these CRTCs.
> + *
> + * Return 0 in case of success, or a negative error code otherwise.
> + */
> +int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_link_bw_limits new_limits = {};
> + struct intel_link_bw_limits old_limits;
> + enum pipe pipe;
> + int ret;
> +
> + for_each_pipe(i915, pipe)
> + new_limits.max_bpp_x16[pipe] = INT_MAX;
> +
> + old_limits = new_limits;
> +
> + while (true) {
> + enum pipe failed_pipe;
> +
> + ret = intel_atomic_check_config(state, &new_limits,
> + &failed_pipe);
> + if (ret) {
> + if (ret == -EINVAL &&
> + reset_link_bpp_limit_to_min(state,
> + &old_limits,
> + &new_limits,
> + failed_pipe))
> + continue;
> +
> + break;
> + }
> +
> + old_limits = new_limits;
> +
> + ret = intel_atomic_check_link(state, &new_limits);
> + if (ret != -EAGAIN)
> + break;
> +
> + if (!assert_link_limit_change_valid(i915,
> + &old_limits,
> + &new_limits)) {
> + ret = -EINVAL;
> + break;
> + }
> + }
> +
> + return ret;
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> index e506f6a873447..bbf3595d52c41 100644
> --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> @@ -20,6 +20,7 @@ struct intel_atomic_state;
> struct intel_connector;
> struct intel_crtc;
> struct intel_crtc_state;
> +struct intel_link_bw_limits;
>
> int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
> const struct drm_connector_state *state,
> @@ -52,4 +53,11 @@ struct intel_crtc_state *
> intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> struct intel_crtc *crtc);
>
> +int intel_atomic_reduce_link_bpp(struct intel_atomic_state *state,
> + struct intel_link_bw_limits *limits,
> + u8 pipe_mask,
> + const char *reason);
> +bool intel_atomic_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
> +int intel_atomic_check_config_and_link(struct intel_atomic_state *state);
> +
> #endif /* __INTEL_ATOMIC_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> index f66340b4caf0f..3322080a574e8 100644
> --- a/drivers/gpu/drm/i915/display/intel_crt.c
> +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> @@ -36,6 +36,7 @@
> #include "i915_drv.h"
> #include "i915_irq.h"
> #include "i915_reg.h"
> +#include "intel_atomic.h"
> #include "intel_connector.h"
> #include "intel_crt.h"
> #include "intel_crtc.h"
> @@ -413,6 +414,9 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
> return -EINVAL;
>
> pipe_config->has_pch_encoder = true;
> + if (!intel_atomic_compute_pipe_bpp(pipe_config))
> + return -EINVAL;
> +
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> return 0;
> @@ -435,6 +439,9 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
> return -EINVAL;
>
> pipe_config->has_pch_encoder = true;
> + if (!intel_atomic_compute_pipe_bpp(pipe_config))
> + return -EINVAL;
> +
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> /* LPT FDI RX only supports 8bpc. */
> diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> index 182c6dd64f47c..1eda6a9f19aa8 100644
> --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> @@ -175,6 +175,7 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
> crtc_state->hsw_workaround_pipe = INVALID_PIPE;
> crtc_state->scaler_state.scaler_id = -1;
> crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
> + crtc_state->max_link_bpp_x16 = INT_MAX;
> }
>
> static struct intel_crtc *intel_crtc_alloc(void)
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> index dbf109a2e738f..32778bd01bb05 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -4641,7 +4641,8 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
>
> static int
> intel_modeset_pipe_config(struct intel_atomic_state *state,
> - struct intel_crtc *crtc)
> + struct intel_crtc *crtc,
> + const struct intel_link_bw_limits *limits)
> {
> struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> struct intel_crtc_state *crtc_state =
> @@ -4650,7 +4651,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> struct drm_connector_state *connector_state;
> int pipe_src_w, pipe_src_h;
> int base_bpp, ret, i;
> - bool retry = true;
>
> crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
>
> @@ -4673,6 +4673,17 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> if (ret)
> return ret;
>
> + crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
> +
> + if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
> + drm_dbg_kms(&i915->drm,
> + "[CRTC:%d:%s] Link bpp limited to %d.%04d\n",
> + crtc->base.base.id, crtc->base.name,
> + to_bpp_int(crtc_state->max_link_bpp_x16),
> + to_bpp_frac_dec(crtc_state->max_link_bpp_x16));
> + crtc_state->bw_constrained = true;
> + }
> +
> base_bpp = crtc_state->pipe_bpp;
>
> /*
> @@ -4714,7 +4725,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> crtc_state->output_types |= BIT(encoder->type);
> }
>
> -encoder_retry:
> /* Ensure the port clock defaults are reset when retrying. */
> crtc_state->port_clock = 0;
> crtc_state->pixel_multiplier = 1;
> @@ -4754,17 +4764,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> ret = intel_crtc_compute_config(state, crtc);
> if (ret == -EDEADLK)
> return ret;
> - if (ret == -EAGAIN) {
> - if (drm_WARN(&i915->drm, !retry,
> - "[CRTC:%d:%s] loop in pipe configuration computation\n",
> - crtc->base.base.id, crtc->base.name))
> - return -EINVAL;
> -
> - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
> - crtc->base.base.id, crtc->base.name);
> - retry = false;
> - goto encoder_retry;
> - }
> if (ret < 0) {
> drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
> crtc->base.base.id, crtc->base.name, ret);
> @@ -6206,7 +6205,9 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
> return 0;
> }
>
> -static int intel_atomic_check_config(struct intel_atomic_state *state)
> +int intel_atomic_check_config(struct intel_atomic_state *state,
> + struct intel_link_bw_limits *limits,
> + enum pipe *failed_pipe)
> {
> struct drm_i915_private *i915 = to_i915(state->base.dev);
> struct intel_crtc_state *new_crtc_state;
> @@ -6214,10 +6215,16 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
> int ret;
> int i;
>
> + *failed_pipe = INVALID_PIPE;
> +
> ret = intel_bigjoiner_add_affected_crtcs(state);
> if (ret)
> return ret;
>
> + ret = intel_fdi_add_affected_crtcs(state);
> + if (ret)
> + return ret;
> +
> for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> if (!intel_crtc_needs_modeset(new_crtc_state)) {
> if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> @@ -6239,7 +6246,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
> if (!new_crtc_state->hw.enable)
> continue;
>
> - ret = intel_modeset_pipe_config(state, crtc);
> + ret = intel_modeset_pipe_config(state, crtc, limits);
> if (ret)
> break;
>
> @@ -6248,6 +6255,9 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
> break;
> }
>
> + if (ret)
> + *failed_pipe = crtc->pipe;
> +
> return ret;
> }
>
> @@ -6295,7 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
> return ret;
> }
>
> - ret = intel_atomic_check_config(state);
> + ret = intel_atomic_check_config_and_link(state);
> if (ret)
> goto fail;
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> index d9a54610d9d5e..2e0535739bd70 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.h
> +++ b/drivers/gpu/drm/i915/display/intel_display.h
> @@ -55,6 +55,7 @@ struct intel_digital_port;
> struct intel_dp;
> struct intel_encoder;
> struct intel_initial_plane_config;
> +struct intel_link_bw_limits;
> struct intel_link_m_n;
> struct intel_plane;
> struct intel_plane_state;
> @@ -391,6 +392,9 @@ enum phy_fia {
> (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
>
> int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
> +int intel_atomic_check_config(struct intel_atomic_state *state,
> + struct intel_link_bw_limits *limits,
> + enum pipe *failed_pipe);
> int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
> u8 intel_calc_active_pipes(struct intel_atomic_state *state,
> diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> index b143085b399eb..6f4f46658df22 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> @@ -66,6 +66,12 @@ struct intel_tc_port;
> * Display related stuff
> */
>
> +struct intel_link_bw_limits {
> + u8 min_bpp_pipes;
> + /* in 1/16 bpp units */
> + int max_bpp_x16[I915_MAX_PIPES];
> +};
> +
> /* these are outputs from the chip - integrated only
> external chips are via DVO or SDVO output */
> enum intel_output_type {
> @@ -1189,7 +1195,8 @@ struct intel_crtc_state {
> u32 ctrl, div;
> } dsi_pll;
>
> - int pipe_bpp;
> + int max_link_bpp_x16; /* in 1/16 bpp units */
> + int pipe_bpp; /* in 1 bpp units */
> struct intel_link_m_n dp_m_n;
>
> /* m2_n2 for eDP downclock */
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 6637bd4768bf7..48f005932ad8b 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2218,7 +2218,8 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> int max_link_bpp_x16;
>
> - max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> + max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
> + to_bpp_x16(limits->pipe.max_bpp));
>
> if (!dsc) {
> max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> index e12b46a84fa11..123ba67f68791 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> @@ -119,6 +119,59 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
> dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
> }
>
> +/**
> + * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs
> + * @state: intel atomic state
> + *
> + * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is
> + * known to affect the available FDI BW for the former CRTC. In practice this
> + * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by
> + * CRTC C) and CRTC C is getting disabled.
> + *
> + * Returns 0 in case of success, or a negative error code otherwise.
> + */
> +int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state)
> +{
> + struct drm_i915_private *i915 = to_i915(state->base.dev);
> + struct intel_crtc_state *old_crtc_state;
> + struct intel_crtc_state *new_crtc_state;
> + struct intel_crtc *crtc;
> +
> + if (!IS_IVYBRIDGE(i915))
> + return 0;
> +
> + crtc = intel_crtc_for_pipe(i915, PIPE_C);
> + new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +
> + if (!new_crtc_state)
> + return 0;
> +
> + old_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> +
> + if (!old_crtc_state->fdi_lanes)
> + return 0;
> +
> + if (!intel_crtc_needs_modeset(new_crtc_state))
> + return 0;
> +
> + if (new_crtc_state->uapi.enable)
> + return 0;
> +
> + crtc = intel_crtc_for_pipe(i915, PIPE_B);
> + new_crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> +
> + if (IS_ERR(new_crtc_state))
> + return PTR_ERR(old_crtc_state);
> +
> + old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> + if (!old_crtc_state->fdi_lanes)
> + return 0;
> +
> + return intel_modeset_pipes_in_mask(state,
> + "FDI link BW decrease on pipe C",
> + BIT(PIPE_B), false);
> +}
> +
> /* units of 100MHz */
> static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
> {
> @@ -129,13 +182,16 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
> }
>
> static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> - struct intel_crtc_state *pipe_config)
> + struct intel_crtc_state *pipe_config,
> + enum pipe *pipe_to_reduce)
> {
> struct drm_i915_private *dev_priv = to_i915(dev);
> struct drm_atomic_state *state = pipe_config->uapi.state;
> struct intel_crtc *other_crtc;
> struct intel_crtc_state *other_crtc_state;
>
> + *pipe_to_reduce = pipe;
> +
> drm_dbg_kms(&dev_priv->drm,
> "checking fdi config on pipe %c, lanes %i\n",
> pipe_name(pipe), pipe_config->fdi_lanes);
> @@ -198,6 +254,9 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
> drm_dbg_kms(&dev_priv->drm,
> "fdi link B uses too many lanes to enable link C\n");
> +
> + *pipe_to_reduce = PIPE_B;
> +
> return -EINVAL;
> }
> return 0;
> @@ -238,10 +297,8 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
> struct drm_device *dev = crtc->base.dev;
> struct drm_i915_private *i915 = to_i915(dev);
> const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> - int lane, link_bw, fdi_dotclock, ret;
> - bool needs_recompute = false;
> + int lane, link_bw, fdi_dotclock;
>
> -retry:
> /* FDI is a binary signal running at ~2.7GHz, encoding
> * each output octet as 10 bits. The actual frequency
> * is stored as a divider into a 100MHz clock, and the
> @@ -261,25 +318,69 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
> intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> link_bw, &pipe_config->fdi_m_n, false);
>
> - ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
> - if (ret == -EDEADLK)
> + return 0;
> +}
> +
> +static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state,
> + struct intel_crtc *crtc,
> + struct intel_crtc_state *pipe_config,
> + struct intel_link_bw_limits *limits)
> +{
> + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> + enum pipe pipe_to_reduce;
> + int ret;
> +
> + ret = ilk_check_fdi_lanes(&i915->drm, crtc->pipe, pipe_config,
> + &pipe_to_reduce);
> + if (ret != -EINVAL)
> return ret;
>
> - if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
> - pipe_config->pipe_bpp -= 2*3;
> - drm_dbg_kms(&i915->drm,
> - "fdi link bw constraint, reducing pipe bpp to %i\n",
> - pipe_config->pipe_bpp);
> - needs_recompute = true;
> - pipe_config->bw_constrained = true;
> + ret = intel_atomic_reduce_link_bpp(state, limits,
> + BIT(pipe_to_reduce),
> + "FDI link BW");
>
> - goto retry;
> - }
> + return ret ? : -EAGAIN;
> +}
>
> - if (needs_recompute)
> - return -EAGAIN;
> +/**
> + * intel_fdi_atomic_check_link - check all modeset FDI link configuration
> + * @state: intel atomic state
> + * @limits: link BW limits
> + *
> + * Check the link configuration for all modeset FDI outputs. If the
> + * configuration is invalid @limits will be updated if possible to
> + * reduce the total BW, after which the configuration for all CRTCs in
> + * @state must be recomputed with the updated @limits.
> + *
> + * Returns:
> + * - 0 if the confugration is valid
> + * - %-EAGAIN, if the configuration is invalid and @limits got updated
> + * with fallback values with which the configuration of all CRTCs
> + * in @state must be recomputed
> + * - Other negative error, if the configuration is invalid without a
> + * fallback possibility, or the check failed for another reason
> + */
> +int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
> + struct intel_link_bw_limits *limits)
> +{
> + struct intel_crtc *crtc;
> + struct intel_crtc_state *crtc_state;
> + int i;
> +
> + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> + int ret;
>
> - return ret;
> + if (!crtc_state->has_pch_encoder ||
> + !intel_crtc_needs_modeset(crtc_state) ||
> + !crtc_state->hw.enable)
> + continue;
> +
> + ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);
> + if (ret)
> + return ret;
> + }
> +
> + return 0;
> }
>
> static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
> diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
> index 1cdb86172702f..eb02b967bb440 100644
> --- a/drivers/gpu/drm/i915/display/intel_fdi.h
> +++ b/drivers/gpu/drm/i915/display/intel_fdi.h
> @@ -8,14 +8,19 @@
>
> enum pipe;
> struct drm_i915_private;
> +struct intel_atomic_state;
> struct intel_crtc;
> struct intel_crtc_state;
> struct intel_encoder;
> +struct intel_link_bw_limits;
>
> +int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state);
> int intel_fdi_link_freq(struct drm_i915_private *i915,
> const struct intel_crtc_state *pipe_config);
> int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
> struct intel_crtc_state *pipe_config);
> +int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
> + struct intel_link_bw_limits *limits);
> void intel_fdi_normal_train(struct intel_crtc *crtc);
> void ilk_fdi_disable(struct intel_crtc *crtc);
> void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc);
> diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> index 3ace56979b70e..08dcc2d10a2c1 100644
> --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> @@ -425,6 +425,12 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
> return -EINVAL;
> }
>
> + if (HAS_PCH_SPLIT(i915)) {
> + crtc_state->has_pch_encoder = true;
> + if (!intel_atomic_compute_pipe_bpp(crtc_state))
> + return -EINVAL;
> + }
> +
> if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
> lvds_bpp = 8*3;
> else
> @@ -453,9 +459,6 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
> if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> return -EINVAL;
>
> - if (HAS_PCH_SPLIT(i915))
> - crtc_state->has_pch_encoder = true;
> -
> ret = intel_panel_fitting(crtc_state, conn_state);
> if (ret)
> return ret;
> diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
> index 7d25a64698e2f..1c6330151f4d6 100644
> --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> @@ -1352,14 +1352,17 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
> struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> struct drm_display_mode *mode = &pipe_config->hw.mode;
>
> + if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
> + pipe_config->has_pch_encoder = true;
> + if (!intel_atomic_compute_pipe_bpp(pipe_config))
> + return -EINVAL;
> + }
> +
> DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
> pipe_config->pipe_bpp = 8*3;
> pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
>
> - if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
> - pipe_config->has_pch_encoder = true;
> -
> /*
> * We need to construct preferred input timings based on our
> * output timings. To do that, we have to set the output
> --
> 2.37.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 08/22] drm/i915/fdi: Improve FDI BW sharing between pipe B and C
2023-09-11 18:59 ` Ville Syrjälä
@ 2023-09-11 20:42 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-09-11 20:42 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx
On Mon, Sep 11, 2023 at 09:59:34PM +0300, Ville Syrjälä wrote:
> On Thu, Aug 24, 2023 at 11:05:03AM +0300, Imre Deak wrote:
> > At the moment modesetting pipe C on IVB will fail if pipe B uses 4 FDI
> > lanes. Make the BW sharing more dynamic by trying to reduce pipe B's
> > link bpp in this case, until pipe B uses only up to 2 FDI lanes.
> >
> > For this instead of the encoder compute config retry loop - which
> > reduced link bpp only for the encoder's pipe - check the overall BW
> > limits after all CRTC states have been computed and if the check fails
> > reduce the maximum link bpp for a selected pipe (for FDI pipe B or C as
> > required) and recompute all the CRTC states. Retry this sequence until
> > either the overall BW limit check passes, or further bpp reduction is
> > not possible (because all pipes/encoders sharing the link BW reached
> > their minimum link bpp).
> >
> > This change also prepares for an upcoming patch resolving BW limits in
> > a similar way on MST links as well.
> >
> > v2:
> > - Rename intel_crtc_state::max_link_bpp to max_link_bpp_x16 and
> > intel_link_bw_limits::max_bpp to max_bpp_x16. (Jani)
> > - Increase back pipe B's link bpp if earlier it was limited due to
> > pipe C and pipe C gets later disabled.
> > - Don't assume that a CRTC is already in the atomic state, while
> > reducing its link bpp.
> > - Add DocBook description to intel_fdi_atomic_check_link().
> >
> > Cc: Jani Nikula <jani.nikula@linux.intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/g4x_hdmi.c | 5 +-
> > drivers/gpu/drm/i915/display/intel_atomic.c | 207 ++++++++++++++++++
> > drivers/gpu/drm/i915/display/intel_atomic.h | 8 +
> > drivers/gpu/drm/i915/display/intel_crt.c | 7 +
> > drivers/gpu/drm/i915/display/intel_crtc.c | 1 +
> > drivers/gpu/drm/i915/display/intel_display.c | 44 ++--
> > drivers/gpu/drm/i915/display/intel_display.h | 4 +
> > .../drm/i915/display/intel_display_types.h | 9 +-
> > drivers/gpu/drm/i915/display/intel_dp.c | 3 +-
> > drivers/gpu/drm/i915/display/intel_fdi.c | 137 ++++++++++--
> > drivers/gpu/drm/i915/display/intel_fdi.h | 5 +
> > drivers/gpu/drm/i915/display/intel_lvds.c | 9 +-
> > drivers/gpu/drm/i915/display/intel_sdvo.c | 9 +-
> > 13 files changed, 404 insertions(+), 44 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> > index 634b14116d9dd..ebbceddc13259 100644
> > --- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
> > +++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
> > @@ -133,8 +133,11 @@ static int g4x_hdmi_compute_config(struct intel_encoder *encoder,
> > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
> > struct drm_i915_private *i915 = to_i915(encoder->base.dev);
> >
> > - if (HAS_PCH_SPLIT(i915))
> > + if (HAS_PCH_SPLIT(i915)) {
> > crtc_state->has_pch_encoder = true;
> > + if (!intel_atomic_compute_pipe_bpp(crtc_state))
> > + return -EINVAL;
> > + }
> >
> > if (IS_G4X(i915))
> > crtc_state->has_hdmi_sink = g4x_compute_has_hdmi_sink(state, crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
> > index 7cf51dd8c0567..ee4cbf80ddb55 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.c
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.c
>
> Not convinced we should put anything there. I think I mostly managed to
> move a bunch or semi-random stuff out now, so all it more or less has is
> the struct intel_atomic_state alloc/free stuff.
>
> You have intel_atomic_check() in intel_display.c and the lower level
> intel_atomic_check_config() is also there, but now the middle man
> intel_atomic_check_config_and_link() ended up in intel_atomic.c for
> whatever reason. I'd just shove all of it into intel_display.c.
I didn't want to add more stuff to intel_display.c, but yes
intel_atomic.c is not the best place for these. How about moving the
link BW config/check functions instead to intel_link_bw.c as in
https://github.com/ideak/linux/commit/9fd9d456da53 ?
> The patch is also rather massive.
I thought it's easier to understand if new function definitions / their
use is in one patch, but I guess here the amount of changes vs. just
additions makes it less clear.
> Can we try to chunk it up to eg. something like:
> 1) add the new infrastructure
> 2) convert the fdi retry stuff to use the new infrastructure
> 3) add intel_fdi_add_affected_crtcs() (which seems more or less
> independent from the rest of the fdi conversion?)
Yes, 3) can be regarded as an additional functionality.
> ?
Ok, will split the changes based on the above points.
> > @@ -38,6 +38,7 @@
> > #include "intel_atomic.h"
> > #include "intel_cdclk.h"
> > #include "intel_display_types.h"
> > +#include "intel_fdi.h"
> > #include "intel_global_state.h"
> > #include "intel_hdcp.h"
> > #include "intel_psr.h"
> > @@ -358,3 +359,209 @@ intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> >
> > return to_intel_crtc_state(crtc_state);
> > }
> > +
> > +/**
> > + * intel_atomic_compute_pipe_bpp - compute pipe bpp limited by max link bpp
> > + * @crtc_state: the crtc state
> > + *
> > + * Compute the pipe bpp limited by the CRTC's maximum link bpp. Encoders can
> > + * call this function during state computation in the simple case where the
> > + * link bpp will always match the pipe bpp. This is the case for all non-DP
> > + * encoders, while DP encoders will use a link bpp lower than pipe bpp in case
> > + * of DSC compression.
> > + *
> > + * Returns %true in case of success, %false if pipe bpp would need to be
> > + * reduced below its valid range.
> > + */
> > +bool intel_atomic_compute_pipe_bpp(struct intel_crtc_state *crtc_state)
> > +{
> > + int pipe_bpp = min(crtc_state->pipe_bpp,
> > + to_bpp_int(crtc_state->max_link_bpp_x16));
> > +
> > + pipe_bpp = rounddown(pipe_bpp, 2 * 3);
> > +
> > + if (pipe_bpp < 6 * 3)
> > + return false;
> > +
> > + crtc_state->pipe_bpp = pipe_bpp;
> > +
> > + return true;
> > +}
> > +
> > +/**
> > + * intel_atomic_reduce_link_bpp - reduce maximum link bpp for a selected pipe
> > + * @state: atomic state
> > + * @limits: link BW limits
> > + * @pipe_mask: mask of pipes to select from
> > + * @reason: explanation of why bpp reduction is needed
> > + *
> > + * Select the pipe from @pipe_mask with the biggest link bpp value and set the
> > + * maximum of link bpp in @limits below this value. Modeset the selected pipe,
> > + * so that its state will get recomputed.
> > + *
> > + * This function can be called to resolve a link's BW overallocation by reducing
> > + * the link bpp of one pipe on the link and hence reducing the total link BW.
> > + *
> > + * Returns
> > + * - 0 in case of success
> > + * - %-EINVAL if no pipe can further reduce its link bpp
> > + * - Other negative error, if modesetting the selected pipe failed
> > + */
> > +int intel_atomic_reduce_link_bpp(struct intel_atomic_state *state,
> > + struct intel_link_bw_limits *limits,
> > + u8 pipe_mask,
> > + const char *reason)
> > +{
> > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > + enum pipe max_bpp_pipe = INVALID_PIPE;
> > + struct intel_crtc *crtc;
> > + int max_bpp = 0;
> > +
> > + for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, pipe_mask) {
> > + struct intel_crtc_state *crtc_state;
> > + int pipe_bpp;
> > +
> > + if (limits->min_bpp_pipes & BIT(crtc->pipe))
> > + continue;
> > +
> > + crtc_state = intel_atomic_get_crtc_state(&state->base,
> > + crtc);
> > + if (IS_ERR(crtc_state))
> > + return PTR_ERR(crtc_state);
> > +
> > + if (crtc_state->dsc.compression_enable)
> > + pipe_bpp = crtc_state->dsc.compressed_bpp;
> > + else
> > + pipe_bpp = crtc_state->pipe_bpp;
> > +
> > + if (pipe_bpp > max_bpp) {
> > + max_bpp = pipe_bpp;
> > + max_bpp_pipe = crtc->pipe;
> > + }
> > + }
> > +
> > + if (max_bpp_pipe == INVALID_PIPE)
> > + return -EINVAL;
> > +
> > + limits->max_bpp_x16[max_bpp_pipe] = to_bpp_x16(max_bpp) - 1;
> > +
> > + return intel_modeset_pipes_in_mask(state, reason,
> > + BIT(max_bpp_pipe), false);
> > +}
> > +
> > +static int intel_atomic_check_link(struct intel_atomic_state *state,
> > + struct intel_link_bw_limits *limits)
> > +{
> > + int ret;
> > +
> > + ret = intel_fdi_atomic_check_link(state, limits);
> > + if (ret)
> > + return ret;
> > +
> > + return 0;
> > +}
> > +
> > +static bool
> > +assert_link_limit_change_valid(struct drm_i915_private *i915,
> > + const struct intel_link_bw_limits *old_limits,
> > + const struct intel_link_bw_limits *new_limits)
> > +{
> > + bool bpps_changed = false;
> > + enum pipe pipe;
> > +
> > + for_each_pipe(i915, pipe) {
> > + /* The bpp limit can only decrease. */
> > + if (drm_WARN_ON(&i915->drm,
> > + new_limits->max_bpp_x16[pipe] >
> > + old_limits->max_bpp_x16[pipe]))
> > + return false;
> > +
> > + if (new_limits->max_bpp_x16[pipe] <
> > + old_limits->max_bpp_x16[pipe])
> > + bpps_changed = true;
> > + }
> > +
> > + if (drm_WARN_ON(&i915->drm,
> > + !bpps_changed))
> > + return false;
> > +
> > + return true;
> > +}
> > +
> > +static bool
> > +reset_link_bpp_limit_to_min(struct intel_atomic_state *state,
> > + const struct intel_link_bw_limits *old_limits,
> > + struct intel_link_bw_limits *new_limits,
> > + enum pipe failed_pipe)
> > +{
> > + if (failed_pipe == INVALID_PIPE)
> > + return false;
> > +
> > + if (new_limits->min_bpp_pipes & BIT(failed_pipe))
> > + return false;
> > +
> > + if (new_limits->max_bpp_x16[failed_pipe] ==
> > + old_limits->max_bpp_x16[failed_pipe])
> > + return false;
> > +
> > + new_limits->max_bpp_x16[failed_pipe] =
> > + old_limits->max_bpp_x16[failed_pipe];
> > + new_limits->min_bpp_pipes |= BIT(failed_pipe);
> > +
> > + return true;
> > +}
> > +
> > +/**
> > + * intel_atomic_check_config_and_link - compute CRTC configs, resolving any BW limits
> > + * @state: atomic state
> > + *
> > + * Compute the configuration of all CRTCs in @state and resolve any BW
> > + * limitations on links shared by these CRTCs.
> > + *
> > + * Return 0 in case of success, or a negative error code otherwise.
> > + */
> > +int intel_atomic_check_config_and_link(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > + struct intel_link_bw_limits new_limits = {};
> > + struct intel_link_bw_limits old_limits;
> > + enum pipe pipe;
> > + int ret;
> > +
> > + for_each_pipe(i915, pipe)
> > + new_limits.max_bpp_x16[pipe] = INT_MAX;
> > +
> > + old_limits = new_limits;
> > +
> > + while (true) {
> > + enum pipe failed_pipe;
> > +
> > + ret = intel_atomic_check_config(state, &new_limits,
> > + &failed_pipe);
> > + if (ret) {
> > + if (ret == -EINVAL &&
> > + reset_link_bpp_limit_to_min(state,
> > + &old_limits,
> > + &new_limits,
> > + failed_pipe))
> > + continue;
> > +
> > + break;
> > + }
> > +
> > + old_limits = new_limits;
> > +
> > + ret = intel_atomic_check_link(state, &new_limits);
> > + if (ret != -EAGAIN)
> > + break;
> > +
> > + if (!assert_link_limit_change_valid(i915,
> > + &old_limits,
> > + &new_limits)) {
> > + ret = -EINVAL;
> > + break;
> > + }
> > + }
> > +
> > + return ret;
> > +}
> > diff --git a/drivers/gpu/drm/i915/display/intel_atomic.h b/drivers/gpu/drm/i915/display/intel_atomic.h
> > index e506f6a873447..bbf3595d52c41 100644
> > --- a/drivers/gpu/drm/i915/display/intel_atomic.h
> > +++ b/drivers/gpu/drm/i915/display/intel_atomic.h
> > @@ -20,6 +20,7 @@ struct intel_atomic_state;
> > struct intel_connector;
> > struct intel_crtc;
> > struct intel_crtc_state;
> > +struct intel_link_bw_limits;
> >
> > int intel_digital_connector_atomic_get_property(struct drm_connector *connector,
> > const struct drm_connector_state *state,
> > @@ -52,4 +53,11 @@ struct intel_crtc_state *
> > intel_atomic_get_crtc_state(struct drm_atomic_state *state,
> > struct intel_crtc *crtc);
> >
> > +int intel_atomic_reduce_link_bpp(struct intel_atomic_state *state,
> > + struct intel_link_bw_limits *limits,
> > + u8 pipe_mask,
> > + const char *reason);
> > +bool intel_atomic_compute_pipe_bpp(struct intel_crtc_state *crtc_state);
> > +int intel_atomic_check_config_and_link(struct intel_atomic_state *state);
> > +
> > #endif /* __INTEL_ATOMIC_H__ */
> > diff --git a/drivers/gpu/drm/i915/display/intel_crt.c b/drivers/gpu/drm/i915/display/intel_crt.c
> > index f66340b4caf0f..3322080a574e8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crt.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crt.c
> > @@ -36,6 +36,7 @@
> > #include "i915_drv.h"
> > #include "i915_irq.h"
> > #include "i915_reg.h"
> > +#include "intel_atomic.h"
> > #include "intel_connector.h"
> > #include "intel_crt.h"
> > #include "intel_crtc.h"
> > @@ -413,6 +414,9 @@ static int pch_crt_compute_config(struct intel_encoder *encoder,
> > return -EINVAL;
> >
> > pipe_config->has_pch_encoder = true;
> > + if (!intel_atomic_compute_pipe_bpp(pipe_config))
> > + return -EINVAL;
> > +
> > pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> >
> > return 0;
> > @@ -435,6 +439,9 @@ static int hsw_crt_compute_config(struct intel_encoder *encoder,
> > return -EINVAL;
> >
> > pipe_config->has_pch_encoder = true;
> > + if (!intel_atomic_compute_pipe_bpp(pipe_config))
> > + return -EINVAL;
> > +
> > pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> >
> > /* LPT FDI RX only supports 8bpc. */
> > diff --git a/drivers/gpu/drm/i915/display/intel_crtc.c b/drivers/gpu/drm/i915/display/intel_crtc.c
> > index 182c6dd64f47c..1eda6a9f19aa8 100644
> > --- a/drivers/gpu/drm/i915/display/intel_crtc.c
> > +++ b/drivers/gpu/drm/i915/display/intel_crtc.c
> > @@ -175,6 +175,7 @@ void intel_crtc_state_reset(struct intel_crtc_state *crtc_state,
> > crtc_state->hsw_workaround_pipe = INVALID_PIPE;
> > crtc_state->scaler_state.scaler_id = -1;
> > crtc_state->mst_master_transcoder = INVALID_TRANSCODER;
> > + crtc_state->max_link_bpp_x16 = INT_MAX;
> > }
> >
> > static struct intel_crtc *intel_crtc_alloc(void)
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
> > index dbf109a2e738f..32778bd01bb05 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -4641,7 +4641,8 @@ intel_crtc_prepare_cleared_state(struct intel_atomic_state *state,
> >
> > static int
> > intel_modeset_pipe_config(struct intel_atomic_state *state,
> > - struct intel_crtc *crtc)
> > + struct intel_crtc *crtc,
> > + const struct intel_link_bw_limits *limits)
> > {
> > struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > struct intel_crtc_state *crtc_state =
> > @@ -4650,7 +4651,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> > struct drm_connector_state *connector_state;
> > int pipe_src_w, pipe_src_h;
> > int base_bpp, ret, i;
> > - bool retry = true;
> >
> > crtc_state->cpu_transcoder = (enum transcoder) crtc->pipe;
> >
> > @@ -4673,6 +4673,17 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> > if (ret)
> > return ret;
> >
> > + crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
> > +
> > + if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
> > + drm_dbg_kms(&i915->drm,
> > + "[CRTC:%d:%s] Link bpp limited to %d.%04d\n",
> > + crtc->base.base.id, crtc->base.name,
> > + to_bpp_int(crtc_state->max_link_bpp_x16),
> > + to_bpp_frac_dec(crtc_state->max_link_bpp_x16));
> > + crtc_state->bw_constrained = true;
> > + }
> > +
> > base_bpp = crtc_state->pipe_bpp;
> >
> > /*
> > @@ -4714,7 +4725,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> > crtc_state->output_types |= BIT(encoder->type);
> > }
> >
> > -encoder_retry:
> > /* Ensure the port clock defaults are reset when retrying. */
> > crtc_state->port_clock = 0;
> > crtc_state->pixel_multiplier = 1;
> > @@ -4754,17 +4764,6 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
> > ret = intel_crtc_compute_config(state, crtc);
> > if (ret == -EDEADLK)
> > return ret;
> > - if (ret == -EAGAIN) {
> > - if (drm_WARN(&i915->drm, !retry,
> > - "[CRTC:%d:%s] loop in pipe configuration computation\n",
> > - crtc->base.base.id, crtc->base.name))
> > - return -EINVAL;
> > -
> > - drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] bw constrained, retrying\n",
> > - crtc->base.base.id, crtc->base.name);
> > - retry = false;
> > - goto encoder_retry;
> > - }
> > if (ret < 0) {
> > drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] config failure: %d\n",
> > crtc->base.base.id, crtc->base.name, ret);
> > @@ -6206,7 +6205,9 @@ static int intel_bigjoiner_add_affected_crtcs(struct intel_atomic_state *state)
> > return 0;
> > }
> >
> > -static int intel_atomic_check_config(struct intel_atomic_state *state)
> > +int intel_atomic_check_config(struct intel_atomic_state *state,
> > + struct intel_link_bw_limits *limits,
> > + enum pipe *failed_pipe)
> > {
> > struct drm_i915_private *i915 = to_i915(state->base.dev);
> > struct intel_crtc_state *new_crtc_state;
> > @@ -6214,10 +6215,16 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
> > int ret;
> > int i;
> >
> > + *failed_pipe = INVALID_PIPE;
> > +
> > ret = intel_bigjoiner_add_affected_crtcs(state);
> > if (ret)
> > return ret;
> >
> > + ret = intel_fdi_add_affected_crtcs(state);
> > + if (ret)
> > + return ret;
> > +
> > for_each_new_intel_crtc_in_state(state, crtc, new_crtc_state, i) {
> > if (!intel_crtc_needs_modeset(new_crtc_state)) {
> > if (intel_crtc_is_bigjoiner_slave(new_crtc_state))
> > @@ -6239,7 +6246,7 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
> > if (!new_crtc_state->hw.enable)
> > continue;
> >
> > - ret = intel_modeset_pipe_config(state, crtc);
> > + ret = intel_modeset_pipe_config(state, crtc, limits);
> > if (ret)
> > break;
> >
> > @@ -6248,6 +6255,9 @@ static int intel_atomic_check_config(struct intel_atomic_state *state)
> > break;
> > }
> >
> > + if (ret)
> > + *failed_pipe = crtc->pipe;
> > +
> > return ret;
> > }
> >
> > @@ -6295,7 +6305,7 @@ int intel_atomic_check(struct drm_device *dev,
> > return ret;
> > }
> >
> > - ret = intel_atomic_check_config(state);
> > + ret = intel_atomic_check_config_and_link(state);
> > if (ret)
> > goto fail;
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
> > index d9a54610d9d5e..2e0535739bd70 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display.h
> > @@ -55,6 +55,7 @@ struct intel_digital_port;
> > struct intel_dp;
> > struct intel_encoder;
> > struct intel_initial_plane_config;
> > +struct intel_link_bw_limits;
> > struct intel_link_m_n;
> > struct intel_plane;
> > struct intel_plane_state;
> > @@ -391,6 +392,9 @@ enum phy_fia {
> > (new_connector_state) = to_intel_digital_connector_state((__state)->base.connectors[__i].new_state), 1))
> >
> > int intel_atomic_check(struct drm_device *dev, struct drm_atomic_state *state);
> > +int intel_atomic_check_config(struct intel_atomic_state *state,
> > + struct intel_link_bw_limits *limits,
> > + enum pipe *failed_pipe);
> > int intel_atomic_add_affected_planes(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
> > u8 intel_calc_active_pipes(struct intel_atomic_state *state,
> > diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
> > index b143085b399eb..6f4f46658df22 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display_types.h
> > +++ b/drivers/gpu/drm/i915/display/intel_display_types.h
> > @@ -66,6 +66,12 @@ struct intel_tc_port;
> > * Display related stuff
> > */
> >
> > +struct intel_link_bw_limits {
> > + u8 min_bpp_pipes;
> > + /* in 1/16 bpp units */
> > + int max_bpp_x16[I915_MAX_PIPES];
> > +};
> > +
> > /* these are outputs from the chip - integrated only
> > external chips are via DVO or SDVO output */
> > enum intel_output_type {
> > @@ -1189,7 +1195,8 @@ struct intel_crtc_state {
> > u32 ctrl, div;
> > } dsi_pll;
> >
> > - int pipe_bpp;
> > + int max_link_bpp_x16; /* in 1/16 bpp units */
> > + int pipe_bpp; /* in 1 bpp units */
> > struct intel_link_m_n dp_m_n;
> >
> > /* m2_n2 for eDP downclock */
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> > index 6637bd4768bf7..48f005932ad8b 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2218,7 +2218,8 @@ intel_dp_compute_config_link_bpp_limits(struct intel_dp *intel_dp,
> > const struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
> > int max_link_bpp_x16;
> >
> > - max_link_bpp_x16 = to_bpp_x16(limits->pipe.max_bpp);
> > + max_link_bpp_x16 = min(crtc_state->max_link_bpp_x16,
> > + to_bpp_x16(limits->pipe.max_bpp));
> >
> > if (!dsc) {
> > max_link_bpp_x16 = rounddown(max_link_bpp_x16, to_bpp_x16(2 * 3));
> > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.c b/drivers/gpu/drm/i915/display/intel_fdi.c
> > index e12b46a84fa11..123ba67f68791 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fdi.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fdi.c
> > @@ -119,6 +119,59 @@ void intel_fdi_link_train(struct intel_crtc *crtc,
> > dev_priv->display.funcs.fdi->fdi_link_train(crtc, crtc_state);
> > }
> >
> > +/**
> > + * intel_fdi_add_affected_crtcs - add CRTCs on FDI affected by other modeset CRTCs
> > + * @state: intel atomic state
> > + *
> > + * Add a CRTC using FDI to @state if changing another CRTC's FDI BW usage is
> > + * known to affect the available FDI BW for the former CRTC. In practice this
> > + * means adding CRTC B on IVYBRIDGE if its use of FDI lanes is limited (by
> > + * CRTC C) and CRTC C is getting disabled.
> > + *
> > + * Returns 0 in case of success, or a negative error code otherwise.
> > + */
> > +int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state)
> > +{
> > + struct drm_i915_private *i915 = to_i915(state->base.dev);
> > + struct intel_crtc_state *old_crtc_state;
> > + struct intel_crtc_state *new_crtc_state;
> > + struct intel_crtc *crtc;
> > +
> > + if (!IS_IVYBRIDGE(i915))
> > + return 0;
> > +
> > + crtc = intel_crtc_for_pipe(i915, PIPE_C);
> > + new_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > +
> > + if (!new_crtc_state)
> > + return 0;
> > +
> > + old_crtc_state = intel_atomic_get_new_crtc_state(state, crtc);
> > +
> > + if (!old_crtc_state->fdi_lanes)
> > + return 0;
> > +
> > + if (!intel_crtc_needs_modeset(new_crtc_state))
> > + return 0;
> > +
> > + if (new_crtc_state->uapi.enable)
> > + return 0;
> > +
> > + crtc = intel_crtc_for_pipe(i915, PIPE_B);
> > + new_crtc_state = intel_atomic_get_crtc_state(&state->base, crtc);
> > +
> > + if (IS_ERR(new_crtc_state))
> > + return PTR_ERR(old_crtc_state);
> > +
> > + old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc);
> > + if (!old_crtc_state->fdi_lanes)
> > + return 0;
> > +
> > + return intel_modeset_pipes_in_mask(state,
> > + "FDI link BW decrease on pipe C",
> > + BIT(PIPE_B), false);
> > +}
> > +
> > /* units of 100MHz */
> > static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
> > {
> > @@ -129,13 +182,16 @@ static int pipe_required_fdi_lanes(struct intel_crtc_state *crtc_state)
> > }
> >
> > static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> > - struct intel_crtc_state *pipe_config)
> > + struct intel_crtc_state *pipe_config,
> > + enum pipe *pipe_to_reduce)
> > {
> > struct drm_i915_private *dev_priv = to_i915(dev);
> > struct drm_atomic_state *state = pipe_config->uapi.state;
> > struct intel_crtc *other_crtc;
> > struct intel_crtc_state *other_crtc_state;
> >
> > + *pipe_to_reduce = pipe;
> > +
> > drm_dbg_kms(&dev_priv->drm,
> > "checking fdi config on pipe %c, lanes %i\n",
> > pipe_name(pipe), pipe_config->fdi_lanes);
> > @@ -198,6 +254,9 @@ static int ilk_check_fdi_lanes(struct drm_device *dev, enum pipe pipe,
> > if (pipe_required_fdi_lanes(other_crtc_state) > 2) {
> > drm_dbg_kms(&dev_priv->drm,
> > "fdi link B uses too many lanes to enable link C\n");
> > +
> > + *pipe_to_reduce = PIPE_B;
> > +
> > return -EINVAL;
> > }
> > return 0;
> > @@ -238,10 +297,8 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
> > struct drm_device *dev = crtc->base.dev;
> > struct drm_i915_private *i915 = to_i915(dev);
> > const struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> > - int lane, link_bw, fdi_dotclock, ret;
> > - bool needs_recompute = false;
> > + int lane, link_bw, fdi_dotclock;
> >
> > -retry:
> > /* FDI is a binary signal running at ~2.7GHz, encoding
> > * each output octet as 10 bits. The actual frequency
> > * is stored as a divider into a 100MHz clock, and the
> > @@ -261,25 +318,69 @@ int ilk_fdi_compute_config(struct intel_crtc *crtc,
> > intel_link_compute_m_n(pipe_config->pipe_bpp, lane, fdi_dotclock,
> > link_bw, &pipe_config->fdi_m_n, false);
> >
> > - ret = ilk_check_fdi_lanes(dev, crtc->pipe, pipe_config);
> > - if (ret == -EDEADLK)
> > + return 0;
> > +}
> > +
> > +static int intel_fdi_atomic_check_bw(struct intel_atomic_state *state,
> > + struct intel_crtc *crtc,
> > + struct intel_crtc_state *pipe_config,
> > + struct intel_link_bw_limits *limits)
> > +{
> > + struct drm_i915_private *i915 = to_i915(crtc->base.dev);
> > + enum pipe pipe_to_reduce;
> > + int ret;
> > +
> > + ret = ilk_check_fdi_lanes(&i915->drm, crtc->pipe, pipe_config,
> > + &pipe_to_reduce);
> > + if (ret != -EINVAL)
> > return ret;
> >
> > - if (ret == -EINVAL && pipe_config->pipe_bpp > 6*3) {
> > - pipe_config->pipe_bpp -= 2*3;
> > - drm_dbg_kms(&i915->drm,
> > - "fdi link bw constraint, reducing pipe bpp to %i\n",
> > - pipe_config->pipe_bpp);
> > - needs_recompute = true;
> > - pipe_config->bw_constrained = true;
> > + ret = intel_atomic_reduce_link_bpp(state, limits,
> > + BIT(pipe_to_reduce),
> > + "FDI link BW");
> >
> > - goto retry;
> > - }
> > + return ret ? : -EAGAIN;
> > +}
> >
> > - if (needs_recompute)
> > - return -EAGAIN;
> > +/**
> > + * intel_fdi_atomic_check_link - check all modeset FDI link configuration
> > + * @state: intel atomic state
> > + * @limits: link BW limits
> > + *
> > + * Check the link configuration for all modeset FDI outputs. If the
> > + * configuration is invalid @limits will be updated if possible to
> > + * reduce the total BW, after which the configuration for all CRTCs in
> > + * @state must be recomputed with the updated @limits.
> > + *
> > + * Returns:
> > + * - 0 if the confugration is valid
> > + * - %-EAGAIN, if the configuration is invalid and @limits got updated
> > + * with fallback values with which the configuration of all CRTCs
> > + * in @state must be recomputed
> > + * - Other negative error, if the configuration is invalid without a
> > + * fallback possibility, or the check failed for another reason
> > + */
> > +int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
> > + struct intel_link_bw_limits *limits)
> > +{
> > + struct intel_crtc *crtc;
> > + struct intel_crtc_state *crtc_state;
> > + int i;
> > +
> > + for_each_new_intel_crtc_in_state(state, crtc, crtc_state, i) {
> > + int ret;
> >
> > - return ret;
> > + if (!crtc_state->has_pch_encoder ||
> > + !intel_crtc_needs_modeset(crtc_state) ||
> > + !crtc_state->hw.enable)
> > + continue;
> > +
> > + ret = intel_fdi_atomic_check_bw(state, crtc, crtc_state, limits);
> > + if (ret)
> > + return ret;
> > + }
> > +
> > + return 0;
> > }
> >
> > static void cpt_set_fdi_bc_bifurcation(struct drm_i915_private *dev_priv, bool enable)
> > diff --git a/drivers/gpu/drm/i915/display/intel_fdi.h b/drivers/gpu/drm/i915/display/intel_fdi.h
> > index 1cdb86172702f..eb02b967bb440 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fdi.h
> > +++ b/drivers/gpu/drm/i915/display/intel_fdi.h
> > @@ -8,14 +8,19 @@
> >
> > enum pipe;
> > struct drm_i915_private;
> > +struct intel_atomic_state;
> > struct intel_crtc;
> > struct intel_crtc_state;
> > struct intel_encoder;
> > +struct intel_link_bw_limits;
> >
> > +int intel_fdi_add_affected_crtcs(struct intel_atomic_state *state);
> > int intel_fdi_link_freq(struct drm_i915_private *i915,
> > const struct intel_crtc_state *pipe_config);
> > int ilk_fdi_compute_config(struct intel_crtc *intel_crtc,
> > struct intel_crtc_state *pipe_config);
> > +int intel_fdi_atomic_check_link(struct intel_atomic_state *state,
> > + struct intel_link_bw_limits *limits);
> > void intel_fdi_normal_train(struct intel_crtc *crtc);
> > void ilk_fdi_disable(struct intel_crtc *crtc);
> > void ilk_fdi_pll_disable(struct intel_crtc *intel_crtc);
> > diff --git a/drivers/gpu/drm/i915/display/intel_lvds.c b/drivers/gpu/drm/i915/display/intel_lvds.c
> > index 3ace56979b70e..08dcc2d10a2c1 100644
> > --- a/drivers/gpu/drm/i915/display/intel_lvds.c
> > +++ b/drivers/gpu/drm/i915/display/intel_lvds.c
> > @@ -425,6 +425,12 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
> > return -EINVAL;
> > }
> >
> > + if (HAS_PCH_SPLIT(i915)) {
> > + crtc_state->has_pch_encoder = true;
> > + if (!intel_atomic_compute_pipe_bpp(crtc_state))
> > + return -EINVAL;
> > + }
> > +
> > if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
> > lvds_bpp = 8*3;
> > else
> > @@ -453,9 +459,6 @@ static int intel_lvds_compute_config(struct intel_encoder *encoder,
> > if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
> > return -EINVAL;
> >
> > - if (HAS_PCH_SPLIT(i915))
> > - crtc_state->has_pch_encoder = true;
> > -
> > ret = intel_panel_fitting(crtc_state, conn_state);
> > if (ret)
> > return ret;
> > diff --git a/drivers/gpu/drm/i915/display/intel_sdvo.c b/drivers/gpu/drm/i915/display/intel_sdvo.c
> > index 7d25a64698e2f..1c6330151f4d6 100644
> > --- a/drivers/gpu/drm/i915/display/intel_sdvo.c
> > +++ b/drivers/gpu/drm/i915/display/intel_sdvo.c
> > @@ -1352,14 +1352,17 @@ static int intel_sdvo_compute_config(struct intel_encoder *encoder,
> > struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode;
> > struct drm_display_mode *mode = &pipe_config->hw.mode;
> >
> > + if (HAS_PCH_SPLIT(to_i915(encoder->base.dev))) {
> > + pipe_config->has_pch_encoder = true;
> > + if (!intel_atomic_compute_pipe_bpp(pipe_config))
> > + return -EINVAL;
> > + }
> > +
> > DRM_DEBUG_KMS("forcing bpc to 8 for SDVO\n");
> > pipe_config->pipe_bpp = 8*3;
> > pipe_config->sink_format = INTEL_OUTPUT_FORMAT_RGB;
> > pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB;
> >
> > - if (HAS_PCH_SPLIT(to_i915(encoder->base.dev)))
> > - pipe_config->has_pch_encoder = true;
> > -
> > /*
> > * We need to construct preferred input timings based on our
> > * output timings. To do that, we have to set the output
> > --
> > 2.37.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (25 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
For fractional bpp values passed to the function in a .4 fixed point
format, the fractional part is currently ignored due to scaling bpp too
early. Fix this by scaling the overhead factor instead and to avoid an
overflow multiplying bpp with the overhead factor instead of the clock
rate.
While at it simplify the formula, and pass the expected fixed point bpp
values in the kunit tests.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index ed96cfcfa3040..bd0f35a0ea5fb 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
* factor in the numerator rather than the denominator to avoid
* integer overflow
*/
+ u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
- if (dsc)
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
- 8 * 54 * 1000 * 1000);
-
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
+ return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
8 * 54 * 1000 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index 545beea33e8c7..ea2182815ebe8 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
},
{
.clock = 332880,
- .bpp = 24,
+ .bpp = 24 << 4,
.dsc = true,
- .expected = 50
+ .expected = 1191
},
{
.clock = 324540,
- .bpp = 24,
+ .bpp = 24 << 4,
.dsc = true,
- .expected = 49
+ .expected = 1161
},
};
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
@ 2023-08-24 8:05 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
For fractional bpp values passed to the function in a .4 fixed point
format, the fractional part is currently ignored due to scaling bpp too
early. Fix this by scaling the overhead factor instead and to avoid an
overflow multiplying bpp with the overhead factor instead of the clock
rate.
While at it simplify the formula, and pass the expected fixed point bpp
values in the kunit tests.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
2 files changed, 6 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index ed96cfcfa3040..bd0f35a0ea5fb 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
* factor in the numerator rather than the denominator to avoid
* integer overflow
*/
+ u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
- if (dsc)
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
- 8 * 54 * 1000 * 1000);
-
- return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
+ return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
8 * 54 * 1000 * 1000);
}
EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index 545beea33e8c7..ea2182815ebe8 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
},
{
.clock = 332880,
- .bpp = 24,
+ .bpp = 24 << 4,
.dsc = true,
- .expected = 50
+ .expected = 1191
},
{
.clock = 324540,
- .bpp = 24,
+ .bpp = 24 << 4,
.dsc = true,
- .expected = 49
+ .expected = 1161
},
};
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
2023-08-24 8:05 ` Imre Deak
@ 2023-08-30 21:27 ` Lyude Paul
-1 siblings, 0 replies; 60+ messages in thread
From: Lyude Paul @ 2023-08-30 21:27 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: dri-devel
Amazing! This work looks awesome Imre, sorry it took me a little bit to get
back to this :). For all of the DP MST helper patches:
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Thu, 2023-08-24 at 11:05 +0300, Imre Deak wrote:
> For fractional bpp values passed to the function in a .4 fixed point
> format, the fractional part is currently ignored due to scaling bpp too
> early. Fix this by scaling the overhead factor instead and to avoid an
> overflow multiplying bpp with the overhead factor instead of the clock
> rate.
>
> While at it simplify the formula, and pass the expected fixed point bpp
> values in the kunit tests.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
> drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
> 2 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index ed96cfcfa3040..bd0f35a0ea5fb 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> * factor in the numerator rather than the denominator to avoid
> * integer overflow
> */
> + u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
>
> - if (dsc)
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
> - 8 * 54 * 1000 * 1000);
> -
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> + return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
> 8 * 54 * 1000 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> index 545beea33e8c7..ea2182815ebe8 100644
> --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> @@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> },
> {
> .clock = 332880,
> - .bpp = 24,
> + .bpp = 24 << 4,
> .dsc = true,
> - .expected = 50
> + .expected = 1191
> },
> {
> .clock = 324540,
> - .bpp = 24,
> + .bpp = 24 << 4,
> .dsc = true,
> - .expected = 49
> + .expected = 1161
> },
> };
>
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
@ 2023-08-30 21:27 ` Lyude Paul
0 siblings, 0 replies; 60+ messages in thread
From: Lyude Paul @ 2023-08-30 21:27 UTC (permalink / raw)
To: Imre Deak, intel-gfx; +Cc: dri-devel
Amazing! This work looks awesome Imre, sorry it took me a little bit to get
back to this :). For all of the DP MST helper patches:
Reviewed-by: Lyude Paul <lyude@redhat.com>
On Thu, 2023-08-24 at 11:05 +0300, Imre Deak wrote:
> For fractional bpp values passed to the function in a .4 fixed point
> format, the fractional part is currently ignored due to scaling bpp too
> early. Fix this by scaling the overhead factor instead and to avoid an
> overflow multiplying bpp with the overhead factor instead of the clock
> rate.
>
> While at it simplify the formula, and pass the expected fixed point bpp
> values in the kunit tests.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
> drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
> 2 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index ed96cfcfa3040..bd0f35a0ea5fb 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> * factor in the numerator rather than the denominator to avoid
> * integer overflow
> */
> + u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
>
> - if (dsc)
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
> - 8 * 54 * 1000 * 1000);
> -
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> + return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
> 8 * 54 * 1000 * 1000);
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> index 545beea33e8c7..ea2182815ebe8 100644
> --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> @@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> },
> {
> .clock = 332880,
> - .bpp = 24,
> + .bpp = 24 << 4,
> .dsc = true,
> - .expected = 50
> + .expected = 1191
> },
> {
> .clock = 324540,
> - .bpp = 24,
> + .bpp = 24 << 4,
> .dsc = true,
> - .expected = 49
> + .expected = 1161
> },
> };
>
--
Cheers,
Lyude Paul (she/her)
Software Engineer at Red Hat
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Intel-gfx] [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
2023-08-24 8:05 ` Imre Deak
(?)
(?)
@ 2023-09-04 2:53 ` Ville Syrjälä
2023-09-04 10:22 ` Imre Deak
-1 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2023-09-04 2:53 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Thu, Aug 24, 2023 at 11:05:04AM +0300, Imre Deak wrote:
> For fractional bpp values passed to the function in a .4 fixed point
> format, the fractional part is currently ignored due to scaling bpp too
> early. Fix this by scaling the overhead factor instead and to avoid an
> overflow multiplying bpp with the overhead factor instead of the clock
> rate.
>
> While at it simplify the formula, and pass the expected fixed point bpp
> values in the kunit tests.
>
> Cc: Lyude Paul <lyude@redhat.com>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
> drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
> 2 files changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> index ed96cfcfa3040..bd0f35a0ea5fb 100644
> --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> @@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> * factor in the numerator rather than the denominator to avoid
> * integer overflow
> */
> + u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
>
> - if (dsc)
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
> - 8 * 54 * 1000 * 1000);
> -
> - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> + return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
> 8 * 54 * 1000 * 1000);
I thought I sorted out this mess already...
https://patchwork.freedesktop.org/patch/535005/?series=117201&rev=3
Apparently I forgot to push that.
> }
> EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> index 545beea33e8c7..ea2182815ebe8 100644
> --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> @@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> },
> {
> .clock = 332880,
> - .bpp = 24,
> + .bpp = 24 << 4,
> .dsc = true,
> - .expected = 50
> + .expected = 1191
> },
> {
> .clock = 324540,
> - .bpp = 24,
> + .bpp = 24 << 4,
> .dsc = true,
> - .expected = 49
> + .expected = 1161
> },
> };
>
> --
> 2.37.2
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
2023-09-04 2:53 ` [Intel-gfx] " Ville Syrjälä
@ 2023-09-04 10:22 ` Imre Deak
2023-09-06 10:45 ` Ville Syrjälä
0 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-09-04 10:22 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Mon, Sep 04, 2023 at 05:53:11AM +0300, Ville Syrjälä wrote:
> On Thu, Aug 24, 2023 at 11:05:04AM +0300, Imre Deak wrote:
> > For fractional bpp values passed to the function in a .4 fixed point
> > format, the fractional part is currently ignored due to scaling bpp too
> > early. Fix this by scaling the overhead factor instead and to avoid an
> > overflow multiplying bpp with the overhead factor instead of the clock
> > rate.
> >
> > While at it simplify the formula, and pass the expected fixed point bpp
> > values in the kunit tests.
> >
> > Cc: Lyude Paul <lyude@redhat.com>
> > Cc: dri-devel@lists.freedesktop.org
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
> > drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
> > 2 files changed, 6 insertions(+), 9 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > index ed96cfcfa3040..bd0f35a0ea5fb 100644
> > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > @@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> > * factor in the numerator rather than the denominator to avoid
> > * integer overflow
> > */
> > + u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
> >
> > - if (dsc)
> > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
> > - 8 * 54 * 1000 * 1000);
> > -
> > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> > + return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
> > 8 * 54 * 1000 * 1000);
>
> I thought I sorted out this mess already...
> https://patchwork.freedesktop.org/patch/535005/?series=117201&rev=3
> Apparently I forgot to push that.
Looks ok, can use that instead. I thought clock * bpp could overflow,
but probably not in practice.
The test cases below would still need to be fixed.
>
> > }
> > EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> > diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > index 545beea33e8c7..ea2182815ebe8 100644
> > --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > @@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> > },
> > {
> > .clock = 332880,
> > - .bpp = 24,
> > + .bpp = 24 << 4,
> > .dsc = true,
> > - .expected = 50
> > + .expected = 1191
> > },
> > {
> > .clock = 324540,
> > - .bpp = 24,
> > + .bpp = 24 << 4,
> > .dsc = true,
> > - .expected = 49
> > + .expected = 1161
> > },
> > };
> >
> > --
> > 2.37.2
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
2023-09-04 10:22 ` Imre Deak
@ 2023-09-06 10:45 ` Ville Syrjälä
2023-09-06 11:14 ` Imre Deak
0 siblings, 1 reply; 60+ messages in thread
From: Ville Syrjälä @ 2023-09-06 10:45 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx, dri-devel
On Mon, Sep 04, 2023 at 01:22:27PM +0300, Imre Deak wrote:
> On Mon, Sep 04, 2023 at 05:53:11AM +0300, Ville Syrjälä wrote:
> > On Thu, Aug 24, 2023 at 11:05:04AM +0300, Imre Deak wrote:
> > > For fractional bpp values passed to the function in a .4 fixed point
> > > format, the fractional part is currently ignored due to scaling bpp too
> > > early. Fix this by scaling the overhead factor instead and to avoid an
> > > overflow multiplying bpp with the overhead factor instead of the clock
> > > rate.
> > >
> > > While at it simplify the formula, and pass the expected fixed point bpp
> > > values in the kunit tests.
> > >
> > > Cc: Lyude Paul <lyude@redhat.com>
> > > Cc: dri-devel@lists.freedesktop.org
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > > drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
> > > drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
> > > 2 files changed, 6 insertions(+), 9 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > index ed96cfcfa3040..bd0f35a0ea5fb 100644
> > > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > @@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> > > * factor in the numerator rather than the denominator to avoid
> > > * integer overflow
> > > */
> > > + u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
> > >
> > > - if (dsc)
> > > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
> > > - 8 * 54 * 1000 * 1000);
> > > -
> > > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> > > + return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
> > > 8 * 54 * 1000 * 1000);
> >
> > I thought I sorted out this mess already...
> > https://patchwork.freedesktop.org/patch/535005/?series=117201&rev=3
> > Apparently I forgot to push that.
>
> Looks ok, can use that instead. I thought clock * bpp could overflow,
> but probably not in practice.
2^32/(16*3*2^4)~=5.6e6 -> 5.6 GHz dotclock. So should be good for
a few more years. But we can of course move bpp to the other side
of the mul_u32_u32() as you do here and then we don't have anything
to worry about as everything else there is constant.
>
> The test cases below would still need to be fixed.
I thought I fixed the tests as well? Maybe they changed...
>
> >
> > > }
> > > EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> > > diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > > index 545beea33e8c7..ea2182815ebe8 100644
> > > --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > > +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > > @@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> > > },
> > > {
> > > .clock = 332880,
> > > - .bpp = 24,
> > > + .bpp = 24 << 4,
> > > .dsc = true,
> > > - .expected = 50
> > > + .expected = 1191
> > > },
> > > {
> > > .clock = 324540,
> > > - .bpp = 24,
> > > + .bpp = 24 << 4,
> > > .dsc = true,
> > > - .expected = 49
> > > + .expected = 1161
> > > },
> > > };
> > >
> > > --
> > > 2.37.2
> >
> > --
> > Ville Syrjälä
> > Intel
--
Ville Syrjälä
Intel
^ permalink raw reply [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 09/22] drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
2023-09-06 10:45 ` Ville Syrjälä
@ 2023-09-06 11:14 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-09-06 11:14 UTC (permalink / raw)
To: Ville Syrjälä; +Cc: intel-gfx, dri-devel
On Wed, Sep 06, 2023 at 01:45:51PM +0300, Ville Syrjälä wrote:
> On Mon, Sep 04, 2023 at 01:22:27PM +0300, Imre Deak wrote:
> > On Mon, Sep 04, 2023 at 05:53:11AM +0300, Ville Syrjälä wrote:
> > > On Thu, Aug 24, 2023 at 11:05:04AM +0300, Imre Deak wrote:
> > > > For fractional bpp values passed to the function in a .4 fixed point
> > > > format, the fractional part is currently ignored due to scaling bpp too
> > > > early. Fix this by scaling the overhead factor instead and to avoid an
> > > > overflow multiplying bpp with the overhead factor instead of the clock
> > > > rate.
> > > >
> > > > While at it simplify the formula, and pass the expected fixed point bpp
> > > > values in the kunit tests.
> > > >
> > > > Cc: Lyude Paul <lyude@redhat.com>
> > > > Cc: dri-devel@lists.freedesktop.org
> > > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > > ---
> > > > drivers/gpu/drm/display/drm_dp_mst_topology.c | 7 ++-----
> > > > drivers/gpu/drm/tests/drm_dp_mst_helper_test.c | 8 ++++----
> > > > 2 files changed, 6 insertions(+), 9 deletions(-)
> > > >
> > > > diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > > index ed96cfcfa3040..bd0f35a0ea5fb 100644
> > > > --- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > > +++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
> > > > @@ -4712,12 +4712,9 @@ int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
> > > > * factor in the numerator rather than the denominator to avoid
> > > > * integer overflow
> > > > */
> > > > + u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
> > > >
> > > > - if (dsc)
> > > > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * (bpp / 16), 64 * 1006),
> > > > - 8 * 54 * 1000 * 1000);
> > > > -
> > > > - return DIV_ROUND_UP_ULL(mul_u32_u32(clock * bpp, 64 * 1006),
> > > > + return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
> > > > 8 * 54 * 1000 * 1000);
> > >
> > > I thought I sorted out this mess already...
> > > https://patchwork.freedesktop.org/patch/535005/?series=117201&rev=3
> > > Apparently I forgot to push that.
> >
> > Looks ok, can use that instead. I thought clock * bpp could overflow,
> > but probably not in practice.
>
> 2^32/(16*3*2^4)~=5.6e6 -> 5.6 GHz dotclock. So should be good for
> a few more years.
Right.
> But we can of course move bpp to the other side
> of the mul_u32_u32() as you do here and then we don't have anything
> to worry about as everything else there is constant.
Either way is ok, could also just add a multiply_overflows check if it
makes sense.
> > The test cases below would still need to be fixed.
>
> I thought I fixed the tests as well? Maybe they changed...
The .dsc = true cases could've been added only later, but there
.expected changes after you pass the correctly shifted bpp.
> > >
> > > > }
> > > > EXPORT_SYMBOL(drm_dp_calc_pbn_mode);
> > > > diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > > > index 545beea33e8c7..ea2182815ebe8 100644
> > > > --- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > > > +++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
> > > > @@ -40,15 +40,15 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
> > > > },
> > > > {
> > > > .clock = 332880,
> > > > - .bpp = 24,
> > > > + .bpp = 24 << 4,
> > > > .dsc = true,
> > > > - .expected = 50
> > > > + .expected = 1191
> > > > },
> > > > {
> > > > .clock = 324540,
> > > > - .bpp = 24,
> > > > + .bpp = 24 << 4,
> > > > .dsc = true,
> > > > - .expected = 49
> > > > + .expected = 1161
> > > > },
> > > > };
> > > >
> > > > --
> > > > 2.37.2
> > >
> > > --
> > > Ville Syrjälä
> > > Intel
>
> --
> Ville Syrjälä
> Intel
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 10/22] drm/dp_mst: Add a way to calculate PBN values with FEC overhead
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (25 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Deucher, Harry Wentland, dri-devel, Wayne Lin
Add a way for drivers to calculate the MST PBN values with FEC overhead.
This is required by 8b/10b links both for DSC and non-DSC (the latter
needed if there are both DSC and non-DSC streams on the same MST link).
Also add kunit test cases for PBN values calculated with FEC overhead.
Cc: Lyude Paul <lyude@redhat.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Wayne Lin <wayne.lin@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 18 +++++++++++----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++--
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
.../gpu/drm/tests/drm_dp_mst_helper_test.c | 23 ++++++++++++++++++-
include/drm/display/drm_dp_mst_helper.h | 2 +-
7 files changed, 42 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 268cb99a4c4bc..22868d6eb8977 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6782,7 +6782,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
max_bpc);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
- dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
+ dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false, false);
}
dm_new_connector_state->vcpi_slots =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 57230661132bd..9acfdefc792d6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1636,7 +1636,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
} else {
/* check if mode could be supported within full_pbn */
bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false, false);
if (pbn > aconnector->mst_output_port->full_pbn)
return DC_FAIL_BANDWIDTH_VALIDATE;
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index bd0f35a0ea5fb..e26f1b7f5a701 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4693,26 +4693,34 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
* @clock: dot clock for the mode
* @bpp: bpp for the mode.
* @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
+ * @fec: FEC overhead.
*
* This uses the formula in the spec to calculate the PBN value for a mode.
*/
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc, bool fec)
{
/*
- * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+ * Overheads:
+ * - SSC downspread and ref clock variation margin:
+ * 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+ * - FEC symbol insertions:
+ * 2.4% as per spec, factor is 1.024
+ *
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
- * peak_kbps *= (1006/1000)
+ * peak_kbps *= (1006/1000) without FEC, or
+ * peak_kbps *= (1030/1000) with FEC
* peak_kbps *= (64/54)
- * peak_kbps *= 8 convert to bytes
+ * peak_kbps /= 8 convert to bytes
*
* If the bpp is in units of 1/16, further divide by 16. Put this
* factor in the numerator rather than the denominator to avoid
* integer overflow
*/
- u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
+ u32 overhead = fec ? 1030 : 1006;
+ u32 bpp_m = (dsc ? 64 / 16 : 64) * overhead * bpp;
return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
8 * 54 * 1000 * 1000);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 525766206fce5..6eeb7dbf5ba67 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -110,7 +110,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
dsc ? bpp << 4 : bpp,
- dsc);
+ dsc,
+ false);
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
@@ -983,7 +984,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
return ret;
if (mode_rate > max_rate || mode->clock > max_dotclk ||
- drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
+ drm_dp_calc_pbn_mode(mode->clock, min_bpp, false, false) > port->full_pbn) {
*status = MODE_CLOCK_HIGH;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 4e7c9c353c511..d71c28e458107 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -967,7 +967,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
asyh->or.bpc = connector->display_info.bpc;
asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
- false);
+ false, false);
}
mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index ea2182815ebe8..3c0c0ffd5f9f5 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -16,6 +16,7 @@ struct drm_dp_mst_calc_pbn_mode_test {
const int clock;
const int bpp;
const bool dsc;
+ const bool fec;
const int expected;
};
@@ -24,39 +25,59 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
.clock = 154000,
.bpp = 30,
.dsc = false,
+ .fec = false,
.expected = 689
},
{
.clock = 234000,
.bpp = 30,
.dsc = false,
+ .fec = false,
.expected = 1047
},
{
.clock = 297000,
.bpp = 24,
.dsc = false,
+ .fec = false,
.expected = 1063
},
{
.clock = 332880,
.bpp = 24 << 4,
.dsc = true,
+ .fec = false,
.expected = 1191
},
{
.clock = 324540,
.bpp = 24 << 4,
.dsc = true,
+ .fec = false,
.expected = 1161
},
+ {
+ .clock = 324540,
+ .bpp = 24 << 4,
+ .dsc = true,
+ .fec = true,
+ .expected = 1189
+ },
+ {
+ .clock = 324540,
+ .bpp = 24,
+ .dsc = false,
+ .fec = true,
+ .expected = 1189
+ },
};
static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test)
{
const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value;
- KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc),
+ KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp,
+ params->dsc, params->fec),
params->expected);
}
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index ed5c9660563c4..0953b7b16a51b 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -832,7 +832,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
int link_rate, int link_lane_count);
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc, bool fec);
void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v2 10/22] drm/dp_mst: Add a way to calculate PBN values with FEC overhead
@ 2023-08-24 8:05 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: Alex Deucher, dri-devel, Wayne Lin
Add a way for drivers to calculate the MST PBN values with FEC overhead.
This is required by 8b/10b links both for DSC and non-DSC (the latter
needed if there are both DSC and non-DSC streams on the same MST link).
Also add kunit test cases for PBN values calculated with FEC overhead.
Cc: Lyude Paul <lyude@redhat.com>
Cc: Harry Wentland <harry.wentland@amd.com>
Cc: Wayne Lin <wayne.lin@amd.com>
Cc: Alex Deucher <alexander.deucher@amd.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c | 2 +-
.../display/amdgpu_dm/amdgpu_dm_mst_types.c | 2 +-
drivers/gpu/drm/display/drm_dp_mst_topology.c | 18 +++++++++++----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 5 ++--
drivers/gpu/drm/nouveau/dispnv50/disp.c | 2 +-
.../gpu/drm/tests/drm_dp_mst_helper_test.c | 23 ++++++++++++++++++-
include/drm/display/drm_dp_mst_helper.h | 2 +-
7 files changed, 42 insertions(+), 12 deletions(-)
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
index 268cb99a4c4bc..22868d6eb8977 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm.c
@@ -6782,7 +6782,7 @@ static int dm_encoder_helper_atomic_check(struct drm_encoder *encoder,
max_bpc);
bpp = convert_dc_color_depth_into_bpc(color_depth) * 3;
clock = adjusted_mode->clock;
- dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false);
+ dm_new_connector_state->pbn = drm_dp_calc_pbn_mode(clock, bpp, false, false);
}
dm_new_connector_state->vcpi_slots =
diff --git a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
index 57230661132bd..9acfdefc792d6 100644
--- a/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
+++ b/drivers/gpu/drm/amd/display/amdgpu_dm/amdgpu_dm_mst_types.c
@@ -1636,7 +1636,7 @@ enum dc_status dm_dp_mst_is_port_support_mode(
} else {
/* check if mode could be supported within full_pbn */
bpp = convert_dc_color_depth_into_bpc(stream->timing.display_color_depth) * 3;
- pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false);
+ pbn = drm_dp_calc_pbn_mode(stream->timing.pix_clk_100hz / 10, bpp, false, false);
if (pbn > aconnector->mst_output_port->full_pbn)
return DC_FAIL_BANDWIDTH_VALIDATE;
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index bd0f35a0ea5fb..e26f1b7f5a701 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -4693,26 +4693,34 @@ EXPORT_SYMBOL(drm_dp_check_act_status);
* @clock: dot clock for the mode
* @bpp: bpp for the mode.
* @dsc: DSC mode. If true, bpp has units of 1/16 of a bit per pixel
+ * @fec: FEC overhead.
*
* This uses the formula in the spec to calculate the PBN value for a mode.
*/
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc)
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc, bool fec)
{
/*
- * margin 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+ * Overheads:
+ * - SSC downspread and ref clock variation margin:
+ * 5300ppm + 300ppm ~ 0.6% as per spec, factor is 1.006
+ * - FEC symbol insertions:
+ * 2.4% as per spec, factor is 1.024
+ *
* The unit of 54/64Mbytes/sec is an arbitrary unit chosen based on
* common multiplier to render an integer PBN for all link rate/lane
* counts combinations
* calculate
- * peak_kbps *= (1006/1000)
+ * peak_kbps *= (1006/1000) without FEC, or
+ * peak_kbps *= (1030/1000) with FEC
* peak_kbps *= (64/54)
- * peak_kbps *= 8 convert to bytes
+ * peak_kbps /= 8 convert to bytes
*
* If the bpp is in units of 1/16, further divide by 16. Put this
* factor in the numerator rather than the denominator to avoid
* integer overflow
*/
- u32 bpp_m = (dsc ? 64 / 16 : 64) * 1006 * bpp;
+ u32 overhead = fec ? 1030 : 1006;
+ u32 bpp_m = (dsc ? 64 / 16 : 64) * overhead * bpp;
return DIV_ROUND_UP_ULL(mul_u32_u32(clock, bpp_m),
8 * 54 * 1000 * 1000);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 525766206fce5..6eeb7dbf5ba67 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -110,7 +110,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
dsc ? bpp << 4 : bpp,
- dsc);
+ dsc,
+ false);
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
@@ -983,7 +984,7 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector,
return ret;
if (mode_rate > max_rate || mode->clock > max_dotclk ||
- drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) {
+ drm_dp_calc_pbn_mode(mode->clock, min_bpp, false, false) > port->full_pbn) {
*status = MODE_CLOCK_HIGH;
return 0;
}
diff --git a/drivers/gpu/drm/nouveau/dispnv50/disp.c b/drivers/gpu/drm/nouveau/dispnv50/disp.c
index 4e7c9c353c511..d71c28e458107 100644
--- a/drivers/gpu/drm/nouveau/dispnv50/disp.c
+++ b/drivers/gpu/drm/nouveau/dispnv50/disp.c
@@ -967,7 +967,7 @@ nv50_msto_atomic_check(struct drm_encoder *encoder,
asyh->or.bpc = connector->display_info.bpc;
asyh->dp.pbn = drm_dp_calc_pbn_mode(clock, asyh->or.bpc * 3,
- false);
+ false, false);
}
mst_state = drm_atomic_get_mst_topology_state(state, &mstm->mgr);
diff --git a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
index ea2182815ebe8..3c0c0ffd5f9f5 100644
--- a/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
+++ b/drivers/gpu/drm/tests/drm_dp_mst_helper_test.c
@@ -16,6 +16,7 @@ struct drm_dp_mst_calc_pbn_mode_test {
const int clock;
const int bpp;
const bool dsc;
+ const bool fec;
const int expected;
};
@@ -24,39 +25,59 @@ static const struct drm_dp_mst_calc_pbn_mode_test drm_dp_mst_calc_pbn_mode_cases
.clock = 154000,
.bpp = 30,
.dsc = false,
+ .fec = false,
.expected = 689
},
{
.clock = 234000,
.bpp = 30,
.dsc = false,
+ .fec = false,
.expected = 1047
},
{
.clock = 297000,
.bpp = 24,
.dsc = false,
+ .fec = false,
.expected = 1063
},
{
.clock = 332880,
.bpp = 24 << 4,
.dsc = true,
+ .fec = false,
.expected = 1191
},
{
.clock = 324540,
.bpp = 24 << 4,
.dsc = true,
+ .fec = false,
.expected = 1161
},
+ {
+ .clock = 324540,
+ .bpp = 24 << 4,
+ .dsc = true,
+ .fec = true,
+ .expected = 1189
+ },
+ {
+ .clock = 324540,
+ .bpp = 24,
+ .dsc = false,
+ .fec = true,
+ .expected = 1189
+ },
};
static void drm_test_dp_mst_calc_pbn_mode(struct kunit *test)
{
const struct drm_dp_mst_calc_pbn_mode_test *params = test->param_value;
- KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp, params->dsc),
+ KUNIT_EXPECT_EQ(test, drm_dp_calc_pbn_mode(params->clock, params->bpp,
+ params->dsc, params->fec),
params->expected);
}
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index ed5c9660563c4..0953b7b16a51b 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -832,7 +832,7 @@ struct edid *drm_dp_mst_get_edid(struct drm_connector *connector,
int drm_dp_get_vc_payload_bw(const struct drm_dp_mst_topology_mgr *mgr,
int link_rate, int link_lane_count);
-int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc);
+int drm_dp_calc_pbn_mode(int clock, int bpp, bool dsc, bool fec);
void drm_dp_mst_update_slots(struct drm_dp_mst_topology_state *mst_state, uint8_t link_encoding_cap);
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 11/22] drm/dp_mst: Add helper to determine if an MST port is downstream of another port
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (25 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 52 +++++++++++++++++++
include/drm/display/drm_dp_mst_helper.h | 3 ++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index e26f1b7f5a701..ced9ae36a9177 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5105,6 +5105,58 @@ static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
return false;
}
+static bool
+drm_dp_mst_port_downstream_of_parent_locked(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ if (!mgr->mst_primary)
+ return false;
+
+ port = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ port);
+ if (!port)
+ return false;
+
+ if (!parent)
+ return true;
+
+ parent = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ parent);
+ if (!parent)
+ return false;
+
+ if (!parent->mstb)
+ return false;
+
+ return drm_dp_mst_port_downstream_of_branch(port, parent->mstb);
+}
+
+/**
+ * drm_dp_mst_port_downstream_of_parent - check if a port is downstream of a parent port
+ * @mgr: MST topology manager
+ * @port: the port being looked up
+ * @parent: the parent port
+ *
+ * The function returns %true if @port is downstream of @parent. If @parent is
+ * %NULL - denoting the root port - the function returns %true if @port is in
+ * @mgr's topology.
+ */
+bool
+drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ bool ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_port_downstream_of_parent_locked(mgr, port, parent);
+ mutex_unlock(&mgr->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
+
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
struct drm_dp_mst_topology_state *state);
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 0953b7b16a51b..097c4204ffae4 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -879,6 +879,9 @@ drm_atomic_get_new_mst_topology_state(struct drm_atomic_state *state,
struct drm_dp_mst_atomic_payload *
drm_atomic_get_mst_payload_state(struct drm_dp_mst_topology_state *state,
struct drm_dp_mst_port *port);
+bool drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent);
int __must_check
drm_dp_atomic_find_time_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v2 11/22] drm/dp_mst: Add helper to determine if an MST port is downstream of another port
@ 2023-08-24 8:05 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Add drm_dp_mst_port_downstream_of_parent() required by the i915
driver in a follow-up patch to resolve a BW overallocation of MST
streams going through a given MST port.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 52 +++++++++++++++++++
include/drm/display/drm_dp_mst_helper.h | 3 ++
2 files changed, 55 insertions(+)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index e26f1b7f5a701..ced9ae36a9177 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5105,6 +5105,58 @@ static bool drm_dp_mst_port_downstream_of_branch(struct drm_dp_mst_port *port,
return false;
}
+static bool
+drm_dp_mst_port_downstream_of_parent_locked(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ if (!mgr->mst_primary)
+ return false;
+
+ port = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ port);
+ if (!port)
+ return false;
+
+ if (!parent)
+ return true;
+
+ parent = drm_dp_mst_topology_get_port_validated_locked(mgr->mst_primary,
+ parent);
+ if (!parent)
+ return false;
+
+ if (!parent->mstb)
+ return false;
+
+ return drm_dp_mst_port_downstream_of_branch(port, parent->mstb);
+}
+
+/**
+ * drm_dp_mst_port_downstream_of_parent - check if a port is downstream of a parent port
+ * @mgr: MST topology manager
+ * @port: the port being looked up
+ * @parent: the parent port
+ *
+ * The function returns %true if @port is downstream of @parent. If @parent is
+ * %NULL - denoting the root port - the function returns %true if @port is in
+ * @mgr's topology.
+ */
+bool
+drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent)
+{
+ bool ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_port_downstream_of_parent_locked(mgr, port, parent);
+ mutex_unlock(&mgr->lock);
+
+ return ret;
+}
+EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
+
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
struct drm_dp_mst_topology_state *state);
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 0953b7b16a51b..097c4204ffae4 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -879,6 +879,9 @@ drm_atomic_get_new_mst_topology_state(struct drm_atomic_state *state,
struct drm_dp_mst_atomic_payload *
drm_atomic_get_mst_payload_state(struct drm_dp_mst_topology_state *state,
struct drm_dp_mst_port *port);
+bool drm_dp_mst_port_downstream_of_parent(struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_port *port,
+ struct drm_dp_mst_port *parent);
int __must_check
drm_dp_atomic_find_time_slots(struct drm_atomic_state *state,
struct drm_dp_mst_topology_mgr *mgr,
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 12/22] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (25 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 93 +++++++++++++++----
include/drm/display/drm_dp_mst_helper.h | 4 +
2 files changed, 78 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index ced9ae36a9177..6b1cbe2260a29 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5159,11 +5159,13 @@ EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state);
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port);
static int
drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
struct drm_dp_mst_port *port;
@@ -5192,7 +5194,7 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
drm_dbg_atomic(mstb->mgr->dev, "[MSTB:%p] Checking bandwidth limits\n", mstb);
list_for_each_entry(port, &mstb->ports, next) {
- ret = drm_dp_mst_atomic_check_port_bw_limit(port, state);
+ ret = drm_dp_mst_atomic_check_port_bw_limit(port, state, failing_port);
if (ret < 0)
return ret;
@@ -5204,7 +5206,8 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
int pbn_used = 0;
@@ -5225,13 +5228,15 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] no BW available for the port\n",
port->parent, port);
+ *failing_port = port;
return -EINVAL;
}
pbn_used = payload->pbn;
} else {
pbn_used = drm_dp_mst_atomic_check_mstb_bw_limit(port->mstb,
- state);
+ state,
+ failing_port);
if (pbn_used <= 0)
return pbn_used;
}
@@ -5240,6 +5245,7 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] required PBN of %d exceeds port limit of %d\n",
port->parent, port, pbn_used, port->full_pbn);
+ *failing_port = port;
return -ENOSPC;
}
@@ -5417,20 +5423,79 @@ int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
}
EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
+/**
+ * drm_dp_mst_atomic_check_mgr - Check the atomic state of an MST topology manager
+ * @state: The global atomic state
+ * @mgr: Manager to check
+ * @mst_state: The MST atomic state for @mgr
+ * @failing_port: Returns the port with a BW limitation
+ *
+ * Checks the given MST manager's topology state for an atomic update to ensure
+ * that it's valid. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
+ *
+ * Any atomic drivers supporting DP MST must make sure to call this or
+ * the drm_dp_mst_atomic_check() function after checking the rest of their state
+ * in their &drm_mode_config_funcs.atomic_check() callback.
+ *
+ * See also:
+ * drm_dp_mst_atomic_check()
+ * drm_dp_atomic_find_time_slots()
+ * drm_dp_atomic_release_time_slots()
+ *
+ * Returns:
+ * - 0 if the new state is valid
+ * - %-ENOSPC, if the new state is invalid, because of BW limitation
+ * @failing_port is set to:
+ * - The non-root port where a BW limit check failed
+ * The returned port pointer is valid until at least
+ * one payload downstream of it exists.
+ * - %NULL if the BW limit check failed at the root port
+ * - %-EINVAL, if the new state is invalid, because the root port has
+ * too many payloads.
+ */
+int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port)
+{
+ int ret;
+
+ *failing_port = NULL;
+
+ if (!mgr->mst_state)
+ return 0;
+
+ ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ if (ret)
+ return ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
+ mst_state,
+ failing_port);
+ mutex_unlock(&mgr->lock);
+
+ return ret < 0 ? ret : 0;
+}
+EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
+
/**
* drm_dp_mst_atomic_check - Check that the new state of an MST topology in an
* atomic update is valid
* @state: Pointer to the new &struct drm_dp_mst_topology_state
*
* Checks the given topology state for an atomic update to ensure that it's
- * valid. This includes checking whether there's enough bandwidth to support
- * the new timeslot allocations in the atomic update.
+ * valid, calling drm_dp_mst_atomic_check_mgr() for all MST manager in the
+ * atomic state. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
*
* Any atomic drivers supporting DP MST must make sure to call this after
* checking the rest of their state in their
* &drm_mode_config_funcs.atomic_check() callback.
*
* See also:
+ * drm_dp_mst_atomic_check_mgr()
* drm_dp_atomic_find_time_slots()
* drm_dp_atomic_release_time_slots()
*
@@ -5445,21 +5510,11 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
int i, ret = 0;
for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
- if (!mgr->mst_state)
- continue;
+ struct drm_dp_mst_port *tmp_port;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ ret = drm_dp_mst_atomic_check_mgr(state, mgr, mst_state, &tmp_port);
if (ret)
break;
-
- mutex_lock(&mgr->lock);
- ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
- mst_state);
- mutex_unlock(&mgr->lock);
- if (ret < 0)
- break;
- else
- ret = 0;
}
return ret;
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 097c4204ffae4..0bbc9b0178f9b 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -903,6 +903,10 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr,
int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
struct drm_dp_query_stream_enc_status_ack_reply *status);
+int __must_check drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port);
int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);
int __must_check drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *new_conn_state,
struct drm_dp_mst_topology_mgr *mgr);
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v2 12/22] drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
@ 2023-08-24 8:05 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
Factor out a helper to check the atomic state for one MST topology
manager, returning the MST port where the BW limit check has failed.
This will be used in a follow-up patch by the i915 driver to improve the
BW sharing between MST streams.
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 93 +++++++++++++++----
include/drm/display/drm_dp_mst_helper.h | 4 +
2 files changed, 78 insertions(+), 19 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index ced9ae36a9177..6b1cbe2260a29 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5159,11 +5159,13 @@ EXPORT_SYMBOL(drm_dp_mst_port_downstream_of_parent);
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state);
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port);
static int
drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
struct drm_dp_mst_port *port;
@@ -5192,7 +5194,7 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
drm_dbg_atomic(mstb->mgr->dev, "[MSTB:%p] Checking bandwidth limits\n", mstb);
list_for_each_entry(port, &mstb->ports, next) {
- ret = drm_dp_mst_atomic_check_port_bw_limit(port, state);
+ ret = drm_dp_mst_atomic_check_port_bw_limit(port, state, failing_port);
if (ret < 0)
return ret;
@@ -5204,7 +5206,8 @@ drm_dp_mst_atomic_check_mstb_bw_limit(struct drm_dp_mst_branch *mstb,
static int
drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
- struct drm_dp_mst_topology_state *state)
+ struct drm_dp_mst_topology_state *state,
+ struct drm_dp_mst_port **failing_port)
{
struct drm_dp_mst_atomic_payload *payload;
int pbn_used = 0;
@@ -5225,13 +5228,15 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] no BW available for the port\n",
port->parent, port);
+ *failing_port = port;
return -EINVAL;
}
pbn_used = payload->pbn;
} else {
pbn_used = drm_dp_mst_atomic_check_mstb_bw_limit(port->mstb,
- state);
+ state,
+ failing_port);
if (pbn_used <= 0)
return pbn_used;
}
@@ -5240,6 +5245,7 @@ drm_dp_mst_atomic_check_port_bw_limit(struct drm_dp_mst_port *port,
drm_dbg_atomic(port->mgr->dev,
"[MSTB:%p] [MST PORT:%p] required PBN of %d exceeds port limit of %d\n",
port->parent, port, pbn_used, port->full_pbn);
+ *failing_port = port;
return -ENOSPC;
}
@@ -5417,20 +5423,79 @@ int drm_dp_mst_atomic_enable_dsc(struct drm_atomic_state *state,
}
EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
+/**
+ * drm_dp_mst_atomic_check_mgr - Check the atomic state of an MST topology manager
+ * @state: The global atomic state
+ * @mgr: Manager to check
+ * @mst_state: The MST atomic state for @mgr
+ * @failing_port: Returns the port with a BW limitation
+ *
+ * Checks the given MST manager's topology state for an atomic update to ensure
+ * that it's valid. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
+ *
+ * Any atomic drivers supporting DP MST must make sure to call this or
+ * the drm_dp_mst_atomic_check() function after checking the rest of their state
+ * in their &drm_mode_config_funcs.atomic_check() callback.
+ *
+ * See also:
+ * drm_dp_mst_atomic_check()
+ * drm_dp_atomic_find_time_slots()
+ * drm_dp_atomic_release_time_slots()
+ *
+ * Returns:
+ * - 0 if the new state is valid
+ * - %-ENOSPC, if the new state is invalid, because of BW limitation
+ * @failing_port is set to:
+ * - The non-root port where a BW limit check failed
+ * The returned port pointer is valid until at least
+ * one payload downstream of it exists.
+ * - %NULL if the BW limit check failed at the root port
+ * - %-EINVAL, if the new state is invalid, because the root port has
+ * too many payloads.
+ */
+int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port)
+{
+ int ret;
+
+ *failing_port = NULL;
+
+ if (!mgr->mst_state)
+ return 0;
+
+ ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ if (ret)
+ return ret;
+
+ mutex_lock(&mgr->lock);
+ ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
+ mst_state,
+ failing_port);
+ mutex_unlock(&mgr->lock);
+
+ return ret < 0 ? ret : 0;
+}
+EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
+
/**
* drm_dp_mst_atomic_check - Check that the new state of an MST topology in an
* atomic update is valid
* @state: Pointer to the new &struct drm_dp_mst_topology_state
*
* Checks the given topology state for an atomic update to ensure that it's
- * valid. This includes checking whether there's enough bandwidth to support
- * the new timeslot allocations in the atomic update.
+ * valid, calling drm_dp_mst_atomic_check_mgr() for all MST manager in the
+ * atomic state. This includes checking whether there's enough bandwidth to
+ * support the new timeslot allocations in the atomic update.
*
* Any atomic drivers supporting DP MST must make sure to call this after
* checking the rest of their state in their
* &drm_mode_config_funcs.atomic_check() callback.
*
* See also:
+ * drm_dp_mst_atomic_check_mgr()
* drm_dp_atomic_find_time_slots()
* drm_dp_atomic_release_time_slots()
*
@@ -5445,21 +5510,11 @@ int drm_dp_mst_atomic_check(struct drm_atomic_state *state)
int i, ret = 0;
for_each_new_mst_mgr_in_state(state, mgr, mst_state, i) {
- if (!mgr->mst_state)
- continue;
+ struct drm_dp_mst_port *tmp_port;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
+ ret = drm_dp_mst_atomic_check_mgr(state, mgr, mst_state, &tmp_port);
if (ret)
break;
-
- mutex_lock(&mgr->lock);
- ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
- mst_state);
- mutex_unlock(&mgr->lock);
- if (ret < 0)
- break;
- else
- ret = 0;
}
return ret;
diff --git a/include/drm/display/drm_dp_mst_helper.h b/include/drm/display/drm_dp_mst_helper.h
index 097c4204ffae4..0bbc9b0178f9b 100644
--- a/include/drm/display/drm_dp_mst_helper.h
+++ b/include/drm/display/drm_dp_mst_helper.h
@@ -903,6 +903,10 @@ int drm_dp_send_power_updown_phy(struct drm_dp_mst_topology_mgr *mgr,
int drm_dp_send_query_stream_enc_status(struct drm_dp_mst_topology_mgr *mgr,
struct drm_dp_mst_port *port,
struct drm_dp_query_stream_enc_status_ack_reply *status);
+int __must_check drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct drm_dp_mst_port **failing_port);
int __must_check drm_dp_mst_atomic_check(struct drm_atomic_state *state);
int __must_check drm_dp_mst_root_conn_atomic_check(struct drm_connector_state *new_conn_state,
struct drm_dp_mst_topology_mgr *mgr);
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 13/22] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:04 ` [Intel-gfx] [PATCH v2 02/22] drm/i915/dp: Track the pipe and link bpp limits separately Imre Deak
` (25 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting
from sink ports continuing towards the root port, so that drivers can
use the @failing_port returned to resolve a BW overallocation in an
ideal way. For instance from streams A,B,C in a topology A,B going
through @failing_port and C not going through it, a BW overallocation of
A,B due to a limit of the port must be resolved first before considering
the limits of other ports closer to the root port. This way can avoid
reducing the BW of stream C unnecessarily due to a BW limit closer to the
root port.
Based on the above swap the order of the BW check for the root port and
the check for all the ports downstream of it (the latter going through
the topology already in the sink->root port direction).
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 6b1cbe2260a29..e536ee1020741 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5448,9 +5448,13 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
* - %-ENOSPC, if the new state is invalid, because of BW limitation
* @failing_port is set to:
* - The non-root port where a BW limit check failed
+ * with all the ports downstream of @failing_port passing
+ * the BW limit check.
* The returned port pointer is valid until at least
* one payload downstream of it exists.
* - %NULL if the BW limit check failed at the root port
+ * with all the ports downstream of the root port passing
+ * the BW limit check.
* - %-EINVAL, if the new state is invalid, because the root port has
* too many payloads.
*/
@@ -5466,17 +5470,16 @@ int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
if (!mgr->mst_state)
return 0;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
- if (ret)
- return ret;
-
mutex_lock(&mgr->lock);
ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
mst_state,
failing_port);
mutex_unlock(&mgr->lock);
- return ret < 0 ? ret : 0;
+ if (ret < 0)
+ return ret;
+
+ return drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
}
EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [PATCH v2 13/22] drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
@ 2023-08-24 8:05 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx; +Cc: dri-devel
drm_dp_mst_atomic_check_mgr() should check for BW limitation starting
from sink ports continuing towards the root port, so that drivers can
use the @failing_port returned to resolve a BW overallocation in an
ideal way. For instance from streams A,B,C in a topology A,B going
through @failing_port and C not going through it, a BW overallocation of
A,B due to a limit of the port must be resolved first before considering
the limits of other ports closer to the root port. This way can avoid
reducing the BW of stream C unnecessarily due to a BW limit closer to the
root port.
Based on the above swap the order of the BW check for the root port and
the check for all the ports downstream of it (the latter going through
the topology already in the sink->root port direction).
Cc: Lyude Paul <lyude@redhat.com>
Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/display/drm_dp_mst_topology.c | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/display/drm_dp_mst_topology.c b/drivers/gpu/drm/display/drm_dp_mst_topology.c
index 6b1cbe2260a29..e536ee1020741 100644
--- a/drivers/gpu/drm/display/drm_dp_mst_topology.c
+++ b/drivers/gpu/drm/display/drm_dp_mst_topology.c
@@ -5448,9 +5448,13 @@ EXPORT_SYMBOL(drm_dp_mst_atomic_enable_dsc);
* - %-ENOSPC, if the new state is invalid, because of BW limitation
* @failing_port is set to:
* - The non-root port where a BW limit check failed
+ * with all the ports downstream of @failing_port passing
+ * the BW limit check.
* The returned port pointer is valid until at least
* one payload downstream of it exists.
* - %NULL if the BW limit check failed at the root port
+ * with all the ports downstream of the root port passing
+ * the BW limit check.
* - %-EINVAL, if the new state is invalid, because the root port has
* too many payloads.
*/
@@ -5466,17 +5470,16 @@ int drm_dp_mst_atomic_check_mgr(struct drm_atomic_state *state,
if (!mgr->mst_state)
return 0;
- ret = drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
- if (ret)
- return ret;
-
mutex_lock(&mgr->lock);
ret = drm_dp_mst_atomic_check_mstb_bw_limit(mgr->mst_primary,
mst_state,
failing_port);
mutex_unlock(&mgr->lock);
- return ret < 0 ? ret : 0;
+ if (ret < 0)
+ return ret;
+
+ return drm_dp_mst_atomic_check_payload_alloc_limits(mgr, mst_state);
}
EXPORT_SYMBOL(drm_dp_mst_atomic_check_mgr);
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 14/22] drm/i915/dp_mst: Fix PBN calculation with FEC overhead
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (12 preceding siblings ...)
2023-08-24 8:05 ` Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
` (12 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
On 8b/10b MST links the PBN value for DSC streams must be calculated
accounting for the FEC overhead. The same applies to 8b/10b non-DSC
streams if there is another DSC stream on the same link. Fix up the PBN
calculation accordingly.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 6eeb7dbf5ba67..930e16b870734 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -111,7 +111,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock,
dsc ? bpp << 4 : bpp,
dsc,
- false);
+ (dsc || crtc_state->fec_enable) &&
+ !intel_dp_is_uhbr(crtc_state));
slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr,
connector->port,
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Intel-gfx] [PATCH v2 15/22] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (13 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 14/22] drm/i915/dp_mst: Fix PBN calculation with FEC overhead Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
` (11 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
If an MST stream is modeset, its state must be checked along all the
other streams on the same MST link, for instance to resolve a BW
overallocation of a non-sink MST port or to make sure that the FEC is
enabled/disabled the same way for all these streams.
To prepare for that this patch adds all the stream CRTCs to the atomic
state and marks them for modeset similarly to tgl+ platforms. (If the
state computation doesn't change the state the CRTC is switched back to
fastset mode.)
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 930e16b870734..fba91d0fd33dc 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -507,9 +507,6 @@ intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector,
struct intel_connector *connector_iter;
int ret = 0;
- if (DISPLAY_VER(dev_priv) < 12)
- return 0;
-
if (!intel_connector_needs_modeset(state, &connector->base))
return 0;
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Intel-gfx] [PATCH v2 16/22] drm/i915/dp_mst: Program the DSC PPS SDP for each stream
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (14 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 15/22] drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
` (10 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
Atm the DSC PPS SDP is programmed only if the first stream is compressed
and then it's programmed only for the first stream. This left all other
compressed streams blank. Program the SDP for all streams.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_ddi.c | 12 +++++++-----
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index b7f4281b86584..4d0f1b23ee162 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -2505,7 +2505,8 @@ static void mtl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 6.o Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (!is_mst)
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2643,7 +2644,8 @@ static void tgl_ddi_pre_enable_dp(struct intel_atomic_state *state,
/* 7.l Configure and enable FEC if needed */
intel_ddi_enable_fec(encoder, crtc_state);
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ if (!is_mst)
+ intel_dsc_dp_pps_write(encoder, crtc_state);
}
static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
@@ -2705,10 +2707,10 @@ static void hsw_ddi_pre_enable_dp(struct intel_atomic_state *state,
intel_ddi_enable_fec(encoder, crtc_state);
- if (!is_mst)
+ if (!is_mst) {
intel_ddi_enable_transcoder_clock(encoder, crtc_state);
-
- intel_dsc_dp_pps_write(encoder, crtc_state);
+ intel_dsc_dp_pps_write(encoder, crtc_state);
+ }
}
static void intel_ddi_pre_enable_dp(struct intel_atomic_state *state,
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index fba91d0fd33dc..b6a717566e7c8 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -43,6 +43,7 @@
#include "intel_dpio_phy.h"
#include "intel_hdcp.h"
#include "intel_hotplug.h"
+#include "intel_vdsc.h"
#include "skl_scaler.h"
static int intel_dp_mst_check_constraints(struct drm_i915_private *i915, int bpp,
@@ -785,6 +786,7 @@ static void intel_mst_pre_enable_dp(struct intel_atomic_state *state,
if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream)
intel_ddi_enable_transcoder_clock(encoder, pipe_config);
+ intel_dsc_dp_pps_write(&dig_port->base, pipe_config);
intel_ddi_set_dp_msa(pipe_config, conn_state);
}
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Intel-gfx] [PATCH v2 17/22] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (15 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 16/22] drm/i915/dp_mst: Program the DSC PPS SDP for each stream Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/dp_mst: Enable DSC decompression if any stream needs this Imre Deak
` (9 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
Atm the DSC PPS SDP will stay enabled after enabling and disabling DSC.
This leaves an output blank after switching off DSC on it. Make sure the
SDP is disabled for an uncompressed output.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_vdsc.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_vdsc.c b/drivers/gpu/drm/i915/display/intel_vdsc.c
index e4c395b4dc46a..2900a9d2bb788 100644
--- a/drivers/gpu/drm/i915/display/intel_vdsc.c
+++ b/drivers/gpu/drm/i915/display/intel_vdsc.c
@@ -908,9 +908,15 @@ void intel_dsc_dsi_pps_write(struct intel_encoder *encoder,
void intel_dsc_dp_pps_write(struct intel_encoder *encoder,
const struct intel_crtc_state *crtc_state)
{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
const struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config;
struct drm_dsc_pps_infoframe dp_dsc_pps_sdp;
+ i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder);
+ u32 val = intel_de_read(dev_priv, reg) & ~VDIP_ENABLE_PPS;
+
+ intel_de_write(dev_priv, reg, val);
+ intel_de_posting_read(dev_priv, reg);
if (!crtc_state->dsc.compression_enable)
return;
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Intel-gfx] [PATCH v2 18/22] drm/i915/dp_mst: Enable DSC decompression if any stream needs this
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (16 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 17/22] drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 9:31 ` Lisovskiy, Stanislav
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
` (8 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
Atm DSC decompression is enabled in the sink only if the first stream is
compressed. This left compressed streams blank if the first stream was
uncompressed.
Enable decompression whenever FEC is enabled, which will be true for all
streams if any stream is compressed. Enabling FEC correctly in all
streams will be only fixed by an upcoming patch.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index 48f005932ad8b..e5b1567d2a9d4 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2907,7 +2907,13 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
int ret;
- if (!crtc_state->dsc.compression_enable)
+ /*
+ * In case of MST any stream can be compressed not just the first. If
+ * any stream is compressed FEC will be enabled in all streams, so toggle
+ * decompression whenever FEC is enabled.
+ */
+ if (!crtc_state->dsc.compression_enable &&
+ !crtc_state->fec_enable)
return;
ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 18/22] drm/i915/dp_mst: Enable DSC decompression if any stream needs this
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/dp_mst: Enable DSC decompression if any stream needs this Imre Deak
@ 2023-08-24 9:31 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 60+ messages in thread
From: Lisovskiy, Stanislav @ 2023-08-24 9:31 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:05:13AM +0300, Imre Deak wrote:
> Atm DSC decompression is enabled in the sink only if the first stream is
> compressed. This left compressed streams blank if the first stream was
> uncompressed.
>
> Enable decompression whenever FEC is enabled, which will be true for all
> streams if any stream is compressed. Enabling FEC correctly in all
> streams will be only fixed by an upcoming patch.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp.c | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
> index 48f005932ad8b..e5b1567d2a9d4 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2907,7 +2907,13 @@ void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp,
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> int ret;
>
> - if (!crtc_state->dsc.compression_enable)
> + /*
> + * In case of MST any stream can be compressed not just the first. If
> + * any stream is compressed FEC will be enabled in all streams, so toggle
> + * decompression whenever FEC is enabled.
> + */
> + if (!crtc_state->dsc.compression_enable &&
> + !crtc_state->fec_enable)
> return;
>
> ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE,
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (17 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 18/22] drm/i915/dp_mst: Enable DSC decompression if any stream needs this Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 9:44 ` Lisovskiy, Stanislav
2023-09-11 12:29 ` Lisovskiy, Stanislav
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device Imre Deak
` (7 subsequent siblings)
26 siblings, 2 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
Add the missing DSC compression disabling step for MST streams,
similarly to how this is done for SST outputs.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index b6a717566e7c8..5eaf309f852f2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -656,6 +656,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
intel_ddi_disable_transcoder_func(old_crtc_state);
+ intel_dsc_disable(old_crtc_state);
+
if (DISPLAY_VER(dev_priv) >= 9)
skl_scaler_disable(old_crtc_state);
else
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
@ 2023-08-24 9:44 ` Lisovskiy, Stanislav
2023-08-24 10:37 ` Imre Deak
2023-09-11 12:29 ` Lisovskiy, Stanislav
1 sibling, 1 reply; 60+ messages in thread
From: Lisovskiy, Stanislav @ 2023-08-24 9:44 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:05:14AM +0300, Imre Deak wrote:
> Add the missing DSC compression disabling step for MST streams,
> similarly to how this is done for SST outputs.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index b6a717566e7c8..5eaf309f852f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -656,6 +656,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
>
> intel_ddi_disable_transcoder_func(old_crtc_state);
>
> + intel_dsc_disable(old_crtc_state);
> +
One thing that a bit I'm a bit concerned is that whether won't it conflict
with that intel_ddi_post_disable hook called for the last mst stream?
I see that it also calls intel_dsc_disable, however there is !mst check first,
however for Bigjoiner case, there is no such check.
Wondering should we add it there?..
> if (DISPLAY_VER(dev_priv) >= 9)
> skl_scaler_disable(old_crtc_state);
> else
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling
2023-08-24 9:44 ` Lisovskiy, Stanislav
@ 2023-08-24 10:37 ` Imre Deak
0 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 10:37 UTC (permalink / raw)
To: Lisovskiy, Stanislav; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 12:44:16PM +0300, Lisovskiy, Stanislav wrote:
> On Thu, Aug 24, 2023 at 11:05:14AM +0300, Imre Deak wrote:
> > Add the missing DSC compression disabling step for MST streams,
> > similarly to how this is done for SST outputs.
> >
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
> > 1 file changed, 2 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > index b6a717566e7c8..5eaf309f852f2 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> > @@ -656,6 +656,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
> >
> > intel_ddi_disable_transcoder_func(old_crtc_state);
> >
> > + intel_dsc_disable(old_crtc_state);
> > +
>
> One thing that a bit I'm a bit concerned is that whether won't it conflict
> with that intel_ddi_post_disable hook called for the last mst stream?
>
> I see that it also calls intel_dsc_disable, however there is !mst check first,
> however for Bigjoiner case, there is no such check.
> Wondering should we add it there?..
Right, I wondered about the same thing. However bigjoiner wouldn't be
enabled for MST streams; not sure if that's possible at all or what all
would be required to enable it. So, I just left that as-is.
>
> > if (DISPLAY_VER(dev_priv) >= 9)
> > skl_scaler_disable(old_crtc_state);
> > else
> > --
> > 2.37.2
> >
^ permalink raw reply [flat|nested] 60+ messages in thread
* Re: [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
2023-08-24 9:44 ` Lisovskiy, Stanislav
@ 2023-09-11 12:29 ` Lisovskiy, Stanislav
1 sibling, 0 replies; 60+ messages in thread
From: Lisovskiy, Stanislav @ 2023-09-11 12:29 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:05:14AM +0300, Imre Deak wrote:
> Add the missing DSC compression disabling step for MST streams,
> similarly to how this is done for SST outputs.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index b6a717566e7c8..5eaf309f852f2 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -656,6 +656,8 @@ static void intel_mst_post_disable_dp(struct intel_atomic_state *state,
>
> intel_ddi_disable_transcoder_func(old_crtc_state);
>
> + intel_dsc_disable(old_crtc_state);
> +
> if (DISPLAY_VER(dev_priv) >= 9)
> skl_scaler_disable(old_crtc_state);
> else
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] [PATCH v2 20/22] drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (18 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 19/22] drm/i915/dp_mst: Add missing DSC compression disabling Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
` (6 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
Atm the driver supports DSC on MST links only by enabling it globally in
the first branch device UFP's physical DPCD (vs. enabling it per-stream
in the virtual DPCD right upstream the DPRX). This means the branch
device will decompress any compressed stream (which it recognizes via
MSA / SDP compression info), but it does this only for streams going to
an SST output port. Accordingly allow DSC only for streams going to an
SST output port of the first branch device.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 26 +++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 5eaf309f852f2..97bf55f289478 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -349,6 +349,27 @@ intel_dp_mst_compute_config_limits(struct intel_dp *intel_dp,
limits);
}
+static bool intel_dp_mst_port_supports_dsc(struct intel_dp *intel_dp,
+ struct intel_crtc_state *crtc_state,
+ struct drm_connector_state *conn_state)
+{
+ struct drm_i915_private *i915 = dp_to_i915(intel_dp);
+ struct intel_connector *connector =
+ to_intel_connector(conn_state->connector);
+ struct intel_crtc *crtc =
+ to_intel_crtc(crtc_state->uapi.crtc);
+
+ if (connector->port->parent != intel_dp->mst_mgr.mst_primary) {
+ drm_dbg_kms(&i915->drm,
+ "[CRTC:%d:%s] DSC only allowed on sink ports of the first branch device\n",
+ crtc->base.base.id, crtc->base.name);
+
+ return false;
+ }
+
+ return true;
+}
+
static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
struct intel_crtc_state *pipe_config,
struct drm_connector_state *conn_state)
@@ -396,6 +417,11 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
str_yes_no(ret),
str_yes_no(intel_dp->force_dsc_en));
+ if (!intel_dp_mst_port_supports_dsc(intel_dp,
+ pipe_config,
+ conn_state))
+ return -EINVAL;
+
if (!intel_dp_mst_compute_config_limits(intel_dp,
pipe_config,
true,
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Intel-gfx] [PATCH v2 21/22] drm/i915/dp_mst: Improve BW sharing between MST streams
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (19 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 20/22] drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
` (5 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
At the moment modesetting a stream CRTC will fail if the stream's BW
along with the current BW of all the other streams on the same MST link
is above the total BW of the MST link. Make the BW sharing more dynamic
by trying to reduce the link bpp of one or more streams on the MST link
in this case.
When selecting a stream to reduce the BW for, take into account which
link segment in the MST topology ran out of BW and which streams go
through this link segment. For instance with A,B,C streams in the same
MST topology A and B may share the BW of a link segment downstream of a
branch device, stream C not downstream of the branch device, hence not
affecting this BW. If this link segment's BW runs out one or both of
stream A/B's BW will be reduced until their total BW is within limits.
While reducing the link bpp for a given stream DSC may need to be
enabled for it, which requires FEC on the whole MST link. Check for this
condition and recompute the state for all streams taking the FEC
overhead into account (on 8b/10b links).
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_atomic.c | 14 +-
drivers/gpu/drm/i915/display/intel_display.c | 5 +-
.../drm/i915/display/intel_display_types.h | 1 +
drivers/gpu/drm/i915/display/intel_dp.c | 13 +-
drivers/gpu/drm/i915/display/intel_dp.h | 2 +
drivers/gpu/drm/i915/display/intel_dp_mst.c | 128 ++++++++++++++++++
drivers/gpu/drm/i915/display/intel_dp_mst.h | 3 +
7 files changed, 156 insertions(+), 10 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_atomic.c b/drivers/gpu/drm/i915/display/intel_atomic.c
index ee4cbf80ddb55..743c3afbdb822 100644
--- a/drivers/gpu/drm/i915/display/intel_atomic.c
+++ b/drivers/gpu/drm/i915/display/intel_atomic.c
@@ -38,6 +38,7 @@
#include "intel_atomic.h"
#include "intel_cdclk.h"
#include "intel_display_types.h"
+#include "intel_dp_mst.h"
#include "intel_fdi.h"
#include "intel_global_state.h"
#include "intel_hdcp.h"
@@ -458,7 +459,7 @@ static int intel_atomic_check_link(struct intel_atomic_state *state,
if (ret)
return ret;
- return 0;
+ return intel_dp_mst_atomic_check_link(state, limits);
}
static bool
@@ -469,6 +470,12 @@ assert_link_limit_change_valid(struct drm_i915_private *i915,
bool bpps_changed = false;
enum pipe pipe;
+ /* FEC can't be forced off after it was forced on. */
+ if (drm_WARN_ON(&i915->drm,
+ (old_limits->force_fec_pipes & new_limits->force_fec_pipes) !=
+ old_limits->force_fec_pipes))
+ return false;
+
for_each_pipe(i915, pipe) {
/* The bpp limit can only decrease. */
if (drm_WARN_ON(&i915->drm,
@@ -481,8 +488,11 @@ assert_link_limit_change_valid(struct drm_i915_private *i915,
bpps_changed = true;
}
+ /* At least one limit must change. */
if (drm_WARN_ON(&i915->drm,
- !bpps_changed))
+ !bpps_changed &&
+ new_limits->force_fec_pipes ==
+ old_limits->force_fec_pipes))
return false;
return true;
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 32778bd01bb05..1200a9d9d29f1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -4673,6 +4673,7 @@ intel_modeset_pipe_config(struct intel_atomic_state *state,
if (ret)
return ret;
+ crtc_state->fec_enable = limits->force_fec_pipes & BIT(crtc->pipe);
crtc_state->max_link_bpp_x16 = limits->max_bpp_x16[crtc->pipe];
if (crtc_state->pipe_bpp > to_bpp_int(crtc_state->max_link_bpp_x16)) {
@@ -6384,10 +6385,6 @@ int intel_atomic_check(struct drm_device *dev,
goto fail;
}
- ret = drm_dp_mst_atomic_check(&state->base);
- if (ret)
- goto fail;
-
ret = intel_atomic_check_planes(state);
if (ret)
goto fail;
diff --git a/drivers/gpu/drm/i915/display/intel_display_types.h b/drivers/gpu/drm/i915/display/intel_display_types.h
index 6f4f46658df22..f5a0fcc340aa1 100644
--- a/drivers/gpu/drm/i915/display/intel_display_types.h
+++ b/drivers/gpu/drm/i915/display/intel_display_types.h
@@ -67,6 +67,7 @@ struct intel_tc_port;
*/
struct intel_link_bw_limits {
+ u8 force_fec_pipes;
u8 min_bpp_pipes;
/* in 1/16 bpp units */
int max_bpp_x16[I915_MAX_PIPES];
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e5b1567d2a9d4..3896532ab670f 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -1369,8 +1369,8 @@ static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp,
return false;
}
-static bool intel_dp_supports_fec(struct intel_dp *intel_dp,
- const struct intel_crtc_state *pipe_config)
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config)
{
return intel_dp_source_supports_fec(intel_dp, pipe_config) &&
drm_dp_sink_supports_fec(intel_dp->fec_capable);
@@ -2110,8 +2110,9 @@ int intel_dp_dsc_compute_config(struct intel_dp *intel_dp,
&pipe_config->hw.adjusted_mode;
int ret;
- pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) &&
- intel_dp_supports_fec(intel_dp, pipe_config);
+ pipe_config->fec_enable = pipe_config->fec_enable ||
+ (!intel_dp_is_edp(intel_dp) &&
+ intel_dp_supports_fec(intel_dp, pipe_config));
if (!intel_dp_supports_dsc(intel_dp, pipe_config))
return -EINVAL;
@@ -2303,6 +2304,10 @@ intel_dp_compute_link_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
+ if (pipe_config->fec_enable &&
+ !intel_dp_supports_fec(intel_dp, pipe_config))
+ return -EINVAL;
+
if (intel_dp_need_bigjoiner(intel_dp, adjusted_mode->crtc_hdisplay,
adjusted_mode->crtc_clock))
pipe_config->bigjoiner_pipes = GENMASK(crtc->pipe + 1, crtc->pipe);
diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h
index 0b8a4bbef8f7d..29b46181fe64e 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.h
+++ b/drivers/gpu/drm/i915/display/intel_dp.h
@@ -132,6 +132,8 @@ static inline unsigned int intel_dp_unused_lane_mask(int lane_count)
return ~((1 << lane_count) - 1) & 0xf;
}
+bool intel_dp_supports_fec(struct intel_dp *intel_dp,
+ const struct intel_crtc_state *pipe_config);
u32 intel_dp_mode_to_fec_clock(u32 mode_clock);
u32 intel_dp_dsc_nearest_valid_bpp(struct drm_i915_private *i915, u32 bpp, u32 pipe_bpp);
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 97bf55f289478..3c9b3a2ac88a2 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -383,6 +383,10 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder,
bool dsc_needed;
int ret = 0;
+ if (pipe_config->fec_enable &&
+ !intel_dp_supports_fec(intel_dp, pipe_config))
+ return -EINVAL;
+
if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)
return -EINVAL;
@@ -504,6 +508,130 @@ intel_dp_mst_transcoder_mask(struct intel_atomic_state *state,
return transcoders;
}
+static u8 get_pipes_downstream_of_mst_port(struct intel_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mst_mgr,
+ struct drm_dp_mst_port *parent_port)
+{
+ const struct intel_digital_connector_state *conn_state;
+ struct intel_connector *connector;
+ u8 mask = 0;
+ int i;
+
+ for_each_new_intel_connector_in_state(state, connector, conn_state, i) {
+ if (!conn_state->base.crtc)
+ continue;
+
+ if (&connector->mst_port->mst_mgr != mst_mgr)
+ continue;
+
+ if (connector->port != parent_port &&
+ !drm_dp_mst_port_downstream_of_parent(mst_mgr,
+ connector->port,
+ parent_port))
+ continue;
+
+ mask |= BIT(to_intel_crtc(conn_state->base.crtc)->pipe);
+ }
+
+ return mask;
+}
+
+static int intel_dp_mst_check_fec_change(struct intel_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mst_mgr,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_i915_private *i915 = to_i915(state->base.dev);
+ struct intel_crtc *crtc;
+ u8 mst_pipe_mask;
+ u8 fec_pipe_mask = 0;
+ int ret;
+
+ mst_pipe_mask = get_pipes_downstream_of_mst_port(state, mst_mgr, NULL);
+
+ for_each_intel_crtc_in_pipe_mask(&i915->drm, crtc, mst_pipe_mask) {
+ struct intel_crtc_state *crtc_state =
+ intel_atomic_get_new_crtc_state(state, crtc);
+
+ /* Atomic connector check should've added all the MST CRTCs. */
+ if (drm_WARN_ON(&i915->drm, !crtc_state))
+ return -EINVAL;
+
+ if (crtc_state->fec_enable)
+ fec_pipe_mask |= BIT(crtc->pipe);
+ }
+
+ if (!fec_pipe_mask || mst_pipe_mask == fec_pipe_mask)
+ return 0;
+
+ limits->force_fec_pipes |= mst_pipe_mask;
+
+ ret = intel_modeset_pipes_in_mask(state, "MST FEC",
+ mst_pipe_mask, false);
+
+ return ret ? : -EAGAIN;
+}
+
+static int intel_dp_mst_check_bw(struct intel_atomic_state *state,
+ struct drm_dp_mst_topology_mgr *mst_mgr,
+ struct drm_dp_mst_topology_state *mst_state,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_dp_mst_port *mst_port;
+ u8 mst_port_pipes;
+ int ret;
+
+ ret = drm_dp_mst_atomic_check_mgr(&state->base, mst_mgr, mst_state, &mst_port);
+ if (ret != -ENOSPC)
+ return ret;
+
+ mst_port_pipes = get_pipes_downstream_of_mst_port(state, mst_mgr, mst_port);
+
+ ret = intel_atomic_reduce_link_bpp(state, limits,
+ mst_port_pipes, "MST link BW");
+
+ return ret ? : -EAGAIN;
+}
+
+/**
+ * intel_dp_mst_atomic_check_link - check all modeset MST link configuration
+ * @state: intel atomic state
+ * @limits: link BW limits
+ *
+ * Check the link configuration for all modeset MST outputs. If the
+ * configuration is invalid @limits will be updated if possible to
+ * reduce the total BW, after which the configuration for all CRTCs in
+ * @state must be recomputed with the updated @limits.
+ *
+ * Returns:
+ * - 0 if the confugration is valid
+ * - %-EAGAIN, if the configuration is invalid and @limits got updated
+ * with fallback values with which the configuration of all CRTCs in
+ * @state must be recomputed
+ * - Other negative error, if the configuration is invalid without a
+ * fallback possibility, or the check failed for another reason
+ */
+int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits)
+{
+ struct drm_dp_mst_topology_mgr *mgr;
+ struct drm_dp_mst_topology_state *mst_state;
+ int ret;
+ int i;
+
+ for_each_new_mst_mgr_in_state(&state->base, mgr, mst_state, i) {
+ ret = intel_dp_mst_check_fec_change(state, mgr, limits);
+ if (ret)
+ return ret;
+
+ ret = intel_dp_mst_check_bw(state, mgr, mst_state,
+ limits);
+ if (ret)
+ return ret;
+ }
+
+ return 0;
+}
+
static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder,
struct intel_crtc_state *crtc_state,
struct drm_connector_state *conn_state)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.h b/drivers/gpu/drm/i915/display/intel_dp_mst.h
index f1815bb722672..4e836b9ac6061 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.h
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.h
@@ -13,6 +13,7 @@ struct intel_crtc;
struct intel_crtc_state;
struct intel_digital_port;
struct intel_dp;
+struct intel_link_bw_limits;
int intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port);
@@ -22,5 +23,7 @@ bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state);
bool intel_dp_mst_source_support(struct intel_dp *intel_dp);
int intel_dp_mst_add_topology_state_for_crtc(struct intel_atomic_state *state,
struct intel_crtc *crtc);
+int intel_dp_mst_atomic_check_link(struct intel_atomic_state *state,
+ struct intel_link_bw_limits *limits);
#endif /* __INTEL_DP_MST_H__ */
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* [Intel-gfx] [PATCH v2 22/22] drm/i915/dp_mst: Check BW limitations only after all streams are computed
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (20 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 21/22] drm/i915/dp_mst: Improve BW sharing between MST streams Imre Deak
@ 2023-08-24 8:05 ` Imre Deak
2023-09-25 7:46 ` Lisovskiy, Stanislav
2023-08-24 9:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev2) Patchwork
` (4 subsequent siblings)
26 siblings, 1 reply; 60+ messages in thread
From: Imre Deak @ 2023-08-24 8:05 UTC (permalink / raw)
To: intel-gfx
After the previous patch the BW limits on the whole MST topology will be
checked after computing the state for all the streams in the topology.
Accordingly remove the check during the stream's encoder compute config
step, to prevent failing an atomic commit due to a BW limit, if this can
be resolved only by reducing the BW of other streams on the same MST
link.
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ++---------
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
index 3c9b3a2ac88a2..1d6d0fe6c3047 100644
--- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
+++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
@@ -121,15 +121,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
if (slots == -EDEADLK)
return slots;
- if (slots >= 0) {
- ret = drm_dp_mst_atomic_check(state);
- /*
- * If we got slots >= 0 and we can fit those based on check
- * then we can exit the loop. Otherwise keep trying.
- */
- if (!ret)
- break;
- }
+ if (slots >= 0)
+ break;
}
/* We failed to find a proper bpp/timeslots, return error */
--
2.37.2
^ permalink raw reply related [flat|nested] 60+ messages in thread* Re: [Intel-gfx] [PATCH v2 22/22] drm/i915/dp_mst: Check BW limitations only after all streams are computed
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
@ 2023-09-25 7:46 ` Lisovskiy, Stanislav
0 siblings, 0 replies; 60+ messages in thread
From: Lisovskiy, Stanislav @ 2023-09-25 7:46 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
On Thu, Aug 24, 2023 at 11:05:17AM +0300, Imre Deak wrote:
> After the previous patch the BW limits on the whole MST topology will be
> checked after computing the state for all the streams in the topology.
> Accordingly remove the check during the stream's encoder compute config
> step, to prevent failing an atomic commit due to a BW limit, if this can
> be resolved only by reducing the BW of other streams on the same MST
> link.
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com>
> ---
> drivers/gpu/drm/i915/display/intel_dp_mst.c | 11 ++---------
> 1 file changed, 2 insertions(+), 9 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> index 3c9b3a2ac88a2..1d6d0fe6c3047 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c
> @@ -121,15 +121,8 @@ static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder,
> if (slots == -EDEADLK)
> return slots;
>
> - if (slots >= 0) {
> - ret = drm_dp_mst_atomic_check(state);
> - /*
> - * If we got slots >= 0 and we can fit those based on check
> - * then we can exit the loop. Otherwise keep trying.
> - */
> - if (!ret)
> - break;
> - }
> + if (slots >= 0)
> + break;
> }
>
> /* We failed to find a proper bpp/timeslots, return error */
> --
> 2.37.2
>
^ permalink raw reply [flat|nested] 60+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev2)
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (21 preceding siblings ...)
2023-08-24 8:05 ` [Intel-gfx] [PATCH v2 22/22] drm/i915/dp_mst: Check BW limitations only after all streams are computed Imre Deak
@ 2023-08-24 9:54 ` Patchwork
2023-08-24 9:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (3 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Patchwork @ 2023-08-24 9:54 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev2)
URL : https://patchwork.freedesktop.org/series/122589/
State : warning
== Summary ==
Error: dim checkpatch failed
/home/kbuild2/linux/maintainer-tools/dim: line 50: /home/kbuild2/.dimrc: No such file or directory
^ permalink raw reply [flat|nested] 60+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Improve BW management on shared display links (rev2)
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (22 preceding siblings ...)
2023-08-24 9:54 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Improve BW management on shared display links (rev2) Patchwork
@ 2023-08-24 9:54 ` Patchwork
2023-08-24 10:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
26 siblings, 0 replies; 60+ messages in thread
From: Patchwork @ 2023-08-24 9:54 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev2)
URL : https://patchwork.freedesktop.org/series/122589/
State : warning
== Summary ==
Error: dim sparse failed
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 60+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Improve BW management on shared display links (rev2)
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (23 preceding siblings ...)
2023-08-24 9:54 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2023-08-24 10:07 ` Patchwork
2023-08-24 17:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-09-04 7:14 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve BW management on shared display links (rev3) Patchwork
26 siblings, 0 replies; 60+ messages in thread
From: Patchwork @ 2023-08-24 10:07 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 6463 bytes --]
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev2)
URL : https://patchwork.freedesktop.org/series/122589/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_13559 -> Patchwork_122589v2
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/index.html
Participating hosts (39 -> 39)
------------------------------
Additional (1): fi-tgl-1115g4
Missing (1): fi-snb-2520m
Known issues
------------
Here are the changes found in Patchwork_122589v2 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- fi-tgl-1115g4: NOTRUN -> [SKIP][1] ([i915#7456])
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/fi-tgl-1115g4/igt@debugfs_test@basic-hwmon.html
* igt@gem_huc_copy@huc-copy:
- fi-tgl-1115g4: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/fi-tgl-1115g4/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-tgl-1115g4: NOTRUN -> [SKIP][3] ([i915#4613]) +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/fi-tgl-1115g4/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@i915_pm_backlight@basic-brightness:
- fi-tgl-1115g4: NOTRUN -> [SKIP][4] ([i915#3546] / [i915#7561])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/fi-tgl-1115g4/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_suspend@basic-s3-without-i915:
- fi-tgl-1115g4: NOTRUN -> [INCOMPLETE][5] ([i915#7443] / [i915#8102])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/fi-tgl-1115g4/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-1115g4: NOTRUN -> [SKIP][6] ([i915#4103]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/fi-tgl-1115g4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-tgl-1115g4: NOTRUN -> [SKIP][7] ([fdo#109285])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/fi-tgl-1115g4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1:
- bat-rplp-1: [PASS][8] -> [ABORT][9] ([i915#8442] / [i915#8668])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/bat-rplp-1/igt@kms_pipe_crc_basic@read-crc-frame-sequence@pipe-d-edp-1.html
* igt@kms_psr@cursor_plane_move:
- fi-tgl-1115g4: NOTRUN -> [SKIP][10] ([fdo#110189]) +3 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/fi-tgl-1115g4/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-1115g4: NOTRUN -> [SKIP][11] ([i915#3555])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/fi-tgl-1115g4/igt@kms_setmode@basic-clone-single-crtc.html
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#7443]: https://gitlab.freedesktop.org/drm/intel/issues/7443
[i915#7456]: https://gitlab.freedesktop.org/drm/intel/issues/7456
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#8102]: https://gitlab.freedesktop.org/drm/intel/issues/8102
[i915#8442]: https://gitlab.freedesktop.org/drm/intel/issues/8442
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
Build changes
-------------
* Linux: CI_DRM_13559 -> Patchwork_122589v2
CI-20190529: 20190529
CI_DRM_13559: 2e6e7e62e019d89689eb44307fcc07f2c59e9b01 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7451: 5d48d1fb231f449fe2f80cda14ea7a1ecfda59fa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_122589v2: 2e6e7e62e019d89689eb44307fcc07f2c59e9b01 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
e3478c50e968 drm/i915/dp_mst: Check BW limitations only after all streams are computed
700a29615b43 drm/i915/dp_mst: Improve BW sharing between MST streams
84e2b6789606 drm/i915/dp_mst: Allow DSC only for sink ports of the first branch device
208883f49eca drm/i915/dp_mst: Add missing DSC compression disabling
1429dea9970a drm/i915/dp_mst: Enable DSC decompression if any stream needs this
720aea68d0b8 drm/i915/dp: Make sure the DSC PPS SDP is disabled whenever DSC is disabled
b811e10ece42 drm/i915/dp_mst: Program the DSC PPS SDP for each stream
8cfd941097a8 drm/i915/dp_mst: Add atomic state for all streams on pre-tgl platforms
e2abf4c73d92 drm/i915/dp_mst: Fix PBN calculation with FEC overhead
ace2416aad2d drm/dp_mst: Swap the order of checking root vs. non-root port BW limitations
9bafd9e9afe2 drm/dp_mst: Factor out a helper to check the atomic state of a topology manager
440743b441a5 drm/dp_mst: Add helper to determine if an MST port is downstream of another port
f72a472cce7f drm/dp_mst: Add a way to calculate PBN values with FEC overhead
624222638024 drm/dp_mst: Fix fractional bpp scaling in drm_dp_calc_pbn_mode()
97aecb8ea0f3 drm/i915/fdi: Improve FDI BW sharing between pipe B and C
176ff291481f drm/i915: Factor out a helper to check/compute all the CRTC states
4e02241b9a81 drm/i915: Add helper to modeset a set of pipes
bcfeef839b83 drm/i915/dp: Limit the output link bpp in DSC mode
6b6ff443f6e5 drm/i915/dp: Update the link bpp limits for DSC mode
0e4fa365aa01 drm/i915/dp: Skip computing a non-DSC link config if DSC is needed
cc61b1ccd329 drm/i915/dp: Track the pipe and link bpp limits separately
2f0b0efb6c70 drm/i915/dp: Factor out helpers to compute the link limits
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/index.html
[-- Attachment #2: Type: text/html, Size: 7436 bytes --]
^ permalink raw reply [flat|nested] 60+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Improve BW management on shared display links (rev2)
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (24 preceding siblings ...)
2023-08-24 10:07 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2023-08-24 17:54 ` Patchwork
2023-09-04 7:14 ` [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve BW management on shared display links (rev3) Patchwork
26 siblings, 0 replies; 60+ messages in thread
From: Patchwork @ 2023-08-24 17:54 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 50369 bytes --]
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev2)
URL : https://patchwork.freedesktop.org/series/122589/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13559_full -> Patchwork_122589v2_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_122589v2_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_122589v2_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (10 -> 9)
------------------------------
Missing (1): shard-rkl0
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_122589v2_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-rkl: [PASS][1] -> [ABORT][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-rkl-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
Known issues
------------
Here are the changes found in Patchwork_122589v2_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@api_intel_bb@blit-reloc-keep-cache:
- shard-dg2: NOTRUN -> [SKIP][3] ([i915#8411])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@api_intel_bb@blit-reloc-keep-cache.html
* igt@device_reset@cold-reset-bound:
- shard-dg2: NOTRUN -> [SKIP][4] ([i915#7701])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@device_reset@cold-reset-bound.html
* igt@drm_fdinfo@all-busy-idle-check-all:
- shard-dg2: NOTRUN -> [SKIP][5] ([i915#8414]) +1 similar issue
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@drm_fdinfo@all-busy-idle-check-all.html
* igt@drm_fdinfo@most-busy-idle-check-all@rcs0:
- shard-rkl: [PASS][6] -> [FAIL][7] ([i915#7742])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-rkl-6/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-2/igt@drm_fdinfo@most-busy-idle-check-all@rcs0.html
* igt@feature_discovery@display-3x:
- shard-dg2: NOTRUN -> [SKIP][8] ([i915#1839])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@feature_discovery@display-3x.html
* igt@gem_busy@semaphore:
- shard-dg2: NOTRUN -> [SKIP][9] ([i915#3936])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@gem_busy@semaphore.html
* igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-lmem0-lmem0:
- shard-dg2: [PASS][10] -> [INCOMPLETE][11] ([i915#6311] / [i915#7297])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg2-12/igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-lmem0-lmem0.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-2/igt@gem_ccs@suspend-resume@tile64-compressed-compfmt0-lmem0-lmem0.html
* igt@gem_ctx_sseu@invalid-args:
- shard-dg2: NOTRUN -> [SKIP][12] ([i915#280])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@gem_ctx_sseu@invalid-args.html
* igt@gem_eio@hibernate:
- shard-dg2: [PASS][13] -> [ABORT][14] ([i915#7975] / [i915#8213])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg2-11/igt@gem_eio@hibernate.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-12/igt@gem_eio@hibernate.html
- shard-rkl: NOTRUN -> [ABORT][15] ([i915#7975] / [i915#8213])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-7/igt@gem_eio@hibernate.html
* igt@gem_exec_balancer@bonded-dual:
- shard-dg2: NOTRUN -> [SKIP][16] ([i915#4771])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@gem_exec_balancer@bonded-dual.html
* igt@gem_exec_balancer@bonded-true-hang:
- shard-dg2: NOTRUN -> [SKIP][17] ([i915#4812]) +1 similar issue
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@gem_exec_balancer@bonded-true-hang.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-glk: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-glk1/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-glk: [PASS][19] -> [FAIL][20] ([i915#2842])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-glk9/igt@gem_exec_fair@basic-pace-share@rcs0.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-glk1/igt@gem_exec_fair@basic-pace-share@rcs0.html
- shard-tglu: [PASS][21] -> [FAIL][22] ([i915#2842])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-tglu-6/igt@gem_exec_fair@basic-pace-share@rcs0.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-tglu-2/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-rkl: [PASS][23] -> [FAIL][24] ([i915#2842])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-rkl-7/igt@gem_exec_fair@basic-pace@rcs0.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-4/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-mtlp: [PASS][25] -> [DMESG-FAIL][26] ([i915#8962] / [i915#9121])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-2/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-4/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-dg2: NOTRUN -> [SKIP][27] ([i915#3539] / [i915#4852]) +1 similar issue
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@gem_exec_flush@basic-uc-rw-default.html
* igt@gem_exec_gttfill@multigpu-basic:
- shard-dg2: NOTRUN -> [SKIP][28] ([i915#7697])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@gem_exec_gttfill@multigpu-basic.html
* igt@gem_exec_params@secure-non-root:
- shard-dg2: NOTRUN -> [SKIP][29] ([fdo#112283])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@gem_exec_params@secure-non-root.html
* igt@gem_exec_reloc@basic-write-wc-noreloc:
- shard-dg2: NOTRUN -> [SKIP][30] ([i915#3281]) +12 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@gem_exec_reloc@basic-write-wc-noreloc.html
* igt@gem_fence_thrash@bo-write-verify-x:
- shard-dg2: NOTRUN -> [SKIP][31] ([i915#4860]) +2 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@gem_fence_thrash@bo-write-verify-x.html
* igt@gem_lmem_swapping@heavy-verify-multi-ccs:
- shard-glk: NOTRUN -> [SKIP][32] ([fdo#109271] / [i915#4613])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-glk1/igt@gem_lmem_swapping@heavy-verify-multi-ccs.html
* igt@gem_media_fill@media-fill:
- shard-dg2: NOTRUN -> [SKIP][33] ([i915#8289])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@gem_media_fill@media-fill.html
* igt@gem_mmap_gtt@cpuset-medium-copy-xy:
- shard-dg2: NOTRUN -> [SKIP][34] ([i915#4077]) +8 similar issues
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@gem_mmap_gtt@cpuset-medium-copy-xy.html
* igt@gem_mmap_wc@copy:
- shard-dg2: NOTRUN -> [SKIP][35] ([i915#4083]) +4 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@gem_mmap_wc@copy.html
* igt@gem_partial_pwrite_pread@reads-uncached:
- shard-dg2: NOTRUN -> [SKIP][36] ([i915#3282]) +4 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@gem_partial_pwrite_pread@reads-uncached.html
* igt@gem_pxp@reject-modify-context-protection-off-3:
- shard-dg2: NOTRUN -> [SKIP][37] ([i915#4270]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@gem_pxp@reject-modify-context-protection-off-3.html
* igt@gem_softpin@evict-snoop-interruptible:
- shard-dg2: NOTRUN -> [SKIP][38] ([i915#4885]) +1 similar issue
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@gem_softpin@evict-snoop-interruptible.html
* igt@gem_tiled_pread_basic:
- shard-dg2: NOTRUN -> [SKIP][39] ([i915#4079])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@gem_tiled_pread_basic.html
* igt@gem_userptr_blits@dmabuf-unsync:
- shard-dg2: NOTRUN -> [SKIP][40] ([i915#3297]) +2 similar issues
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@gem_userptr_blits@dmabuf-unsync.html
* igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy:
- shard-dg2: NOTRUN -> [SKIP][41] ([i915#3297] / [i915#4880]) +1 similar issue
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@gem_userptr_blits@map-fixed-invalidate-overlap-busy.html
* igt@gem_userptr_blits@vma-merge:
- shard-dg2: NOTRUN -> [FAIL][42] ([i915#3318])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@gem_userptr_blits@vma-merge.html
* igt@gen3_mixed_blits:
- shard-dg2: NOTRUN -> [SKIP][43] ([fdo#109289]) +1 similar issue
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@gen3_mixed_blits.html
* igt@gen9_exec_parse@unaligned-jump:
- shard-dg2: NOTRUN -> [SKIP][44] ([i915#2856]) +3 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@gen9_exec_parse@unaligned-jump.html
* igt@i915_fb_tiling:
- shard-dg2: NOTRUN -> [SKIP][45] ([i915#4881])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@i915_fb_tiling.html
* igt@i915_pm_backlight@fade-with-dpms:
- shard-dg2: NOTRUN -> [SKIP][46] ([i915#5354] / [i915#7561])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@i915_pm_backlight@fade-with-dpms.html
* igt@i915_pm_rpm@dpms-mode-unset-lpsp:
- shard-dg2: NOTRUN -> [SKIP][47] ([i915#1397])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
- shard-rkl: [PASS][48] -> [SKIP][49] ([i915#1397])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-rkl-7/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-6/igt@i915_pm_rpm@dpms-mode-unset-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp:
- shard-dg2: [PASS][50] -> [SKIP][51] ([i915#1397])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg2-6/igt@i915_pm_rpm@modeset-non-lpsp.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-12/igt@i915_pm_rpm@modeset-non-lpsp.html
* igt@i915_pm_rps@thresholds-idle@gt0:
- shard-dg2: NOTRUN -> [SKIP][52] ([i915#8925])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@i915_pm_rps@thresholds-idle@gt0.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- shard-dg2: NOTRUN -> [SKIP][53] ([i915#4212])
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-4-mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][54] ([i915#8502] / [i915#8709]) +11 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-1/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-4-mc_ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc_ccs:
- shard-dg1: NOTRUN -> [SKIP][55] ([i915#8502]) +7 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-13/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-a-hdmi-a-3-y-rc_ccs.html
* igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][56] ([i915#8502]) +3 similar issues
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-7/igt@kms_async_flips@async-flip-with-page-flip-events@pipe-b-hdmi-a-1-y-rc_ccs.html
* igt@kms_async_flips@crc@pipe-b-dp-2:
- shard-dg2: NOTRUN -> [FAIL][57] ([i915#8247]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-12/igt@kms_async_flips@crc@pipe-b-dp-2.html
* igt@kms_async_flips@crc@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [FAIL][58] ([i915#8247]) +3 similar issues
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-15/igt@kms_async_flips@crc@pipe-d-hdmi-a-4.html
* igt@kms_atomic@plane-primary-overlay-mutable-zpos:
- shard-dg2: NOTRUN -> [SKIP][59] ([i915#404])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@kms_atomic@plane-primary-overlay-mutable-zpos.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip:
- shard-mtlp: [PASS][60] -> [FAIL][61] ([i915#5138])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-4/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-0-hflip.html
* igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-mtlp: [PASS][62] -> [FAIL][63] ([i915#3743]) +1 similar issue
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-7/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-6/igt@kms_big_fb@4-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@x-tiled-32bpp-rotate-270:
- shard-dg2: NOTRUN -> [SKIP][64] ([fdo#111614]) +2 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_big_fb@x-tiled-32bpp-rotate-270.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-mtlp: NOTRUN -> [SKIP][65] ([fdo#111615])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][66] ([i915#5190]) +12 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-dg2: NOTRUN -> [SKIP][67] ([i915#4538] / [i915#5190]) +4 similar issues
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_big_joiner@basic:
- shard-dg2: NOTRUN -> [SKIP][68] ([i915#2705])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_big_joiner@basic.html
* igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs:
- shard-mtlp: NOTRUN -> [SKIP][69] ([i915#6095]) +1 similar issue
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-3/igt@kms_ccs@pipe-b-crc-primary-basic-yf_tiled_ccs.html
* igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc:
- shard-dg2: NOTRUN -> [SKIP][70] ([i915#3689] / [i915#3886] / [i915#5354]) +6 similar issues
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_ccs@pipe-b-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs:
- shard-dg2: NOTRUN -> [SKIP][71] ([i915#5354]) +45 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@kms_ccs@pipe-c-bad-rotation-90-4_tiled_mtl_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-mtlp: NOTRUN -> [SKIP][72] ([i915#3886] / [i915#6095])
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-3/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs:
- shard-rkl: NOTRUN -> [SKIP][73] ([i915#5354]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-7/igt@kms_ccs@pipe-c-crc-sprite-planes-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_rc_ccs:
- shard-dg2: NOTRUN -> [SKIP][74] ([i915#3689] / [i915#5354]) +19 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_ccs@pipe-d-crc-primary-basic-y_tiled_gen12_rc_ccs.html
* igt@kms_cdclk@mode-transition@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][75] ([i915#4087] / [i915#7213]) +3 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_cdclk@mode-transition@pipe-d-dp-4.html
* igt@kms_chamelium_color@ctm-blue-to-red:
- shard-dg2: NOTRUN -> [SKIP][76] ([fdo#111827]) +1 similar issue
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@kms_chamelium_color@ctm-blue-to-red.html
* igt@kms_chamelium_frames@dp-frame-dump:
- shard-rkl: NOTRUN -> [SKIP][77] ([i915#7828])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-7/igt@kms_chamelium_frames@dp-frame-dump.html
* igt@kms_chamelium_frames@hdmi-crc-multiple:
- shard-dg2: NOTRUN -> [SKIP][78] ([i915#7828]) +7 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@kms_chamelium_frames@hdmi-crc-multiple.html
* igt@kms_chamelium_hpd@dp-hpd-after-suspend:
- shard-mtlp: NOTRUN -> [SKIP][79] ([i915#7828])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-3/igt@kms_chamelium_hpd@dp-hpd-after-suspend.html
* igt@kms_content_protection@dp-mst-type-0:
- shard-dg2: NOTRUN -> [SKIP][80] ([i915#3299]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@kms_content_protection@dp-mst-type-0.html
* igt@kms_content_protection@type1:
- shard-dg2: NOTRUN -> [SKIP][81] ([i915#7118] / [i915#7162])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_content_protection@type1.html
* igt@kms_content_protection@uevent:
- shard-dg2: NOTRUN -> [SKIP][82] ([i915#7118]) +1 similar issue
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@kms_content_protection@uevent.html
* igt@kms_cursor_crc@cursor-onscreen-max-size:
- shard-dg2: NOTRUN -> [SKIP][83] ([i915#3555]) +5 similar issues
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_cursor_crc@cursor-onscreen-max-size.html
* igt@kms_cursor_crc@cursor-random-512x170:
- shard-dg2: NOTRUN -> [SKIP][84] ([i915#3359])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_cursor_crc@cursor-random-512x170.html
* igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy:
- shard-glk: [PASS][85] -> [FAIL][86] ([i915#72])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-glk9/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-glk1/igt@kms_cursor_legacy@2x-long-flip-vs-cursor-legacy.html
* igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size:
- shard-dg2: NOTRUN -> [SKIP][87] ([fdo#109274] / [i915#5354]) +2 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_cursor_legacy@cursorb-vs-flipb-varying-size.html
* igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions:
- shard-dg2: NOTRUN -> [SKIP][88] ([i915#4103] / [i915#4213]) +1 similar issue
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_cursor_legacy@short-busy-flip-before-cursor-atomic-transitions.html
* igt@kms_dsc@dsc-basic:
- shard-dg2: NOTRUN -> [SKIP][89] ([i915#3555] / [i915#3840]) +1 similar issue
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@kms_dsc@dsc-basic.html
* igt@kms_flip@2x-flip-vs-expired-vblank-interruptible:
- shard-rkl: NOTRUN -> [SKIP][90] ([fdo#111767] / [fdo#111825])
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-7/igt@kms_flip@2x-flip-vs-expired-vblank-interruptible.html
* igt@kms_flip@2x-flip-vs-fences-interruptible:
- shard-dg2: NOTRUN -> [SKIP][91] ([i915#8381])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@kms_flip@2x-flip-vs-fences-interruptible.html
* igt@kms_flip@2x-flip-vs-rmfb-interruptible:
- shard-snb: NOTRUN -> [SKIP][92] ([fdo#109271] / [fdo#111767])
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-snb6/igt@kms_flip@2x-flip-vs-rmfb-interruptible.html
* igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1:
- shard-snb: NOTRUN -> [DMESG-WARN][93] ([i915#8841])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-snb1/igt@kms_flip@2x-flip-vs-suspend@ab-vga1-hdmi-a1.html
* igt@kms_flip@2x-plain-flip-ts-check:
- shard-dg2: NOTRUN -> [SKIP][94] ([fdo#109274]) +2 similar issues
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_flip@2x-plain-flip-ts-check.html
* igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode:
- shard-dg2: NOTRUN -> [SKIP][95] ([i915#2672]) +4 similar issues
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@kms_flip_scaled_crc@flip-32bpp-yftile-to-32bpp-yftileccs-downscaling@pipe-a-valid-mode.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
- shard-dg2: NOTRUN -> [SKIP][96] ([i915#8708]) +16 similar issues
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@fbcpsr-tiling-y:
- shard-mtlp: NOTRUN -> [SKIP][97] ([i915#5460])
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-3/igt@kms_frontbuffer_tracking@fbcpsr-tiling-y.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move:
- shard-mtlp: NOTRUN -> [SKIP][98] ([i915#1825])
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-move.html
* igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary:
- shard-dg2: NOTRUN -> [SKIP][99] ([i915#3458]) +12 similar issues
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_frontbuffer_tracking@psr-indfb-scaledprimary.html
* igt@kms_getfb@getfb-addfb-different-handles:
- shard-mtlp: [PASS][100] -> [DMESG-WARN][101] ([i915#2017] / [i915#9157])
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-6/igt@kms_getfb@getfb-addfb-different-handles.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-7/igt@kms_getfb@getfb-addfb-different-handles.html
* igt@kms_hdr@bpc-switch-dpms:
- shard-rkl: NOTRUN -> [SKIP][102] ([i915#3555] / [i915#8228])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-6/igt@kms_hdr@bpc-switch-dpms.html
* igt@kms_hdr@static-toggle-dpms:
- shard-dg2: NOTRUN -> [SKIP][103] ([i915#3555] / [i915#8228]) +1 similar issue
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@kms_hdr@static-toggle-dpms.html
* igt@kms_plane@pixel-format-source-clamping@pipe-b-planes:
- shard-mtlp: [PASS][104] -> [FAIL][105] ([i915#1623])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-2/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-4/igt@kms_plane@pixel-format-source-clamping@pipe-b-planes.html
* igt@kms_plane_lowres@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][106] ([i915#3555] / [i915#8821])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@kms_plane_lowres@tiling-yf.html
* igt@kms_plane_multiple@tiling-yf:
- shard-dg2: NOTRUN -> [SKIP][107] ([i915#3555] / [i915#8806])
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@kms_plane_multiple@tiling-yf.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4:
- shard-dg2: NOTRUN -> [FAIL][108] ([i915#8292])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_plane_scaling@intel-max-src-size@pipe-a-dp-4.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1:
- shard-dg1: NOTRUN -> [FAIL][109] ([i915#8292])
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-19/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-1.html
* igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [FAIL][110] ([i915#8292])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-4/igt@kms_plane_scaling@intel-max-src-size@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-dp-4:
- shard-dg2: NOTRUN -> [SKIP][111] ([i915#5176]) +3 similar issues
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_plane_scaling@plane-downscale-with-rotation-factor-0-25@pipe-d-dp-4.html
* igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-hdmi-a-1:
- shard-dg1: NOTRUN -> [SKIP][112] ([i915#5176]) +19 similar issues
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-19/igt@kms_plane_scaling@plane-scaler-with-clipping-clamping-rotation@pipe-d-hdmi-a-1.html
* igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2:
- shard-rkl: NOTRUN -> [SKIP][113] ([i915#5176]) +3 similar issues
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-6/igt@kms_plane_scaling@plane-upscale-with-rotation-factor-0-25@pipe-a-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2:
- shard-dg2: NOTRUN -> [SKIP][114] ([i915#5235]) +15 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-2/igt@kms_plane_scaling@planes-downscale-factor-0-25@pipe-d-hdmi-a-2.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1:
- shard-snb: NOTRUN -> [SKIP][115] ([fdo#109271]) +20 similar issues
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-snb6/igt@kms_plane_scaling@planes-downscale-factor-0-5-unity-scaling@pipe-b-vga-1.html
* igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4:
- shard-dg1: NOTRUN -> [SKIP][116] ([i915#5235]) +11 similar issues
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-16/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-d-hdmi-a-4.html
* igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
- shard-glk: NOTRUN -> [SKIP][117] ([fdo#109271] / [i915#658])
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-glk1/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-dg2: NOTRUN -> [SKIP][118] ([i915#658]) +3 similar issues
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr@psr2_sprite_mmap_gtt:
- shard-dg2: NOTRUN -> [SKIP][119] ([i915#1072]) +8 similar issues
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@kms_psr@psr2_sprite_mmap_gtt.html
* igt@kms_rotation_crc@sprite-rotation-90:
- shard-dg2: NOTRUN -> [SKIP][120] ([i915#4235]) +1 similar issue
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@kms_rotation_crc@sprite-rotation-90.html
- shard-rkl: [PASS][121] -> [ABORT][122] ([i915#8178])
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-rkl-3/igt@kms_rotation_crc@sprite-rotation-90.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-6/igt@kms_rotation_crc@sprite-rotation-90.html
* igt@kms_selftest@framebuffer:
- shard-dg2: NOTRUN -> [SKIP][123] ([i915#8661])
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@kms_selftest@framebuffer.html
* igt@kms_sysfs_edid_timing:
- shard-dg2: [PASS][124] -> [FAIL][125] ([IGT#2])
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg2-11/igt@kms_sysfs_edid_timing.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-2/igt@kms_sysfs_edid_timing.html
* igt@perf@global-sseu-config-invalid:
- shard-dg2: NOTRUN -> [SKIP][126] ([i915#7387])
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@perf@global-sseu-config-invalid.html
* igt@perf@non-zero-reason@0-rcs0:
- shard-dg2: [PASS][127] -> [FAIL][128] ([i915#7484])
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg2-1/igt@perf@non-zero-reason@0-rcs0.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@perf@non-zero-reason@0-rcs0.html
* igt@perf_pmu@rc6-suspend:
- shard-dg2: [PASS][129] -> [FAIL][130] ([fdo#103375])
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg2-5/igt@perf_pmu@rc6-suspend.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@perf_pmu@rc6-suspend.html
* igt@prime_vgem@basic-read:
- shard-dg2: NOTRUN -> [SKIP][131] ([i915#3291] / [i915#3708])
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@prime_vgem@basic-read.html
* igt@prime_vgem@fence-read-hang:
- shard-dg2: NOTRUN -> [SKIP][132] ([i915#3708])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@prime_vgem@fence-read-hang.html
* igt@v3d/v3d_perfmon@create-perfmon-invalid-counters:
- shard-dg2: NOTRUN -> [SKIP][133] ([i915#2575]) +11 similar issues
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-8/igt@v3d/v3d_perfmon@create-perfmon-invalid-counters.html
* igt@v3d/v3d_submit_csd@bad-extension:
- shard-glk: NOTRUN -> [SKIP][134] ([fdo#109271]) +15 similar issues
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-glk1/igt@v3d/v3d_submit_csd@bad-extension.html
* igt@vc4/vc4_perfmon@create-two-perfmon:
- shard-mtlp: NOTRUN -> [SKIP][135] ([i915#7711])
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-3/igt@vc4/vc4_perfmon@create-two-perfmon.html
* igt@vc4/vc4_wait_seqno@bad-seqno-1ns:
- shard-dg2: NOTRUN -> [SKIP][136] ([i915#7711]) +6 similar issues
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-11/igt@vc4/vc4_wait_seqno@bad-seqno-1ns.html
#### Possible fixes ####
* igt@gem_ctx_isolation@preservation-s3@vcs0:
- shard-mtlp: [FAIL][137] ([fdo#103375]) -> [PASS][138]
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-1/igt@gem_ctx_isolation@preservation-s3@vcs0.html
* igt@gem_eio@kms:
- shard-dg2: [INCOMPLETE][139] ([i915#7892]) -> [PASS][140]
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg2-1/igt@gem_eio@kms.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-3/igt@gem_eio@kms.html
* igt@gem_eio@reset-stress:
- shard-dg1: [FAIL][141] ([i915#5784]) -> [PASS][142]
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg1-16/igt@gem_eio@reset-stress.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-13/igt@gem_eio@reset-stress.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [FAIL][143] ([i915#2846]) -> [PASS][144]
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-glk2/igt@gem_exec_fair@basic-deadline.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-glk3/igt@gem_exec_fair@basic-deadline.html
* igt@gem_lmem_swapping@smem-oom@lmem0:
- shard-dg1: [TIMEOUT][145] ([i915#5493]) -> [PASS][146]
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-14/igt@gem_lmem_swapping@smem-oom@lmem0.html
* igt@gem_workarounds@suspend-resume-context:
- shard-dg2: [FAIL][147] ([fdo#103375]) -> [PASS][148]
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg2-5/igt@gem_workarounds@suspend-resume-context.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-5/igt@gem_workarounds@suspend-resume-context.html
* igt@i915_pipe_stress@stress-xrgb8888-untiled:
- shard-mtlp: [FAIL][149] ([i915#8691]) -> [PASS][150]
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-2/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-4/igt@i915_pipe_stress@stress-xrgb8888-untiled.html
* igt@i915_pm_rc6_residency@rc6-idle@rcs0:
- shard-dg1: [FAIL][151] ([i915#3591]) -> [PASS][152] +1 similar issue
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg1-15/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-18/igt@i915_pm_rc6_residency@rc6-idle@rcs0.html
* igt@i915_pm_rpm@dpms-lpsp:
- shard-rkl: [SKIP][153] ([i915#1397]) -> [PASS][154]
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-rkl-3/igt@i915_pm_rpm@dpms-lpsp.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-7/igt@i915_pm_rpm@dpms-lpsp.html
* igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait:
- shard-dg1: [SKIP][155] ([i915#1397]) -> [PASS][156]
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg1-19/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-16/igt@i915_pm_rpm@modeset-non-lpsp-stress-no-wait.html
* igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1:
- shard-mtlp: [FAIL][157] ([i915#2521]) -> [PASS][158]
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-4/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-1/igt@kms_async_flips@alternate-sync-async-flip@pipe-a-edp-1.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-mtlp: [FAIL][159] ([i915#3743]) -> [PASS][160]
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-3/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-2/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [FAIL][161] ([i915#2346]) -> [PASS][162] +1 similar issue
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-glk2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-glk3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-apl: [FAIL][163] ([i915#2346]) -> [PASS][164]
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-apl6/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-apl2/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2:
- shard-glk: [FAIL][165] ([i915#2122]) -> [PASS][166]
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-glk8/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-glk6/igt@kms_flip@2x-plain-flip-ts-check-interruptible@ab-hdmi-a1-hdmi-a2.html
* igt@kms_plane@pixel-format@pipe-b-planes:
- shard-mtlp: [FAIL][167] ([i915#1623]) -> [PASS][168]
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-1/igt@kms_plane@pixel-format@pipe-b-planes.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-7/igt@kms_plane@pixel-format@pipe-b-planes.html
#### Warnings ####
* igt@i915_pm_rc6_residency@rc6-idle@vecs0:
- shard-tglu: [WARN][169] ([i915#2681]) -> [FAIL][170] ([i915#2681] / [i915#3591])
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-tglu-6/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-tglu-2/igt@i915_pm_rc6_residency@rc6-idle@vecs0.html
* igt@kms_content_protection@mei_interface:
- shard-dg2: [SKIP][171] ([i915#7118] / [i915#7162]) -> [SKIP][172] ([i915#7118])
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg2-11/igt@kms_content_protection@mei_interface.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg2-2/igt@kms_content_protection@mei_interface.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size:
- shard-mtlp: [DMESG-FAIL][173] ([i915#1982] / [i915#2017] / [i915#5954]) -> [FAIL][174] ([i915#2346])
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-3/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions-varying-size.html
* igt@kms_force_connector_basic@force-load-detect:
- shard-rkl: [SKIP][175] ([fdo#109285]) -> [SKIP][176] ([fdo#109285] / [i915#4098])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-rkl-7/igt@kms_force_connector_basic@force-load-detect.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-rkl-4/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_psr@cursor_plane_move:
- shard-dg1: [SKIP][177] ([i915#1072]) -> [SKIP][178] ([i915#1072] / [i915#4078])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-dg1-17/igt@kms_psr@cursor_plane_move.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-dg1-18/igt@kms_psr@cursor_plane_move.html
* igt@syncobj_timeline@invalid-wait-illegal-handle:
- shard-mtlp: [DMESG-WARN][179] ([i915#9157]) -> [DMESG-WARN][180] ([i915#2017])
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13559/shard-mtlp-6/igt@syncobj_timeline@invalid-wait-illegal-handle.html
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/shard-mtlp-7/igt@syncobj_timeline@invalid-wait-illegal-handle.html
[IGT#2]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/2
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111767]: https://bugs.freedesktop.org/show_bug.cgi?id=111767
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112283]: https://bugs.freedesktop.org/show_bug.cgi?id=112283
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1623]: https://gitlab.freedesktop.org/drm/intel/issues/1623
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2017]: https://gitlab.freedesktop.org/drm/intel/issues/2017
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2521]: https://gitlab.freedesktop.org/drm/intel/issues/2521
[i915#2575]: https://gitlab.freedesktop.org/drm/intel/issues/2575
[i915#2672]: https://gitlab.freedesktop.org/drm/intel/issues/2672
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3318]: https://gitlab.freedesktop.org/drm/intel/issues/3318
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3743]: https://gitlab.freedesktop.org/drm/intel/issues/3743
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3936]: https://gitlab.freedesktop.org/drm/intel/issues/3936
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4087]: https://gitlab.freedesktop.org/drm/intel/issues/4087
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4235]: https://gitlab.freedesktop.org/drm/intel/issues/4235
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4771]: https://gitlab.freedesktop.org/drm/intel/issues/4771
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4881]: https://gitlab.freedesktop.org/drm/intel/issues/4881
[i915#4885]: https://gitlab.freedesktop.org/drm/intel/issues/4885
[i915#5138]: https://gitlab.freedesktop.org/drm/intel/issues/5138
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5460]: https://gitlab.freedesktop.org/drm/intel/issues/5460
[i915#5493]: https://gitlab.freedesktop.org/drm/intel/issues/5493
[i915#5784]: https://gitlab.freedesktop.org/drm/intel/issues/5784
[i915#5954]: https://gitlab.freedesktop.org/drm/intel/issues/5954
[i915#6095]: https://gitlab.freedesktop.org/drm/intel/issues/6095
[i915#6311]: https://gitlab.freedesktop.org/drm/intel/issues/6311
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#7118]: https://gitlab.freedesktop.org/drm/intel/issues/7118
[i915#7162]: https://gitlab.freedesktop.org/drm/intel/issues/7162
[i915#72]: https://gitlab.freedesktop.org/drm/intel/issues/72
[i915#7213]: https://gitlab.freedesktop.org/drm/intel/issues/7213
[i915#7297]: https://gitlab.freedesktop.org/drm/intel/issues/7297
[i915#7387]: https://gitlab.freedesktop.org/drm/intel/issues/7387
[i915#7484]: https://gitlab.freedesktop.org/drm/intel/issues/7484
[i915#7561]: https://gitlab.freedesktop.org/drm/intel/issues/7561
[i915#7697]: https://gitlab.freedesktop.org/drm/intel/issues/7697
[i915#7701]: https://gitlab.freedesktop.org/drm/intel/issues/7701
[i915#7711]: https://gitlab.freedesktop.org/drm/intel/issues/7711
[i915#7742]: https://gitlab.freedesktop.org/drm/intel/issues/7742
[i915#7828]: https://gitlab.freedesktop.org/drm/intel/issues/7828
[i915#7892]: https://gitlab.freedesktop.org/drm/intel/issues/7892
[i915#7975]: https://gitlab.freedesktop.org/drm/intel/issues/7975
[i915#8178]: https://gitlab.freedesktop.org/drm/intel/issues/8178
[i915#8213]: https://gitlab.freedesktop.org/drm/intel/issues/8213
[i915#8228]: https://gitlab.freedesktop.org/drm/intel/issues/8228
[i915#8247]: https://gitlab.freedesktop.org/drm/intel/issues/8247
[i915#8289]: https://gitlab.freedesktop.org/drm/intel/issues/8289
[i915#8292]: https://gitlab.freedesktop.org/drm/intel/issues/8292
[i915#8381]: https://gitlab.freedesktop.org/drm/intel/issues/8381
[i915#8411]: https://gitlab.freedesktop.org/drm/intel/issues/8411
[i915#8414]: https://gitlab.freedesktop.org/drm/intel/issues/8414
[i915#8502]: https://gitlab.freedesktop.org/drm/intel/issues/8502
[i915#8661]: https://gitlab.freedesktop.org/drm/intel/issues/8661
[i915#8691]: https://gitlab.freedesktop.org/drm/intel/issues/8691
[i915#8708]: https://gitlab.freedesktop.org/drm/intel/issues/8708
[i915#8709]: https://gitlab.freedesktop.org/drm/intel/issues/8709
[i915#8806]: https://gitlab.freedesktop.org/drm/intel/issues/8806
[i915#8821]: https://gitlab.freedesktop.org/drm/intel/issues/8821
[i915#8841]: https://gitlab.freedesktop.org/drm/intel/issues/8841
[i915#8925]: https://gitlab.freedesktop.org/drm/intel/issues/8925
[i915#8962]: https://gitlab.freedesktop.org/drm/intel/issues/8962
[i915#9121]: https://gitlab.freedesktop.org/drm/intel/issues/9121
[i915#9157]: https://gitlab.freedesktop.org/drm/intel/issues/9157
Build changes
-------------
* Linux: CI_DRM_13559 -> Patchwork_122589v2
CI-20190529: 20190529
CI_DRM_13559: 2e6e7e62e019d89689eb44307fcc07f2c59e9b01 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7451: 5d48d1fb231f449fe2f80cda14ea7a1ecfda59fa @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_122589v2: 2e6e7e62e019d89689eb44307fcc07f2c59e9b01 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_122589v2/index.html
[-- Attachment #2: Type: text/html, Size: 58440 bytes --]
^ permalink raw reply [flat|nested] 60+ messages in thread* [Intel-gfx] ✗ Fi.CI.BUILD: failure for drm/i915: Improve BW management on shared display links (rev3)
2023-08-24 8:04 [Intel-gfx] [PATCH v2 00/22] drm/i915: Improve BW management on shared display links Imre Deak
` (25 preceding siblings ...)
2023-08-24 17:54 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2023-09-04 7:14 ` Patchwork
26 siblings, 0 replies; 60+ messages in thread
From: Patchwork @ 2023-09-04 7:14 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Improve BW management on shared display links (rev3)
URL : https://patchwork.freedesktop.org/series/122589/
State : failure
== Summary ==
Error: patch https://patchwork.freedesktop.org/api/1.0/series/122589/revisions/3/mbox/ not applied
Applying: drm/i915/dp: Factor out helpers to compute the link limits
Using index info to reconstruct a base tree...
M drivers/gpu/drm/i915/display/intel_dp.c
M drivers/gpu/drm/i915/display/intel_dp_mst.c
Falling back to patching base and 3-way merge...
Auto-merging drivers/gpu/drm/i915/display/intel_dp_mst.c
CONFLICT (content): Merge conflict in drivers/gpu/drm/i915/display/intel_dp_mst.c
Auto-merging drivers/gpu/drm/i915/display/intel_dp.c
error: Failed to merge in the changes.
hint: Use 'git am --show-current-patch=diff' to see the failed patch
Patch failed at 0001 drm/i915/dp: Factor out helpers to compute the link limits
When you have resolved this problem, run "git am --continue".
If you prefer to skip this patch, run "git am --skip" instead.
To restore the original branch and stop patching, run "git am --abort".
Build failed, no error log produced
^ permalink raw reply [flat|nested] 60+ messages in thread