From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Alexander Usyskin <alexander.usyskin@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Lucas De Marchi <lucas.demarchi@intel.com>,
linux-kernel@vger.kernel.org,
Tomas Winkler <tomas.winkler@intel.com>,
intel-xe@lists.freedesktop.org
Subject: Re: [Intel-xe] [PATCH v2 1/4] drm/xe/gsc: add HECI2 register offsets
Date: Mon, 18 Sep 2023 12:07:03 -0400 [thread overview]
Message-ID: <ZQh1p5umcz7V4jXG@intel.com> (raw)
In-Reply-To: <20230914080138.4178295-2-alexander.usyskin@intel.com>
On Thu, Sep 14, 2023 at 11:01:35AM +0300, Alexander Usyskin wrote:
> From: Vitaly Lubart <vitaly.lubart@intel.com>
>
> Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h
>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 39d7b0740bf0..4cbc3062cb9a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -33,6 +33,10 @@
> #define XEHPC_BCS6_RING_BASE 0x3ea000
> #define XEHPC_BCS7_RING_BASE 0x3ec000
> #define XEHPC_BCS8_RING_BASE 0x3ee000
> +
> +#define DG1_GSC_HECI2_BASE 0x00259000
> +#define DG2_GSC_HECI2_BASE 0x00374000
matches the i915 ones, so
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> +
> #define GSCCS_RING_BASE 0x11a000
> #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
> #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8)
> --
> 2.34.1
>
WARNING: multiple messages have this Message-ID (diff)
From: Rodrigo Vivi <rodrigo.vivi@intel.com>
To: Alexander Usyskin <alexander.usyskin@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Lucas De Marchi <lucas.demarchi@intel.com>,
Daniele Ceraolo Spurio <daniele.ceraolospurio@intel.com>,
<linux-kernel@vger.kernel.org>,
"Tomas Winkler" <tomas.winkler@intel.com>,
<intel-xe@lists.freedesktop.org>
Subject: Re: [Intel-xe] [PATCH v2 1/4] drm/xe/gsc: add HECI2 register offsets
Date: Mon, 18 Sep 2023 12:07:03 -0400 [thread overview]
Message-ID: <ZQh1p5umcz7V4jXG@intel.com> (raw)
In-Reply-To: <20230914080138.4178295-2-alexander.usyskin@intel.com>
On Thu, Sep 14, 2023 at 11:01:35AM +0300, Alexander Usyskin wrote:
> From: Vitaly Lubart <vitaly.lubart@intel.com>
>
> Add HECI2 register offsets for DG1 and DG2 to regs/xe_regs.h
>
> Signed-off-by: Vitaly Lubart <vitaly.lubart@intel.com>
> Signed-off-by: Alexander Usyskin <alexander.usyskin@intel.com>
> ---
> drivers/gpu/drm/xe/regs/xe_regs.h | 4 ++++
> 1 file changed, 4 insertions(+)
>
> diff --git a/drivers/gpu/drm/xe/regs/xe_regs.h b/drivers/gpu/drm/xe/regs/xe_regs.h
> index 39d7b0740bf0..4cbc3062cb9a 100644
> --- a/drivers/gpu/drm/xe/regs/xe_regs.h
> +++ b/drivers/gpu/drm/xe/regs/xe_regs.h
> @@ -33,6 +33,10 @@
> #define XEHPC_BCS6_RING_BASE 0x3ea000
> #define XEHPC_BCS7_RING_BASE 0x3ec000
> #define XEHPC_BCS8_RING_BASE 0x3ee000
> +
> +#define DG1_GSC_HECI2_BASE 0x00259000
> +#define DG2_GSC_HECI2_BASE 0x00374000
matches the i915 ones, so
Reviewed-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
> +
> #define GSCCS_RING_BASE 0x11a000
> #define GT_WAIT_SEMAPHORE_INTERRUPT REG_BIT(11)
> #define GT_CONTEXT_SWITCH_INTERRUPT REG_BIT(8)
> --
> 2.34.1
>
next prev parent reply other threads:[~2023-09-18 16:11 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-09-14 8:01 [Intel-xe] [PATCH v2 0/4] drm/xe/gsc: add initial gsc support Alexander Usyskin
2023-09-14 8:01 ` Alexander Usyskin
2023-09-14 8:01 ` [Intel-xe] [PATCH v2 1/4] drm/xe/gsc: add HECI2 register offsets Alexander Usyskin
2023-09-14 8:01 ` Alexander Usyskin
2023-09-18 16:07 ` Rodrigo Vivi [this message]
2023-09-18 16:07 ` [Intel-xe] " Rodrigo Vivi
2023-09-14 8:01 ` [Intel-xe] [PATCH v2 2/4] drm/xe/gsc: add has_heci_gscfi indication to device Alexander Usyskin
2023-09-14 8:01 ` Alexander Usyskin
2023-09-18 16:09 ` [Intel-xe] " Rodrigo Vivi
2023-09-18 16:09 ` Rodrigo Vivi
2023-09-14 8:01 ` [Intel-xe] [PATCH v2 3/4] drm/xe/gsc: add gsc device support Alexander Usyskin
2023-09-14 8:01 ` Alexander Usyskin
2023-09-18 16:25 ` [Intel-xe] " Rodrigo Vivi
2023-09-18 16:25 ` Rodrigo Vivi
2023-09-19 14:51 ` Usyskin, Alexander
2023-09-19 14:51 ` Usyskin, Alexander
2023-09-20 8:59 ` Usyskin, Alexander
2023-09-20 8:59 ` Usyskin, Alexander
2023-09-14 8:01 ` [Intel-xe] [PATCH v2 4/4] mei: gsc: add support for auxiliary device created by Xe driver Alexander Usyskin
2023-09-14 8:01 ` Alexander Usyskin
2023-09-18 16:26 ` [Intel-xe] " Rodrigo Vivi
2023-09-18 16:26 ` Rodrigo Vivi
2023-09-14 9:27 ` [Intel-xe] ✓ CI.Patch_applied: success for drm/xe/gsc: add initial gsc support (rev2) Patchwork
2023-09-14 9:27 ` [Intel-xe] ✗ CI.checkpatch: warning " Patchwork
2023-09-14 9:28 ` [Intel-xe] ✓ CI.KUnit: success " Patchwork
2023-09-14 9:35 ` [Intel-xe] ✓ CI.Build: " Patchwork
2023-09-14 9:36 ` [Intel-xe] ✗ CI.Hooks: failure " Patchwork
2023-09-14 9:37 ` [Intel-xe] ✓ CI.checksparse: success " Patchwork
2023-09-14 10:12 ` [Intel-xe] ✓ CI.BAT: " Patchwork
2023-09-18 16:06 ` [Intel-xe] [PATCH v2 0/4] drm/xe/gsc: add initial gsc support Rodrigo Vivi
2023-09-18 16:06 ` Rodrigo Vivi
2023-09-20 6:15 ` Usyskin, Alexander
2023-09-20 6:15 ` Usyskin, Alexander
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