* [PATCH v6 01/14] iommu/amd: Remove unused amd_io_pgtable.pt_root variable
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 02/14] iommu/amd: Consolidate timeout pre-define to amd_iommu_type.h Vasant Hegde
` (13 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
It has been no longer used since the commit 6eedb59c18a3 ("iommu/amd:
Remove amd_iommu_domain_get_pgtable").
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/amd_iommu.h | 1 -
drivers/iommu/amd/amd_iommu_types.h | 1 -
2 files changed, 2 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index e2857109e966..c5090e00b3aa 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -105,7 +105,6 @@ static inline void *iommu_phys_to_virt(unsigned long paddr)
static inline
void amd_iommu_domain_set_pt_root(struct protection_domain *domain, u64 root)
{
- atomic64_set(&domain->iop.pt_root, root);
domain->iop.root = (u64 *)(root & PAGE_MASK);
domain->iop.mode = root & 7; /* lowest 3 bits encode pgtable mode */
}
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 7dc30c2b56b3..081d8d0f29d5 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -544,7 +544,6 @@ struct amd_io_pgtable {
struct io_pgtable iop;
int mode;
u64 *root;
- atomic64_t pt_root; /* pgtable root and pgtable mode */
u64 *pgd; /* v2 pgtable pgd pointer */
};
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 02/14] iommu/amd: Consolidate timeout pre-define to amd_iommu_type.h
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 01/14] iommu/amd: Remove unused amd_io_pgtable.pt_root variable Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 03/14] iommu/amd: Consolidate logic to allocate protection domain Vasant Hegde
` (12 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
To allow inclusion in other files in subsequent patches.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/amd_iommu_types.h | 4 ++++
drivers/iommu/amd/init.c | 10 ++++------
drivers/iommu/amd/iommu.c | 2 --
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 081d8d0f29d5..a8d264026f7f 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -451,6 +451,10 @@
#define PD_IOMMUV2_MASK BIT(3) /* domain has gcr3 table */
#define PD_GIOV_MASK BIT(4) /* domain enable GIOV support */
+/* Timeout stuff */
+#define LOOP_TIMEOUT 100000
+#define MMIO_STATUS_TIMEOUT 2000000
+
extern bool amd_iommu_dump;
#define DUMP_printk(format, arg...) \
do { \
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 45efb7e5d725..852e40b13d20 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -83,8 +83,6 @@
#define ACPI_DEVFLAG_LINT1 0x80
#define ACPI_DEVFLAG_ATSDIS 0x10000000
-#define LOOP_TIMEOUT 2000000
-
#define IVRS_GET_SBDF_ID(seg, bus, dev, fn) (((seg & 0xffff) << 16) | ((bus & 0xff) << 8) \
| ((dev & 0x1f) << 3) | (fn & 0x7))
@@ -985,14 +983,14 @@ static int iommu_ga_log_enable(struct amd_iommu *iommu)
iommu_feature_enable(iommu, CONTROL_GAINT_EN);
iommu_feature_enable(iommu, CONTROL_GALOG_EN);
- for (i = 0; i < LOOP_TIMEOUT; ++i) {
+ for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) {
status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
if (status & (MMIO_STATUS_GALOG_RUN_MASK))
break;
udelay(10);
}
- if (WARN_ON(i >= LOOP_TIMEOUT))
+ if (WARN_ON(i >= MMIO_STATUS_TIMEOUT))
return -EINVAL;
return 0;
@@ -2900,14 +2898,14 @@ static void enable_iommus_vapic(void)
* Need to set and poll check the GALOGRun bit to zero before
* we can set/ modify GA Log registers safely.
*/
- for (i = 0; i < LOOP_TIMEOUT; ++i) {
+ for (i = 0; i < MMIO_STATUS_TIMEOUT; ++i) {
status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
if (!(status & MMIO_STATUS_GALOG_RUN_MASK))
break;
udelay(10);
}
- if (WARN_ON(i >= LOOP_TIMEOUT))
+ if (WARN_ON(i >= MMIO_STATUS_TIMEOUT))
return;
}
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 95bd7c25ba6f..6fa6a0527d7b 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -44,8 +44,6 @@
#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
-#define LOOP_TIMEOUT 100000
-
/* IO virtual address start page frame number */
#define IOVA_START_PFN (1)
#define IOVA_PFN(addr) ((addr) >> PAGE_SHIFT)
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 03/14] iommu/amd: Consolidate logic to allocate protection domain
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 01/14] iommu/amd: Remove unused amd_io_pgtable.pt_root variable Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 02/14] iommu/amd: Consolidate timeout pre-define to amd_iommu_type.h Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 04/14] iommu/amd: Refactor protection domain allocation code Vasant Hegde
` (11 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Move the logic into the common caller function to simplify the code.
No functional changes intended.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/iommu.c | 19 +++++++------------
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 6fa6a0527d7b..c99611139ab5 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2046,12 +2046,6 @@ static int protection_domain_init_v1(struct protection_domain *domain, int mode)
BUG_ON(mode < PAGE_MODE_NONE || mode > PAGE_MODE_6_LEVEL);
- spin_lock_init(&domain->lock);
- domain->id = domain_id_alloc();
- if (!domain->id)
- return -ENOMEM;
- INIT_LIST_HEAD(&domain->dev_list);
-
if (mode != PAGE_MODE_NONE) {
pt_root = (void *)get_zeroed_page(GFP_KERNEL);
if (!pt_root) {
@@ -2067,12 +2061,6 @@ static int protection_domain_init_v1(struct protection_domain *domain, int mode)
static int protection_domain_init_v2(struct protection_domain *domain)
{
- spin_lock_init(&domain->lock);
- domain->id = domain_id_alloc();
- if (!domain->id)
- return -ENOMEM;
- INIT_LIST_HEAD(&domain->dev_list);
-
domain->flags |= PD_GIOV_MASK;
domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2;
@@ -2112,6 +2100,13 @@ static struct protection_domain *protection_domain_alloc(unsigned int type)
if (!domain)
return NULL;
+ domain->id = domain_id_alloc();
+ if (!domain->id)
+ goto out_err;
+
+ spin_lock_init(&domain->lock);
+ INIT_LIST_HEAD(&domain->dev_list);
+
switch (pgtable) {
case AMD_IOMMU_V1:
ret = protection_domain_init_v1(domain, mode);
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 04/14] iommu/amd: Refactor protection domain allocation code
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (2 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 03/14] iommu/amd: Consolidate logic to allocate protection domain Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 05/14] iommu/amd: Introduce helper functions for managing GCR3 table Vasant Hegde
` (10 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
To replace if-else with switch-case statement due to increasing number of
domain types.
No functional changes intended.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/iommu.c | 45 +++++++++++++++++++--------------------
1 file changed, 22 insertions(+), 23 deletions(-)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index c99611139ab5..bc1fa6e43794 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2078,24 +2078,8 @@ static struct protection_domain *protection_domain_alloc(unsigned int type)
struct io_pgtable_ops *pgtbl_ops;
struct protection_domain *domain;
int pgtable;
- int mode = DEFAULT_PGTABLE_LEVEL;
int ret;
- /*
- * Force IOMMU v1 page table when iommu=pt and
- * when allocating domain for pass-through devices.
- */
- if (type == IOMMU_DOMAIN_IDENTITY) {
- pgtable = AMD_IOMMU_V1;
- mode = PAGE_MODE_NONE;
- } else if (type == IOMMU_DOMAIN_UNMANAGED) {
- pgtable = AMD_IOMMU_V1;
- } else if (type == IOMMU_DOMAIN_DMA || type == IOMMU_DOMAIN_DMA_FQ) {
- pgtable = amd_iommu_pgtable;
- } else {
- return NULL;
- }
-
domain = kzalloc(sizeof(*domain), GFP_KERNEL);
if (!domain)
return NULL;
@@ -2106,27 +2090,42 @@ static struct protection_domain *protection_domain_alloc(unsigned int type)
spin_lock_init(&domain->lock);
INIT_LIST_HEAD(&domain->dev_list);
+ domain->nid = NUMA_NO_NODE;
+
+ switch (type) {
+ /* No need to allocate io pgtable ops in passthrough mode */
+ case IOMMU_DOMAIN_IDENTITY:
+ return domain;
+ case IOMMU_DOMAIN_DMA:
+ case IOMMU_DOMAIN_DMA_FQ:
+ pgtable = amd_iommu_pgtable;
+ break;
+ /*
+ * Force IOMMU v1 page table when allocating
+ * domain for pass-through devices.
+ */
+ case IOMMU_DOMAIN_UNMANAGED:
+ pgtable = AMD_IOMMU_V1;
+ break;
+ default:
+ goto out_err;
+ }
switch (pgtable) {
case AMD_IOMMU_V1:
- ret = protection_domain_init_v1(domain, mode);
+ ret = protection_domain_init_v1(domain, DEFAULT_PGTABLE_LEVEL);
break;
case AMD_IOMMU_V2:
ret = protection_domain_init_v2(domain);
break;
default:
ret = -EINVAL;
+ break;
}
if (ret)
goto out_err;
- /* No need to allocate io pgtable ops in passthrough mode */
- if (type == IOMMU_DOMAIN_IDENTITY)
- return domain;
-
- domain->nid = NUMA_NO_NODE;
-
pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain);
if (!pgtbl_ops) {
domain_id_free(domain->id);
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 05/14] iommu/amd: Introduce helper functions for managing GCR3 table
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (3 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 04/14] iommu/amd: Refactor protection domain allocation code Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 06/14] iommu/amd: Do not set amd_iommu_pgtable in pass-through mode Vasant Hegde
` (9 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Refactor domain_enable_v2() into helper functions for managing GCR3 table
(i.e. setup_gcr3_table() and get_gcr3_levels()), which will be used in
subsequent patches. Also re-arrange code and remove forward declaration.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/iommu.c | 65 +++++++++++++++++++++++----------------
1 file changed, 38 insertions(+), 27 deletions(-)
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index bc1fa6e43794..46a10b489cf5 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -77,7 +77,6 @@ struct iommu_cmd {
struct kmem_cache *amd_iommu_irq_cache;
static void detach_device(struct device *dev);
-static int domain_enable_v2(struct protection_domain *domain, int pasids);
/****************************************************************************
*
@@ -1575,6 +1574,42 @@ static void free_gcr3_table(struct protection_domain *domain)
free_page((unsigned long)domain->gcr3_tbl);
}
+/*
+ * Number of GCR3 table levels required. Level must be 4-Kbyte
+ * page and can contain up to 512 entries.
+ */
+static int get_gcr3_levels(int pasids)
+{
+ int levels;
+
+ if (pasids == -1)
+ return amd_iommu_max_glx_val;
+
+ levels = get_count_order(pasids);
+
+ return levels ? (DIV_ROUND_UP(levels, 9) - 1) : levels;
+}
+
+/* Note: This function expects iommu_domain->lock to be held prior calling the function. */
+static int setup_gcr3_table(struct protection_domain *domain, int pasids)
+{
+ int levels = get_gcr3_levels(pasids);
+
+ if (levels > amd_iommu_max_glx_val)
+ return -EINVAL;
+
+ domain->gcr3_tbl = alloc_pgtable_page(domain->nid, GFP_ATOMIC);
+ if (domain->gcr3_tbl == NULL)
+ return -ENOMEM;
+
+ domain->glx = levels;
+ domain->flags |= PD_IOMMUV2_MASK;
+
+ amd_iommu_domain_update(domain);
+
+ return 0;
+}
+
static void set_dte_entry(struct amd_iommu *iommu, u16 devid,
struct protection_domain *domain, bool ats, bool ppr)
{
@@ -2065,7 +2100,7 @@ static int protection_domain_init_v2(struct protection_domain *domain)
domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2;
- if (domain_enable_v2(domain, 1)) {
+ if (setup_gcr3_table(domain, 1)) {
domain_id_free(domain->id);
return -ENOMEM;
}
@@ -2514,30 +2549,6 @@ void amd_iommu_domain_direct_map(struct iommu_domain *dom)
}
EXPORT_SYMBOL(amd_iommu_domain_direct_map);
-/* Note: This function expects iommu_domain->lock to be held prior calling the function. */
-static int domain_enable_v2(struct protection_domain *domain, int pasids)
-{
- int levels;
-
- /* Number of GCR3 table levels required */
- for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
- levels += 1;
-
- if (levels > amd_iommu_max_glx_val)
- return -EINVAL;
-
- domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
- if (domain->gcr3_tbl == NULL)
- return -ENOMEM;
-
- domain->glx = levels;
- domain->flags |= PD_IOMMUV2_MASK;
-
- amd_iommu_domain_update(domain);
-
- return 0;
-}
-
int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
{
struct protection_domain *pdom = to_pdomain(dom);
@@ -2556,7 +2567,7 @@ int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
goto out;
if (!pdom->gcr3_tbl)
- ret = domain_enable_v2(pdom, pasids);
+ ret = setup_gcr3_table(pdom, pasids);
out:
spin_unlock_irqrestore(&pdom->lock, flags);
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 06/14] iommu/amd: Do not set amd_iommu_pgtable in pass-through mode
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (4 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 05/14] iommu/amd: Introduce helper functions for managing GCR3 table Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 07/14] iommu/amd: Miscellaneous clean up when free domain Vasant Hegde
` (8 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
Since AMD IOMMU page table is not used in passthrough mode, switching to
v1 page table is not required.
Therefore, remove redundant amd_iommu_pgtable update and misleading
warning message.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/init.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 852e40b13d20..2b01dfde6cab 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -2134,9 +2134,6 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
!iommu_feature(iommu, FEATURE_GT)) {
pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n");
amd_iommu_pgtable = AMD_IOMMU_V1;
- } else if (iommu_default_passthrough()) {
- pr_warn("V2 page table doesn't support passthrough mode. Fallback to v1.\n");
- amd_iommu_pgtable = AMD_IOMMU_V1;
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 07/14] iommu/amd: Miscellaneous clean up when free domain
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (5 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 06/14] iommu/amd: Do not set amd_iommu_pgtable in pass-through mode Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 08/14] iommu/amd: Consolidate feature detection and reporting logic Vasant Hegde
` (7 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
* Use the protection_domain_free() helper function to free domain.
The function has been modified to also free memory used for the v1 and v2
page tables. Also clear gcr3 table in v2 page table free path.
* Refactor code into cleanup_domain() for reusability. Change BUG_ON to
WARN_ON in cleanup path.
* Protection domain dev_cnt should be read when the domain is locked.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/io_pgtable_v2.c | 8 +++---
drivers/iommu/amd/iommu.c | 44 +++++++++++++++----------------
2 files changed, 26 insertions(+), 26 deletions(-)
diff --git a/drivers/iommu/amd/io_pgtable_v2.c b/drivers/iommu/amd/io_pgtable_v2.c
index e9ef2e0a62f6..f818a7e254d4 100644
--- a/drivers/iommu/amd/io_pgtable_v2.c
+++ b/drivers/iommu/amd/io_pgtable_v2.c
@@ -363,10 +363,10 @@ static void v2_free_pgtable(struct io_pgtable *iop)
if (!(pdom->flags & PD_IOMMUV2_MASK))
return;
- /*
- * Make changes visible to IOMMUs. No need to clear gcr3 entry
- * as gcr3 table is already freed.
- */
+ /* Clear gcr3 entry */
+ amd_iommu_domain_clear_gcr3(&pdom->domain, 0);
+
+ /* Make changes visible to IOMMUs */
amd_iommu_domain_update(pdom);
/* Free page table */
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 46a10b489cf5..0dd8390113af 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -2047,9 +2047,11 @@ void amd_iommu_domain_update(struct protection_domain *domain)
static void cleanup_domain(struct protection_domain *domain)
{
struct iommu_dev_data *entry;
- unsigned long flags;
- spin_lock_irqsave(&domain->lock, flags);
+ lockdep_assert_held(&domain->lock);
+
+ if (!domain->dev_cnt)
+ return;
while (!list_empty(&domain->dev_list)) {
entry = list_first_entry(&domain->dev_list,
@@ -2057,8 +2059,7 @@ static void cleanup_domain(struct protection_domain *domain)
BUG_ON(!entry->domain);
do_detach(entry);
}
-
- spin_unlock_irqrestore(&domain->lock, flags);
+ WARN_ON(domain->dev_cnt != 0);
}
static void protection_domain_free(struct protection_domain *domain)
@@ -2069,6 +2070,12 @@ static void protection_domain_free(struct protection_domain *domain)
if (domain->iop.pgtbl_cfg.tlb)
free_io_pgtable_ops(&domain->iop.iop.ops);
+ if (domain->flags & PD_IOMMUV2_MASK)
+ free_gcr3_table(domain);
+
+ if (domain->iop.root)
+ free_page((unsigned long)domain->iop.root);
+
if (domain->id)
domain_id_free(domain->id);
@@ -2083,10 +2090,8 @@ static int protection_domain_init_v1(struct protection_domain *domain, int mode)
if (mode != PAGE_MODE_NONE) {
pt_root = (void *)get_zeroed_page(GFP_KERNEL);
- if (!pt_root) {
- domain_id_free(domain->id);
+ if (!pt_root)
return -ENOMEM;
- }
}
amd_iommu_domain_set_pgtable(domain, pt_root, mode);
@@ -2100,10 +2105,8 @@ static int protection_domain_init_v2(struct protection_domain *domain)
domain->domain.pgsize_bitmap = AMD_IOMMU_PGSIZES_V2;
- if (setup_gcr3_table(domain, 1)) {
- domain_id_free(domain->id);
+ if (setup_gcr3_table(domain, 1))
return -ENOMEM;
- }
return 0;
}
@@ -2162,14 +2165,12 @@ static struct protection_domain *protection_domain_alloc(unsigned int type)
goto out_err;
pgtbl_ops = alloc_io_pgtable_ops(pgtable, &domain->iop.pgtbl_cfg, domain);
- if (!pgtbl_ops) {
- domain_id_free(domain->id);
+ if (!pgtbl_ops)
goto out_err;
- }
return domain;
out_err:
- kfree(domain);
+ protection_domain_free(domain);
return NULL;
}
@@ -2207,19 +2208,18 @@ static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
static void amd_iommu_domain_free(struct iommu_domain *dom)
{
struct protection_domain *domain;
+ unsigned long flags;
- domain = to_pdomain(dom);
+ if (!dom)
+ return;
- if (domain->dev_cnt > 0)
- cleanup_domain(domain);
+ domain = to_pdomain(dom);
- BUG_ON(domain->dev_cnt != 0);
+ spin_lock_irqsave(&domain->lock, flags);
- if (!dom)
- return;
+ cleanup_domain(domain);
- if (domain->flags & PD_IOMMUV2_MASK)
- free_gcr3_table(domain);
+ spin_unlock_irqrestore(&domain->lock, flags);
protection_domain_free(domain);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 08/14] iommu/amd: Consolidate feature detection and reporting logic
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (6 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 07/14] iommu/amd: Miscellaneous clean up when free domain Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 09/14] iommu/amd: Modify logic for checking GT and PPR features Vasant Hegde
` (6 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Currently, IOMMU driver assumes capabilities on all IOMMU instances to be
homogeneous. During early_amd_iommu_init(), the driver probes all IVHD
blocks and do sanity check to make sure that only features common among all
IOMMU instances are supported. This is tracked in the global amd_iommu_efr
and amd_iommu_efr2, which should be used whenever the driver need to check
hardware capabilities.
Therefore, introduce check_feature() and check_feature2(), and modify
the driver to adopt the new helper functions.
In addition, clean up the print_iommu_info() to avoid reporting redundant
EFR/EFR2 for each IOMMU instance.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/amd_iommu.h | 17 ++++--
drivers/iommu/amd/amd_iommu_types.h | 4 ++
drivers/iommu/amd/init.c | 89 ++++++++++++-----------------
drivers/iommu/amd/iommu.c | 4 +-
4 files changed, 54 insertions(+), 60 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index c5090e00b3aa..e1b0eeead074 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -87,9 +87,19 @@ static inline bool is_rd890_iommu(struct pci_dev *pdev)
(pdev->device == PCI_DEVICE_ID_RD890_IOMMU);
}
-static inline bool iommu_feature(struct amd_iommu *iommu, u64 mask)
+static inline bool check_feature(u64 mask)
{
- return !!(iommu->features & mask);
+ return (amd_iommu_efr & mask);
+}
+
+static inline bool check_feature2(u64 mask)
+{
+ return (amd_iommu_efr2 & mask);
+}
+
+static inline int check_feature_gpt_level(void)
+{
+ return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK);
}
static inline u64 iommu_virt_to_phys(void *vaddr)
@@ -145,8 +155,5 @@ void amd_iommu_domain_set_pgtable(struct protection_domain *domain,
u64 *root, int mode);
struct dev_table_entry *get_dev_table(struct amd_iommu *iommu);
-extern u64 amd_iommu_efr;
-extern u64 amd_iommu_efr2;
-
extern bool amd_iommu_snp_en;
#endif
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index a8d264026f7f..22bdfb0ddfb7 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -897,6 +897,10 @@ extern bool amd_iommu_force_isolation;
/* Max levels of glxval supported */
extern int amd_iommu_max_glx_val;
+/* Global EFR and EFR2 registers */
+extern u64 amd_iommu_efr;
+extern u64 amd_iommu_efr2;
+
/*
* This function flushes all internal caches of
* the IOMMU used by this driver.
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 2b01dfde6cab..d0d506ad9cc9 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -270,7 +270,7 @@ int amd_iommu_get_num_iommus(void)
* Iterate through all the IOMMUs to get common EFR
* masks among all IOMMUs and warn if found inconsistency.
*/
-static void get_global_efr(void)
+static __init void get_global_efr(void)
{
struct amd_iommu *iommu;
@@ -302,16 +302,6 @@ static void get_global_efr(void)
pr_info("Using global IVHD EFR:%#llx, EFR2:%#llx\n", amd_iommu_efr, amd_iommu_efr2);
}
-static bool check_feature_on_all_iommus(u64 mask)
-{
- return !!(amd_iommu_efr & mask);
-}
-
-static inline int check_feature_gpt_level(void)
-{
- return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK);
-}
-
/*
* For IVHD type 0x11/0x40, EFR is also available via IVHD.
* Default to IVHD EFR since it is available sooner
@@ -397,7 +387,7 @@ static void iommu_set_cwwb_range(struct amd_iommu *iommu)
u64 start = iommu_virt_to_phys((void *)iommu->cmd_sem);
u64 entry = start & PM_ADDR_MASK;
- if (!check_feature_on_all_iommus(FEATURE_SNP))
+ if (!check_feature(FEATURE_SNP))
return;
/* Note:
@@ -867,7 +857,7 @@ static void *__init iommu_alloc_4k_pages(struct amd_iommu *iommu,
void *buf = (void *)__get_free_pages(gfp, order);
if (buf &&
- check_feature_on_all_iommus(FEATURE_SNP) &&
+ check_feature(FEATURE_SNP) &&
set_memory_4k((unsigned long)buf, (1 << order))) {
free_pages((unsigned long)buf, order);
buf = NULL;
@@ -1046,7 +1036,7 @@ static void iommu_enable_xt(struct amd_iommu *iommu)
static void iommu_enable_gt(struct amd_iommu *iommu)
{
- if (!iommu_feature(iommu, FEATURE_GT))
+ if (!check_feature(FEATURE_GT))
return;
iommu_feature_enable(iommu, CONTROL_GT_EN);
@@ -1985,7 +1975,7 @@ static void init_iommu_perf_ctr(struct amd_iommu *iommu)
u64 val;
struct pci_dev *pdev = iommu->dev;
- if (!iommu_feature(iommu, FEATURE_PC))
+ if (!check_feature(FEATURE_PC))
return;
amd_iommu_pc_present = true;
@@ -2012,8 +2002,7 @@ static ssize_t amd_iommu_show_features(struct device *dev,
struct device_attribute *attr,
char *buf)
{
- struct amd_iommu *iommu = dev_to_amd_iommu(dev);
- return sysfs_emit(buf, "%llx:%llx\n", iommu->features2, iommu->features);
+ return sysfs_emit(buf, "%llx:%llx\n", amd_iommu_efr, amd_iommu_efr2);
}
static DEVICE_ATTR(features, S_IRUGO, amd_iommu_show_features, NULL);
@@ -2049,9 +2038,9 @@ static void __init late_iommu_features_init(struct amd_iommu *iommu)
features = readq(iommu->mmio_base + MMIO_EXT_FEATURES);
features2 = readq(iommu->mmio_base + MMIO_EXT_FEATURES2);
- if (!iommu->features) {
- iommu->features = features;
- iommu->features2 = features2;
+ if (!amd_iommu_efr) {
+ amd_iommu_efr = features;
+ amd_iommu_efr2 = features2;
return;
}
@@ -2059,12 +2048,12 @@ static void __init late_iommu_features_init(struct amd_iommu *iommu)
* Sanity check and warn if EFR values from
* IVHD and MMIO conflict.
*/
- if (features != iommu->features ||
- features2 != iommu->features2) {
+ if (features != amd_iommu_efr ||
+ features2 != amd_iommu_efr2) {
pr_warn(FW_WARN
"EFR mismatch. Use IVHD EFR (%#llx : %#llx), EFR2 (%#llx : %#llx).\n",
- features, iommu->features,
- features2, iommu->features2);
+ features, amd_iommu_efr,
+ features2, amd_iommu_efr2);
}
}
@@ -2090,12 +2079,12 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
late_iommu_features_init(iommu);
- if (iommu_feature(iommu, FEATURE_GT)) {
+ if (check_feature(FEATURE_GT)) {
int glxval;
u32 max_pasid;
u64 pasmax;
- pasmax = iommu->features & FEATURE_PASID_MASK;
+ pasmax = amd_iommu_efr & FEATURE_PASID_MASK;
pasmax >>= FEATURE_PASID_SHIFT;
max_pasid = (1 << (pasmax + 1)) - 1;
@@ -2103,7 +2092,7 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
- glxval = iommu->features & FEATURE_GLXVAL_MASK;
+ glxval = amd_iommu_efr & FEATURE_GLXVAL_MASK;
glxval >>= FEATURE_GLXVAL_SHIFT;
if (amd_iommu_max_glx_val == -1)
@@ -2112,13 +2101,13 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
}
- if (iommu_feature(iommu, FEATURE_GT) &&
- iommu_feature(iommu, FEATURE_PPR)) {
+ if (check_feature(FEATURE_GT) &&
+ check_feature(FEATURE_PPR)) {
iommu->is_iommu_v2 = true;
amd_iommu_v2_present = true;
}
- if (iommu_feature(iommu, FEATURE_PPR) && alloc_ppr_log(iommu))
+ if (check_feature(FEATURE_PPR) && alloc_ppr_log(iommu))
return -ENOMEM;
if (iommu->cap & (1UL << IOMMU_CAP_NPCACHE)) {
@@ -2130,8 +2119,8 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
init_iommu_perf_ctr(iommu);
if (amd_iommu_pgtable == AMD_IOMMU_V2) {
- if (!iommu_feature(iommu, FEATURE_GIOSUP) ||
- !iommu_feature(iommu, FEATURE_GT)) {
+ if (!check_feature(FEATURE_GIOSUP) ||
+ !check_feature(FEATURE_GT)) {
pr_warn("Cannot enable v2 page table for DMA-API. Fallback to v1.\n");
amd_iommu_pgtable = AMD_IOMMU_V1;
}
@@ -2181,35 +2170,29 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
static void print_iommu_info(void)
{
+ int i;
static const char * const feat_str[] = {
"PreF", "PPR", "X2APIC", "NX", "GT", "[5]",
"IA", "GA", "HE", "PC"
};
- struct amd_iommu *iommu;
-
- for_each_iommu(iommu) {
- struct pci_dev *pdev = iommu->dev;
- int i;
-
- pci_info(pdev, "Found IOMMU cap 0x%x\n", iommu->cap_ptr);
- if (iommu->cap & (1 << IOMMU_CAP_EFR)) {
- pr_info("Extended features (%#llx, %#llx):", iommu->features, iommu->features2);
+ if (amd_iommu_efr) {
+ pr_info("Extended features (%#llx, %#llx):", amd_iommu_efr, amd_iommu_efr2);
- for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
- if (iommu_feature(iommu, (1ULL << i)))
- pr_cont(" %s", feat_str[i]);
- }
+ for (i = 0; i < ARRAY_SIZE(feat_str); ++i) {
+ if (check_feature(1ULL << i))
+ pr_cont(" %s", feat_str[i]);
+ }
- if (iommu->features & FEATURE_GAM_VAPIC)
- pr_cont(" GA_vAPIC");
+ if (check_feature(FEATURE_GAM_VAPIC))
+ pr_cont(" GA_vAPIC");
- if (iommu->features & FEATURE_SNP)
- pr_cont(" SNP");
+ if (check_feature(FEATURE_SNP))
+ pr_cont(" SNP");
- pr_cont("\n");
- }
+ pr_cont("\n");
}
+
if (irq_remapping_enabled) {
pr_info("Interrupt remapping enabled\n");
if (amd_iommu_xt_mode == IRQ_REMAP_X2APIC_MODE)
@@ -2907,7 +2890,7 @@ static void enable_iommus_vapic(void)
}
if (AMD_IOMMU_GUEST_IR_VAPIC(amd_iommu_guest_ir) &&
- !check_feature_on_all_iommus(FEATURE_GAM_VAPIC)) {
+ !check_feature(FEATURE_GAM_VAPIC)) {
amd_iommu_guest_ir = AMD_IOMMU_GUEST_IR_LEGACY_GA;
return;
}
@@ -3819,7 +3802,7 @@ int amd_iommu_snp_enable(void)
return -EINVAL;
}
- amd_iommu_snp_en = check_feature_on_all_iommus(FEATURE_SNP);
+ amd_iommu_snp_en = check_feature(FEATURE_SNP);
if (!amd_iommu_snp_en)
return -EINVAL;
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 0dd8390113af..6b9c4a9ef150 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1295,7 +1295,7 @@ static void amd_iommu_flush_irt_all(struct amd_iommu *iommu)
void iommu_flush_all_caches(struct amd_iommu *iommu)
{
- if (iommu_feature(iommu, FEATURE_IA)) {
+ if (check_feature(FEATURE_IA)) {
amd_iommu_flush_all(iommu);
} else {
amd_iommu_flush_dte_all(iommu);
@@ -1639,7 +1639,7 @@ static void set_dte_entry(struct amd_iommu *iommu, u16 devid,
flags |= DTE_FLAG_IOTLB;
if (ppr) {
- if (iommu_feature(iommu, FEATURE_EPHSUP))
+ if (check_feature(FEATURE_EPHSUP))
pte_root |= 1ULL << DEV_ENTRY_PPR;
}
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 09/14] iommu/amd: Modify logic for checking GT and PPR features
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (7 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 08/14] iommu/amd: Consolidate feature detection and reporting logic Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 10/14] iommu/amd: Rename ats related variables Vasant Hegde
` (5 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
In order to support v2 page table, IOMMU driver need to check if the
hardware can support Guest Translation (GT) and Peripheral Page Request
(PPR) features. Currently, IOMMU driver uses global (amd_iommu_v2_present)
and per-iommu (struct amd_iommu.is_iommu_v2) variables to track the
features. There variables area redundant since we could simply just check
the global EFR mask.
Therefore, replace it with a helper function with appropriate name.
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/amd_iommu.h | 6 ++++++
drivers/iommu/amd/amd_iommu_types.h | 5 -----
drivers/iommu/amd/init.c | 9 +--------
drivers/iommu/amd/iommu.c | 2 +-
4 files changed, 8 insertions(+), 14 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index e1b0eeead074..5395a21215b9 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -102,6 +102,12 @@ static inline int check_feature_gpt_level(void)
return ((amd_iommu_efr >> FEATURE_GATS_SHIFT) & FEATURE_GATS_MASK);
}
+static inline bool amd_iommu_gt_ppr_supported(void)
+{
+ return (check_feature(FEATURE_GT) &&
+ check_feature(FEATURE_PPR));
+}
+
static inline u64 iommu_virt_to_phys(void *vaddr)
{
return (u64)__sme_set(virt_to_phys(vaddr));
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 22bdfb0ddfb7..29e76c1e9f9e 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -679,9 +679,6 @@ struct amd_iommu {
/* Extended features 2 */
u64 features2;
- /* IOMMUv2 */
- bool is_iommu_v2;
-
/* PCI device id of the IOMMU device */
u16 devid;
@@ -890,8 +887,6 @@ extern unsigned long *amd_iommu_pd_alloc_bitmap;
/* Smallest max PASID supported by any IOMMU in the system */
extern u32 amd_iommu_max_pasid;
-extern bool amd_iommu_v2_present;
-
extern bool amd_iommu_force_isolation;
/* Max levels of glxval supported */
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index d0d506ad9cc9..06b319006ce2 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -187,7 +187,6 @@ bool amd_iommu_iotlb_sup __read_mostly = true;
u32 amd_iommu_max_pasid __read_mostly = ~0;
-bool amd_iommu_v2_present __read_mostly;
static bool amd_iommu_pc_present __read_mostly;
bool amdr_ivrs_remap_support __read_mostly;
@@ -2101,12 +2100,6 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
amd_iommu_max_glx_val = min(amd_iommu_max_glx_val, glxval);
}
- if (check_feature(FEATURE_GT) &&
- check_feature(FEATURE_PPR)) {
- iommu->is_iommu_v2 = true;
- amd_iommu_v2_present = true;
- }
-
if (check_feature(FEATURE_PPR) && alloc_ppr_log(iommu))
return -ENOMEM;
@@ -3676,7 +3669,7 @@ bool amd_iommu_v2_supported(void)
* (i.e. EFR[SNPSup]=1), IOMMUv2 page table cannot be used without
* setting up IOMMUv1 page table.
*/
- return amd_iommu_v2_present && !amd_iommu_snp_en;
+ return amd_iommu_gt_ppr_supported() && !amd_iommu_snp_en;
}
EXPORT_SYMBOL(amd_iommu_v2_supported);
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 6b9c4a9ef150..126f58784829 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -397,7 +397,7 @@ static int iommu_init_device(struct amd_iommu *iommu, struct device *dev)
*/
if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
- dev_data->iommu_v2 = iommu->is_iommu_v2;
+ dev_data->iommu_v2 = amd_iommu_gt_ppr_supported();
}
dev_iommu_priv_set(dev, dev_data);
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 10/14] iommu/amd: Rename ats related variables
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (8 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 09/14] iommu/amd: Modify logic for checking GT and PPR features Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 11/14] iommu/amd: Introduce iommu_dev_data.ppr Vasant Hegde
` (4 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
Remove nested structure and make it as 'ats_{enable/qdep}'.
Also convert 'dev_data.pri_tlp' to bit field.
No functional changes intended.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/amd_iommu_types.h | 8 +++-----
drivers/iommu/amd/iommu.c | 28 ++++++++++++++--------------
2 files changed, 17 insertions(+), 19 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 29e76c1e9f9e..1c61dca63824 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -812,11 +812,9 @@ struct iommu_dev_data {
struct device *dev;
u16 devid; /* PCI Device ID */
bool iommu_v2; /* Device can make use of IOMMUv2 */
- struct {
- bool enabled;
- int qdep;
- } ats; /* ATS state */
- bool pri_tlp; /* PASID TLB required for
+ int ats_qdep;
+ u8 ats_enabled :1; /* ATS state */
+ u8 pri_tlp :1; /* PASID TLB required for
PPR completions */
bool use_vapic; /* Enable device to use vapic mode */
bool defer_attach;
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 126f58784829..433000276923 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1091,7 +1091,7 @@ static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, u32 pasid,
}
static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, u32 pasid,
- int status, int tag, bool gn)
+ int status, int tag, u8 gn)
{
memset(cmd, 0, sizeof(*cmd));
@@ -1314,7 +1314,7 @@ static int device_flush_iotlb(struct iommu_dev_data *dev_data,
struct iommu_cmd cmd;
int qdep;
- qdep = dev_data->ats.qdep;
+ qdep = dev_data->ats_qdep;
iommu = rlookup_amd_iommu(dev_data->dev);
if (!iommu)
return -EINVAL;
@@ -1365,7 +1365,7 @@ static int device_flush_dte(struct iommu_dev_data *dev_data)
return ret;
}
- if (dev_data->ats.enabled)
+ if (dev_data->ats_enabled)
ret = device_flush_iotlb(dev_data, 0, ~0UL);
return ret;
@@ -1398,7 +1398,7 @@ static void __domain_flush_pages(struct protection_domain *domain,
list_for_each_entry(dev_data, &domain->dev_list, list) {
- if (!dev_data->ats.enabled)
+ if (!dev_data->ats_enabled)
continue;
ret |= device_flush_iotlb(dev_data, address, size);
@@ -1718,7 +1718,7 @@ static void do_attach(struct iommu_dev_data *dev_data,
iommu = rlookup_amd_iommu(dev_data->dev);
if (!iommu)
return;
- ats = dev_data->ats.enabled;
+ ats = dev_data->ats_enabled;
/* Update data structures */
dev_data->domain = domain;
@@ -1856,14 +1856,14 @@ static int attach_device(struct device *dev,
if (pdev_pri_ats_enable(pdev) != 0)
goto out;
- dev_data->ats.enabled = true;
- dev_data->ats.qdep = pci_ats_queue_depth(pdev);
+ dev_data->ats_enabled = 1;
+ dev_data->ats_qdep = pci_ats_queue_depth(pdev);
dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
}
} else if (amd_iommu_iotlb_sup &&
pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
- dev_data->ats.enabled = true;
- dev_data->ats.qdep = pci_ats_queue_depth(pdev);
+ dev_data->ats_enabled = 1;
+ dev_data->ats_qdep = pci_ats_queue_depth(pdev);
}
skip_ats_check:
@@ -1920,10 +1920,10 @@ static void detach_device(struct device *dev)
if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
pdev_iommuv2_disable(to_pci_dev(dev));
- else if (dev_data->ats.enabled)
+ else if (dev_data->ats_enabled)
pci_disable_ats(to_pci_dev(dev));
- dev_data->ats.enabled = false;
+ dev_data->ats_enabled = 0;
out:
spin_unlock(&dev_data->lock);
@@ -2013,7 +2013,7 @@ static void update_device_table(struct protection_domain *domain)
if (!iommu)
continue;
set_dte_entry(iommu, dev_data->devid, domain,
- dev_data->ats.enabled, dev_data->iommu_v2);
+ dev_data->ats_enabled, dev_data->iommu_v2);
clone_aliases(iommu, dev_data->dev);
}
}
@@ -2612,10 +2612,10 @@ static int __flush_pasid(struct protection_domain *domain, u32 pasid,
There might be non-IOMMUv2 capable devices in an IOMMUv2
* domain.
*/
- if (!dev_data->ats.enabled)
+ if (!dev_data->ats_enabled)
continue;
- qdep = dev_data->ats.qdep;
+ qdep = dev_data->ats_qdep;
iommu = rlookup_amd_iommu(dev_data->dev);
if (!iommu)
continue;
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 11/14] iommu/amd: Introduce iommu_dev_data.ppr
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (9 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 10/14] iommu/amd: Rename ats related variables Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 12/14] iommu/amd: Introduce iommu_dev_data.flags to track device capabilities Vasant Hegde
` (3 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
From: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
For AMD IOMMU, the PPR feature is needed to support IO page fault (IOPF).
PPR is enabled per PCI end-point device, and is configured by the PPR bit
in the IOMMU device table entry (i.e DTE[PPR]).
Introducing struct iommu_dev_data.ppr track PPR setting for each device.
Also iommu_dev_data.ppr will be set only when IOMMU supports PPR. Hence
remove redundant feature support check in set_dte_entry().
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Co-developed-by: Vasant Hegde <vasant.hegde@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/amd_iommu_types.h | 1 +
drivers/iommu/amd/iommu.c | 10 ++++------
2 files changed, 5 insertions(+), 6 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 1c61dca63824..87fa39c490e8 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -816,6 +816,7 @@ struct iommu_dev_data {
u8 ats_enabled :1; /* ATS state */
u8 pri_tlp :1; /* PASID TLB required for
PPR completions */
+ u8 ppr :1; /* Enable device PPR support */
bool use_vapic; /* Enable device to use vapic mode */
bool defer_attach;
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 433000276923..4ee69ccdc17b 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -1638,10 +1638,8 @@ static void set_dte_entry(struct amd_iommu *iommu, u16 devid,
if (ats)
flags |= DTE_FLAG_IOTLB;
- if (ppr) {
- if (check_feature(FEATURE_EPHSUP))
- pte_root |= 1ULL << DEV_ENTRY_PPR;
- }
+ if (ppr)
+ pte_root |= 1ULL << DEV_ENTRY_PPR;
if (domain->flags & PD_IOMMUV2_MASK) {
u64 gcr3 = iommu_virt_to_phys(domain->gcr3_tbl);
@@ -1734,7 +1732,7 @@ static void do_attach(struct iommu_dev_data *dev_data,
/* Update device table */
set_dte_entry(iommu, dev_data->devid, domain,
- ats, dev_data->iommu_v2);
+ ats, dev_data->ppr);
clone_aliases(iommu, dev_data->dev);
device_flush_dte(dev_data);
@@ -2013,7 +2011,7 @@ static void update_device_table(struct protection_domain *domain)
if (!iommu)
continue;
set_dte_entry(iommu, dev_data->devid, domain,
- dev_data->ats_enabled, dev_data->iommu_v2);
+ dev_data->ats_enabled, dev_data->ppr);
clone_aliases(iommu, dev_data->dev);
}
}
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 12/14] iommu/amd: Introduce iommu_dev_data.flags to track device capabilities
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (10 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 11/14] iommu/amd: Introduce iommu_dev_data.ppr Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 13/14] iommu/amd: Enable device ATS/PASID/PRI capabilities independently Vasant Hegde
` (2 subsequent siblings)
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
Currently we use struct iommu_dev_data.iommu_v2 to keep track of the device
ATS, PRI, and PASID capabilities. But these capabilities can be enabled
independently (except PRI requires ATS support). Hence, replace
the iommu_v2 variable with a flags variable, which keep track of the device
capabilities.
From commit 9bf49e36d718 ("PCI/ATS: Handle sharing of PF PRI Capability
with all VFs"), device PRI/PASID is shared between PF and any associated
VFs. Hence use pci_pri_supported() and pci_pasid_features() instead of
pci_find_ext_capability() to check device PRI/PASID support.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/amd_iommu_types.h | 3 +-
drivers/iommu/amd/iommu.c | 46 ++++++++++++++++++-----------
2 files changed, 30 insertions(+), 19 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 87fa39c490e8..07f8919ee34e 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -811,7 +811,8 @@ struct iommu_dev_data {
struct protection_domain *domain; /* Domain the device is bound to */
struct device *dev;
u16 devid; /* PCI Device ID */
- bool iommu_v2; /* Device can make use of IOMMUv2 */
+
+ u32 flags; /* Holds AMD_IOMMU_DEVICE_FLAG_<*> */
int ats_qdep;
u8 ats_enabled :1; /* ATS state */
u8 pri_tlp :1; /* PASID TLB required for
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 4ee69ccdc17b..151f405686e3 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -319,24 +319,34 @@ static struct iommu_group *acpihid_device_group(struct device *dev)
return entry->group;
}
-static bool pci_iommuv2_capable(struct pci_dev *pdev)
+static inline bool pdev_pasid_supported(struct iommu_dev_data *dev_data)
{
- static const int caps[] = {
- PCI_EXT_CAP_ID_PRI,
- PCI_EXT_CAP_ID_PASID,
- };
- int i, pos;
+ return (dev_data->flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP);
+}
- if (!pci_ats_supported(pdev))
- return false;
+static u32 pdev_get_caps(struct pci_dev *pdev)
+{
+ int features;
+ u32 flags = 0;
+
+ if (pci_ats_supported(pdev))
+ flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
+
+ if (pci_pri_supported(pdev))
+ flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
- for (i = 0; i < 2; ++i) {
- pos = pci_find_ext_capability(pdev, caps[i]);
- if (pos == 0)
- return false;
+ features = pci_pasid_features(pdev);
+ if (features >= 0) {
+ flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
+
+ if (features & PCI_PASID_CAP_EXEC)
+ flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
+
+ if (features & PCI_PASID_CAP_PRIV)
+ flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
}
- return true;
+ return flags;
}
/*
@@ -396,8 +406,8 @@ static int iommu_init_device(struct amd_iommu *iommu, struct device *dev)
* it'll be forced to go into translation mode.
*/
if ((iommu_default_passthrough() || !amd_iommu_force_isolation) &&
- dev_is_pci(dev) && pci_iommuv2_capable(to_pci_dev(dev))) {
- dev_data->iommu_v2 = amd_iommu_gt_ppr_supported();
+ dev_is_pci(dev) && amd_iommu_gt_ppr_supported()) {
+ dev_data->flags = pdev_get_caps(to_pci_dev(dev));
}
dev_iommu_priv_set(dev, dev_data);
@@ -1850,7 +1860,7 @@ static int attach_device(struct device *dev,
goto out;
}
- if (dev_data->iommu_v2) {
+ if (pdev_pasid_supported(dev_data)) {
if (pdev_pri_ats_enable(pdev) != 0)
goto out;
@@ -1916,7 +1926,7 @@ static void detach_device(struct device *dev)
if (!dev_is_pci(dev))
goto out;
- if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
+ if (domain->flags & PD_IOMMUV2_MASK && pdev_pasid_supported(dev_data))
pdev_iommuv2_disable(to_pci_dev(dev));
else if (dev_data->ats_enabled)
pci_disable_ats(to_pci_dev(dev));
@@ -2471,7 +2481,7 @@ static int amd_iommu_def_domain_type(struct device *dev)
* and require remapping.
* - SNP is enabled, because it prohibits DTE[Mode]=0.
*/
- if (dev_data->iommu_v2 &&
+ if (pdev_pasid_supported(dev_data) &&
!cc_platform_has(CC_ATTR_MEM_ENCRYPT) &&
!amd_iommu_snp_en) {
return IOMMU_DOMAIN_IDENTITY;
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 13/14] iommu/amd: Enable device ATS/PASID/PRI capabilities independently
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (11 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 12/14] iommu/amd: Introduce iommu_dev_data.flags to track device capabilities Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:21 ` [PATCH v6 14/14] iommu/amd: Initialize iommu_device->max_pasids Vasant Hegde
2023-09-21 9:49 ` [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
Introduce helper functions to enable/disable device ATS/PASID/PRI
capabilities independently along with the new pasid_enabled and
pri_enabled variables in struct iommu_dev_data to keep track,
which allows attach_device() and detach_device() to be simplified.
Co-developed-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/amd_iommu.h | 4 +
drivers/iommu/amd/amd_iommu_types.h | 2 +
drivers/iommu/amd/iommu.c | 203 ++++++++++++++++------------
3 files changed, 120 insertions(+), 89 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu.h b/drivers/iommu/amd/amd_iommu.h
index 5395a21215b9..9df53961d5ef 100644
--- a/drivers/iommu/amd/amd_iommu.h
+++ b/drivers/iommu/amd/amd_iommu.h
@@ -51,6 +51,10 @@ int amd_iommu_pc_get_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
int amd_iommu_pc_set_reg(struct amd_iommu *iommu, u8 bank, u8 cntr,
u8 fxn, u64 *value);
+/* Device capabilities */
+int amd_iommu_pdev_enable_cap_pri(struct pci_dev *pdev);
+void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev);
+
int amd_iommu_register_ppr_notifier(struct notifier_block *nb);
int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb);
void amd_iommu_domain_direct_map(struct iommu_domain *dom);
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index 07f8919ee34e..c6d47cb7a0ee 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -815,6 +815,8 @@ struct iommu_dev_data {
u32 flags; /* Holds AMD_IOMMU_DEVICE_FLAG_<*> */
int ats_qdep;
u8 ats_enabled :1; /* ATS state */
+ u8 pri_enabled :1; /* PRI state */
+ u8 pasid_enabled:1; /* PASID state */
u8 pri_tlp :1; /* PASID TLB required for
PPR completions */
u8 ppr :1; /* Enable device PPR support */
diff --git a/drivers/iommu/amd/iommu.c b/drivers/iommu/amd/iommu.c
index 151f405686e3..f3448a2b6c0e 100644
--- a/drivers/iommu/amd/iommu.c
+++ b/drivers/iommu/amd/iommu.c
@@ -349,6 +349,113 @@ static u32 pdev_get_caps(struct pci_dev *pdev)
return flags;
}
+static inline int pdev_enable_cap_ats(struct pci_dev *pdev)
+{
+ struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev);
+ int ret = -EINVAL;
+
+ if (dev_data->ats_enabled)
+ return 0;
+
+ if (amd_iommu_iotlb_sup &&
+ (dev_data->flags & AMD_IOMMU_DEVICE_FLAG_ATS_SUP)) {
+ ret = pci_enable_ats(pdev, PAGE_SHIFT);
+ if (!ret) {
+ dev_data->ats_enabled = 1;
+ dev_data->ats_qdep = pci_ats_queue_depth(pdev);
+ }
+ }
+
+ return ret;
+}
+
+static inline void pdev_disable_cap_ats(struct pci_dev *pdev)
+{
+ struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev);
+
+ if (dev_data->ats_enabled) {
+ pci_disable_ats(pdev);
+ dev_data->ats_enabled = 0;
+ }
+}
+
+int amd_iommu_pdev_enable_cap_pri(struct pci_dev *pdev)
+{
+ struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev);
+ int ret = -EINVAL;
+
+ if (dev_data->pri_enabled)
+ return 0;
+
+ if (dev_data->flags & AMD_IOMMU_DEVICE_FLAG_PRI_SUP) {
+ /*
+ * First reset the PRI state of the device.
+ * FIXME: Hardcode number of outstanding requests for now
+ */
+ if (!pci_reset_pri(pdev) && !pci_enable_pri(pdev, 32)) {
+ dev_data->pri_enabled = 1;
+ dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
+
+ ret = 0;
+ }
+ }
+
+ return ret;
+}
+
+void amd_iommu_pdev_disable_cap_pri(struct pci_dev *pdev)
+{
+ struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev);
+
+ if (dev_data->pri_enabled) {
+ pci_disable_pri(pdev);
+ dev_data->pri_enabled = 0;
+ }
+}
+
+static inline int pdev_enable_cap_pasid(struct pci_dev *pdev)
+{
+ struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev);
+ int ret = -EINVAL;
+
+ if (dev_data->pasid_enabled)
+ return 0;
+
+ if (dev_data->flags & AMD_IOMMU_DEVICE_FLAG_PASID_SUP) {
+ /* Only allow access to user-accessible pages */
+ ret = pci_enable_pasid(pdev, 0);
+ if (!ret)
+ dev_data->pasid_enabled = 1;
+ }
+
+ return ret;
+}
+
+static inline void pdev_disable_cap_pasid(struct pci_dev *pdev)
+{
+ struct iommu_dev_data *dev_data = dev_iommu_priv_get(&pdev->dev);
+
+ if (dev_data->pasid_enabled) {
+ pci_disable_pasid(pdev);
+ dev_data->pasid_enabled = 0;
+ }
+}
+
+static void pdev_enable_caps(struct pci_dev *pdev)
+{
+ pdev_enable_cap_ats(pdev);
+ pdev_enable_cap_pasid(pdev);
+ amd_iommu_pdev_enable_cap_pri(pdev);
+
+}
+
+static void pdev_disable_caps(struct pci_dev *pdev)
+{
+ pdev_disable_cap_ats(pdev);
+ pdev_disable_cap_pasid(pdev);
+ amd_iommu_pdev_disable_cap_pri(pdev);
+}
+
/*
* This function checks if the driver got a valid device from the caller to
* avoid dereferencing invalid pointers.
@@ -1777,48 +1884,6 @@ static void do_detach(struct iommu_dev_data *dev_data)
domain->dev_cnt -= 1;
}
-static void pdev_iommuv2_disable(struct pci_dev *pdev)
-{
- pci_disable_ats(pdev);
- pci_disable_pri(pdev);
- pci_disable_pasid(pdev);
-}
-
-static int pdev_pri_ats_enable(struct pci_dev *pdev)
-{
- int ret;
-
- /* Only allow access to user-accessible pages */
- ret = pci_enable_pasid(pdev, 0);
- if (ret)
- return ret;
-
- /* First reset the PRI state of the device */
- ret = pci_reset_pri(pdev);
- if (ret)
- goto out_err_pasid;
-
- /* Enable PRI */
- /* FIXME: Hardcode number of outstanding requests for now */
- ret = pci_enable_pri(pdev, 32);
- if (ret)
- goto out_err_pasid;
-
- ret = pci_enable_ats(pdev, PAGE_SHIFT);
- if (ret)
- goto out_err_pri;
-
- return 0;
-
-out_err_pri:
- pci_disable_pri(pdev);
-
-out_err_pasid:
- pci_disable_pasid(pdev);
-
- return ret;
-}
-
/*
* If a device is not yet associated with a domain, this function makes the
* device visible in the domain
@@ -1827,9 +1892,8 @@ static int attach_device(struct device *dev,
struct protection_domain *domain)
{
struct iommu_dev_data *dev_data;
- struct pci_dev *pdev;
unsigned long flags;
- int ret;
+ int ret = 0;
spin_lock_irqsave(&domain->lock, flags);
@@ -1837,45 +1901,13 @@ static int attach_device(struct device *dev,
spin_lock(&dev_data->lock);
- ret = -EBUSY;
- if (dev_data->domain != NULL)
+ if (dev_data->domain != NULL) {
+ ret = -EBUSY;
goto out;
-
- if (!dev_is_pci(dev))
- goto skip_ats_check;
-
- pdev = to_pci_dev(dev);
- if (domain->flags & PD_IOMMUV2_MASK) {
- struct iommu_domain *def_domain = iommu_get_dma_domain(dev);
-
- ret = -EINVAL;
-
- /*
- * In case of using AMD_IOMMU_V1 page table mode and the device
- * is enabling for PPR/ATS support (using v2 table),
- * we need to make sure that the domain type is identity map.
- */
- if ((amd_iommu_pgtable == AMD_IOMMU_V1) &&
- def_domain->type != IOMMU_DOMAIN_IDENTITY) {
- goto out;
- }
-
- if (pdev_pasid_supported(dev_data)) {
- if (pdev_pri_ats_enable(pdev) != 0)
- goto out;
-
- dev_data->ats_enabled = 1;
- dev_data->ats_qdep = pci_ats_queue_depth(pdev);
- dev_data->pri_tlp = pci_prg_resp_pasid_required(pdev);
- }
- } else if (amd_iommu_iotlb_sup &&
- pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
- dev_data->ats_enabled = 1;
- dev_data->ats_qdep = pci_ats_queue_depth(pdev);
}
-skip_ats_check:
- ret = 0;
+ if (dev_is_pci(dev))
+ pdev_enable_caps(to_pci_dev(dev));
do_attach(dev_data, domain);
@@ -1923,15 +1955,8 @@ static void detach_device(struct device *dev)
do_detach(dev_data);
- if (!dev_is_pci(dev))
- goto out;
-
- if (domain->flags & PD_IOMMUV2_MASK && pdev_pasid_supported(dev_data))
- pdev_iommuv2_disable(to_pci_dev(dev));
- else if (dev_data->ats_enabled)
- pci_disable_ats(to_pci_dev(dev));
-
- dev_data->ats_enabled = 0;
+ if (dev_is_pci(dev))
+ pdev_disable_caps(to_pci_dev(dev));
out:
spin_unlock(&dev_data->lock);
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* [PATCH v6 14/14] iommu/amd: Initialize iommu_device->max_pasids
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (12 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 13/14] iommu/amd: Enable device ATS/PASID/PRI capabilities independently Vasant Hegde
@ 2023-09-21 9:21 ` Vasant Hegde
2023-09-21 9:49 ` [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
14 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:21 UTC (permalink / raw)
To: iommu, joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg, Vasant Hegde,
Jason Gunthorpe
Commit 1adf3cc20d69 ("iommu: Add max_pasids field in struct iommu_device")
introduced a variable struct iommu_device.max_pasids to track max
PASIDS supported by each IOMMU.
Let us initialize this field for AMD IOMMU. IOMMU core will use this value
to set max PASIDs per device (see __iommu_probe_device()).
Also remove unused global 'amd_iommu_max_pasid' variable.
Signed-off-by: Vasant Hegde <vasant.hegde@amd.com>
Reviewed-by: Jason Gunthorpe <jgg@nvidia.com>
Reviewed-by: Jerry Snitselaar <jsnitsel@redhat.com>
---
drivers/iommu/amd/amd_iommu_types.h | 3 ---
drivers/iommu/amd/init.c | 9 ++-------
2 files changed, 2 insertions(+), 10 deletions(-)
diff --git a/drivers/iommu/amd/amd_iommu_types.h b/drivers/iommu/amd/amd_iommu_types.h
index c6d47cb7a0ee..5be563d55ad6 100644
--- a/drivers/iommu/amd/amd_iommu_types.h
+++ b/drivers/iommu/amd/amd_iommu_types.h
@@ -886,9 +886,6 @@ extern unsigned amd_iommu_aperture_order;
/* allocation bitmap for domain ids */
extern unsigned long *amd_iommu_pd_alloc_bitmap;
-/* Smallest max PASID supported by any IOMMU in the system */
-extern u32 amd_iommu_max_pasid;
-
extern bool amd_iommu_force_isolation;
/* Max levels of glxval supported */
diff --git a/drivers/iommu/amd/init.c b/drivers/iommu/amd/init.c
index 06b319006ce2..463e68a88b17 100644
--- a/drivers/iommu/amd/init.c
+++ b/drivers/iommu/amd/init.c
@@ -185,8 +185,6 @@ static int amd_iommus_present;
bool amd_iommu_np_cache __read_mostly;
bool amd_iommu_iotlb_sup __read_mostly = true;
-u32 amd_iommu_max_pasid __read_mostly = ~0;
-
static bool amd_iommu_pc_present __read_mostly;
bool amdr_ivrs_remap_support __read_mostly;
@@ -2080,16 +2078,13 @@ static int __init iommu_init_pci(struct amd_iommu *iommu)
if (check_feature(FEATURE_GT)) {
int glxval;
- u32 max_pasid;
u64 pasmax;
pasmax = amd_iommu_efr & FEATURE_PASID_MASK;
pasmax >>= FEATURE_PASID_SHIFT;
- max_pasid = (1 << (pasmax + 1)) - 1;
-
- amd_iommu_max_pasid = min(amd_iommu_max_pasid, max_pasid);
+ iommu->iommu.max_pasids = (1 << (pasmax + 1)) - 1;
- BUG_ON(amd_iommu_max_pasid & ~PASID_MASK);
+ BUG_ON(iommu->iommu.max_pasids & ~PASID_MASK);
glxval = amd_iommu_efr & FEATURE_GLXVAL_MASK;
glxval >>= FEATURE_GLXVAL_SHIFT;
--
2.31.1
^ permalink raw reply related [flat|nested] 19+ messages in thread* Re: [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring
2023-09-21 9:21 [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
` (13 preceding siblings ...)
2023-09-21 9:21 ` [PATCH v6 14/14] iommu/amd: Initialize iommu_device->max_pasids Vasant Hegde
@ 2023-09-21 9:49 ` Vasant Hegde
2023-09-21 17:21 ` Jason Gunthorpe
14 siblings, 1 reply; 19+ messages in thread
From: Vasant Hegde @ 2023-09-21 9:49 UTC (permalink / raw)
To: joro
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel, jgg,
iommu@lists.linux.dev
Hi Joerg,
On 9/21/2023 2:51 PM, Vasant Hegde wrote:
> This is part 1 of the 4-part series to introduce Share Virtual Address
> (SVA) support, which focuses on cleaning up and refactoring the existing
> code in preparation for subsequent series.
>
> It contains the following enhancements:
>
> * Patch 1 - 7:
> Clean up, refactoring and miscellaneous improvements.
>
> * Patch 8 - 9:
> Use global functions to check iommu features
>
> * Patch 10 - 14:
> Modify logic to independently enable PCI capabilities (ATS/PASID/PRI)
> for devices. This allows more flexibility in preparation for SVA and
> IOPF supports.
This is an independent part of bigger SVA series. This particular series is
tested independently and it works fine. Can you consider picking this series
while we work on sorting out Part3/4?
-Vasant
>
> This patch series is based on top of linux v6.6-rc1.
> Base commit : 0bb80ecc33a (Linux 6.6-rc1)
>
> This is also available at github :
> https://github.com/AMDESE/linux/tree/iommu_sva_part1_v6_v6.6_rc1
>
> Thanks Jason, Jerry, Robin for reviewing previous versions and providing valuable
> feedbacks.
>
>
> Changes from v5 -> v6:
> - Rebased on top v6.6-rc1
> - Added Review-by tags
>
> v5: https://lore.kernel.org/linux-iommu/20230821104227.706997-1-vasant.hegde@amd.com/T/#t
>
> Changes from v4 -> v5:
> - Changed dev_data.ppr from bool to bit field
> - Reverted sysfs_emit that was changing existing behaviour
>
> v4 : https://lore.kernel.org/linux-iommu/20230815102202.565012-1-vasant.hegde@amd.com/T/#t
>
> Changes from v3 -> v4:
> - Dropped patches that were touching iommu_v2.c as we will be deprecating
> iommu_v2 module.
> - Dropped Review-by tags for the patches which got modified (mostly the
> patches that were touching iommu_v2.c code).
> - Introduced new patch to use global EFR/EFR2 to check the iommu features
> - Pass enum to set_dte_entry() instead of bool
> - Used DIV_ROUND_UP instead of loop to calculate gcr3 levels
>
> v3 : https://lore.kernel.org/linux-iommu/20230804064216.835544-1-vasant.hegde@amd.com/T/#t
>
> Changes from v2 -> v3:
> - Removed fallthrough from switch-case
> - Added lockdep_assert_held() instead of comment on top of the function
> - Moved macro defination (PPR_HANDLER_IOPF) to the patch where its
> actually used
> - Use helper function to allocate memory instead of get_zeroed_page()
> - Converted boolean to bit fields
>
> v2 : https://lore.kernel.org/linux-iommu/20230728053609.165183-1-vasant.hegde@amd.com/T/#t
>
> Changes from v1 -> v2:
> - Dropped GCR3 related changes from Part1. We are reworking
> GCR3 management based on Jason's comment. We will post them
> as separate part.
> - Addressed review comment from Jason
> - Added iommu_dev_data.ppr to track PPR status
>
> v1 : https://lore.kernel.org/linux-iommu/20230712141516.154144-1-vasant.hegde@amd.com/
>
>
> Thank you,
> Vasant / Suravee
>
>
> Suravee Suthikulpanit (8):
> iommu/amd: Remove unused amd_io_pgtable.pt_root variable
> iommu/amd: Consolidate timeout pre-define to amd_iommu_type.h
> iommu/amd: Consolidate logic to allocate protection domain
> iommu/amd: Introduce helper functions for managing GCR3 table
> iommu/amd: Miscellaneous clean up when free domain
> iommu/amd: Consolidate feature detection and reporting logic
> iommu/amd: Modify logic for checking GT and PPR features
> iommu/amd: Introduce iommu_dev_data.ppr
>
> Vasant Hegde (6):
> iommu/amd: Refactor protection domain allocation code
> iommu/amd: Do not set amd_iommu_pgtable in pass-through mode
> iommu/amd: Rename ats related variables
> iommu/amd: Introduce iommu_dev_data.flags to track device capabilities
> iommu/amd: Enable device ATS/PASID/PRI capabilities independently
> iommu/amd: Initialize iommu_device->max_pasids
>
> drivers/iommu/amd/amd_iommu.h | 28 +-
> drivers/iommu/amd/amd_iommu_types.h | 31 +-
> drivers/iommu/amd/init.c | 116 +++-----
> drivers/iommu/amd/io_pgtable_v2.c | 8 +-
> drivers/iommu/amd/iommu.c | 442 +++++++++++++++-------------
> 5 files changed, 322 insertions(+), 303 deletions(-)
>
^ permalink raw reply [flat|nested] 19+ messages in thread* Re: [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring
2023-09-21 9:49 ` [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring Vasant Hegde
@ 2023-09-21 17:21 ` Jason Gunthorpe
2023-09-25 10:40 ` Joerg Roedel
0 siblings, 1 reply; 19+ messages in thread
From: Jason Gunthorpe @ 2023-09-21 17:21 UTC (permalink / raw)
To: Vasant Hegde
Cc: joro, suravee.suthikulpanit, wei.huang2, jsnitsel,
iommu@lists.linux.dev
On Thu, Sep 21, 2023 at 03:19:37PM +0530, Vasant Hegde wrote:
> On 9/21/2023 2:51 PM, Vasant Hegde wrote:
> > This is part 1 of the 4-part series to introduce Share Virtual Address
> > (SVA) support, which focuses on cleaning up and refactoring the existing
> > code in preparation for subsequent series.
> >
> > It contains the following enhancements:
> >
> > * Patch 1 - 7:
> > Clean up, refactoring and miscellaneous improvements.
> >
> > * Patch 8 - 9:
> > Use global functions to check iommu features
> >
> > * Patch 10 - 14:
> > Modify logic to independently enable PCI capabilities (ATS/PASID/PRI)
> > for devices. This allows more flexibility in preparation for SVA and
> > IOPF supports.
>
>
> This is an independent part of bigger SVA series. This particular series is
> tested independently and it works fine. Can you consider picking this series
> while we work on sorting out Part3/4?
+1
Also the v2 API removal:
https://lore.kernel.org/linux-iommu/20230921093140.6162-1-vasant.hegde@amd.com/
Jason
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring
2023-09-21 17:21 ` Jason Gunthorpe
@ 2023-09-25 10:40 ` Joerg Roedel
2023-09-25 11:02 ` Vasant Hegde
0 siblings, 1 reply; 19+ messages in thread
From: Joerg Roedel @ 2023-09-25 10:40 UTC (permalink / raw)
To: Jason Gunthorpe
Cc: Vasant Hegde, suravee.suthikulpanit, wei.huang2, jsnitsel,
iommu@lists.linux.dev
On Thu, Sep 21, 2023 at 02:21:47PM -0300, Jason Gunthorpe wrote:
> On Thu, Sep 21, 2023 at 03:19:37PM +0530, Vasant Hegde wrote:
> > On 9/21/2023 2:51 PM, Vasant Hegde wrote:
> > This is an independent part of bigger SVA series. This particular series is
> > tested independently and it works fine. Can you consider picking this series
> > while we work on sorting out Part3/4?
>
> +1
Applied this, thanks.
> Also the v2 API removal:
>
> https://lore.kernel.org/linux-iommu/20230921093140.6162-1-vasant.hegde@amd.com/
For that I need more validation that it will not cause regressions on
older hardware.
Regards,
Joerg
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH v6 00/14] iommu/amd: SVA Support (Part 1) - cleanup/refactoring
2023-09-25 10:40 ` Joerg Roedel
@ 2023-09-25 11:02 ` Vasant Hegde
0 siblings, 0 replies; 19+ messages in thread
From: Vasant Hegde @ 2023-09-25 11:02 UTC (permalink / raw)
To: Joerg Roedel, Jason Gunthorpe, Alex Deucher
Cc: suravee.suthikulpanit, wei.huang2, jsnitsel,
iommu@lists.linux.dev
Joerg,
+ Alex
On 9/25/2023 4:10 PM, Joerg Roedel wrote:
> On Thu, Sep 21, 2023 at 02:21:47PM -0300, Jason Gunthorpe wrote:
>> On Thu, Sep 21, 2023 at 03:19:37PM +0530, Vasant Hegde wrote:
>>> On 9/21/2023 2:51 PM, Vasant Hegde wrote:
>>> This is an independent part of bigger SVA series. This particular series is
>>> tested independently and it works fine. Can you consider picking this series
>>> while we work on sorting out Part3/4?
>>
>> +1
>
> Applied this, thanks.
Thanks!
>
>> Also the v2 API removal:
>>
>> https://lore.kernel.org/linux-iommu/20230921093140.6162-1-vasant.hegde@amd.com/
>
> For that I need more validation that it will not cause regressions on
> older hardware.
AMD GPU driver which was the only in kernel user of iommu_v2 module has removed
iommu_v2 dependency in v6.6. (commit 461f35f014466 - Merge tag
'drm-next-2023-08-30' of git://anongit.freedesktop.org/drm/drm).
Summarizing Alex concern:
AMD IOMMU driver forces passthrough domain for PASID/PRI capable devices. Alex
mentioned if we change this then it may break older GPU hardware.
Part2 of SVA series only removes iommu_v2 related code. It does not touch the
default domain allocation code. Hence it shouldn't cause any regression for GPU
hardware. IMO part2 is good to go.
We will do the default domain allocation cleanup later (after SVA series).
During that time we will account Alex's concern and make sure not to break
existing hardware.
-Vasant
^ permalink raw reply [flat|nested] 19+ messages in thread