* [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading
@ 2023-10-07 8:54 Lang Yu
2023-10-07 8:54 ` [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO Lang Yu
` (2 more replies)
0 siblings, 3 replies; 12+ messages in thread
From: Lang Yu @ 2023-10-07 8:54 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Yifan Zhang, Lang Yu, Veerabadhran Gopalakrishnan
These changes are missed in rebase.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 35 +++---
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h | 18 +++-
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 107 ++++++++-----------
3 files changed, 72 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index aeff9926412f..9d89c4186989 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -75,17 +75,6 @@ struct umsch_mm_test {
uint32_t num_queues;
};
-int umsch_mm_psp_update_sram(struct amdgpu_device *adev, u32 ucode_size)
-{
- struct amdgpu_firmware_info ucode = {
- .ucode_id = AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
- .mc_addr = adev->umsch_mm.cmd_buf_gpu_addr,
- .ucode_size = ucode_size,
- };
-
- return psp_execute_ip_fw_load(&adev->psp, &ucode);
-}
-
static int map_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,
struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,
uint64_t addr, uint32_t size)
@@ -694,15 +683,17 @@ int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch)
return 0;
}
-void* amdgpu_umsch_mm_add_cmd(struct amdgpu_umsch_mm *umsch,
- void* cmd_ptr, uint32_t reg_offset, uint32_t reg_data)
+int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch)
{
- uint32_t* ptr = (uint32_t *)cmd_ptr;
-
- *ptr++ = (reg_offset << 2);
- *ptr++ = reg_data;
+ struct amdgpu_device *adev = umsch->ring.adev;
+ struct amdgpu_firmware_info ucode = {
+ .ucode_id = AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
+ .mc_addr = adev->umsch_mm.cmd_buf_gpu_addr,
+ .ucode_size = ((uintptr_t)adev->umsch_mm.cmd_buf_curr_ptr -
+ (uintptr_t)adev->umsch_mm.cmd_buf_ptr),
+ };
- return ptr;
+ return psp_execute_ip_fw_load(&adev->psp, &ucode);
}
static void umsch_mm_agdb_index_init(struct amdgpu_device *adev)
@@ -824,11 +815,9 @@ static int umsch_mm_hw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
- r = umsch_mm_load_microcode(&adev->umsch_mm);
- if (r)
- return r;
- }
+ r = umsch_mm_load_microcode(&adev->umsch_mm);
+ if (r)
+ return r;
umsch_mm_ring_start(&adev->umsch_mm);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
index d83fdf2da464..8258a43a6236 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
@@ -150,6 +150,7 @@ struct amdgpu_umsch_mm {
struct amdgpu_bo *cmd_buf_obj;
uint64_t cmd_buf_gpu_addr;
uint32_t *cmd_buf_ptr;
+ uint32_t *cmd_buf_curr_ptr;
uint32_t wb_index;
uint64_t sch_ctx_gpu_addr;
@@ -167,19 +168,28 @@ struct amdgpu_umsch_mm {
struct mutex mutex_hidden;
};
-int umsch_mm_psp_update_sram(struct amdgpu_device *adev, u32 ucode_size);
-
int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws);
int amdgpu_umsch_mm_query_fence(struct amdgpu_umsch_mm *umsch);
int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch);
int amdgpu_umsch_mm_allocate_ucode_buffer(struct amdgpu_umsch_mm *umsch);
int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch);
-void* amdgpu_umsch_mm_add_cmd(struct amdgpu_umsch_mm *umsch,
- void* cmd_ptr, uint32_t reg_offset, uint32_t reg_data);
+
+int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch);
int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch);
+#define WREG32_SOC15_UMSCH(reg, value) \
+ do { \
+ uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { \
+ *adev->umsch_mm.cmd_buf_curr_ptr++ = (reg_offset << 2); \
+ *adev->umsch_mm.cmd_buf_curr_ptr++ = value; \
+ } else { \
+ WREG32(reg_offset, value); \
+ } \
+ } while (0)
+
#define umsch_mm_set_hw_resources(umsch) \
((umsch)->funcs->set_hw_resources ? (umsch)->funcs->set_hw_resources((umsch)) : 0)
#define umsch_mm_add_queue(umsch, input) \
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index 99713949b61f..a60178156c77 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -34,23 +34,10 @@
#include "umsch_mm_4_0_api_def.h"
#include "umsch_mm_v4_0.h"
-#define WREG32_SOC15_UMSCH(ptr, reg, value) \
-({ void *ret = ptr; \
- do { \
- uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) \
- ret = amdgpu_umsch_mm_add_cmd((&adev->umsch_mm), (ptr), (reg_offset), (value)); \
- else \
- WREG32(reg_offset, value); \
- } while (0); \
- ret; \
-})
-
static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
{
struct amdgpu_device *adev = umsch->ring.adev;
- void* ptr = umsch->cmd_buf_ptr;
- uint32_t data;
+ uint64_t data;
int r;
r = amdgpu_umsch_mm_allocate_ucode_buffer(umsch);
@@ -61,97 +48,95 @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
if (r)
goto err_free_ucode_bo;
+ umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
+
data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regUMSCH_MES_RESET_CTRL, data);
+ WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data);
data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 1);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 1);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 0);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);
data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL);
data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0);
data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, EXE_DISABLE, 0);
data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, CACHE_POLICY, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_BASE_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START,
+ lower_32_bits(adev->umsch_mm.irq_start_addr >> 2));
+ WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START_HI,
+ upper_32_bits(adev->umsch_mm.irq_start_addr >> 2));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_INTR_ROUTINE_START,
- lower_32_bits(adev->umsch_mm.irq_start_addr >> 2));
+ WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START,
+ lower_32_bits(adev->umsch_mm.uc_start_addr >> 2));
+ WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START_HI,
+ upper_32_bits(adev->umsch_mm.uc_start_addr >> 2));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_INTR_ROUTINE_START_HI,
- upper_32_bits(adev->umsch_mm.irq_start_addr >> 2));
-
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_PRGRM_CNTR_START,
- lower_32_bits(adev->umsch_mm.uc_start_addr >> 2));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_PRGRM_CNTR_START_HI,
- upper_32_bits(adev->umsch_mm.uc_start_addr >> 2));
-
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_BASE_LO, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_BASE_HI, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_LO, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_HI, 0);
data = adev->umsch_mm.uc_start_addr + adev->umsch_mm.ucode_size - 1;
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_MASK_HI, upper_32_bits(data));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_HI, upper_32_bits(data));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_BASE_LO,
- lower_32_bits(adev->umsch_mm.ucode_fw_gpu_addr));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_BASE_HI,
- upper_32_bits(adev->umsch_mm.ucode_fw_gpu_addr));
+ data = adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ?
+ 0 : adev->umsch_mm.ucode_fw_gpu_addr;
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_LO, lower_32_bits(data));
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_HI, upper_32_bits(data));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_MIBOUND_LO, 0x1FFFFF);
+ WREG32_SOC15_UMSCH(regVCN_MES_MIBOUND_LO, 0x1FFFFF);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_BASE0_LO,
- lower_32_bits(adev->umsch_mm.data_start_addr));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_BASE0_HI,
- upper_32_bits(adev->umsch_mm.data_start_addr));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_LO,
+ lower_32_bits(adev->umsch_mm.data_start_addr));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_HI,
+ upper_32_bits(adev->umsch_mm.data_start_addr));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_MASK0_LO,
- lower_32_bits(adev->umsch_mm.data_size - 1));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_MASK0_HI,
- upper_32_bits(adev->umsch_mm.data_size - 1));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_LO,
+ lower_32_bits(adev->umsch_mm.data_size - 1));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_HI,
+ upper_32_bits(adev->umsch_mm.data_size - 1));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_DC_BASE_LO,
- lower_32_bits(adev->umsch_mm.data_fw_gpu_addr));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_DC_BASE_HI,
- upper_32_bits(adev->umsch_mm.data_fw_gpu_addr));
+ data = adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ?
+ 0 : adev->umsch_mm.data_fw_gpu_addr;
+ WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_LO, lower_32_bits(data));
+ WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_HI, upper_32_bits(data));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_MDBOUND_LO, 0x3FFFF);
+ WREG32_SOC15_UMSCH(regVCN_MES_MDBOUND_LO, 0x3FFFF);
data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE);
data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, IC_FORCE_GPUVM, 1);
data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, DC_FORCE_GPUVM, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regUVD_UMSCH_FORCE, data);
+ WREG32_SOC15_UMSCH(regUVD_UMSCH_FORCE, data);
data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);
data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_OP_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);
data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);
data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_OP_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP0_LO, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP0_HI, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP1_LO, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP1_HI, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_GP1_LO, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_GP1_HI, 0);
data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 0);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 0);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 0);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
- umsch_mm_psp_update_sram(adev,
- (u32)((uintptr_t)ptr - (uintptr_t)umsch->cmd_buf_ptr));
- }
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
+ amdgpu_umsch_mm_psp_execute_cmd_buf(umsch);
r = SOC15_WAIT_ON_RREG(VCN, 0, regVCN_MES_MSTATUS_LO, 0xAAAAAAAA, 0xFFFFFFFF);
if (r) {
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
2023-10-07 8:54 [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading Lang Yu
@ 2023-10-07 8:54 ` Lang Yu
2023-10-09 15:05 ` Gopalakrishnan, Veerabadhran (Veera)
` (2 more replies)
2023-10-07 8:54 ` [PATCH 3/3] drm/amdgpu/umsch: enable doorbell for umsch Lang Yu
2023-10-09 15:04 ` [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading Gopalakrishnan, Veerabadhran (Veera)
2 siblings, 3 replies; 12+ messages in thread
From: Lang Yu @ 2023-10-07 8:54 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Yifan Zhang, Lang Yu, Veerabadhran Gopalakrishnan
VCN 4.0.5 uses DLDO.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index a60178156c77..7e79954c833b 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -34,6 +34,16 @@
#include "umsch_mm_4_0_api_def.h"
#include "umsch_mm_v4_0.h"
+#define regUVD_IPX_DLDO_CONFIG 0x0064
+#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
+#define regUVD_IPX_DLDO_STATUS 0x0065
+#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
+
+#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT 0x00000002
+#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK 0x0000000cUL
+#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT 0x00000001
+#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK 0x00000002UL
+
static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
{
struct amdgpu_device *adev = umsch->ring.adev;
@@ -50,6 +60,14 @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
+ if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
+ WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
+ 1 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
+ SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
+ 0 << UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
+ UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
+ }
+
data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);
WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data);
@@ -229,6 +247,14 @@ static int umsch_mm_v4_0_ring_stop(struct amdgpu_umsch_mm *umsch)
data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
+ if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
+ WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
+ 2 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
+ SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
+ 1 << UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
+ UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
+ }
+
return 0;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* RE: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
2023-10-07 8:54 ` [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO Lang Yu
@ 2023-10-09 15:05 ` Gopalakrishnan, Veerabadhran (Veera)
2023-10-09 19:36 ` Deucher, Alexander
2023-10-09 19:44 ` Deucher, Alexander
2 siblings, 0 replies; 12+ messages in thread
From: Gopalakrishnan, Veerabadhran (Veera) @ 2023-10-09 15:05 UTC (permalink / raw)
To: Yu, Lang, amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander, Zhang, Yifan
[AMD Official Use Only - General]
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
-Veera
-----Original Message-----
From: Yu, Lang <Lang.Yu@amd.com>
Sent: Saturday, October 7, 2023 2:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Gopalakrishnan, Veerabadhran (Veera) <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
Subject: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
VCN 4.0.5 uses DLDO.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index a60178156c77..7e79954c833b 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -34,6 +34,16 @@
#include "umsch_mm_4_0_api_def.h"
#include "umsch_mm_v4_0.h"
+#define regUVD_IPX_DLDO_CONFIG 0x0064
+#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
+#define regUVD_IPX_DLDO_STATUS 0x0065
+#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
+
+#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT 0x00000002
+#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK 0x0000000cUL
+#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT 0x00000001
+#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK 0x00000002UL
+
static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch) {
struct amdgpu_device *adev = umsch->ring.adev; @@ -50,6 +60,14 @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
+ if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
+ WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
+ 1 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
+ SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
+ 0 << UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
+ UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
+ }
+
data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);
WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data); @@ -229,6 +247,14 @@ static int umsch_mm_v4_0_ring_stop(struct amdgpu_umsch_mm *umsch)
data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
+ if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
+ WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
+ 2 << UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
+ SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
+ 1 << UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
+ UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
+ }
+
return 0;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread* RE: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
2023-10-07 8:54 ` [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO Lang Yu
2023-10-09 15:05 ` Gopalakrishnan, Veerabadhran (Veera)
@ 2023-10-09 19:36 ` Deucher, Alexander
2023-10-10 0:45 ` Lang Yu
2023-10-09 19:44 ` Deucher, Alexander
2 siblings, 1 reply; 12+ messages in thread
From: Deucher, Alexander @ 2023-10-09 19:36 UTC (permalink / raw)
To: Yu, Lang, amd-gfx@lists.freedesktop.org
Cc: Zhang, Yifan, Gopalakrishnan, Veerabadhran (Veera)
[Public]
> -----Original Message-----
> From: Yu, Lang <Lang.Yu@amd.com>
> Sent: Saturday, October 7, 2023 4:54 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
> <Yifan1.Zhang@amd.com>; Gopalakrishnan, Veerabadhran (Veera)
> <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
> Subject: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
>
> VCN 4.0.5 uses DLDO.
>
> Signed-off-by: Lang Yu <Lang.Yu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 26
> ++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> index a60178156c77..7e79954c833b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> @@ -34,6 +34,16 @@
> #include "umsch_mm_4_0_api_def.h"
> #include "umsch_mm_v4_0.h"
>
> +#define regUVD_IPX_DLDO_CONFIG 0x0064
> +#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
> +#define regUVD_IPX_DLDO_STATUS 0x0065
> +#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
> +
> +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT
> 0x00000002
> +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK
> 0x0000000cUL
> +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT
> 0x00000001
> +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK
> 0x00000002UL
> +
> static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> *umsch) {
> struct amdgpu_device *adev = umsch->ring.adev; @@ -50,6 +60,14
> @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> *umsch)
>
> umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
>
> + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
This switched to a function call. Amdgpu_ip_version().
> + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> + 1 <<
> UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> + 0 <<
> UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> +
> UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> + }
> +
> data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
> data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL,
> MES_CORE_SOFT_RESET, 0);
> WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data); @@ -
> 229,6 +247,14 @@ static int umsch_mm_v4_0_ring_stop(struct
> amdgpu_umsch_mm *umsch)
> data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
> WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
>
> + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
Same here.
Alex
> + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> + 2 <<
> UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> + 1 <<
> UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> +
> UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> + }
> +
> return 0;
> }
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
2023-10-09 19:36 ` Deucher, Alexander
@ 2023-10-10 0:45 ` Lang Yu
0 siblings, 0 replies; 12+ messages in thread
From: Lang Yu @ 2023-10-10 0:45 UTC (permalink / raw)
To: Deucher, Alexander
Cc: Zhang, Yifan, amd-gfx@lists.freedesktop.org,
Gopalakrishnan, Veerabadhran (Veera)
On 10/10/ , Deucher, Alexander wrote:
> [Public]
>
> > -----Original Message-----
> > From: Yu, Lang <Lang.Yu@amd.com>
> > Sent: Saturday, October 7, 2023 4:54 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
> > <Yifan1.Zhang@amd.com>; Gopalakrishnan, Veerabadhran (Veera)
> > <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
> > Subject: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
> >
> > VCN 4.0.5 uses DLDO.
> >
> > Signed-off-by: Lang Yu <Lang.Yu@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 26
> > ++++++++++++++++++++++
> > 1 file changed, 26 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > index a60178156c77..7e79954c833b 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > @@ -34,6 +34,16 @@
> > #include "umsch_mm_4_0_api_def.h"
> > #include "umsch_mm_v4_0.h"
> >
> > +#define regUVD_IPX_DLDO_CONFIG 0x0064
> > +#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
> > +#define regUVD_IPX_DLDO_STATUS 0x0065
> > +#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
> > +
> > +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT
> > 0x00000002
> > +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK
> > 0x0000000cUL
> > +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT
> > 0x00000001
> > +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK
> > 0x00000002UL
> > +
> > static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> > *umsch) {
> > struct amdgpu_device *adev = umsch->ring.adev; @@ -50,6 +60,14
> > @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> > *umsch)
> >
> > umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
> >
> > + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
>
> This switched to a function call. Amdgpu_ip_version().
>
> > + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> > + 1 <<
> > UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> > + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> > + 0 <<
> > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> > +
> > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> > + }
> > +
> > data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
> > data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL,
> > MES_CORE_SOFT_RESET, 0);
> > WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data); @@ -
> > 229,6 +247,14 @@ static int umsch_mm_v4_0_ring_stop(struct
> > amdgpu_umsch_mm *umsch)
> > data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
> > WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
> >
> > + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
>
> Same here.
Thanks for pointing out them. Will fix this.
Regards,
Lang
> Alex
>
> > + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> > + 2 <<
> > UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> > + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> > + 1 <<
> > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> > +
> > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> > + }
> > +
> > return 0;
> > }
> >
> > --
> > 2.25.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* RE: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
2023-10-07 8:54 ` [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO Lang Yu
2023-10-09 15:05 ` Gopalakrishnan, Veerabadhran (Veera)
2023-10-09 19:36 ` Deucher, Alexander
@ 2023-10-09 19:44 ` Deucher, Alexander
2023-10-10 0:44 ` Lang Yu
2 siblings, 1 reply; 12+ messages in thread
From: Deucher, Alexander @ 2023-10-09 19:44 UTC (permalink / raw)
To: Yu, Lang, amd-gfx@lists.freedesktop.org
Cc: Zhang, Yifan, Gopalakrishnan, Veerabadhran (Veera)
[Public]
> -----Original Message-----
> From: Yu, Lang <Lang.Yu@amd.com>
> Sent: Saturday, October 7, 2023 4:54 AM
> To: amd-gfx@lists.freedesktop.org
> Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
> <Yifan1.Zhang@amd.com>; Gopalakrishnan, Veerabadhran (Veera)
> <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
> Subject: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
>
> VCN 4.0.5 uses DLDO.
>
> Signed-off-by: Lang Yu <Lang.Yu@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 26
> ++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> index a60178156c77..7e79954c833b 100644
> --- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> @@ -34,6 +34,16 @@
> #include "umsch_mm_4_0_api_def.h"
> #include "umsch_mm_v4_0.h"
>
> +#define regUVD_IPX_DLDO_CONFIG 0x0064
> +#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
> +#define regUVD_IPX_DLDO_STATUS 0x0065
> +#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
> +
> +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT
> 0x00000002
> +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK
> 0x0000000cUL
> +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT
> 0x00000001
> +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK
> 0x00000002UL
> +
> static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> *umsch) {
> struct amdgpu_device *adev = umsch->ring.adev; @@ -50,6 +60,14
> @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> *umsch)
>
> umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
>
> + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
> + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> + 1 <<
> UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> + 0 <<
> UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> +
> UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> + }
> +
Is this the right place for this? umsch_mm_hw_init() only calls this for FW_LOAD_DIRECT. Maybe that check needs to be dropped?
Alex
> data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
> data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL,
> MES_CORE_SOFT_RESET, 0);
> WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data); @@ -
> 229,6 +247,14 @@ static int umsch_mm_v4_0_ring_stop(struct
> amdgpu_umsch_mm *umsch)
> data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
> WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
>
> + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
> + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> + 2 <<
> UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> + 1 <<
> UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> +
> UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> + }
> +
> return 0;
> }
>
> --
> 2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
2023-10-09 19:44 ` Deucher, Alexander
@ 2023-10-10 0:44 ` Lang Yu
2023-10-10 14:01 ` Alex Deucher
0 siblings, 1 reply; 12+ messages in thread
From: Lang Yu @ 2023-10-10 0:44 UTC (permalink / raw)
To: Deucher, Alexander
Cc: Zhang, Yifan, amd-gfx@lists.freedesktop.org,
Gopalakrishnan, Veerabadhran (Veera)
On 10/10/ , Deucher, Alexander wrote:
> [Public]
>
> > -----Original Message-----
> > From: Yu, Lang <Lang.Yu@amd.com>
> > Sent: Saturday, October 7, 2023 4:54 AM
> > To: amd-gfx@lists.freedesktop.org
> > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
> > <Yifan1.Zhang@amd.com>; Gopalakrishnan, Veerabadhran (Veera)
> > <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
> > Subject: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
> >
> > VCN 4.0.5 uses DLDO.
> >
> > Signed-off-by: Lang Yu <Lang.Yu@amd.com>
> > ---
> > drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 26
> > ++++++++++++++++++++++
> > 1 file changed, 26 insertions(+)
> >
> > diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > index a60178156c77..7e79954c833b 100644
> > --- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > +++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > @@ -34,6 +34,16 @@
> > #include "umsch_mm_4_0_api_def.h"
> > #include "umsch_mm_v4_0.h"
> >
> > +#define regUVD_IPX_DLDO_CONFIG 0x0064
> > +#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
> > +#define regUVD_IPX_DLDO_STATUS 0x0065
> > +#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
> > +
> > +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT
> > 0x00000002
> > +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK
> > 0x0000000cUL
> > +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT
> > 0x00000001
> > +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK
> > 0x00000002UL
> > +
> > static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> > *umsch) {
> > struct amdgpu_device *adev = umsch->ring.adev; @@ -50,6 +60,14
> > @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> > *umsch)
> >
> > umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
> >
> > + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
> > + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> > + 1 <<
> > UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> > + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> > + 0 <<
> > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> > +
> > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> > + }
> > +
>
> Is this the right place for this? umsch_mm_hw_init() only calls this for FW_LOAD_DIRECT. Maybe that check needs to be dropped?
That check is dropped in [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading.
PMFW removed DLDO programing in PPSMC_MSG_PowerUpUmsch function.
So driver needs to program it explicitly.
Regards,
Lang
> Alex
>
> > data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
> > data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL,
> > MES_CORE_SOFT_RESET, 0);
> > WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data); @@ -
> > 229,6 +247,14 @@ static int umsch_mm_v4_0_ring_stop(struct
> > amdgpu_umsch_mm *umsch)
> > data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
> > WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
> >
> > + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
> > + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> > + 2 <<
> > UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> > + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> > + 1 <<
> > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> > +
> > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> > + }
> > +
> > return 0;
> > }
> >
> > --
> > 2.25.1
>
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
2023-10-10 0:44 ` Lang Yu
@ 2023-10-10 14:01 ` Alex Deucher
2023-10-11 2:16 ` Lang Yu
0 siblings, 1 reply; 12+ messages in thread
From: Alex Deucher @ 2023-10-10 14:01 UTC (permalink / raw)
To: Lang Yu
Cc: Deucher, Alexander, Zhang, Yifan, amd-gfx@lists.freedesktop.org,
Gopalakrishnan, Veerabadhran (Veera)
On Tue, Oct 10, 2023 at 9:42 AM Lang Yu <Lang.Yu@amd.com> wrote:
>
> On 10/10/ , Deucher, Alexander wrote:
> > [Public]
> >
> > > -----Original Message-----
> > > From: Yu, Lang <Lang.Yu@amd.com>
> > > Sent: Saturday, October 7, 2023 4:54 AM
> > > To: amd-gfx@lists.freedesktop.org
> > > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
> > > <Yifan1.Zhang@amd.com>; Gopalakrishnan, Veerabadhran (Veera)
> > > <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
> > > Subject: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
> > >
> > > VCN 4.0.5 uses DLDO.
> > >
> > > Signed-off-by: Lang Yu <Lang.Yu@amd.com>
> > > ---
> > > drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 26
> > > ++++++++++++++++++++++
> > > 1 file changed, 26 insertions(+)
> > >
> > > diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > > b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > > index a60178156c77..7e79954c833b 100644
> > > --- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > > +++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > > @@ -34,6 +34,16 @@
> > > #include "umsch_mm_4_0_api_def.h"
> > > #include "umsch_mm_v4_0.h"
> > >
> > > +#define regUVD_IPX_DLDO_CONFIG 0x0064
> > > +#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
> > > +#define regUVD_IPX_DLDO_STATUS 0x0065
> > > +#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
> > > +
> > > +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT
> > > 0x00000002
> > > +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK
> > > 0x0000000cUL
> > > +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT
> > > 0x00000001
> > > +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK
> > > 0x00000002UL
> > > +
> > > static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> > > *umsch) {
> > > struct amdgpu_device *adev = umsch->ring.adev; @@ -50,6 +60,14
> > > @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> > > *umsch)
> > >
> > > umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
> > >
> > > + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
> > > + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> > > + 1 <<
> > > UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> > > + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> > > + 0 <<
> > > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> > > +
> > > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> > > + }
> > > +
> >
> > Is this the right place for this? umsch_mm_hw_init() only calls this for FW_LOAD_DIRECT. Maybe that check needs to be dropped?
>
> That check is dropped in [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading.
Ah, I checked that, but I missed it. Thanks.
>
> PMFW removed DLDO programing in PPSMC_MSG_PowerUpUmsch function.
> So driver needs to program it explicitly.
Ok. So is the SMC message still required in addition?
Alex
>
> Regards,
> Lang
>
> > Alex
> >
> > > data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
> > > data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL,
> > > MES_CORE_SOFT_RESET, 0);
> > > WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data); @@ -
> > > 229,6 +247,14 @@ static int umsch_mm_v4_0_ring_stop(struct
> > > amdgpu_umsch_mm *umsch)
> > > data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
> > > WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
> > >
> > > + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
> > > + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> > > + 2 <<
> > > UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> > > + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> > > + 1 <<
> > > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> > > +
> > > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> > > + }
> > > +
> > > return 0;
> > > }
> > >
> > > --
> > > 2.25.1
> >
^ permalink raw reply [flat|nested] 12+ messages in thread* Re: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
2023-10-10 14:01 ` Alex Deucher
@ 2023-10-11 2:16 ` Lang Yu
0 siblings, 0 replies; 12+ messages in thread
From: Lang Yu @ 2023-10-11 2:16 UTC (permalink / raw)
To: Alex Deucher
Cc: Deucher, Alexander, Zhang, Yifan, amd-gfx@lists.freedesktop.org,
Gopalakrishnan, Veerabadhran (Veera)
On 10/10/ , Alex Deucher wrote:
> On Tue, Oct 10, 2023 at 9:42 AM Lang Yu <Lang.Yu@amd.com> wrote:
> >
> > On 10/10/ , Deucher, Alexander wrote:
> > > [Public]
> > >
> > > > -----Original Message-----
> > > > From: Yu, Lang <Lang.Yu@amd.com>
> > > > Sent: Saturday, October 7, 2023 4:54 AM
> > > > To: amd-gfx@lists.freedesktop.org
> > > > Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan
> > > > <Yifan1.Zhang@amd.com>; Gopalakrishnan, Veerabadhran (Veera)
> > > > <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
> > > > Subject: [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO
> > > >
> > > > VCN 4.0.5 uses DLDO.
> > > >
> > > > Signed-off-by: Lang Yu <Lang.Yu@amd.com>
> > > > ---
> > > > drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 26
> > > > ++++++++++++++++++++++
> > > > 1 file changed, 26 insertions(+)
> > > >
> > > > diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > > > b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > > > index a60178156c77..7e79954c833b 100644
> > > > --- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > > > +++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
> > > > @@ -34,6 +34,16 @@
> > > > #include "umsch_mm_4_0_api_def.h"
> > > > #include "umsch_mm_v4_0.h"
> > > >
> > > > +#define regUVD_IPX_DLDO_CONFIG 0x0064
> > > > +#define regUVD_IPX_DLDO_CONFIG_BASE_IDX 1
> > > > +#define regUVD_IPX_DLDO_STATUS 0x0065
> > > > +#define regUVD_IPX_DLDO_STATUS_BASE_IDX 1
> > > > +
> > > > +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT
> > > > 0x00000002
> > > > +#define UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG_MASK
> > > > 0x0000000cUL
> > > > +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT
> > > > 0x00000001
> > > > +#define UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK
> > > > 0x00000002UL
> > > > +
> > > > static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> > > > *umsch) {
> > > > struct amdgpu_device *adev = umsch->ring.adev; @@ -50,6 +60,14
> > > > @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm
> > > > *umsch)
> > > >
> > > > umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
> > > >
> > > > + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
> > > > + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> > > > + 1 <<
> > > > UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> > > > + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> > > > + 0 <<
> > > > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> > > > +
> > > > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> > > > + }
> > > > +
> > >
> > > Is this the right place for this? umsch_mm_hw_init() only calls this for FW_LOAD_DIRECT. Maybe that check needs to be dropped?
> >
> > That check is dropped in [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading.
>
> Ah, I checked that, but I missed it. Thanks.
>
> >
> > PMFW removed DLDO programing in PPSMC_MSG_PowerUpUmsch function.
> > So driver needs to program it explicitly.
>
> Ok. So is the SMC message still required in addition?
Yes. Some masks need to be updated.
Regards,
Lang
> Alex
>
> >
> > Regards,
> > Lang
> >
> > > Alex
> > >
> > > > data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
> > > > data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL,
> > > > MES_CORE_SOFT_RESET, 0);
> > > > WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data); @@ -
> > > > 229,6 +247,14 @@ static int umsch_mm_v4_0_ring_stop(struct
> > > > amdgpu_umsch_mm *umsch)
> > > > data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 0);
> > > > WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
> > > >
> > > > + if (adev->ip_versions[VCN_HWIP][0] == IP_VERSION(4, 0, 5)) {
> > > > + WREG32_SOC15(VCN, 0, regUVD_IPX_DLDO_CONFIG,
> > > > + 2 <<
> > > > UVD_IPX_DLDO_CONFIG__ONO0_PWR_CONFIG__SHIFT);
> > > > + SOC15_WAIT_ON_RREG(VCN, 0, regUVD_IPX_DLDO_STATUS,
> > > > + 1 <<
> > > > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS__SHIFT,
> > > > +
> > > > UVD_IPX_DLDO_STATUS__ONO0_PWR_STATUS_MASK);
> > > > + }
> > > > +
> > > > return 0;
> > > > }
> > > >
> > > > --
> > > > 2.25.1
> > >
^ permalink raw reply [flat|nested] 12+ messages in thread
* [PATCH 3/3] drm/amdgpu/umsch: enable doorbell for umsch
2023-10-07 8:54 [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading Lang Yu
2023-10-07 8:54 ` [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO Lang Yu
@ 2023-10-07 8:54 ` Lang Yu
2023-10-09 15:08 ` Gopalakrishnan, Veerabadhran (Veera)
2023-10-09 15:04 ` [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading Gopalakrishnan, Veerabadhran (Veera)
2 siblings, 1 reply; 12+ messages in thread
From: Lang Yu @ 2023-10-07 8:54 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Yifan Zhang, Lang Yu, Veerabadhran Gopalakrishnan
Program vcn_doorbell_range with vcn_ring0_1.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 9d89c4186989..4bd076e9e367 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -554,7 +554,7 @@ int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch)
struct amdgpu_ring *ring = &umsch->ring;
ring->vm_hub = AMDGPU_MMHUB0(0);
- ring->use_doorbell = 0;
+ ring->use_doorbell = true;
ring->no_scheduler = true;
ring->doorbell_index = (AMDGPU_NAVI10_DOORBELL64_VCN0_1 << 1) + 6;
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index 7e79954c833b..17c73aaa1e82 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -217,7 +217,8 @@ static int umsch_mm_v4_0_ring_start(struct amdgpu_umsch_mm *umsch)
data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 1);
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
- adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, ring->doorbell_index, 0);
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_LO, lower_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* RE: [PATCH 3/3] drm/amdgpu/umsch: enable doorbell for umsch
2023-10-07 8:54 ` [PATCH 3/3] drm/amdgpu/umsch: enable doorbell for umsch Lang Yu
@ 2023-10-09 15:08 ` Gopalakrishnan, Veerabadhran (Veera)
0 siblings, 0 replies; 12+ messages in thread
From: Gopalakrishnan, Veerabadhran (Veera) @ 2023-10-09 15:08 UTC (permalink / raw)
To: Yu, Lang, amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander, Zhang, Yifan
[AMD Official Use Only - General]
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
-Veera
-----Original Message-----
From: Yu, Lang <Lang.Yu@amd.com>
Sent: Saturday, October 7, 2023 2:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Gopalakrishnan, Veerabadhran (Veera) <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
Subject: [PATCH 3/3] drm/amdgpu/umsch: enable doorbell for umsch
Program vcn_doorbell_range with vcn_ring0_1.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 2 +-
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 3 ++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index 9d89c4186989..4bd076e9e367 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -554,7 +554,7 @@ int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch)
struct amdgpu_ring *ring = &umsch->ring;
ring->vm_hub = AMDGPU_MMHUB0(0);
- ring->use_doorbell = 0;
+ ring->use_doorbell = true;
ring->no_scheduler = true;
ring->doorbell_index = (AMDGPU_NAVI10_DOORBELL64_VCN0_1 << 1) + 6;
diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index 7e79954c833b..17c73aaa1e82 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -217,7 +217,8 @@ static int umsch_mm_v4_0_ring_start(struct amdgpu_umsch_mm *umsch)
data = REG_SET_FIELD(data, VCN_UMSCH_RB_DB_CTRL, EN, 1);
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_DB_CTRL, data);
- adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell, ring->doorbell_index, 0);
+ adev->nbio.funcs->vcn_doorbell_range(adev, ring->use_doorbell,
+ (adev->doorbell_index.vcn.vcn_ring0_1 << 1), 0);
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_LO, lower_32_bits(ring->gpu_addr));
WREG32_SOC15(VCN, 0, regVCN_UMSCH_RB_BASE_HI, upper_32_bits(ring->gpu_addr));
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* RE: [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading
2023-10-07 8:54 [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading Lang Yu
2023-10-07 8:54 ` [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO Lang Yu
2023-10-07 8:54 ` [PATCH 3/3] drm/amdgpu/umsch: enable doorbell for umsch Lang Yu
@ 2023-10-09 15:04 ` Gopalakrishnan, Veerabadhran (Veera)
2 siblings, 0 replies; 12+ messages in thread
From: Gopalakrishnan, Veerabadhran (Veera) @ 2023-10-09 15:04 UTC (permalink / raw)
To: Yu, Lang, amd-gfx@lists.freedesktop.org; +Cc: Deucher, Alexander, Zhang, Yifan
[AMD Official Use Only - General]
Reviewed-by: Veerabadhran Gopalakrishnan <Veerabadhran.Gopalakrishnan@amd.com>
-Veera
-----Original Message-----
From: Yu, Lang <Lang.Yu@amd.com>
Sent: Saturday, October 7, 2023 2:24 PM
To: amd-gfx@lists.freedesktop.org
Cc: Deucher, Alexander <Alexander.Deucher@amd.com>; Zhang, Yifan <Yifan1.Zhang@amd.com>; Gopalakrishnan, Veerabadhran (Veera) <Veerabadhran.Gopalakrishnan@amd.com>; Yu, Lang <Lang.Yu@amd.com>
Subject: [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading
These changes are missed in rebase.
Signed-off-by: Lang Yu <Lang.Yu@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c | 35 +++--- drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h | 18 +++-
drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c | 107 ++++++++-----------
3 files changed, 72 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
index aeff9926412f..9d89c4186989 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.c
@@ -75,17 +75,6 @@ struct umsch_mm_test {
uint32_t num_queues;
};
-int umsch_mm_psp_update_sram(struct amdgpu_device *adev, u32 ucode_size) -{
- struct amdgpu_firmware_info ucode = {
- .ucode_id = AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
- .mc_addr = adev->umsch_mm.cmd_buf_gpu_addr,
- .ucode_size = ucode_size,
- };
-
- return psp_execute_ip_fw_load(&adev->psp, &ucode);
-}
-
static int map_ring_data(struct amdgpu_device *adev, struct amdgpu_vm *vm,
struct amdgpu_bo *bo, struct amdgpu_bo_va **bo_va,
uint64_t addr, uint32_t size)
@@ -694,15 +683,17 @@ int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch)
return 0;
}
-void* amdgpu_umsch_mm_add_cmd(struct amdgpu_umsch_mm *umsch,
- void* cmd_ptr, uint32_t reg_offset, uint32_t reg_data)
+int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch)
{
- uint32_t* ptr = (uint32_t *)cmd_ptr;
-
- *ptr++ = (reg_offset << 2);
- *ptr++ = reg_data;
+ struct amdgpu_device *adev = umsch->ring.adev;
+ struct amdgpu_firmware_info ucode = {
+ .ucode_id = AMDGPU_UCODE_ID_UMSCH_MM_CMD_BUFFER,
+ .mc_addr = adev->umsch_mm.cmd_buf_gpu_addr,
+ .ucode_size = ((uintptr_t)adev->umsch_mm.cmd_buf_curr_ptr -
+ (uintptr_t)adev->umsch_mm.cmd_buf_ptr),
+ };
- return ptr;
+ return psp_execute_ip_fw_load(&adev->psp, &ucode);
}
static void umsch_mm_agdb_index_init(struct amdgpu_device *adev) @@ -824,11 +815,9 @@ static int umsch_mm_hw_init(void *handle)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int r;
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_DIRECT) {
- r = umsch_mm_load_microcode(&adev->umsch_mm);
- if (r)
- return r;
- }
+ r = umsch_mm_load_microcode(&adev->umsch_mm);
+ if (r)
+ return r;
umsch_mm_ring_start(&adev->umsch_mm);
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
index d83fdf2da464..8258a43a6236 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_umsch_mm.h
@@ -150,6 +150,7 @@ struct amdgpu_umsch_mm {
struct amdgpu_bo *cmd_buf_obj;
uint64_t cmd_buf_gpu_addr;
uint32_t *cmd_buf_ptr;
+ uint32_t *cmd_buf_curr_ptr;
uint32_t wb_index;
uint64_t sch_ctx_gpu_addr;
@@ -167,19 +168,28 @@ struct amdgpu_umsch_mm {
struct mutex mutex_hidden;
};
-int umsch_mm_psp_update_sram(struct amdgpu_device *adev, u32 ucode_size);
-
int amdgpu_umsch_mm_submit_pkt(struct amdgpu_umsch_mm *umsch, void *pkt, int ndws); int amdgpu_umsch_mm_query_fence(struct amdgpu_umsch_mm *umsch);
int amdgpu_umsch_mm_init_microcode(struct amdgpu_umsch_mm *umsch); int amdgpu_umsch_mm_allocate_ucode_buffer(struct amdgpu_umsch_mm *umsch); int amdgpu_umsch_mm_allocate_ucode_data_buffer(struct amdgpu_umsch_mm *umsch);
-void* amdgpu_umsch_mm_add_cmd(struct amdgpu_umsch_mm *umsch,
- void* cmd_ptr, uint32_t reg_offset, uint32_t reg_data);
+
+int amdgpu_umsch_mm_psp_execute_cmd_buf(struct amdgpu_umsch_mm *umsch);
int amdgpu_umsch_mm_ring_init(struct amdgpu_umsch_mm *umsch);
+#define WREG32_SOC15_UMSCH(reg, value) \
+ do { \
+ uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) { \
+ *adev->umsch_mm.cmd_buf_curr_ptr++ = (reg_offset << 2); \
+ *adev->umsch_mm.cmd_buf_curr_ptr++ = value; \
+ } else { \
+ WREG32(reg_offset, value); \
+ } \
+ } while (0)
+
#define umsch_mm_set_hw_resources(umsch) \
((umsch)->funcs->set_hw_resources ? (umsch)->funcs->set_hw_resources((umsch)) : 0) #define umsch_mm_add_queue(umsch, input) \ diff --git a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
index 99713949b61f..a60178156c77 100644
--- a/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/umsch_mm_v4_0.c
@@ -34,23 +34,10 @@
#include "umsch_mm_4_0_api_def.h"
#include "umsch_mm_v4_0.h"
-#define WREG32_SOC15_UMSCH(ptr, reg, value) \
-({ void *ret = ptr; \
- do { \
- uint32_t reg_offset = adev->reg_offset[VCN_HWIP][0][reg##_BASE_IDX] + reg; \
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) \
- ret = amdgpu_umsch_mm_add_cmd((&adev->umsch_mm), (ptr), (reg_offset), (value)); \
- else \
- WREG32(reg_offset, value); \
- } while (0); \
- ret; \
-})
-
static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch) {
struct amdgpu_device *adev = umsch->ring.adev;
- void* ptr = umsch->cmd_buf_ptr;
- uint32_t data;
+ uint64_t data;
int r;
r = amdgpu_umsch_mm_allocate_ucode_buffer(umsch);
@@ -61,97 +48,95 @@ static int umsch_mm_v4_0_load_microcode(struct amdgpu_umsch_mm *umsch)
if (r)
goto err_free_ucode_bo;
+ umsch->cmd_buf_curr_ptr = umsch->cmd_buf_ptr;
+
data = RREG32_SOC15(VCN, 0, regUMSCH_MES_RESET_CTRL);
data = REG_SET_FIELD(data, UMSCH_MES_RESET_CTRL, MES_CORE_SOFT_RESET, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regUMSCH_MES_RESET_CTRL, data);
+ WREG32_SOC15_UMSCH(regUMSCH_MES_RESET_CTRL, data);
data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 1);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 1);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 0);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);
data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_BASE_CNTL);
data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, VMID, 0);
data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, EXE_DISABLE, 0);
data = REG_SET_FIELD(data, VCN_MES_IC_BASE_CNTL, CACHE_POLICY, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_BASE_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START,
+ lower_32_bits(adev->umsch_mm.irq_start_addr >> 2));
+ WREG32_SOC15_UMSCH(regVCN_MES_INTR_ROUTINE_START_HI,
+ upper_32_bits(adev->umsch_mm.irq_start_addr >> 2));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_INTR_ROUTINE_START,
- lower_32_bits(adev->umsch_mm.irq_start_addr >> 2));
+ WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START,
+ lower_32_bits(adev->umsch_mm.uc_start_addr >> 2));
+ WREG32_SOC15_UMSCH(regVCN_MES_PRGRM_CNTR_START_HI,
+ upper_32_bits(adev->umsch_mm.uc_start_addr >> 2));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_INTR_ROUTINE_START_HI,
- upper_32_bits(adev->umsch_mm.irq_start_addr >> 2));
-
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_PRGRM_CNTR_START,
- lower_32_bits(adev->umsch_mm.uc_start_addr >> 2));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_PRGRM_CNTR_START_HI,
- upper_32_bits(adev->umsch_mm.uc_start_addr >> 2));
-
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_BASE_LO, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_BASE_HI, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_LO, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_BASE_HI, 0);
data = adev->umsch_mm.uc_start_addr + adev->umsch_mm.ucode_size - 1;
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_INSTR_MASK_HI, upper_32_bits(data));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_LO, lower_32_bits(data));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_INSTR_MASK_HI,
+upper_32_bits(data));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_BASE_LO,
- lower_32_bits(adev->umsch_mm.ucode_fw_gpu_addr));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_BASE_HI,
- upper_32_bits(adev->umsch_mm.ucode_fw_gpu_addr));
+ data = adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ?
+ 0 : adev->umsch_mm.ucode_fw_gpu_addr;
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_LO, lower_32_bits(data));
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_BASE_HI, upper_32_bits(data));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_MIBOUND_LO, 0x1FFFFF);
+ WREG32_SOC15_UMSCH(regVCN_MES_MIBOUND_LO, 0x1FFFFF);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_BASE0_LO,
- lower_32_bits(adev->umsch_mm.data_start_addr));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_BASE0_HI,
- upper_32_bits(adev->umsch_mm.data_start_addr));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_LO,
+ lower_32_bits(adev->umsch_mm.data_start_addr));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_BASE0_HI,
+ upper_32_bits(adev->umsch_mm.data_start_addr));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_MASK0_LO,
- lower_32_bits(adev->umsch_mm.data_size - 1));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_LOCAL_MASK0_HI,
- upper_32_bits(adev->umsch_mm.data_size - 1));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_LO,
+ lower_32_bits(adev->umsch_mm.data_size - 1));
+ WREG32_SOC15_UMSCH(regVCN_MES_LOCAL_MASK0_HI,
+ upper_32_bits(adev->umsch_mm.data_size - 1));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_DC_BASE_LO,
- lower_32_bits(adev->umsch_mm.data_fw_gpu_addr));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_DC_BASE_HI,
- upper_32_bits(adev->umsch_mm.data_fw_gpu_addr));
+ data = adev->firmware.load_type == AMDGPU_FW_LOAD_PSP ?
+ 0 : adev->umsch_mm.data_fw_gpu_addr;
+ WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_LO, lower_32_bits(data));
+ WREG32_SOC15_UMSCH(regVCN_MES_DC_BASE_HI, upper_32_bits(data));
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_MDBOUND_LO, 0x3FFFF);
+ WREG32_SOC15_UMSCH(regVCN_MES_MDBOUND_LO, 0x3FFFF);
data = RREG32_SOC15(VCN, 0, regUVD_UMSCH_FORCE);
data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, IC_FORCE_GPUVM, 1);
data = REG_SET_FIELD(data, UVD_UMSCH_FORCE, DC_FORCE_GPUVM, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regUVD_UMSCH_FORCE, data);
+ WREG32_SOC15_UMSCH(regUVD_UMSCH_FORCE, data);
data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);
data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 0);
data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, INVALIDATE_CACHE, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_OP_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);
data = RREG32_SOC15(VCN, 0, regVCN_MES_IC_OP_CNTL);
data = REG_SET_FIELD(data, VCN_MES_IC_OP_CNTL, PRIME_ICACHE, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_IC_OP_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_IC_OP_CNTL, data);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP0_LO, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP0_HI, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_GP0_LO, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_GP0_HI, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP1_LO, 0);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_GP1_HI, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_GP1_LO, 0);
+ WREG32_SOC15_UMSCH(regVCN_MES_GP1_HI, 0);
data = RREG32_SOC15(VCN, 0, regVCN_MES_CNTL);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_INVALIDATE_ICACHE, 0);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_RESET, 0);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_HALT, 0);
data = REG_SET_FIELD(data, VCN_MES_CNTL, MES_PIPE0_ACTIVE, 1);
- ptr = WREG32_SOC15_UMSCH(ptr, regVCN_MES_CNTL, data);
+ WREG32_SOC15_UMSCH(regVCN_MES_CNTL, data);
- if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP) {
- umsch_mm_psp_update_sram(adev,
- (u32)((uintptr_t)ptr - (uintptr_t)umsch->cmd_buf_ptr));
- }
+ if (adev->firmware.load_type == AMDGPU_FW_LOAD_PSP)
+ amdgpu_umsch_mm_psp_execute_cmd_buf(umsch);
r = SOC15_WAIT_ON_RREG(VCN, 0, regVCN_MES_MSTATUS_LO, 0xAAAAAAAA, 0xFFFFFFFF);
if (r) {
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
end of thread, other threads:[~2023-10-11 2:17 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-07 8:54 [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading Lang Yu
2023-10-07 8:54 ` [PATCH 2/3] drm/amdgpu/umsch: power on/off UMSCH by DLDO Lang Yu
2023-10-09 15:05 ` Gopalakrishnan, Veerabadhran (Veera)
2023-10-09 19:36 ` Deucher, Alexander
2023-10-10 0:45 ` Lang Yu
2023-10-09 19:44 ` Deucher, Alexander
2023-10-10 0:44 ` Lang Yu
2023-10-10 14:01 ` Alex Deucher
2023-10-11 2:16 ` Lang Yu
2023-10-07 8:54 ` [PATCH 3/3] drm/amdgpu/umsch: enable doorbell for umsch Lang Yu
2023-10-09 15:08 ` Gopalakrishnan, Veerabadhran (Veera)
2023-10-09 15:04 ` [PATCH 1/3] drm/amdgpu/umsch: fix psp frontdoor loading Gopalakrishnan, Veerabadhran (Veera)
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