Re: [PATCH v2 1/2] riscv: errata: thead: use riscv_nonstd_cache_ops for CMO

[Jisheng Zhang <jszhang@kernel.org>]

On Thu, Oct 12, 2023 at 02:43:18PM +0200, Clément Léger wrote:
> 
> 
> On 01/10/2023 12:34, Jisheng Zhang wrote:
> > Previously, we use alternative mechanism to dynamically patch
> > the CMO operations for THEAD C906/C910 during boot for performance
> > reason. But as pointed out by Arnd, "there is already a significant
> > cost in accessing the invalidated cache lines afterwards, which is
> > likely going to be much higher than the cost of an indirect branch".
> > And indeed, there's no performance difference with GMAC and EMMC per
> > my test on Sipeed Lichee Pi 4A board.
> > 
> > Use riscv_nonstd_cache_ops for THEAD C906/C910 CMO to simplify
> > the alternative code, and to acchieve Arnd's goal -- "I think
> > moving the THEAD ops at the same level as all nonstandard operations
> > makes sense, but I'd still leave CMO as an explicit fast path that
> > avoids the indirect branch. This seems like the right thing to do both
> > for readability and for platforms on which the indirect branch has a
> > noticeable overhead."
> > 
> > Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> > Tested-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> > ---
> >  arch/riscv/Kconfig.errata            |  1 +
> >  arch/riscv/errata/thead/errata.c     | 75 +++++++++++++++++++++++++++-
> >  arch/riscv/include/asm/errata_list.h | 50 +++----------------
> >  3 files changed, 80 insertions(+), 46 deletions(-)
> > 
> > diff --git a/arch/riscv/Kconfig.errata b/arch/riscv/Kconfig.errata
> > index 566bcefeab50..d7972914f9de 100644
> > --- a/arch/riscv/Kconfig.errata
> > +++ b/arch/riscv/Kconfig.errata
> > @@ -78,6 +78,7 @@ config ERRATA_THEAD_CMO
> >  	bool "Apply T-Head cache management errata"
> >  	depends on ERRATA_THEAD && MMU
> >  	select RISCV_DMA_NONCOHERENT
> > +	select RISCV_NONSTANDARD_CACHE_OPS
> >  	default y
> >  	help
> >  	  This will apply the cache management errata to handle the
> > diff --git a/arch/riscv/errata/thead/errata.c b/arch/riscv/errata/thead/errata.c
> > index 0554ed4bf087..3fefeb1b456e 100644
> > --- a/arch/riscv/errata/thead/errata.c
> > +++ b/arch/riscv/errata/thead/errata.c
> > @@ -12,8 +12,10 @@
> >  #include <asm/alternative.h>
> >  #include <asm/cacheflush.h>
> >  #include <asm/cpufeature.h>
> > +#include <asm/dma-noncoherent.h>
> >  #include <asm/errata_list.h>
> >  #include <asm/hwprobe.h>
> > +#include <asm/io.h>
> >  #include <asm/patch.h>
> >  #include <asm/vendorid_list.h>
> >  
> > @@ -33,6 +35,75 @@ static bool errata_probe_pbmt(unsigned int stage,
> >  	return false;
> >  }
> >  
> > +/*
> > + * dcache.ipa rs1 (invalidate, physical address)
> > + * | 31 - 25 | 24 - 20 | 19 - 15 | 14 - 12 | 11 - 7 | 6 - 0 |
> > + *   0000001    01010      rs1       000      00000  0001011
> > + * dache.iva rs1 (invalida, virtual address)
> 
> Small typo here: invalidate instead of invalida

another typo: s/dache/dcache
these typo have existed there for a long time ;) I just fixed them in
v3.

Thanks for pointing this out.

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