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From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: <linux-riscv@lists.indradead.org>, <conor@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Chen-Yu Tsai <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	"Emil Renner Berthing" <kernel@esmil.dk>,
	Jisheng Zhang <jszhang@kernel.org>, Guo Ren <guoren@kernel.org>,
	Fu Wei <wefu@redhat.com>, Chen Wang <unicorn_wang@outlook.com>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-sunxi@lists.linux.dev>,
	<linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v3 4/6] riscv: dts: renesas: convert isa detection to new properties
Date: Mon, 16 Oct 2023 14:09:46 +0800	[thread overview]
Message-ID: <ZSzTqgVNSD9Q7V6H@APC323> (raw)
In-Reply-To: <20231009-smog-gag-3ba67e68126b@wendy>

On Mon, Oct 09, 2023 at 10:37:48AM +0100, Conor Dooley wrote:
> Convert the RZ/Five devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> index b0796015e36b..eb301d8eb2b0 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -24,6 +24,9 @@ cpu0: cpu@0 {
>  			reg = <0x0>;
>  			status = "okay";
>  			riscv,isa = "rv64imafdc";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> +					       "zifencei", "zihpm";

We do have zihpm, and OpenSBI can also probe its existence.

Boot HART ISA Extensions  : zihpm
Boot HART MHPM Info       : 4 (0x00000078)

By the way, we will append "xandespmu" here.
I hope this is an appropriate way to add a new custom extension.

>  			mmu-type = "riscv,sv39";
>  			i-cache-size = <0x8000>;
>  			i-cache-line-size = <0x40>;

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WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Conor Dooley <conor.dooley@microchip.com>
Cc: <linux-riscv@lists.indradead.org>, <conor@kernel.org>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Conor Dooley <conor+dt@kernel.org>,
	"Paul Walmsley" <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>, Chen-Yu Tsai <wens@csie.org>,
	"Jernej Skrabec" <jernej.skrabec@gmail.com>,
	Samuel Holland <samuel@sholland.org>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Geert Uytterhoeven <geert+renesas@glider.be>,
	Magnus Damm <magnus.damm@gmail.com>,
	"Emil Renner Berthing" <kernel@esmil.dk>,
	Jisheng Zhang <jszhang@kernel.org>, Guo Ren <guoren@kernel.org>,
	Fu Wei <wefu@redhat.com>, Chen Wang <unicorn_wang@outlook.com>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-sunxi@lists.linux.dev>,
	<linux-renesas-soc@vger.kernel.org>
Subject: Re: [PATCH v3 4/6] riscv: dts: renesas: convert isa detection to new properties
Date: Mon, 16 Oct 2023 14:09:46 +0800	[thread overview]
Message-ID: <ZSzTqgVNSD9Q7V6H@APC323> (raw)
In-Reply-To: <20231009-smog-gag-3ba67e68126b@wendy>

On Mon, Oct 09, 2023 at 10:37:48AM +0100, Conor Dooley wrote:
> Convert the RZ/Five devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
> 
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
> ---
>  arch/riscv/boot/dts/renesas/r9a07g043f.dtsi | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> index b0796015e36b..eb301d8eb2b0 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> @@ -24,6 +24,9 @@ cpu0: cpu@0 {
>  			reg = <0x0>;
>  			status = "okay";
>  			riscv,isa = "rv64imafdc";
> +			riscv,isa-base = "rv64i";
> +			riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> +					       "zifencei", "zihpm";

We do have zihpm, and OpenSBI can also probe its existence.

Boot HART ISA Extensions  : zihpm
Boot HART MHPM Info       : 4 (0x00000078)

By the way, we will append "xandespmu" here.
I hope this is an appropriate way to add a new custom extension.

>  			mmu-type = "riscv,sv39";
>  			i-cache-size = <0x8000>;
>  			i-cache-line-size = <0x40>;

  parent reply	other threads:[~2023-10-16  6:10 UTC|newest]

Thread overview: 32+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-09  9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
2023-10-09  9:37 ` Conor Dooley
2023-10-09  9:37 ` [PATCH v3 1/6] riscv: dts: microchip: convert isa detection to new properties Conor Dooley
2023-10-09  9:37   ` Conor Dooley
2023-10-09  9:37 ` [PATCH v3 2/6] riscv: dts: sifive: " Conor Dooley
2023-10-09  9:37   ` Conor Dooley
2023-10-09  9:37 ` [PATCH v3 3/6] riscv: dts: starfive: " Conor Dooley
2023-10-09  9:37   ` Conor Dooley
2023-10-09  9:37 ` [PATCH v3 4/6] riscv: dts: renesas: " Conor Dooley
2023-10-09  9:37   ` Conor Dooley
2023-10-09 12:15   ` Geert Uytterhoeven
2023-10-09 12:15     ` Geert Uytterhoeven
2023-10-09 16:16     ` Conor Dooley
2023-10-09 16:16       ` Conor Dooley
2023-10-16  6:09   ` Yu-Chien Peter Lin [this message]
2023-10-16  6:09     ` Yu-Chien Peter Lin
2023-10-16  7:17     ` Geert Uytterhoeven
2023-10-16  7:17       ` Geert Uytterhoeven
2023-10-09  9:37 ` [PATCH v3 5/6] riscv: dts: allwinner: " Conor Dooley
2023-10-09  9:37   ` Conor Dooley
2023-10-13 19:22   ` Jernej Škrabec
2023-10-13 19:22     ` Jernej Škrabec
2023-10-09  9:37 ` [PATCH v3 6/6] riscv: dts: thead: " Conor Dooley
2023-10-09  9:37   ` Conor Dooley
2023-10-15 12:22 ` (subset) [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
2023-10-15 12:22   ` Conor Dooley
2023-10-16  7:23   ` Geert Uytterhoeven
2023-10-16  7:23     ` Geert Uytterhoeven
2023-10-16  8:09     ` Conor Dooley
2023-10-16  8:09       ` Conor Dooley
2023-11-12  0:55 ` patchwork-bot+linux-riscv
2023-11-12  0:55   ` patchwork-bot+linux-riscv

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