From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: <magnus.damm@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <linux-renesas-soc@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>, <tim609@andestech.com>,
<dylan@andestech.com>, <locus84@andestech.com>,
<dminus@andestech.com>
Subject: Re: [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension
Date: Fri, 20 Oct 2023 16:20:15 +0800 [thread overview]
Message-ID: <ZTI4P9KIfS58WKuU@APC323> (raw)
In-Reply-To: <CAMuHMdW1Ua4skxtT+9kyoSDiqt2kNiNG-1jHE8rf4+b14hX4Vg@mail.gmail.com>
Hi Geert,
On Fri, Oct 20, 2023 at 09:32:45AM +0200, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Thu, Oct 19, 2023 at 4:05 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> > Add "xandespmu" to ISA extensions, the SBI PMU driver will
> > probe the extension and use the non-standard irq source.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > ---
> > Changes v1 -> v2:
> > - New patch
>
> Thanks for your patch!
>
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -26,7 +26,7 @@ cpu0: cpu@0 {
> > riscv,isa = "rv64imafdc";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > - "zifencei", "zihpm";
> > + "zifencei", "zihpm", "xandespmu";
> > mmu-type = "riscv,sv39";
> > i-cache-size = <0x8000>;
> > i-cache-line-size = <0x40>;
>
> This extension is not documented in
> Documentation/devicetree/bindings/riscv/extensions.yaml. Perhaps it was
> introduced in an earlier patch in the series, to which I was not CCed?
Yes, I missed adding the extension to dt bindings.
Thanks for the pointer.
Best regards,
Peter Lin
>
> Threading is broken, so I can't easily find the whole series in lore:
> https://lore.kernel.org/all/20231019140232.3660375-1-peterlin@andestech.com/
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
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WARNING: multiple messages have this Message-ID (diff)
From: Yu-Chien Peter Lin <peterlin@andestech.com>
To: Geert Uytterhoeven <geert@linux-m68k.org>
Cc: <magnus.damm@gmail.com>, <robh+dt@kernel.org>,
<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <linux-renesas-soc@vger.kernel.org>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-kernel@vger.kernel.org>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>, <tim609@andestech.com>,
<dylan@andestech.com>, <locus84@andestech.com>,
<dminus@andestech.com>
Subject: Re: [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension
Date: Fri, 20 Oct 2023 16:20:15 +0800 [thread overview]
Message-ID: <ZTI4P9KIfS58WKuU@APC323> (raw)
In-Reply-To: <CAMuHMdW1Ua4skxtT+9kyoSDiqt2kNiNG-1jHE8rf4+b14hX4Vg@mail.gmail.com>
Hi Geert,
On Fri, Oct 20, 2023 at 09:32:45AM +0200, Geert Uytterhoeven wrote:
> Hi Peter,
>
> On Thu, Oct 19, 2023 at 4:05 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> > Add "xandespmu" to ISA extensions, the SBI PMU driver will
> > probe the extension and use the non-standard irq source.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > ---
> > Changes v1 -> v2:
> > - New patch
>
> Thanks for your patch!
>
> > --- a/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > +++ b/arch/riscv/boot/dts/renesas/r9a07g043f.dtsi
> > @@ -26,7 +26,7 @@ cpu0: cpu@0 {
> > riscv,isa = "rv64imafdc";
> > riscv,isa-base = "rv64i";
> > riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
> > - "zifencei", "zihpm";
> > + "zifencei", "zihpm", "xandespmu";
> > mmu-type = "riscv,sv39";
> > i-cache-size = <0x8000>;
> > i-cache-line-size = <0x40>;
>
> This extension is not documented in
> Documentation/devicetree/bindings/riscv/extensions.yaml. Perhaps it was
> introduced in an earlier patch in the series, to which I was not CCed?
Yes, I missed adding the extension to dt bindings.
Thanks for the pointer.
Best regards,
Peter Lin
>
> Threading is broken, so I can't easily find the whole series in lore:
> https://lore.kernel.org/all/20231019140232.3660375-1-peterlin@andestech.com/
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
>
> In personal conversations with technical people, I call myself a hacker. But
> when I'm talking to journalists I just say "programmer" or something like that.
> -- Linus Torvalds
next prev parent reply other threads:[~2023-10-20 8:20 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-19 14:02 [PATCH v2 09/10] riscv: dts: renesas: Add Andes PMU extension Yu Chien Peter Lin
2023-10-19 14:02 ` Yu Chien Peter Lin
2023-10-20 7:32 ` Geert Uytterhoeven
2023-10-20 7:32 ` Geert Uytterhoeven
2023-10-20 8:20 ` Yu-Chien Peter Lin [this message]
2023-10-20 8:20 ` Yu-Chien Peter Lin
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