* [PATCH v2 01/11] sbi: sbi_pmu: Improve sbi_pmu_init() error handling
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 6:32 ` Anup Patel
2023-10-19 11:37 ` [PATCH v2 02/11] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Yu Chien Peter Lin
` (10 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
This patch makes the following changes:
- As sbi_platform_pmu_init() returns a negative error code on
failure, let sbi_pmu_init() to hang by propagating the error
code.
- In order to distinguish the SBI_EFAIL error returned by
sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
generic_pmu_init() ignores such case.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
---
lib/sbi/sbi_pmu.c | 5 ++++-
lib/utils/fdt/fdt_pmu.c | 2 +-
platform/generic/platform.c | 8 +++++++-
3 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index f4c8fc4..3cbd4ff 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -957,6 +957,7 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
int hpm_count = sbi_fls(sbi_hart_mhpm_mask(scratch));
struct sbi_pmu_hart_state *phs;
const struct sbi_platform *plat;
+ int rc;
if (cold_boot) {
hw_event_map = sbi_calloc(sizeof(*hw_event_map),
@@ -972,7 +973,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
plat = sbi_platform_ptr(scratch);
/* Initialize hw pmu events */
- sbi_platform_pmu_init(plat);
+ rc = sbi_platform_pmu_init(plat);
+ if (rc)
+ return rc;
/* mcycle & minstret is available always */
if (!hpm_count)
diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c
index 83301bb..a8d7648 100644
--- a/lib/utils/fdt/fdt_pmu.c
+++ b/lib/utils/fdt/fdt_pmu.c
@@ -74,7 +74,7 @@ int fdt_pmu_setup(void *fdt)
pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu");
if (pmu_offset < 0)
- return SBI_EFAIL;
+ return SBI_ENOENT;
event_ctr_map = fdt_getprop(fdt, pmu_offset,
"riscv,event-to-mhpmcounters", &len);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index 66a0b77..cb9270d 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -265,7 +265,13 @@ static u32 generic_tlb_num_entries(void)
static int generic_pmu_init(void)
{
- return fdt_pmu_setup(fdt_get_address());
+ int rc;
+
+ rc = fdt_pmu_setup(fdt_get_address());
+ if (rc && rc != SBI_ENOENT)
+ return rc;
+
+ return 0;
}
static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx,
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 01/11] sbi: sbi_pmu: Improve sbi_pmu_init() error handling
2023-10-19 11:37 ` [PATCH v2 01/11] sbi: sbi_pmu: Improve sbi_pmu_init() error handling Yu Chien Peter Lin
@ 2023-11-16 6:32 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:32 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:10?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch makes the following changes:
>
> - As sbi_platform_pmu_init() returns a negative error code on
> failure, let sbi_pmu_init() to hang by propagating the error
> code.
>
> - In order to distinguish the SBI_EFAIL error returned by
> sbi_pmu_add_*_counter_map(), return SBI_ENOENT to indicate
> that fdt_pmu_setup() failed to locate "riscv,pmu" node, and
> generic_pmu_init() ignores such case.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> Changes v1 -> v2:
> - New patch
> ---
> lib/sbi/sbi_pmu.c | 5 ++++-
> lib/utils/fdt/fdt_pmu.c | 2 +-
> platform/generic/platform.c | 8 +++++++-
> 3 files changed, 12 insertions(+), 3 deletions(-)
>
> diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> index f4c8fc4..3cbd4ff 100644
> --- a/lib/sbi/sbi_pmu.c
> +++ b/lib/sbi/sbi_pmu.c
> @@ -957,6 +957,7 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
> int hpm_count = sbi_fls(sbi_hart_mhpm_mask(scratch));
> struct sbi_pmu_hart_state *phs;
> const struct sbi_platform *plat;
> + int rc;
>
> if (cold_boot) {
> hw_event_map = sbi_calloc(sizeof(*hw_event_map),
> @@ -972,7 +973,9 @@ int sbi_pmu_init(struct sbi_scratch *scratch, bool cold_boot)
>
> plat = sbi_platform_ptr(scratch);
> /* Initialize hw pmu events */
> - sbi_platform_pmu_init(plat);
> + rc = sbi_platform_pmu_init(plat);
> + if (rc)
> + return rc;
>
> /* mcycle & minstret is available always */
> if (!hpm_count)
> diff --git a/lib/utils/fdt/fdt_pmu.c b/lib/utils/fdt/fdt_pmu.c
> index 83301bb..a8d7648 100644
> --- a/lib/utils/fdt/fdt_pmu.c
> +++ b/lib/utils/fdt/fdt_pmu.c
> @@ -74,7 +74,7 @@ int fdt_pmu_setup(void *fdt)
>
> pmu_offset = fdt_node_offset_by_compatible(fdt, -1, "riscv,pmu");
> if (pmu_offset < 0)
> - return SBI_EFAIL;
> + return SBI_ENOENT;
>
> event_ctr_map = fdt_getprop(fdt, pmu_offset,
> "riscv,event-to-mhpmcounters", &len);
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index 66a0b77..cb9270d 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -265,7 +265,13 @@ static u32 generic_tlb_num_entries(void)
>
> static int generic_pmu_init(void)
> {
> - return fdt_pmu_setup(fdt_get_address());
> + int rc;
> +
> + rc = fdt_pmu_setup(fdt_get_address());
> + if (rc && rc != SBI_ENOENT)
> + return rc;
> +
> + return 0;
> }
>
> static uint64_t generic_pmu_xlate_to_mhpmevent(uint32_t event_idx,
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 02/11] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
2023-10-19 11:37 ` [PATCH v2 01/11] sbi: sbi_pmu: Improve sbi_pmu_init() error handling Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 6:36 ` Anup Patel
2023-10-19 11:37 ` [PATCH v2 03/11] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
` (9 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
Add support for custom PMU extensions to set inhibit bits
on custom CSRs by introducing the PMU device callback
hw_counter_filter_mode(). This allows the perf tool to
restrict event counting under a specified privileged
mode by appending a modifier, e.g. perf record -e event:k
to count events only happening in kernel mode.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- No change
---
include/sbi/sbi_pmu.h | 6 ++++++
lib/sbi/sbi_pmu.c | 5 ++++-
2 files changed, 10 insertions(+), 1 deletion(-)
diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
index 16f6877..d63149c 100644
--- a/include/sbi/sbi_pmu.h
+++ b/include/sbi/sbi_pmu.h
@@ -89,6 +89,12 @@ struct sbi_pmu_device {
* Custom function returning the machine-specific irq-bit.
*/
int (*hw_counter_irq_bit)(void);
+
+ /**
+ * Custom function to inhibit counting of events while in
+ * specified mode.
+ */
+ void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
};
/** Get the PMU platform device */
diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
index 3cbd4ff..7e3723f 100644
--- a/lib/sbi/sbi_pmu.c
+++ b/lib/sbi/sbi_pmu.c
@@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
pmu_dev->hw_counter_disable_irq(ctr_idx);
/* Update the inhibit flags based on inhibit flags received from supervisor */
- pmu_update_inhibit_flags(flags, &mhpmevent_val);
+ if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
+ pmu_update_inhibit_flags(flags, &mhpmevent_val);
+ if (pmu_dev && pmu_dev->hw_counter_filter_mode)
+ pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
#if __riscv_xlen == 32
csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 02/11] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
2023-10-19 11:37 ` [PATCH v2 02/11] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Yu Chien Peter Lin
@ 2023-11-16 6:36 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:36 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:10?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add support for custom PMU extensions to set inhibit bits
> on custom CSRs by introducing the PMU device callback
> hw_counter_filter_mode(). This allows the perf tool to
> restrict event counting under a specified privileged
> mode by appending a modifier, e.g. perf record -e event:k
> to count events only happening in kernel mode.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - No change
> ---
> include/sbi/sbi_pmu.h | 6 ++++++
> lib/sbi/sbi_pmu.c | 5 ++++-
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/include/sbi/sbi_pmu.h b/include/sbi/sbi_pmu.h
> index 16f6877..d63149c 100644
> --- a/include/sbi/sbi_pmu.h
> +++ b/include/sbi/sbi_pmu.h
> @@ -89,6 +89,12 @@ struct sbi_pmu_device {
> * Custom function returning the machine-specific irq-bit.
> */
> int (*hw_counter_irq_bit)(void);
> +
> + /**
> + * Custom function to inhibit counting of events while in
> + * specified mode.
> + */
> + void (*hw_counter_filter_mode)(unsigned long flags, int counter_index);
> };
>
> /** Get the PMU platform device */
> diff --git a/lib/sbi/sbi_pmu.c b/lib/sbi/sbi_pmu.c
> index 3cbd4ff..7e3723f 100644
> --- a/lib/sbi/sbi_pmu.c
> +++ b/lib/sbi/sbi_pmu.c
> @@ -599,7 +599,10 @@ static int pmu_update_hw_mhpmevent(struct sbi_pmu_hw_event *hw_evt, int ctr_idx,
> pmu_dev->hw_counter_disable_irq(ctr_idx);
>
> /* Update the inhibit flags based on inhibit flags received from supervisor */
> - pmu_update_inhibit_flags(flags, &mhpmevent_val);
> + if (sbi_hart_has_extension(scratch, SBI_HART_EXT_SSCOFPMF))
> + pmu_update_inhibit_flags(flags, &mhpmevent_val);
pmu_update_inhibit_flags() is called from other places as well.
Looks like this patch needs to be rebased on the latest OpenSBI.
> + if (pmu_dev && pmu_dev->hw_counter_filter_mode)
> + pmu_dev->hw_counter_filter_mode(flags, ctr_idx);
>
> #if __riscv_xlen == 32
> csr_write_num(CSR_MHPMEVENT3 + ctr_idx - 3, mhpmevent_val & 0xFFFFFFFF);
> --
> 2.34.1
>
Regards,
Anup
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 03/11] platform: include: andes45: Add PMU related CSR defines
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
2023-10-19 11:37 ` [PATCH v2 01/11] sbi: sbi_pmu: Improve sbi_pmu_init() error handling Yu Chien Peter Lin
2023-10-19 11:37 ` [PATCH v2 02/11] sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 6:39 ` Anup Patel
2023-10-19 11:37 ` [PATCH v2 04/11] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
` (8 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
This patch adds CSR for Andes PMU extension.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- Rename andes_pmu() -> has_andes_pmu()
---
platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
index f570994..ce31617 100644
--- a/platform/generic/include/andes/andes45.h
+++ b/platform/generic/include/andes/andes45.h
@@ -12,6 +12,17 @@
#define CSR_MDCM_CFG 0xfc1
#define CSR_MMSC_CFG 0xfc2
+/* Machine Trap Related Registers */
+#define CSR_MSLIDELEG 0x7d5
+
+/* Counter Related Registers */
+#define CSR_MCOUNTERWEN 0x7ce
+#define CSR_MCOUNTERINTEN 0x7cf
+#define CSR_MCOUNTERMASK_M 0x7d1
+#define CSR_MCOUNTERMASK_S 0x7d2
+#define CSR_MCOUNTERMASK_U 0x7d3
+#define CSR_MCOUNTEROVF 0x7d4
+
#define MICM_CFG_ISZ_OFFSET 6
#define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
@@ -26,4 +37,19 @@
#define MCACHE_CTL_CCTL_SUEN_OFFSET 8
#define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
+/* Performance monitor */
+#define MMSC_CFG_PMNDS_MASK (1 << 15)
+#define MIP_PMOVI (1 << 18)
+
+#ifndef __ASSEMBLER__
+
+#define has_andes_pmu() \
+({ \
+ (((csr_read(CSR_MMSC_CFG) & \
+ MMSC_CFG_PMNDS_MASK) \
+ && misa_extension('S')) ? true : false); \
+})
+
+#endif /* __ASSEMBLER__ */
+
#endif /* _RISCV_ANDES45_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 03/11] platform: include: andes45: Add PMU related CSR defines
2023-10-19 11:37 ` [PATCH v2 03/11] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
@ 2023-11-16 6:39 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:39 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:10?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch adds CSR for Andes PMU extension.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> Changes v1 -> v2:
> - Rename andes_pmu() -> has_andes_pmu()
> ---
> platform/generic/include/andes/andes45.h | 26 ++++++++++++++++++++++++
> 1 file changed, 26 insertions(+)
>
> diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
> index f570994..ce31617 100644
> --- a/platform/generic/include/andes/andes45.h
> +++ b/platform/generic/include/andes/andes45.h
> @@ -12,6 +12,17 @@
> #define CSR_MDCM_CFG 0xfc1
> #define CSR_MMSC_CFG 0xfc2
>
> +/* Machine Trap Related Registers */
> +#define CSR_MSLIDELEG 0x7d5
> +
> +/* Counter Related Registers */
> +#define CSR_MCOUNTERWEN 0x7ce
> +#define CSR_MCOUNTERINTEN 0x7cf
> +#define CSR_MCOUNTERMASK_M 0x7d1
> +#define CSR_MCOUNTERMASK_S 0x7d2
> +#define CSR_MCOUNTERMASK_U 0x7d3
> +#define CSR_MCOUNTEROVF 0x7d4
> +
> #define MICM_CFG_ISZ_OFFSET 6
> #define MICM_CFG_ISZ_MASK (0x7 << MICM_CFG_ISZ_OFFSET)
>
> @@ -26,4 +37,19 @@
> #define MCACHE_CTL_CCTL_SUEN_OFFSET 8
> #define MCACHE_CTL_CCTL_SUEN_MASK (0x1 << MCACHE_CTL_CCTL_SUEN_OFFSET)
>
> +/* Performance monitor */
> +#define MMSC_CFG_PMNDS_MASK (1 << 15)
> +#define MIP_PMOVI (1 << 18)
> +
> +#ifndef __ASSEMBLER__
> +
> +#define has_andes_pmu() \
> +({ \
> + (((csr_read(CSR_MMSC_CFG) & \
> + MMSC_CFG_PMNDS_MASK) \
> + && misa_extension('S')) ? true : false); \
> +})
> +
> +#endif /* __ASSEMBLER__ */
> +
> #endif /* _RISCV_ANDES45_H */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 04/11] platform: andes: Add Andes custom PMU support
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
` (2 preceding siblings ...)
2023-10-19 11:37 ` [PATCH v2 03/11] platform: include: andes45: Add PMU related CSR defines Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 6:41 ` Anup Patel
2023-10-19 11:37 ` [PATCH v2 05/11] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
` (7 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
Before the ratification of Sscofpmf, the Andes PMU extension
was designed to support the sampling and filtering with hardware
performance counters, it works with the current SBI PMU extension
and Linux SBI PMU driver.
This patch implements the PMU device callbacks that update the
corresponding bits on custom CSRs.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- Fix mode filtering in andes_hw_counter_filter_mode()
- Return early if pmu is not supported in andes_pmu_init() (suggested by Prabhakar)
- Don't grant write permissions via CSR_MCOUNTERWEN as not needed
---
platform/generic/andes/Kconfig | 4 ++
platform/generic/andes/andes_pmu.c | 81 ++++++++++++++++++++++
platform/generic/andes/objects.mk | 1 +
platform/generic/include/andes/andes_pmu.h | 8 +++
4 files changed, 94 insertions(+)
create mode 100644 platform/generic/andes/andes_pmu.c
create mode 100644 platform/generic/include/andes/andes_pmu.h
diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
index a91fb9c..555e4fe 100644
--- a/platform/generic/andes/Kconfig
+++ b/platform/generic/andes/Kconfig
@@ -7,3 +7,7 @@ config ANDES45_PMA
config ANDES_SBI
bool "Andes SBI support"
default n
+
+config ANDES_PMU
+ bool "Andes custom PMU extension support"
+ default n
diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
new file mode 100644
index 0000000..0f6ecc0
--- /dev/null
+++ b/platform/generic/andes/andes_pmu.c
@@ -0,0 +1,81 @@
+// SPDX-License-Identifier: BSD-2-Clause
+/*
+ * Copyright (C) 2023 Andes Technology Corporation
+ */
+#include <andes/andes45.h>
+#include <andes/andes_pmu.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_bitops.h>
+#include <sbi/sbi_error.h>
+#include <sbi/sbi_hart.h>
+#include <sbi/sbi_pmu.h>
+#include <sbi/sbi_scratch.h>
+
+static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
+{
+ unsigned long mip_val;
+
+ if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
+ return;
+
+ mip_val = csr_read(CSR_MIP);
+ if (!(mip_val & MIP_PMOVI))
+ csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
+
+ csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
+{
+ csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
+}
+
+static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
+{
+ if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
+ csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
+ else
+ csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
+
+ if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
+ csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
+ else
+ csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
+}
+
+static struct sbi_pmu_device andes_pmu = {
+ .name = "andes_pmu",
+ .hw_counter_enable_irq = andes_hw_counter_enable_irq,
+ .hw_counter_disable_irq = andes_hw_counter_disable_irq,
+ /*
+ * We set delegation of supervisor local interrupts via
+ * 18th bit on mslideleg instead of mideleg, so leave
+ * hw_counter_irq_bit() callback unimplemented.
+ */
+ .hw_counter_irq_bit = NULL,
+ .hw_counter_filter_mode = andes_hw_counter_filter_mode
+};
+
+int andes_pmu_init(void)
+{
+ if (!has_andes_pmu())
+ return SBI_ENOTSUPP;
+
+ /*
+ * It is not reasonable for an Andes CPU to support
+ * both Andes PMU and standard Sscofpmf, as they
+ * serve the same purpose.
+ */
+ if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
+ SBI_HART_EXT_SSCOFPMF))
+ sbi_hart_hang();
+
+ /* Inhibit HPM counter in M-mode */
+ csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
+ /* Delegate S-mode local interrupt to S-mode */
+ csr_write(CSR_MSLIDELEG, MIP_PMOVI);
+
+ sbi_pmu_set_device(&andes_pmu);
+
+ return 0;
+}
diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
index e8f86ea..6a8c66c 100644
--- a/platform/generic/andes/objects.mk
+++ b/platform/generic/andes/objects.mk
@@ -7,3 +7,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
+platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
diff --git a/platform/generic/include/andes/andes_pmu.h b/platform/generic/include/andes/andes_pmu.h
new file mode 100644
index 0000000..70b3a12
--- /dev/null
+++ b/platform/generic/include/andes/andes_pmu.h
@@ -0,0 +1,8 @@
+// SPDX-License-Identifier: BSD-2-Clause
+
+#ifndef _RISCV_ANDES_PMU_H
+#define _RISCV_ANDES_PMU_H
+
+int andes_pmu_init(void);
+
+#endif /* _RISCV_ANDES_PMU_H */
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 04/11] platform: andes: Add Andes custom PMU support
2023-10-19 11:37 ` [PATCH v2 04/11] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
@ 2023-11-16 6:41 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:41 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:10?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Before the ratification of Sscofpmf, the Andes PMU extension
> was designed to support the sampling and filtering with hardware
> performance counters, it works with the current SBI PMU extension
> and Linux SBI PMU driver.
>
> This patch implements the PMU device callbacks that update the
> corresponding bits on custom CSRs.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> Changes v1 -> v2:
> - Fix mode filtering in andes_hw_counter_filter_mode()
> - Return early if pmu is not supported in andes_pmu_init() (suggested by Prabhakar)
> - Don't grant write permissions via CSR_MCOUNTERWEN as not needed
> ---
> platform/generic/andes/Kconfig | 4 ++
> platform/generic/andes/andes_pmu.c | 81 ++++++++++++++++++++++
> platform/generic/andes/objects.mk | 1 +
> platform/generic/include/andes/andes_pmu.h | 8 +++
> 4 files changed, 94 insertions(+)
> create mode 100644 platform/generic/andes/andes_pmu.c
> create mode 100644 platform/generic/include/andes/andes_pmu.h
>
> diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> index a91fb9c..555e4fe 100644
> --- a/platform/generic/andes/Kconfig
> +++ b/platform/generic/andes/Kconfig
> @@ -7,3 +7,7 @@ config ANDES45_PMA
> config ANDES_SBI
> bool "Andes SBI support"
> default n
> +
> +config ANDES_PMU
> + bool "Andes custom PMU extension support"
> + default n
> diff --git a/platform/generic/andes/andes_pmu.c b/platform/generic/andes/andes_pmu.c
> new file mode 100644
> index 0000000..0f6ecc0
> --- /dev/null
> +++ b/platform/generic/andes/andes_pmu.c
> @@ -0,0 +1,81 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +/*
> + * Copyright (C) 2023 Andes Technology Corporation
> + */
> +#include <andes/andes45.h>
> +#include <andes/andes_pmu.h>
> +#include <sbi/riscv_asm.h>
> +#include <sbi/sbi_bitops.h>
> +#include <sbi/sbi_error.h>
> +#include <sbi/sbi_hart.h>
> +#include <sbi/sbi_pmu.h>
> +#include <sbi/sbi_scratch.h>
> +
> +static void andes_hw_counter_enable_irq(uint32_t ctr_idx)
> +{
> + unsigned long mip_val;
> +
> + if (ctr_idx >= SBI_PMU_HW_CTR_MAX)
> + return;
> +
> + mip_val = csr_read(CSR_MIP);
> + if (!(mip_val & MIP_PMOVI))
> + csr_clear(CSR_MCOUNTEROVF, BIT(ctr_idx));
> +
> + csr_set(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> +}
> +
> +static void andes_hw_counter_disable_irq(uint32_t ctr_idx)
> +{
> + csr_clear(CSR_MCOUNTERINTEN, BIT(ctr_idx));
> +}
> +
> +static void andes_hw_counter_filter_mode(unsigned long flags, int ctr_idx)
> +{
> + if (flags & SBI_PMU_CFG_FLAG_SET_UINH)
> + csr_set(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> + else
> + csr_clear(CSR_MCOUNTERMASK_U, BIT(ctr_idx));
> +
> + if (flags & SBI_PMU_CFG_FLAG_SET_SINH)
> + csr_set(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> + else
> + csr_clear(CSR_MCOUNTERMASK_S, BIT(ctr_idx));
> +}
> +
> +static struct sbi_pmu_device andes_pmu = {
> + .name = "andes_pmu",
> + .hw_counter_enable_irq = andes_hw_counter_enable_irq,
> + .hw_counter_disable_irq = andes_hw_counter_disable_irq,
> + /*
> + * We set delegation of supervisor local interrupts via
> + * 18th bit on mslideleg instead of mideleg, so leave
> + * hw_counter_irq_bit() callback unimplemented.
> + */
> + .hw_counter_irq_bit = NULL,
> + .hw_counter_filter_mode = andes_hw_counter_filter_mode
> +};
> +
> +int andes_pmu_init(void)
> +{
> + if (!has_andes_pmu())
> + return SBI_ENOTSUPP;
> +
> + /*
> + * It is not reasonable for an Andes CPU to support
> + * both Andes PMU and standard Sscofpmf, as they
> + * serve the same purpose.
> + */
> + if (sbi_hart_has_extension(sbi_scratch_thishart_ptr(),
> + SBI_HART_EXT_SSCOFPMF))
> + sbi_hart_hang();
> +
> + /* Inhibit HPM counter in M-mode */
> + csr_write(CSR_MCOUNTERMASK_M, 0xfffffffd);
> + /* Delegate S-mode local interrupt to S-mode */
> + csr_write(CSR_MSLIDELEG, MIP_PMOVI);
> +
> + sbi_pmu_set_device(&andes_pmu);
> +
> + return 0;
> +}
> diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
> index e8f86ea..6a8c66c 100644
> --- a/platform/generic/andes/objects.mk
> +++ b/platform/generic/andes/objects.mk
> @@ -7,3 +7,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
>
> platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
> platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
> +platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
> diff --git a/platform/generic/include/andes/andes_pmu.h b/platform/generic/include/andes/andes_pmu.h
> new file mode 100644
> index 0000000..70b3a12
> --- /dev/null
> +++ b/platform/generic/include/andes/andes_pmu.h
> @@ -0,0 +1,8 @@
> +// SPDX-License-Identifier: BSD-2-Clause
> +
> +#ifndef _RISCV_ANDES_PMU_H
> +#define _RISCV_ANDES_PMU_H
> +
> +int andes_pmu_init(void);
> +
> +#endif /* _RISCV_ANDES_PMU_H */
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 05/11] platform: andes: Enable Andes PMU for AE350
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
` (3 preceding siblings ...)
2023-10-19 11:37 ` [PATCH v2 04/11] platform: andes: Add Andes custom PMU support Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 6:45 ` Anup Patel
2023-10-19 11:37 ` [PATCH v2 06/11] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
` (6 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
Enable Andes PMU extension support for AE350 platforms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- Implement ae350_extensions_init()
---
platform/generic/Kconfig | 1 +
platform/generic/andes/ae350.c | 13 +++++++++++++
2 files changed, 14 insertions(+)
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index e7bd94e..9b2f9c7 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
config PLATFORM_ANDES_AE350
bool "Andes AE350 support"
select SYS_ATCSMU
+ select ANDES_PMU
default n
config PLATFORM_RENESAS_RZFIVE
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
index 80eca05..c3f280d 100644
--- a/platform/generic/andes/ae350.c
+++ b/platform/generic/andes/ae350.c
@@ -8,6 +8,7 @@
*/
#include <platform_override.h>
+#include <andes/andes_pmu.h>
#include <sbi_utils/fdt/fdt_helper.h>
#include <sbi_utils/fdt/fdt_fixup.h>
#include <sbi_utils/sys/atcsmu.h>
@@ -110,6 +111,17 @@ static int ae350_final_init(bool cold_boot, const struct fdt_match *match)
return 0;
}
+static int ae350_extensions_init(const struct fdt_match *match,
+ struct sbi_hart_features *hfeatures)
+{
+ int rc;
+ rc = andes_pmu_init();
+ if (rc && rc != SBI_ENOTSUPP)
+ return rc;
+
+ return 0;
+}
+
static const struct fdt_match andes_ae350_match[] = {
{ .compatible = "andestech,ae350" },
{ },
@@ -118,4 +130,5 @@ static const struct fdt_match andes_ae350_match[] = {
const struct platform_override andes_ae350 = {
.match_table = andes_ae350_match,
.final_init = ae350_final_init,
+ .extensions_init = ae350_extensions_init,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 05/11] platform: andes: Enable Andes PMU for AE350
2023-10-19 11:37 ` [PATCH v2 05/11] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
@ 2023-11-16 6:45 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:45 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:10?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Enable Andes PMU extension support for AE350 platforms.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - Implement ae350_extensions_init()
> ---
> platform/generic/Kconfig | 1 +
> platform/generic/andes/ae350.c | 13 +++++++++++++
> 2 files changed, 14 insertions(+)
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index e7bd94e..9b2f9c7 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
> config PLATFORM_ANDES_AE350
> bool "Andes AE350 support"
> select SYS_ATCSMU
> + select ANDES_PMU
> default n
>
> config PLATFORM_RENESAS_RZFIVE
> diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
> index 80eca05..c3f280d 100644
> --- a/platform/generic/andes/ae350.c
> +++ b/platform/generic/andes/ae350.c
> @@ -8,6 +8,7 @@
> */
>
> #include <platform_override.h>
> +#include <andes/andes_pmu.h>
> #include <sbi_utils/fdt/fdt_helper.h>
> #include <sbi_utils/fdt/fdt_fixup.h>
> #include <sbi_utils/sys/atcsmu.h>
> @@ -110,6 +111,17 @@ static int ae350_final_init(bool cold_boot, const struct fdt_match *match)
> return 0;
> }
>
> +static int ae350_extensions_init(const struct fdt_match *match,
> + struct sbi_hart_features *hfeatures)
> +{
> + int rc;
> + rc = andes_pmu_init();
> + if (rc && rc != SBI_ENOTSUPP)
> + return rc;
> +
> + return 0;
> +}
> +
> static const struct fdt_match andes_ae350_match[] = {
> { .compatible = "andestech,ae350" },
> { },
> @@ -118,4 +130,5 @@ static const struct fdt_match andes_ae350_match[] = {
> const struct platform_override andes_ae350 = {
> .match_table = andes_ae350_match,
> .final_init = ae350_final_init,
> + .extensions_init = ae350_extensions_init,
This is not the right way.
Add a new callback pmu_init() in "struct platform_override" and
implement that here.
The generic_pmu_init() will call pmu_init() in "struct platform_override"
if it is available otherwise it will call fdt_pmu_setup().
> };
> --
> 2.34.1
>
Regards,
Anup
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 06/11] platform: rzfive: Enable Andes PMU for RZ/Five
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
` (4 preceding siblings ...)
2023-10-19 11:37 ` [PATCH v2 05/11] platform: andes: Enable Andes PMU for AE350 Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 6:45 ` Anup Patel
2023-10-19 11:37 ` [PATCH v2 07/11] lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function Yu Chien Peter Lin
` (5 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
Enable Andes PMU extension support for RZ/Five.
This patch also staticize renesas_rzfive_early_init() as
it is not used outside of this unit.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- Implement renesas_rzfive_extensions_init()
- staticize renesas_rzfive_early_init()
---
platform/generic/Kconfig | 1 +
platform/generic/renesas/rzfive/rzfive.c | 16 +++++++++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index 9b2f9c7..d6dafef 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -38,6 +38,7 @@ config PLATFORM_RENESAS_RZFIVE
bool "Renesas RZ/Five support"
select ANDES45_PMA
select ANDES_SBI
+ select ANDES_PMU
default n
config PLATFORM_SIFIVE_FU540
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
index a69797b..2f772c8 100644
--- a/platform/generic/renesas/rzfive/rzfive.c
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -5,9 +5,11 @@
*/
#include <andes/andes45_pma.h>
+#include <andes/andes_pmu.h>
#include <andes/andes_sbi.h>
#include <platform_override.h>
#include <sbi/sbi_domain.h>
+#include <sbi/sbi_error.h>
#include <sbi_utils/fdt/fdt_helper.h>
static const struct andes45_pma_region renesas_rzfive_pma_regions[] = {
@@ -29,7 +31,7 @@ static int renesas_rzfive_final_init(bool cold_boot, const struct fdt_match *mat
array_size(renesas_rzfive_pma_regions));
}
-int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
+static int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
{
/*
* Renesas RZ/Five RISC-V SoC has Instruction local memory and
@@ -47,6 +49,17 @@ int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
SBI_DOMAIN_MEMREGION_M_RWX);
}
+static int renesas_rzfive_extensions_init(const struct fdt_match *match,
+ struct sbi_hart_features *hfeatures)
+{
+ int rc;
+ rc = andes_pmu_init();
+ if (rc && rc != SBI_ENOTSUPP)
+ return rc;
+
+ return 0;
+}
+
static const struct fdt_match renesas_rzfive_match[] = {
{ .compatible = "renesas,r9a07g043f01" },
{ /* sentinel */ }
@@ -57,4 +70,5 @@ const struct platform_override renesas_rzfive = {
.early_init = renesas_rzfive_early_init,
.final_init = renesas_rzfive_final_init,
.vendor_ext_provider = andes_sbi_vendor_ext_provider,
+ .extensions_init = renesas_rzfive_extensions_init,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 06/11] platform: rzfive: Enable Andes PMU for RZ/Five
2023-10-19 11:37 ` [PATCH v2 06/11] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
@ 2023-11-16 6:45 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:45 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:10?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Enable Andes PMU extension support for RZ/Five.
> This patch also staticize renesas_rzfive_early_init() as
> it is not used outside of this unit.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
> ---
> Changes v1 -> v2:
> - Implement renesas_rzfive_extensions_init()
> - staticize renesas_rzfive_early_init()
> ---
> platform/generic/Kconfig | 1 +
> platform/generic/renesas/rzfive/rzfive.c | 16 +++++++++++++++-
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index 9b2f9c7..d6dafef 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -38,6 +38,7 @@ config PLATFORM_RENESAS_RZFIVE
> bool "Renesas RZ/Five support"
> select ANDES45_PMA
> select ANDES_SBI
> + select ANDES_PMU
> default n
>
> config PLATFORM_SIFIVE_FU540
> diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
> index a69797b..2f772c8 100644
> --- a/platform/generic/renesas/rzfive/rzfive.c
> +++ b/platform/generic/renesas/rzfive/rzfive.c
> @@ -5,9 +5,11 @@
> */
>
> #include <andes/andes45_pma.h>
> +#include <andes/andes_pmu.h>
> #include <andes/andes_sbi.h>
> #include <platform_override.h>
> #include <sbi/sbi_domain.h>
> +#include <sbi/sbi_error.h>
> #include <sbi_utils/fdt/fdt_helper.h>
>
> static const struct andes45_pma_region renesas_rzfive_pma_regions[] = {
> @@ -29,7 +31,7 @@ static int renesas_rzfive_final_init(bool cold_boot, const struct fdt_match *mat
> array_size(renesas_rzfive_pma_regions));
> }
>
> -int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
> +static int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
> {
> /*
> * Renesas RZ/Five RISC-V SoC has Instruction local memory and
> @@ -47,6 +49,17 @@ int renesas_rzfive_early_init(bool cold_boot, const struct fdt_match *match)
> SBI_DOMAIN_MEMREGION_M_RWX);
> }
>
> +static int renesas_rzfive_extensions_init(const struct fdt_match *match,
> + struct sbi_hart_features *hfeatures)
> +{
> + int rc;
> + rc = andes_pmu_init();
> + if (rc && rc != SBI_ENOTSUPP)
> + return rc;
> +
> + return 0;
> +}
> +
> static const struct fdt_match renesas_rzfive_match[] = {
> { .compatible = "renesas,r9a07g043f01" },
> { /* sentinel */ }
> @@ -57,4 +70,5 @@ const struct platform_override renesas_rzfive = {
> .early_init = renesas_rzfive_early_init,
> .final_init = renesas_rzfive_final_init,
> .vendor_ext_provider = andes_sbi_vendor_ext_provider,
> + .extensions_init = renesas_rzfive_extensions_init,
Same comment as PATCH5.
> };
> --
> 2.34.1
>
Regards,
Anup
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 07/11] lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
` (5 preceding siblings ...)
2023-10-19 11:37 ` [PATCH v2 06/11] platform: rzfive: Enable Andes PMU for RZ/Five Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-10-21 12:25 ` [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override Inochi Amaoto
2023-11-16 6:59 ` [PATCH v2 07/11] lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function Anup Patel
2023-10-19 11:37 ` [PATCH v2 08/11] lib: utils: fdt_fixup: Allow preserving PMU properties Yu Chien Peter Lin
` (4 subsequent siblings)
11 siblings, 2 replies; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
Add fdt_add_pmu_mappings() that creates entries of riscv,*event-to-mhpm*
property from arrays right before fdt_pmu_setup() populating the mapping
tables (i.e. hw_event_map[] and fdt_pmu_evt_select[]).
The helper function will skip the creation of those properties if a
"/pmu" node with "riscv,pmu" compatible string is provided.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
---
include/sbi_utils/fdt/fdt_fixup.h | 48 ++++++++++
lib/utils/fdt/fdt_fixup.c | 95 ++++++++++++++++++++
platform/generic/include/platform_override.h | 1 +
platform/generic/platform.c | 10 ++-
4 files changed, 153 insertions(+), 1 deletion(-)
diff --git a/include/sbi_utils/fdt/fdt_fixup.h b/include/sbi_utils/fdt/fdt_fixup.h
index ecd55a7..9b72df8 100644
--- a/include/sbi_utils/fdt/fdt_fixup.h
+++ b/include/sbi_utils/fdt/fdt_fixup.h
@@ -19,6 +19,54 @@ struct sbi_cpu_idle_state {
uint32_t wakeup_latency_us;
};
+struct sbi_pmu_event_select_map {
+ /**
+ * The description of an entry in
+ * riscv,event-to-mhpmevent property
+ */
+ uint32_t eidx;
+ uint64_t select;
+};
+
+struct sbi_pmu_event_counter_map {
+ /**
+ * The description of an entry in
+ * riscv,event-to-mhpmcounters property
+ */
+ uint32_t eidx_start;
+ uint32_t eidx_end;
+ uint32_t ctr_map;
+};
+
+struct sbi_pmu_raw_event_counter_map {
+ /**
+ * The description of an entry in
+ * riscv,raw-event-to-mhpmcounters property
+ */
+ uint64_t select;
+ uint64_t select_mask;
+ uint32_t ctr_map;
+};
+
+/**
+ * Add PMU properties in the DT
+ *
+ * Add information about event to selector/counter mappings to the
+ * devicetree.
+ *
+ * @param fdt: device tree blob
+ * @param selects: array of event index to selector value mapping
+ * descriptions, ending with empty element
+ * @param counters: array of event indexes to counters mapping
+ * descriptions, ending with empty element
+ * @param rcounters: array of raw events to counters mapping
+ * descriptions, ending with empty element
+ * @return zero on success and -ve on failure
+ */
+int fdt_add_pmu_mappings(void *fdt, const struct sbi_pmu_event_select_map *selects,
+ const struct sbi_pmu_event_counter_map *counters,
+ const struct sbi_pmu_raw_event_counter_map *rcounters);
+
/**
* Add CPU idle states to cpu nodes in the DT
*
diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
index e213ded..67e2e2e 100644
--- a/lib/utils/fdt/fdt_fixup.c
+++ b/lib/utils/fdt/fdt_fixup.c
@@ -20,6 +20,101 @@
#include <sbi_utils/fdt/fdt_pmu.h>
#include <sbi_utils/fdt/fdt_helper.h>
+int fdt_add_pmu_mappings(void *fdt, const struct sbi_pmu_event_select_map *selects,
+ const struct sbi_pmu_event_counter_map *counters,
+ const struct sbi_pmu_raw_event_counter_map *rcounters)
+{
+ int i, err, pmu_noff, root_noff;
+ const char *comp;
+ fdt32_t evt_to_mhpmevent[3];
+ fdt32_t evt_to_mhpmcounters[3];
+ fdt32_t raw_evt_to_mhpmcounters[5];
+
+ /* Try to locate pmu node */
+ pmu_noff = fdt_path_offset(fdt, "/pmu");
+
+ if (pmu_noff > 0) {
+ /*
+ * If compatible string is "riscv,pmu",
+ * we assume a valid pmu node has been
+ * provided.
+ */
+ comp = fdt_getprop(fdt, pmu_noff, "compatible", NULL);
+ if (comp && !strcmp(comp, "riscv,pmu"))
+ return 0;
+ else
+ return -FDT_ERR_BADVALUE;
+ }
+
+ if (pmu_noff < 0 && pmu_noff != -FDT_ERR_NOTFOUND)
+ return pmu_noff;
+
+ /*
+ * If "riscv,event-to-mhpmevent" is present, "riscv,event-to-mhpmcounters"
+ * must be provided as well, but not vice versa (OpenSBI will direct mapping
+ * event_idx as selector value).
+ */
+ if (selects && !counters) {
+ sbi_printf("%s: ERR: riscv,event-to-mhpmcounters is mandatory if"
+ " riscv,event-to-mhpmevent is present.", __func__);
+ return SBI_EINVAL;
+ }
+
+ /*
+ * Create pmu node based on given @selects, @counters
+ * and @rcounters.
+ */
+ root_noff = fdt_path_offset(fdt, "/");
+ pmu_noff = fdt_add_subnode(fdt, root_noff, "pmu");
+ if (pmu_noff < 0)
+ return pmu_noff;
+
+ err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 1024);
+ if (err < 0)
+ return err;
+
+ err = fdt_setprop_string(fdt, pmu_noff, "compatible", "riscv,pmu");
+ if (err)
+ return err;
+
+ /* Add riscv,event-to-mhpmevent */
+ for (i = 0; selects && selects[i].eidx; i++) {
+ evt_to_mhpmevent[0] = cpu_to_fdt32(selects[i].eidx);
+ evt_to_mhpmevent[1] = cpu_to_fdt32(selects[i].select >> 32);
+ evt_to_mhpmevent[2] = cpu_to_fdt32(selects[i].select & ~0UL);
+ err = fdt_appendprop(fdt, pmu_noff, "riscv,event-to-mhpmevent",
+ evt_to_mhpmevent, 3 * sizeof(fdt32_t));
+ if (err)
+ return err;
+ }
+
+ /* Add riscv,event-to-mhpmcounters */
+ for (i = 0; counters && counters[i].eidx_start; i++) {
+ evt_to_mhpmcounters[0] = cpu_to_fdt32(counters[i].eidx_start);
+ evt_to_mhpmcounters[1] = cpu_to_fdt32(counters[i].eidx_end);
+ evt_to_mhpmcounters[2] = cpu_to_fdt32(counters[i].ctr_map);
+ err = fdt_appendprop(fdt, pmu_noff, "riscv,event-to-mhpmcounters",
+ evt_to_mhpmcounters, 3 * sizeof(fdt32_t));
+ if (err)
+ return err;
+ }
+
+ /* Add riscv,raw-event-to-mhpmcounters */
+ for (i = 0; rcounters && rcounters[i].select; i++) {
+ raw_evt_to_mhpmcounters[0] = cpu_to_fdt32(rcounters[i].select >> 32);
+ raw_evt_to_mhpmcounters[1] = cpu_to_fdt32(rcounters[i].select & ~0UL);
+ raw_evt_to_mhpmcounters[2] = cpu_to_fdt32(rcounters[i].select_mask >> 32);
+ raw_evt_to_mhpmcounters[3] = cpu_to_fdt32(rcounters[i].select_mask & ~0UL);
+ raw_evt_to_mhpmcounters[4] = cpu_to_fdt32(rcounters[i].ctr_map);
+ err = fdt_appendprop(fdt, pmu_noff, "riscv,raw-event-to-mhpmcounters",
+ raw_evt_to_mhpmcounters, 5 * sizeof(fdt32_t));
+ if (err)
+ return err;
+ }
+
+ return 0;
+}
+
int fdt_add_cpu_idle_states(void *fdt, const struct sbi_cpu_idle_state *state)
{
int cpu_node, cpus_node, err, idle_states_node;
diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
index bf4b112..bd34d2a 100644
--- a/platform/generic/include/platform_override.h
+++ b/platform/generic/include/platform_override.h
@@ -19,6 +19,7 @@ struct platform_override {
u64 (*features)(const struct fdt_match *match);
u64 (*tlbr_flush_limit)(const struct fdt_match *match);
u32 (*tlb_num_entries)(const struct fdt_match *match);
+ int (*fdt_add_pmu_mappings)(void *fdt, const struct fdt_match *match);
bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
int (*early_init)(bool cold_boot, const struct fdt_match *match);
int (*final_init)(bool cold_boot, const struct fdt_match *match);
diff --git a/platform/generic/platform.c b/platform/generic/platform.c
index cb9270d..a48a8b7 100644
--- a/platform/generic/platform.c
+++ b/platform/generic/platform.c
@@ -265,9 +265,17 @@ static u32 generic_tlb_num_entries(void)
static int generic_pmu_init(void)
{
+ void *fdt = fdt_get_address();
int rc;
- rc = fdt_pmu_setup(fdt_get_address());
+ if (generic_plat && generic_plat->fdt_add_pmu_mappings) {
+ rc = generic_plat->fdt_add_pmu_mappings(fdt,
+ generic_plat_match);
+ if (rc)
+ return rc;
+ }
+
+ rc = fdt_pmu_setup(fdt);
if (rc && rc != SBI_ENOENT)
return rc;
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override
2023-10-19 11:37 ` [PATCH v2 07/11] lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function Yu Chien Peter Lin
@ 2023-10-21 12:25 ` Inochi Amaoto
2023-10-22 6:50 ` Yu-Chien Peter Lin
2023-11-16 6:59 ` [PATCH v2 07/11] lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function Anup Patel
1 sibling, 1 reply; 27+ messages in thread
From: Inochi Amaoto @ 2023-10-21 12:25 UTC (permalink / raw)
To: opensbi
>Implement the andes_fdt_add_pmu_mappings() callback, which creates PMU
>node properties that will later be populated with mapping tables.
>
>Currently we only support 45-series event mappings.
>
>Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
>---
>Changes v1 -> v2:
> - New patch
>---
> include/sbi/sbi_ecall_interface.h | 5 +
> platform/generic/Kconfig | 2 +
> platform/generic/andes/Kconfig | 7 +
> platform/generic/andes/ae350.c | 2 +
> platform/generic/andes/andes_hpm.c | 381 +++++++++++++++++++++
> platform/generic/andes/objects.mk | 1 +
> platform/generic/include/andes/andes_hpm.h | 83 +++++
> platform/generic/renesas/rzfive/rzfive.c | 2 +
> 8 files changed, 483 insertions(+)
> create mode 100644 platform/generic/andes/andes_hpm.c
> create mode 100644 platform/generic/include/andes/andes_hpm.h
>
>diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
>index 1fe469e..89187e7 100644
>--- a/include/sbi/sbi_ecall_interface.h
>+++ b/include/sbi/sbi_ecall_interface.h
>@@ -155,6 +155,11 @@ enum sbi_pmu_hw_cache_op_result_id {
> SBI_PMU_HW_CACHE_RESULT_MAX,
> };
>
>+#define SBI_PMU_HW_CACHE_EVENT_IDX(id, op, res) \
>+ (SBI_PMU_EVENT_TYPE_HW_CACHE << SBI_PMU_EVENT_IDX_TYPE_OFFSET | \
>+ SBI_PMU_HW_CACHE_##id << 3 | SBI_PMU_HW_CACHE_OP_##op << 1 | \
>+ SBI_PMU_HW_CACHE_RESULT_##res)
>+
> /**
> * Special "firmware" events provided by the OpenSBI, even if the hardware
> * does not support performance events. These events are encoded as a raw
>diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
>index d6dafef..fbcd870 100644
>--- a/platform/generic/Kconfig
>+++ b/platform/generic/Kconfig
>@@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
> config PLATFORM_ANDES_AE350
> bool "Andes AE350 support"
> select SYS_ATCSMU
>+ select ANDES_HPM
> select ANDES_PMU
> default n
>
>@@ -38,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
> bool "Renesas RZ/Five support"
> select ANDES45_PMA
> select ANDES_SBI
>+ select ANDES_HPM
> select ANDES_PMU
> default n
>
>diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
>index 555e4fe..8af2704 100644
>--- a/platform/generic/andes/Kconfig
>+++ b/platform/generic/andes/Kconfig
>@@ -8,6 +8,13 @@ config ANDES_SBI
> bool "Andes SBI support"
> default n
>
>+config ANDES_HPM
>+ bool "Andes HPM support"
>+ default n
>+ help
>+ This provides Andes platform override for creating
>+ event to counter mappings in pmu node.
>+
> config ANDES_PMU
> bool "Andes custom PMU extension support"
> default n
>diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
>index 80cd294..28c187e 100644
>--- a/platform/generic/andes/ae350.c
>+++ b/platform/generic/andes/ae350.c
>@@ -19,6 +19,7 @@
> #include <sbi/sbi_ipi.h>
> #include <sbi/sbi_init.h>
> #include <andes/andes45.h>
>+#include <andes/andes_hpm.h>
>
> static struct smu_data smu = { 0 };
> extern void __ae350_enable_coherency_warmboot(void);
>@@ -128,5 +129,6 @@ static const struct fdt_match andes_ae350_match[] = {
> const struct platform_override andes_ae350 = {
> .match_table = andes_ae350_match,
> .final_init = ae350_final_init,
>+ .fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> .extensions_init = ae350_extensions_init,
> };
>diff --git a/platform/generic/andes/andes_hpm.c b/platform/generic/andes/andes_hpm.c
>new file mode 100644
>index 0000000..f9e6d2e
>--- /dev/null
>+++ b/platform/generic/andes/andes_hpm.c
>@@ -0,0 +1,381 @@
>+/*
>+ * SPDX-License-Identifier: BSD-2-Clause
>+ *
>+ * Copyright (c) 2023 Andes Technology Corporation
>+ */
>+
>+#include <andes/andes45.h>
>+#include <andes/andes_hpm.h>
>+#include <sbi/riscv_asm.h>
>+#include <sbi/sbi_ecall_interface.h>
>+#include <sbi_utils/fdt/fdt_fixup.h>
>+
>+static const struct sbi_pmu_event_select_map andes45_hw_evt_selects[] = {
>+ /* Hardware general events (Type #0) */
>+ {
>+ /* perf: cycles (eidx: 0x1) */
>+ .eidx = SBI_PMU_HW_CPU_CYCLES,
>+ .select = ANDES_CYCLES
>+ },
>+ {
>+ /* perf: instructions (eidx: 0x2) */
>+ .eidx = SBI_PMU_HW_INSTRUCTIONS,
>+ .select = ANDES_INSTRET
>+ },
>+ {
>+ /* perf: cache-references (eidx: 0x3) */
>+ .eidx = SBI_PMU_HW_CACHE_REFERENCES,
>+ .select = ANDES_DCACHE_ACCESS
>+ },
>+ {
>+ /* perf: cache-misses (eidx: 0x4) */
>+ .eidx = SBI_PMU_HW_CACHE_MISSES,
>+ .select = ANDES_DCACHE_MISS
>+ },
>+ {
>+ /* perf: branches (eidx: 0x5) */
>+ .eidx = SBI_PMU_HW_BRANCH_INSTRUCTIONS,
>+ .select = ANDES_CONDITION_BR,
>+ },
>+ {
>+ /* perf: branch-misses (eidx: 0x6) */
>+ .eidx = SBI_PMU_HW_BRANCH_MISSES,
>+ .select = ANDES_MISPREDICT_CONDITION_BR,
>+ },
>+ /* Hardware cache events (Type #1) */
>+ {
>+ /* perf: L1-dcache-loads (eidx: 0x10000) */
>+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
>+ .select = ANDES_DCACHE_LOAD_ACCESS
>+ },
>+ {
>+ /* perf: L1-dcache-loads-misses (eidx: 0x10001) */
>+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, MISS),
>+ .select = ANDES_DCACHE_LOAD_MISS
>+ },
>+ {
>+ /* perf: L1-dcache-stores (eidx: 0x10002) */
>+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, ACCESS),
>+ .select = ANDES_DCACHE_STORE_ACCESS
>+ },
>+ {
>+ /* perf: L1-dcache-store-misses (eidx: 0x10003) */
>+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
>+ .select = ANDES_DCACHE_STORE_MISS
>+ },
>+ {
>+ /* perf: L1-icache-load (eidx: 0x10008) */
>+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
>+ .select = ANDES_ICACHE_ACCESS
>+ },
>+ {
>+ /* perf: L1-icache-load-misses (eidx: 0x10009) */
>+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
>+ .select = ANDES_ICACHE_MISS
>+ },
>+ { /* sentinel */ }
>+};
>+
>+static const struct sbi_pmu_event_counter_map andes45_hw_evt_counters[] = {
>+ {
>+ /* perf: cycles (eidx: 0x1) */
>+ .eidx_start = SBI_PMU_HW_CPU_CYCLES,
>+ /* perf: branch-misses (eidx: 0x6) */
>+ .eidx_end = SBI_PMU_HW_BRANCH_MISSES,
>+ .ctr_map = ANDES_MHPM_MAP,
>+ },
>+ {
>+ /* perf: L1-dcache-loads (eidx: 0x10000) */
>+ .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
>+ /* perf: L1-dcache-store-misses (eidx: 0x10003) */
>+ .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
>+ .ctr_map = ANDES_MHPM_MAP,
>+ },
>+ {
>+ /* perf: L1-icache-load (eidx: 0x10008) */
>+ .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
>+ /* perf: L1-icache-load-misses (eidx: 0x10009) */
>+ .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
>+ .ctr_map = ANDES_MHPM_MAP,
>+ },
>+ { /* sentinel */ }
>+};
>+
>+static const struct sbi_pmu_raw_event_counter_map andes45_raw_evt_counters[] = {
>+ {
>+ .select = ANDES_CYCLES,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_INSTRET,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_INT_LOAD_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_INT_STORE_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_ATOMIC_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_SYS_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_INT_COMPUTE_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_CONDITION_BR,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_TAKEN_CONDITION_BR,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_JAL_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_JALR_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_RET_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_CONTROL_TRANS_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_EX9_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_INT_MUL_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_INT_DIV_REMAINDER_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_FLOAT_LOAD_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_FLOAT_STORE_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_FLOAT_ADD_SUB_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_FLOAT_MUL_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_FLOAT_FUSED_MULADD_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_FLOAT_DIV_SQUARE_ROOT_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_OTHER_FLOAT_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_INT_MUL_AND_SUB_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_RETIRED_OP,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_ILM_ACCESS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_DLM_ACCESS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_ICACHE_ACCESS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_ICACHE_MISS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_DCACHE_ACCESS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_DCACHE_MISS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_DCACHE_LOAD_ACCESS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_DCACHE_LOAD_MISS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_DCACHE_STORE_ACCESS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_DCACHE_STORE_MISS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_DCACHE_WB,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_CYCLE_WAIT_ICACHE_FILL,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_CYCLE_WAIT_DCACHE_FILL,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_UNCACHED_IFETCH_FROM_BUS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_UNCACHED_LOAD_FROM_BUS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_CYCLE_WAIT_UNCACHED_IFETCH,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_CYCLE_WAIT_UNCACHED_LOAD,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_MAIN_ITLB_ACCESS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_MAIN_ITLB_MISS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_MAIN_DTLB_ACCESS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_MAIN_DTLB_MISS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_CYCLE_WAIT_ITLB_FILL,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_PIPE_STALL_CYCLE_DTLB_MISS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_HW_PREFETCH_BUS_ACCESS,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_MISPREDICT_CONDITION_BR,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_MISPREDICT_TAKE_CONDITION_BR,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ {
>+ .select = ANDES_MISPREDICT_TARGET_RET_INST,
>+ .select_mask = ANDES_RAW_EVENT_MASK,
>+ .ctr_map = ANDES_MHPM_MAP
>+ },
>+ { /* sentinel */ }
>+};
Why not use DT? I just see everything is fixed.
Adding fdt_add_pmu_mappings is not a good idea. Opensbi can use its own
DT by setting FW_FDT_PATH, so you do not need to add this mapping table.
>+
>+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match)
>+{
>+ /*
>+ * At the moment, simply create mapping for any 45-series core
>+ * based on marchid, we may check and differentiate the mapping
>+ * by mimpid.
>+ */
>+ if (is_andes(45))
>+ return fdt_add_pmu_mappings(fdt, andes45_hw_evt_selects,
>+ andes45_hw_evt_counters,
>+ andes45_raw_evt_counters);
>+
>+ return 0;
>+}
>diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
>index 6a8c66c..57caaf6 100644
>--- a/platform/generic/andes/objects.mk
>+++ b/platform/generic/andes/objects.mk
>@@ -8,3 +8,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
> platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
> platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
> platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
>+platform-objs-$(CONFIG_ANDES_HPM) += andes/andes_hpm.o
>diff --git a/platform/generic/include/andes/andes_hpm.h b/platform/generic/include/andes/andes_hpm.h
>new file mode 100644
>index 0000000..0f301db
>--- /dev/null
>+++ b/platform/generic/include/andes/andes_hpm.h
>@@ -0,0 +1,83 @@
>+/*
>+ * SPDX-License-Identifier: BSD-2-Clause
>+ *
>+ * Copyright (c) 2023 Andes Technology Corporation
>+ */
>+
>+#ifndef _ANDES_HPM_H_
>+#define _ANDES_HPM_H_
>+
>+#include <sbi_utils/fdt/fdt_helper.h>
>+
>+#define ANDES_MHPM_MAP 0x78
>+#define ANDES_RAW_EVENT_MASK ~0ULL
>+
>+/* Event code for instruction commit events */
>+#define ANDES_CYCLES 0x10
>+#define ANDES_INSTRET 0x20
>+#define ANDES_INT_LOAD_INST 0x30
>+#define ANDES_INT_STORE_INST 0x40
>+#define ANDES_ATOMIC_INST 0x50
>+#define ANDES_SYS_INST 0x60
>+#define ANDES_INT_COMPUTE_INST 0x70
>+#define ANDES_CONDITION_BR 0x80
>+#define ANDES_TAKEN_CONDITION_BR 0x90
>+#define ANDES_JAL_INST 0xA0
>+#define ANDES_JALR_INST 0xB0
>+#define ANDES_RET_INST 0xC0
>+#define ANDES_CONTROL_TRANS_INST 0xD0
>+#define ANDES_EX9_INST 0xE0
>+#define ANDES_INT_MUL_INST 0xF0
>+#define ANDES_INT_DIV_REMAINDER_INST 0x100
>+#define ANDES_FLOAT_LOAD_INST 0x110
>+#define ANDES_FLOAT_STORE_INST 0x120
>+#define ANDES_FLOAT_ADD_SUB_INST 0x130
>+#define ANDES_FLOAT_MUL_INST 0x140
>+#define ANDES_FLOAT_FUSED_MULADD_INST 0x150
>+#define ANDES_FLOAT_DIV_SQUARE_ROOT_INST 0x160
>+#define ANDES_OTHER_FLOAT_INST 0x170
>+#define ANDES_INT_MUL_AND_SUB_INST 0x180
>+#define ANDES_RETIRED_OP 0x190
>+
>+/* Event code for memory system events */
>+#define ANDES_ILM_ACCESS 0x01
>+#define ANDES_DLM_ACCESS 0x11
>+#define ANDES_ICACHE_ACCESS 0x21
>+#define ANDES_ICACHE_MISS 0x31
>+#define ANDES_DCACHE_ACCESS 0x41
>+#define ANDES_DCACHE_MISS 0x51
>+#define ANDES_DCACHE_LOAD_ACCESS 0x61
>+#define ANDES_DCACHE_LOAD_MISS 0x71
>+#define ANDES_DCACHE_STORE_ACCESS 0x81
>+#define ANDES_DCACHE_STORE_MISS 0x91
>+#define ANDES_DCACHE_WB 0xA1
>+#define ANDES_CYCLE_WAIT_ICACHE_FILL 0xB1
>+#define ANDES_CYCLE_WAIT_DCACHE_FILL 0xC1
>+#define ANDES_UNCACHED_IFETCH_FROM_BUS 0xD1
>+#define ANDES_UNCACHED_LOAD_FROM_BUS 0xE1
>+#define ANDES_CYCLE_WAIT_UNCACHED_IFETCH 0xF1
>+#define ANDES_CYCLE_WAIT_UNCACHED_LOAD 0x101
>+#define ANDES_MAIN_ITLB_ACCESS 0x111
>+#define ANDES_MAIN_ITLB_MISS 0x121
>+#define ANDES_MAIN_DTLB_ACCESS 0x131
>+#define ANDES_MAIN_DTLB_MISS 0x141
>+#define ANDES_CYCLE_WAIT_ITLB_FILL 0x151
>+#define ANDES_PIPE_STALL_CYCLE_DTLB_MISS 0x161
>+#define ANDES_HW_PREFETCH_BUS_ACCESS 0x171
>+
>+/* Event code for microarchitecture events */
>+#define ANDES_MISPREDICT_CONDITION_BR 0x02
>+#define ANDES_MISPREDICT_TAKE_CONDITION_BR 0x12
>+#define ANDES_MISPREDICT_TARGET_RET_INST 0x22
>+
>+#ifdef CONFIG_ANDES_HPM
>+
>+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match);
>+
>+#else
>+
>+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match) { return 0; }
>+
>+#endif /* CONFIG_ANDES_HPM */
>+
>+#endif /* _ANDES_HPM_H_ */
>diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
>index 2f772c8..fafbff0 100644
>--- a/platform/generic/renesas/rzfive/rzfive.c
>+++ b/platform/generic/renesas/rzfive/rzfive.c
>@@ -5,6 +5,7 @@
> */
>
> #include <andes/andes45_pma.h>
>+#include <andes/andes_hpm.h>
> #include <andes/andes_pmu.h>
> #include <andes/andes_sbi.h>
> #include <platform_override.h>
>@@ -69,6 +70,7 @@ const struct platform_override renesas_rzfive = {
> .match_table = renesas_rzfive_match,
> .early_init = renesas_rzfive_early_init,
> .final_init = renesas_rzfive_final_init,
>+ .fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> .vendor_ext_provider = andes_sbi_vendor_ext_provider,
> .extensions_init = renesas_rzfive_extensions_init,
> };
>--
>2.34.1
>
>
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override
2023-10-21 12:25 ` [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override Inochi Amaoto
@ 2023-10-22 6:50 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 27+ messages in thread
From: Yu-Chien Peter Lin @ 2023-10-22 6:50 UTC (permalink / raw)
To: opensbi
Hi Inochi Amaoto,
On Sat, Oct 21, 2023 at 08:25:30PM +0800, Inochi Amaoto wrote:
> >Implement the andes_fdt_add_pmu_mappings() callback, which creates PMU
> >node properties that will later be populated with mapping tables.
> >
> >Currently we only support 45-series event mappings.
> >
> >Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> >---
> >Changes v1 -> v2:
> > - New patch
> >---
> > include/sbi/sbi_ecall_interface.h | 5 +
> > platform/generic/Kconfig | 2 +
> > platform/generic/andes/Kconfig | 7 +
> > platform/generic/andes/ae350.c | 2 +
> > platform/generic/andes/andes_hpm.c | 381 +++++++++++++++++++++
> > platform/generic/andes/objects.mk | 1 +
> > platform/generic/include/andes/andes_hpm.h | 83 +++++
> > platform/generic/renesas/rzfive/rzfive.c | 2 +
> > 8 files changed, 483 insertions(+)
> > create mode 100644 platform/generic/andes/andes_hpm.c
> > create mode 100644 platform/generic/include/andes/andes_hpm.h
> >
> >diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
> >index 1fe469e..89187e7 100644
> >--- a/include/sbi/sbi_ecall_interface.h
> >+++ b/include/sbi/sbi_ecall_interface.h
> >@@ -155,6 +155,11 @@ enum sbi_pmu_hw_cache_op_result_id {
> > SBI_PMU_HW_CACHE_RESULT_MAX,
> > };
> >
> >+#define SBI_PMU_HW_CACHE_EVENT_IDX(id, op, res) \
> >+ (SBI_PMU_EVENT_TYPE_HW_CACHE << SBI_PMU_EVENT_IDX_TYPE_OFFSET | \
> >+ SBI_PMU_HW_CACHE_##id << 3 | SBI_PMU_HW_CACHE_OP_##op << 1 | \
> >+ SBI_PMU_HW_CACHE_RESULT_##res)
> >+
> > /**
> > * Special "firmware" events provided by the OpenSBI, even if the hardware
> > * does not support performance events. These events are encoded as a raw
> >diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> >index d6dafef..fbcd870 100644
> >--- a/platform/generic/Kconfig
> >+++ b/platform/generic/Kconfig
> >@@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
> > config PLATFORM_ANDES_AE350
> > bool "Andes AE350 support"
> > select SYS_ATCSMU
> >+ select ANDES_HPM
> > select ANDES_PMU
> > default n
> >
> >@@ -38,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
> > bool "Renesas RZ/Five support"
> > select ANDES45_PMA
> > select ANDES_SBI
> >+ select ANDES_HPM
> > select ANDES_PMU
> > default n
> >
> >diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> >index 555e4fe..8af2704 100644
> >--- a/platform/generic/andes/Kconfig
> >+++ b/platform/generic/andes/Kconfig
> >@@ -8,6 +8,13 @@ config ANDES_SBI
> > bool "Andes SBI support"
> > default n
> >
> >+config ANDES_HPM
> >+ bool "Andes HPM support"
> >+ default n
> >+ help
> >+ This provides Andes platform override for creating
> >+ event to counter mappings in pmu node.
> >+
> > config ANDES_PMU
> > bool "Andes custom PMU extension support"
> > default n
> >diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
> >index 80cd294..28c187e 100644
> >--- a/platform/generic/andes/ae350.c
> >+++ b/platform/generic/andes/ae350.c
> >@@ -19,6 +19,7 @@
> > #include <sbi/sbi_ipi.h>
> > #include <sbi/sbi_init.h>
> > #include <andes/andes45.h>
> >+#include <andes/andes_hpm.h>
> >
> > static struct smu_data smu = { 0 };
> > extern void __ae350_enable_coherency_warmboot(void);
> >@@ -128,5 +129,6 @@ static const struct fdt_match andes_ae350_match[] = {
> > const struct platform_override andes_ae350 = {
> > .match_table = andes_ae350_match,
> > .final_init = ae350_final_init,
> >+ .fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> > .extensions_init = ae350_extensions_init,
> > };
> >diff --git a/platform/generic/andes/andes_hpm.c b/platform/generic/andes/andes_hpm.c
> >new file mode 100644
> >index 0000000..f9e6d2e
> >--- /dev/null
> >+++ b/platform/generic/andes/andes_hpm.c
> >@@ -0,0 +1,381 @@
> >+/*
> >+ * SPDX-License-Identifier: BSD-2-Clause
> >+ *
> >+ * Copyright (c) 2023 Andes Technology Corporation
> >+ */
> >+
> >+#include <andes/andes45.h>
> >+#include <andes/andes_hpm.h>
> >+#include <sbi/riscv_asm.h>
> >+#include <sbi/sbi_ecall_interface.h>
> >+#include <sbi_utils/fdt/fdt_fixup.h>
> >+
> >+static const struct sbi_pmu_event_select_map andes45_hw_evt_selects[] = {
> >+ /* Hardware general events (Type #0) */
> >+ {
> >+ /* perf: cycles (eidx: 0x1) */
> >+ .eidx = SBI_PMU_HW_CPU_CYCLES,
> >+ .select = ANDES_CYCLES
> >+ },
> >+ {
> >+ /* perf: instructions (eidx: 0x2) */
> >+ .eidx = SBI_PMU_HW_INSTRUCTIONS,
> >+ .select = ANDES_INSTRET
> >+ },
> >+ {
> >+ /* perf: cache-references (eidx: 0x3) */
> >+ .eidx = SBI_PMU_HW_CACHE_REFERENCES,
> >+ .select = ANDES_DCACHE_ACCESS
> >+ },
> >+ {
> >+ /* perf: cache-misses (eidx: 0x4) */
> >+ .eidx = SBI_PMU_HW_CACHE_MISSES,
> >+ .select = ANDES_DCACHE_MISS
> >+ },
> >+ {
> >+ /* perf: branches (eidx: 0x5) */
> >+ .eidx = SBI_PMU_HW_BRANCH_INSTRUCTIONS,
> >+ .select = ANDES_CONDITION_BR,
> >+ },
> >+ {
> >+ /* perf: branch-misses (eidx: 0x6) */
> >+ .eidx = SBI_PMU_HW_BRANCH_MISSES,
> >+ .select = ANDES_MISPREDICT_CONDITION_BR,
> >+ },
> >+ /* Hardware cache events (Type #1) */
> >+ {
> >+ /* perf: L1-dcache-loads (eidx: 0x10000) */
> >+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
> >+ .select = ANDES_DCACHE_LOAD_ACCESS
> >+ },
> >+ {
> >+ /* perf: L1-dcache-loads-misses (eidx: 0x10001) */
> >+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, MISS),
> >+ .select = ANDES_DCACHE_LOAD_MISS
> >+ },
> >+ {
> >+ /* perf: L1-dcache-stores (eidx: 0x10002) */
> >+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, ACCESS),
> >+ .select = ANDES_DCACHE_STORE_ACCESS
> >+ },
> >+ {
> >+ /* perf: L1-dcache-store-misses (eidx: 0x10003) */
> >+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
> >+ .select = ANDES_DCACHE_STORE_MISS
> >+ },
> >+ {
> >+ /* perf: L1-icache-load (eidx: 0x10008) */
> >+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
> >+ .select = ANDES_ICACHE_ACCESS
> >+ },
> >+ {
> >+ /* perf: L1-icache-load-misses (eidx: 0x10009) */
> >+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
> >+ .select = ANDES_ICACHE_MISS
> >+ },
> >+ { /* sentinel */ }
> >+};
> >+
> >+static const struct sbi_pmu_event_counter_map andes45_hw_evt_counters[] = {
> >+ {
> >+ /* perf: cycles (eidx: 0x1) */
> >+ .eidx_start = SBI_PMU_HW_CPU_CYCLES,
> >+ /* perf: branch-misses (eidx: 0x6) */
> >+ .eidx_end = SBI_PMU_HW_BRANCH_MISSES,
> >+ .ctr_map = ANDES_MHPM_MAP,
> >+ },
> >+ {
> >+ /* perf: L1-dcache-loads (eidx: 0x10000) */
> >+ .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
> >+ /* perf: L1-dcache-store-misses (eidx: 0x10003) */
> >+ .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
> >+ .ctr_map = ANDES_MHPM_MAP,
> >+ },
> >+ {
> >+ /* perf: L1-icache-load (eidx: 0x10008) */
> >+ .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
> >+ /* perf: L1-icache-load-misses (eidx: 0x10009) */
> >+ .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
> >+ .ctr_map = ANDES_MHPM_MAP,
> >+ },
> >+ { /* sentinel */ }
> >+};
> >+
> >+static const struct sbi_pmu_raw_event_counter_map andes45_raw_evt_counters[] = {
> >+ {
> >+ .select = ANDES_CYCLES,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_INSTRET,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_INT_LOAD_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_INT_STORE_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_ATOMIC_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_SYS_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_INT_COMPUTE_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_CONDITION_BR,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_TAKEN_CONDITION_BR,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_JAL_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_JALR_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_RET_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_CONTROL_TRANS_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_EX9_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_INT_MUL_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_INT_DIV_REMAINDER_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_FLOAT_LOAD_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_FLOAT_STORE_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_FLOAT_ADD_SUB_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_FLOAT_MUL_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_FLOAT_FUSED_MULADD_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_FLOAT_DIV_SQUARE_ROOT_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_OTHER_FLOAT_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_INT_MUL_AND_SUB_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_RETIRED_OP,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_ILM_ACCESS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_DLM_ACCESS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_ICACHE_ACCESS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_ICACHE_MISS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_DCACHE_ACCESS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_DCACHE_MISS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_DCACHE_LOAD_ACCESS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_DCACHE_LOAD_MISS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_DCACHE_STORE_ACCESS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_DCACHE_STORE_MISS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_DCACHE_WB,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_CYCLE_WAIT_ICACHE_FILL,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_CYCLE_WAIT_DCACHE_FILL,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_UNCACHED_IFETCH_FROM_BUS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_UNCACHED_LOAD_FROM_BUS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_CYCLE_WAIT_UNCACHED_IFETCH,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_CYCLE_WAIT_UNCACHED_LOAD,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_MAIN_ITLB_ACCESS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_MAIN_ITLB_MISS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_MAIN_DTLB_ACCESS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_MAIN_DTLB_MISS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_CYCLE_WAIT_ITLB_FILL,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_PIPE_STALL_CYCLE_DTLB_MISS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_HW_PREFETCH_BUS_ACCESS,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_MISPREDICT_CONDITION_BR,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_MISPREDICT_TAKE_CONDITION_BR,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ {
> >+ .select = ANDES_MISPREDICT_TARGET_RET_INST,
> >+ .select_mask = ANDES_RAW_EVENT_MASK,
> >+ .ctr_map = ANDES_MHPM_MAP
> >+ },
> >+ { /* sentinel */ }
> >+};
>
> Why not use DT? I just see everything is fixed.
>
> Adding fdt_add_pmu_mappings is not a good idea. Opensbi can use its own
> DT by setting FW_FDT_PATH, so you do not need to add this mapping table.
Thanks for the feedback.
We use this to ensure that a valid pmu node is available, but
if most people don't need this, I'm happy to drop this patch.
Best regards,
Peter Lin
> >+
> >+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match)
> >+{
> >+ /*
> >+ * At the moment, simply create mapping for any 45-series core
> >+ * based on marchid, we may check and differentiate the mapping
> >+ * by mimpid.
> >+ */
> >+ if (is_andes(45))
> >+ return fdt_add_pmu_mappings(fdt, andes45_hw_evt_selects,
> >+ andes45_hw_evt_counters,
> >+ andes45_raw_evt_counters);
> >+
> >+ return 0;
> >+}
> >diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
> >index 6a8c66c..57caaf6 100644
> >--- a/platform/generic/andes/objects.mk
> >+++ b/platform/generic/andes/objects.mk
> >@@ -8,3 +8,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
> > platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
> > platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
> > platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
> >+platform-objs-$(CONFIG_ANDES_HPM) += andes/andes_hpm.o
> >diff --git a/platform/generic/include/andes/andes_hpm.h b/platform/generic/include/andes/andes_hpm.h
> >new file mode 100644
> >index 0000000..0f301db
> >--- /dev/null
> >+++ b/platform/generic/include/andes/andes_hpm.h
> >@@ -0,0 +1,83 @@
> >+/*
> >+ * SPDX-License-Identifier: BSD-2-Clause
> >+ *
> >+ * Copyright (c) 2023 Andes Technology Corporation
> >+ */
> >+
> >+#ifndef _ANDES_HPM_H_
> >+#define _ANDES_HPM_H_
> >+
> >+#include <sbi_utils/fdt/fdt_helper.h>
> >+
> >+#define ANDES_MHPM_MAP 0x78
> >+#define ANDES_RAW_EVENT_MASK ~0ULL
> >+
> >+/* Event code for instruction commit events */
> >+#define ANDES_CYCLES 0x10
> >+#define ANDES_INSTRET 0x20
> >+#define ANDES_INT_LOAD_INST 0x30
> >+#define ANDES_INT_STORE_INST 0x40
> >+#define ANDES_ATOMIC_INST 0x50
> >+#define ANDES_SYS_INST 0x60
> >+#define ANDES_INT_COMPUTE_INST 0x70
> >+#define ANDES_CONDITION_BR 0x80
> >+#define ANDES_TAKEN_CONDITION_BR 0x90
> >+#define ANDES_JAL_INST 0xA0
> >+#define ANDES_JALR_INST 0xB0
> >+#define ANDES_RET_INST 0xC0
> >+#define ANDES_CONTROL_TRANS_INST 0xD0
> >+#define ANDES_EX9_INST 0xE0
> >+#define ANDES_INT_MUL_INST 0xF0
> >+#define ANDES_INT_DIV_REMAINDER_INST 0x100
> >+#define ANDES_FLOAT_LOAD_INST 0x110
> >+#define ANDES_FLOAT_STORE_INST 0x120
> >+#define ANDES_FLOAT_ADD_SUB_INST 0x130
> >+#define ANDES_FLOAT_MUL_INST 0x140
> >+#define ANDES_FLOAT_FUSED_MULADD_INST 0x150
> >+#define ANDES_FLOAT_DIV_SQUARE_ROOT_INST 0x160
> >+#define ANDES_OTHER_FLOAT_INST 0x170
> >+#define ANDES_INT_MUL_AND_SUB_INST 0x180
> >+#define ANDES_RETIRED_OP 0x190
> >+
> >+/* Event code for memory system events */
> >+#define ANDES_ILM_ACCESS 0x01
> >+#define ANDES_DLM_ACCESS 0x11
> >+#define ANDES_ICACHE_ACCESS 0x21
> >+#define ANDES_ICACHE_MISS 0x31
> >+#define ANDES_DCACHE_ACCESS 0x41
> >+#define ANDES_DCACHE_MISS 0x51
> >+#define ANDES_DCACHE_LOAD_ACCESS 0x61
> >+#define ANDES_DCACHE_LOAD_MISS 0x71
> >+#define ANDES_DCACHE_STORE_ACCESS 0x81
> >+#define ANDES_DCACHE_STORE_MISS 0x91
> >+#define ANDES_DCACHE_WB 0xA1
> >+#define ANDES_CYCLE_WAIT_ICACHE_FILL 0xB1
> >+#define ANDES_CYCLE_WAIT_DCACHE_FILL 0xC1
> >+#define ANDES_UNCACHED_IFETCH_FROM_BUS 0xD1
> >+#define ANDES_UNCACHED_LOAD_FROM_BUS 0xE1
> >+#define ANDES_CYCLE_WAIT_UNCACHED_IFETCH 0xF1
> >+#define ANDES_CYCLE_WAIT_UNCACHED_LOAD 0x101
> >+#define ANDES_MAIN_ITLB_ACCESS 0x111
> >+#define ANDES_MAIN_ITLB_MISS 0x121
> >+#define ANDES_MAIN_DTLB_ACCESS 0x131
> >+#define ANDES_MAIN_DTLB_MISS 0x141
> >+#define ANDES_CYCLE_WAIT_ITLB_FILL 0x151
> >+#define ANDES_PIPE_STALL_CYCLE_DTLB_MISS 0x161
> >+#define ANDES_HW_PREFETCH_BUS_ACCESS 0x171
> >+
> >+/* Event code for microarchitecture events */
> >+#define ANDES_MISPREDICT_CONDITION_BR 0x02
> >+#define ANDES_MISPREDICT_TAKE_CONDITION_BR 0x12
> >+#define ANDES_MISPREDICT_TARGET_RET_INST 0x22
> >+
> >+#ifdef CONFIG_ANDES_HPM
> >+
> >+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match);
> >+
> >+#else
> >+
> >+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match) { return 0; }
> >+
> >+#endif /* CONFIG_ANDES_HPM */
> >+
> >+#endif /* _ANDES_HPM_H_ */
> >diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
> >index 2f772c8..fafbff0 100644
> >--- a/platform/generic/renesas/rzfive/rzfive.c
> >+++ b/platform/generic/renesas/rzfive/rzfive.c
> >@@ -5,6 +5,7 @@
> > */
> >
> > #include <andes/andes45_pma.h>
> >+#include <andes/andes_hpm.h>
> > #include <andes/andes_pmu.h>
> > #include <andes/andes_sbi.h>
> > #include <platform_override.h>
> >@@ -69,6 +70,7 @@ const struct platform_override renesas_rzfive = {
> > .match_table = renesas_rzfive_match,
> > .early_init = renesas_rzfive_early_init,
> > .final_init = renesas_rzfive_final_init,
> >+ .fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> > .vendor_ext_provider = andes_sbi_vendor_ext_provider,
> > .extensions_init = renesas_rzfive_extensions_init,
> > };
> >--
> >2.34.1
> >
> >
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 07/11] lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function
2023-10-19 11:37 ` [PATCH v2 07/11] lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function Yu Chien Peter Lin
2023-10-21 12:25 ` [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override Inochi Amaoto
@ 2023-11-16 6:59 ` Anup Patel
1 sibling, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:59 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:11?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add fdt_add_pmu_mappings() that creates entries of riscv,*event-to-mhpm*
> property from arrays right before fdt_pmu_setup() populating the mapping
> tables (i.e. hw_event_map[] and fdt_pmu_evt_select[]).
>
> The helper function will skip the creation of those properties if a
> "/pmu" node with "riscv,pmu" compatible string is provided.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
This patch can be dropped. See my comment in PATCH10.
Regards,
Anup
> ---
> Changes v1 -> v2:
> - New patch
> ---
> include/sbi_utils/fdt/fdt_fixup.h | 48 ++++++++++
> lib/utils/fdt/fdt_fixup.c | 95 ++++++++++++++++++++
> platform/generic/include/platform_override.h | 1 +
> platform/generic/platform.c | 10 ++-
> 4 files changed, 153 insertions(+), 1 deletion(-)
>
> diff --git a/include/sbi_utils/fdt/fdt_fixup.h b/include/sbi_utils/fdt/fdt_fixup.h
> index ecd55a7..9b72df8 100644
> --- a/include/sbi_utils/fdt/fdt_fixup.h
> +++ b/include/sbi_utils/fdt/fdt_fixup.h
> @@ -19,6 +19,54 @@ struct sbi_cpu_idle_state {
> uint32_t wakeup_latency_us;
> };
>
> +struct sbi_pmu_event_select_map {
> + /**
> + * The description of an entry in
> + * riscv,event-to-mhpmevent property
> + */
> + uint32_t eidx;
> + uint64_t select;
> +};
> +
> +struct sbi_pmu_event_counter_map {
> + /**
> + * The description of an entry in
> + * riscv,event-to-mhpmcounters property
> + */
> + uint32_t eidx_start;
> + uint32_t eidx_end;
> + uint32_t ctr_map;
> +};
> +
> +struct sbi_pmu_raw_event_counter_map {
> + /**
> + * The description of an entry in
> + * riscv,raw-event-to-mhpmcounters property
> + */
> + uint64_t select;
> + uint64_t select_mask;
> + uint32_t ctr_map;
> +};
> +
> +/**
> + * Add PMU properties in the DT
> + *
> + * Add information about event to selector/counter mappings to the
> + * devicetree.
> + *
> + * @param fdt: device tree blob
> + * @param selects: array of event index to selector value mapping
> + * descriptions, ending with empty element
> + * @param counters: array of event indexes to counters mapping
> + * descriptions, ending with empty element
> + * @param rcounters: array of raw events to counters mapping
> + * descriptions, ending with empty element
> + * @return zero on success and -ve on failure
> + */
> +int fdt_add_pmu_mappings(void *fdt, const struct sbi_pmu_event_select_map *selects,
> + const struct sbi_pmu_event_counter_map *counters,
> + const struct sbi_pmu_raw_event_counter_map *rcounters);
> +
> /**
> * Add CPU idle states to cpu nodes in the DT
> *
> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> index e213ded..67e2e2e 100644
> --- a/lib/utils/fdt/fdt_fixup.c
> +++ b/lib/utils/fdt/fdt_fixup.c
> @@ -20,6 +20,101 @@
> #include <sbi_utils/fdt/fdt_pmu.h>
> #include <sbi_utils/fdt/fdt_helper.h>
>
> +int fdt_add_pmu_mappings(void *fdt, const struct sbi_pmu_event_select_map *selects,
> + const struct sbi_pmu_event_counter_map *counters,
> + const struct sbi_pmu_raw_event_counter_map *rcounters)
> +{
> + int i, err, pmu_noff, root_noff;
> + const char *comp;
> + fdt32_t evt_to_mhpmevent[3];
> + fdt32_t evt_to_mhpmcounters[3];
> + fdt32_t raw_evt_to_mhpmcounters[5];
> +
> + /* Try to locate pmu node */
> + pmu_noff = fdt_path_offset(fdt, "/pmu");
> +
> + if (pmu_noff > 0) {
> + /*
> + * If compatible string is "riscv,pmu",
> + * we assume a valid pmu node has been
> + * provided.
> + */
> + comp = fdt_getprop(fdt, pmu_noff, "compatible", NULL);
> + if (comp && !strcmp(comp, "riscv,pmu"))
> + return 0;
> + else
> + return -FDT_ERR_BADVALUE;
> + }
> +
> + if (pmu_noff < 0 && pmu_noff != -FDT_ERR_NOTFOUND)
> + return pmu_noff;
> +
> + /*
> + * If "riscv,event-to-mhpmevent" is present, "riscv,event-to-mhpmcounters"
> + * must be provided as well, but not vice versa (OpenSBI will direct mapping
> + * event_idx as selector value).
> + */
> + if (selects && !counters) {
> + sbi_printf("%s: ERR: riscv,event-to-mhpmcounters is mandatory if"
> + " riscv,event-to-mhpmevent is present.", __func__);
> + return SBI_EINVAL;
> + }
> +
> + /*
> + * Create pmu node based on given @selects, @counters
> + * and @rcounters.
> + */
> + root_noff = fdt_path_offset(fdt, "/");
> + pmu_noff = fdt_add_subnode(fdt, root_noff, "pmu");
> + if (pmu_noff < 0)
> + return pmu_noff;
> +
> + err = fdt_open_into(fdt, fdt, fdt_totalsize(fdt) + 1024);
> + if (err < 0)
> + return err;
> +
> + err = fdt_setprop_string(fdt, pmu_noff, "compatible", "riscv,pmu");
> + if (err)
> + return err;
> +
> + /* Add riscv,event-to-mhpmevent */
> + for (i = 0; selects && selects[i].eidx; i++) {
> + evt_to_mhpmevent[0] = cpu_to_fdt32(selects[i].eidx);
> + evt_to_mhpmevent[1] = cpu_to_fdt32(selects[i].select >> 32);
> + evt_to_mhpmevent[2] = cpu_to_fdt32(selects[i].select & ~0UL);
> + err = fdt_appendprop(fdt, pmu_noff, "riscv,event-to-mhpmevent",
> + evt_to_mhpmevent, 3 * sizeof(fdt32_t));
> + if (err)
> + return err;
> + }
> +
> + /* Add riscv,event-to-mhpmcounters */
> + for (i = 0; counters && counters[i].eidx_start; i++) {
> + evt_to_mhpmcounters[0] = cpu_to_fdt32(counters[i].eidx_start);
> + evt_to_mhpmcounters[1] = cpu_to_fdt32(counters[i].eidx_end);
> + evt_to_mhpmcounters[2] = cpu_to_fdt32(counters[i].ctr_map);
> + err = fdt_appendprop(fdt, pmu_noff, "riscv,event-to-mhpmcounters",
> + evt_to_mhpmcounters, 3 * sizeof(fdt32_t));
> + if (err)
> + return err;
> + }
> +
> + /* Add riscv,raw-event-to-mhpmcounters */
> + for (i = 0; rcounters && rcounters[i].select; i++) {
> + raw_evt_to_mhpmcounters[0] = cpu_to_fdt32(rcounters[i].select >> 32);
> + raw_evt_to_mhpmcounters[1] = cpu_to_fdt32(rcounters[i].select & ~0UL);
> + raw_evt_to_mhpmcounters[2] = cpu_to_fdt32(rcounters[i].select_mask >> 32);
> + raw_evt_to_mhpmcounters[3] = cpu_to_fdt32(rcounters[i].select_mask & ~0UL);
> + raw_evt_to_mhpmcounters[4] = cpu_to_fdt32(rcounters[i].ctr_map);
> + err = fdt_appendprop(fdt, pmu_noff, "riscv,raw-event-to-mhpmcounters",
> + raw_evt_to_mhpmcounters, 5 * sizeof(fdt32_t));
> + if (err)
> + return err;
> + }
> +
> + return 0;
> +}
> +
> int fdt_add_cpu_idle_states(void *fdt, const struct sbi_cpu_idle_state *state)
> {
> int cpu_node, cpus_node, err, idle_states_node;
> diff --git a/platform/generic/include/platform_override.h b/platform/generic/include/platform_override.h
> index bf4b112..bd34d2a 100644
> --- a/platform/generic/include/platform_override.h
> +++ b/platform/generic/include/platform_override.h
> @@ -19,6 +19,7 @@ struct platform_override {
> u64 (*features)(const struct fdt_match *match);
> u64 (*tlbr_flush_limit)(const struct fdt_match *match);
> u32 (*tlb_num_entries)(const struct fdt_match *match);
> + int (*fdt_add_pmu_mappings)(void *fdt, const struct fdt_match *match);
> bool (*cold_boot_allowed)(u32 hartid, const struct fdt_match *match);
> int (*early_init)(bool cold_boot, const struct fdt_match *match);
> int (*final_init)(bool cold_boot, const struct fdt_match *match);
> diff --git a/platform/generic/platform.c b/platform/generic/platform.c
> index cb9270d..a48a8b7 100644
> --- a/platform/generic/platform.c
> +++ b/platform/generic/platform.c
> @@ -265,9 +265,17 @@ static u32 generic_tlb_num_entries(void)
>
> static int generic_pmu_init(void)
> {
> + void *fdt = fdt_get_address();
> int rc;
>
> - rc = fdt_pmu_setup(fdt_get_address());
> + if (generic_plat && generic_plat->fdt_add_pmu_mappings) {
> + rc = generic_plat->fdt_add_pmu_mappings(fdt,
> + generic_plat_match);
> + if (rc)
> + return rc;
> + }
> +
> + rc = fdt_pmu_setup(fdt);
> if (rc && rc != SBI_ENOENT)
> return rc;
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 08/11] lib: utils: fdt_fixup: Allow preserving PMU properties
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
` (6 preceding siblings ...)
2023-10-19 11:37 ` [PATCH v2 07/11] lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 6:48 ` Anup Patel
2023-10-19 11:37 ` [PATCH v2 09/11] platform: andes: Factor out is_andes() helper Yu Chien Peter Lin
` (3 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
Add a scratch option to control PMU fixup, so the next
stage software can dump the PMU node including event
mapping information for debugging purposes.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
---
include/sbi/sbi_scratch.h | 2 ++
lib/utils/fdt/fdt_fixup.c | 6 +++++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
index e6a33ba..7914dfb 100644
--- a/include/sbi/sbi_scratch.h
+++ b/include/sbi/sbi_scratch.h
@@ -151,6 +151,8 @@ enum sbi_scratch_options {
SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
/** Enable runtime debug prints */
SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
+ /** Preserve PMU node properties */
+ SBI_SCRATCH_PRESERVE_PMU_PROP = (1 << 2),
};
/** Get pointer to sbi_scratch for current HART */
diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
index 67e2e2e..b0c885f 100644
--- a/lib/utils/fdt/fdt_fixup.c
+++ b/lib/utils/fdt/fdt_fixup.c
@@ -482,6 +482,8 @@ int fdt_reserved_memory_fixup(void *fdt)
void fdt_fixups(void *fdt)
{
+ struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
+
fdt_aplic_fixup(fdt);
fdt_imsic_fixup(fdt);
@@ -489,5 +491,7 @@ void fdt_fixups(void *fdt)
fdt_plic_fixup(fdt);
fdt_reserved_memory_fixup(fdt);
- fdt_pmu_fixup(fdt);
+
+ if (!(scratch->options & SBI_SCRATCH_PRESERVE_PMU_PROP))
+ fdt_pmu_fixup(fdt);
}
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 08/11] lib: utils: fdt_fixup: Allow preserving PMU properties
2023-10-19 11:37 ` [PATCH v2 08/11] lib: utils: fdt_fixup: Allow preserving PMU properties Yu Chien Peter Lin
@ 2023-11-16 6:48 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:48 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:11?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add a scratch option to control PMU fixup, so the next
> stage software can dump the PMU node including event
> mapping information for debugging purposes.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v1 -> v2:
> - New patch
> ---
> include/sbi/sbi_scratch.h | 2 ++
> lib/utils/fdt/fdt_fixup.c | 6 +++++-
> 2 files changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/include/sbi/sbi_scratch.h b/include/sbi/sbi_scratch.h
> index e6a33ba..7914dfb 100644
> --- a/include/sbi/sbi_scratch.h
> +++ b/include/sbi/sbi_scratch.h
> @@ -151,6 +151,8 @@ enum sbi_scratch_options {
> SBI_SCRATCH_NO_BOOT_PRINTS = (1 << 0),
> /** Enable runtime debug prints */
> SBI_SCRATCH_DEBUG_PRINTS = (1 << 1),
> + /** Preserve PMU node properties */
> + SBI_SCRATCH_PRESERVE_PMU_PROP = (1 << 2),
s/SBI_SCRATCH_PRESERVE_PMU_PROP/SBI_SCRATCH_PRESERVE_PMU_NODE/
> };
>
> /** Get pointer to sbi_scratch for current HART */
> diff --git a/lib/utils/fdt/fdt_fixup.c b/lib/utils/fdt/fdt_fixup.c
> index 67e2e2e..b0c885f 100644
> --- a/lib/utils/fdt/fdt_fixup.c
> +++ b/lib/utils/fdt/fdt_fixup.c
> @@ -482,6 +482,8 @@ int fdt_reserved_memory_fixup(void *fdt)
>
> void fdt_fixups(void *fdt)
> {
> + struct sbi_scratch *scratch = sbi_scratch_thishart_ptr();
> +
> fdt_aplic_fixup(fdt);
>
> fdt_imsic_fixup(fdt);
> @@ -489,5 +491,7 @@ void fdt_fixups(void *fdt)
> fdt_plic_fixup(fdt);
>
> fdt_reserved_memory_fixup(fdt);
> - fdt_pmu_fixup(fdt);
> +
> + if (!(scratch->options & SBI_SCRATCH_PRESERVE_PMU_PROP))
> + fdt_pmu_fixup(fdt);
> }
> --
> 2.34.1
>
Otherwise, it looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 09/11] platform: andes: Factor out is_andes() helper
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
` (7 preceding siblings ...)
2023-10-19 11:37 ` [PATCH v2 08/11] lib: utils: fdt_fixup: Allow preserving PMU properties Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 6:49 ` Anup Patel
2023-10-19 11:37 ` [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override Yu Chien Peter Lin
` (2 subsequent siblings)
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
We will need is_andes(45) in the following patch,
so factor out the code that parses marchid to make
it reusable for checking any Andes CPU variants.
Also improves the comment in ae350_hart_start().
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
---
platform/generic/andes/ae350.c | 16 +++++++---------
platform/generic/include/andes/andes45.h | 6 ++++++
2 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
index c3f280d..80cd294 100644
--- a/platform/generic/andes/ae350.c
+++ b/platform/generic/andes/ae350.c
@@ -24,16 +24,14 @@ static struct smu_data smu = { 0 };
extern void __ae350_enable_coherency_warmboot(void);
extern void __ae350_disable_coherency(void);
-static __always_inline bool is_andes25(void)
-{
- ulong marchid = csr_read(CSR_MARCHID);
- return !!(EXTRACT_FIELD(marchid, CSR_MARCHID_MICROID) == 0xa25);
-}
-
static int ae350_hart_start(u32 hartid, ulong saddr)
{
- /* Don't send wakeup command at boot-time */
- if (!sbi_init_count(hartid) || (is_andes25() && hartid == 0))
+ /*
+ * Don't send wakeup command
+ * 1) at boot-time
+ * 2) the target hart is non-sleepable 25-series hart0
+ */
+ if (!sbi_init_count(hartid) || (is_andes(25) && hartid == 0))
return sbi_ipi_raw_send(sbi_hartid_to_hartindex(hartid));
/* Write wakeup command to the sleep hart */
@@ -52,7 +50,7 @@ static int ae350_hart_stop(void)
* L2-cache, instead of turning it off, it should fall
* through and jump to warmboot_addr.
*/
- if (is_andes25() && hartid == 0)
+ if (is_andes(25) && hartid == 0)
return SBI_ENOTSUPP;
if (!smu_support_sleep_mode(&smu, DEEPSLEEP_MODE, hartid))
diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
index ce31617..01f63d4 100644
--- a/platform/generic/include/andes/andes45.h
+++ b/platform/generic/include/andes/andes45.h
@@ -43,6 +43,12 @@
#ifndef __ASSEMBLER__
+#define is_andes(series) \
+({ \
+ char value = csr_read(CSR_MARCHID) & 0xff; \
+ (series) == (value >> 4) * 10 + (value & 0x0f); \
+})
+
#define has_andes_pmu() \
({ \
(((csr_read(CSR_MMSC_CFG) & \
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 09/11] platform: andes: Factor out is_andes() helper
2023-10-19 11:37 ` [PATCH v2 09/11] platform: andes: Factor out is_andes() helper Yu Chien Peter Lin
@ 2023-11-16 6:49 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:49 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:11?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> We will need is_andes(45) in the following patch,
> so factor out the code that parses marchid to make
> it reusable for checking any Andes CPU variants.
>
> Also improves the comment in ae350_hart_start().
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> Changes v1 -> v2:
> - New patch
> ---
> platform/generic/andes/ae350.c | 16 +++++++---------
> platform/generic/include/andes/andes45.h | 6 ++++++
> 2 files changed, 13 insertions(+), 9 deletions(-)
>
> diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
> index c3f280d..80cd294 100644
> --- a/platform/generic/andes/ae350.c
> +++ b/platform/generic/andes/ae350.c
> @@ -24,16 +24,14 @@ static struct smu_data smu = { 0 };
> extern void __ae350_enable_coherency_warmboot(void);
> extern void __ae350_disable_coherency(void);
>
> -static __always_inline bool is_andes25(void)
> -{
> - ulong marchid = csr_read(CSR_MARCHID);
> - return !!(EXTRACT_FIELD(marchid, CSR_MARCHID_MICROID) == 0xa25);
> -}
> -
> static int ae350_hart_start(u32 hartid, ulong saddr)
> {
> - /* Don't send wakeup command at boot-time */
> - if (!sbi_init_count(hartid) || (is_andes25() && hartid == 0))
> + /*
> + * Don't send wakeup command
> + * 1) at boot-time
> + * 2) the target hart is non-sleepable 25-series hart0
> + */
> + if (!sbi_init_count(hartid) || (is_andes(25) && hartid == 0))
> return sbi_ipi_raw_send(sbi_hartid_to_hartindex(hartid));
>
> /* Write wakeup command to the sleep hart */
> @@ -52,7 +50,7 @@ static int ae350_hart_stop(void)
> * L2-cache, instead of turning it off, it should fall
> * through and jump to warmboot_addr.
> */
> - if (is_andes25() && hartid == 0)
> + if (is_andes(25) && hartid == 0)
> return SBI_ENOTSUPP;
>
> if (!smu_support_sleep_mode(&smu, DEEPSLEEP_MODE, hartid))
> diff --git a/platform/generic/include/andes/andes45.h b/platform/generic/include/andes/andes45.h
> index ce31617..01f63d4 100644
> --- a/platform/generic/include/andes/andes45.h
> +++ b/platform/generic/include/andes/andes45.h
> @@ -43,6 +43,12 @@
>
> #ifndef __ASSEMBLER__
>
> +#define is_andes(series) \
> +({ \
> + char value = csr_read(CSR_MARCHID) & 0xff; \
> + (series) == (value >> 4) * 10 + (value & 0x0f); \
> +})
> +
> #define has_andes_pmu() \
> ({ \
> (((csr_read(CSR_MMSC_CFG) & \
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
` (8 preceding siblings ...)
2023-10-19 11:37 ` [PATCH v2 09/11] platform: andes: Factor out is_andes() helper Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 6:58 ` Anup Patel
2023-10-19 11:37 ` [PATCH v2 11/11] docs: pmu: Add Andes PMU node example Yu Chien Peter Lin
2023-11-16 7:01 ` [PATCH v2 00/11] Add Andes PMU extension support Anup Patel
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
Implement the andes_fdt_add_pmu_mappings() callback, which creates PMU
node properties that will later be populated with mapping tables.
Currently we only support 45-series event mappings.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
---
Changes v1 -> v2:
- New patch
---
include/sbi/sbi_ecall_interface.h | 5 +
platform/generic/Kconfig | 2 +
platform/generic/andes/Kconfig | 7 +
platform/generic/andes/ae350.c | 2 +
platform/generic/andes/andes_hpm.c | 381 +++++++++++++++++++++
platform/generic/andes/objects.mk | 1 +
platform/generic/include/andes/andes_hpm.h | 83 +++++
platform/generic/renesas/rzfive/rzfive.c | 2 +
8 files changed, 483 insertions(+)
create mode 100644 platform/generic/andes/andes_hpm.c
create mode 100644 platform/generic/include/andes/andes_hpm.h
diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
index 1fe469e..89187e7 100644
--- a/include/sbi/sbi_ecall_interface.h
+++ b/include/sbi/sbi_ecall_interface.h
@@ -155,6 +155,11 @@ enum sbi_pmu_hw_cache_op_result_id {
SBI_PMU_HW_CACHE_RESULT_MAX,
};
+#define SBI_PMU_HW_CACHE_EVENT_IDX(id, op, res) \
+ (SBI_PMU_EVENT_TYPE_HW_CACHE << SBI_PMU_EVENT_IDX_TYPE_OFFSET | \
+ SBI_PMU_HW_CACHE_##id << 3 | SBI_PMU_HW_CACHE_OP_##op << 1 | \
+ SBI_PMU_HW_CACHE_RESULT_##res)
+
/**
* Special "firmware" events provided by the OpenSBI, even if the hardware
* does not support performance events. These events are encoded as a raw
diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
index d6dafef..fbcd870 100644
--- a/platform/generic/Kconfig
+++ b/platform/generic/Kconfig
@@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
config PLATFORM_ANDES_AE350
bool "Andes AE350 support"
select SYS_ATCSMU
+ select ANDES_HPM
select ANDES_PMU
default n
@@ -38,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
bool "Renesas RZ/Five support"
select ANDES45_PMA
select ANDES_SBI
+ select ANDES_HPM
select ANDES_PMU
default n
diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
index 555e4fe..8af2704 100644
--- a/platform/generic/andes/Kconfig
+++ b/platform/generic/andes/Kconfig
@@ -8,6 +8,13 @@ config ANDES_SBI
bool "Andes SBI support"
default n
+config ANDES_HPM
+ bool "Andes HPM support"
+ default n
+ help
+ This provides Andes platform override for creating
+ event to counter mappings in pmu node.
+
config ANDES_PMU
bool "Andes custom PMU extension support"
default n
diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
index 80cd294..28c187e 100644
--- a/platform/generic/andes/ae350.c
+++ b/platform/generic/andes/ae350.c
@@ -19,6 +19,7 @@
#include <sbi/sbi_ipi.h>
#include <sbi/sbi_init.h>
#include <andes/andes45.h>
+#include <andes/andes_hpm.h>
static struct smu_data smu = { 0 };
extern void __ae350_enable_coherency_warmboot(void);
@@ -128,5 +129,6 @@ static const struct fdt_match andes_ae350_match[] = {
const struct platform_override andes_ae350 = {
.match_table = andes_ae350_match,
.final_init = ae350_final_init,
+ .fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
.extensions_init = ae350_extensions_init,
};
diff --git a/platform/generic/andes/andes_hpm.c b/platform/generic/andes/andes_hpm.c
new file mode 100644
index 0000000..f9e6d2e
--- /dev/null
+++ b/platform/generic/andes/andes_hpm.c
@@ -0,0 +1,381 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#include <andes/andes45.h>
+#include <andes/andes_hpm.h>
+#include <sbi/riscv_asm.h>
+#include <sbi/sbi_ecall_interface.h>
+#include <sbi_utils/fdt/fdt_fixup.h>
+
+static const struct sbi_pmu_event_select_map andes45_hw_evt_selects[] = {
+ /* Hardware general events (Type #0) */
+ {
+ /* perf: cycles (eidx: 0x1) */
+ .eidx = SBI_PMU_HW_CPU_CYCLES,
+ .select = ANDES_CYCLES
+ },
+ {
+ /* perf: instructions (eidx: 0x2) */
+ .eidx = SBI_PMU_HW_INSTRUCTIONS,
+ .select = ANDES_INSTRET
+ },
+ {
+ /* perf: cache-references (eidx: 0x3) */
+ .eidx = SBI_PMU_HW_CACHE_REFERENCES,
+ .select = ANDES_DCACHE_ACCESS
+ },
+ {
+ /* perf: cache-misses (eidx: 0x4) */
+ .eidx = SBI_PMU_HW_CACHE_MISSES,
+ .select = ANDES_DCACHE_MISS
+ },
+ {
+ /* perf: branches (eidx: 0x5) */
+ .eidx = SBI_PMU_HW_BRANCH_INSTRUCTIONS,
+ .select = ANDES_CONDITION_BR,
+ },
+ {
+ /* perf: branch-misses (eidx: 0x6) */
+ .eidx = SBI_PMU_HW_BRANCH_MISSES,
+ .select = ANDES_MISPREDICT_CONDITION_BR,
+ },
+ /* Hardware cache events (Type #1) */
+ {
+ /* perf: L1-dcache-loads (eidx: 0x10000) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
+ .select = ANDES_DCACHE_LOAD_ACCESS
+ },
+ {
+ /* perf: L1-dcache-loads-misses (eidx: 0x10001) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, MISS),
+ .select = ANDES_DCACHE_LOAD_MISS
+ },
+ {
+ /* perf: L1-dcache-stores (eidx: 0x10002) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, ACCESS),
+ .select = ANDES_DCACHE_STORE_ACCESS
+ },
+ {
+ /* perf: L1-dcache-store-misses (eidx: 0x10003) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
+ .select = ANDES_DCACHE_STORE_MISS
+ },
+ {
+ /* perf: L1-icache-load (eidx: 0x10008) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
+ .select = ANDES_ICACHE_ACCESS
+ },
+ {
+ /* perf: L1-icache-load-misses (eidx: 0x10009) */
+ .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
+ .select = ANDES_ICACHE_MISS
+ },
+ { /* sentinel */ }
+};
+
+static const struct sbi_pmu_event_counter_map andes45_hw_evt_counters[] = {
+ {
+ /* perf: cycles (eidx: 0x1) */
+ .eidx_start = SBI_PMU_HW_CPU_CYCLES,
+ /* perf: branch-misses (eidx: 0x6) */
+ .eidx_end = SBI_PMU_HW_BRANCH_MISSES,
+ .ctr_map = ANDES_MHPM_MAP,
+ },
+ {
+ /* perf: L1-dcache-loads (eidx: 0x10000) */
+ .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
+ /* perf: L1-dcache-store-misses (eidx: 0x10003) */
+ .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
+ .ctr_map = ANDES_MHPM_MAP,
+ },
+ {
+ /* perf: L1-icache-load (eidx: 0x10008) */
+ .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
+ /* perf: L1-icache-load-misses (eidx: 0x10009) */
+ .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
+ .ctr_map = ANDES_MHPM_MAP,
+ },
+ { /* sentinel */ }
+};
+
+static const struct sbi_pmu_raw_event_counter_map andes45_raw_evt_counters[] = {
+ {
+ .select = ANDES_CYCLES,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INSTRET,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_LOAD_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_STORE_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_ATOMIC_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_SYS_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_COMPUTE_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CONDITION_BR,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_TAKEN_CONDITION_BR,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_JAL_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_JALR_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_RET_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CONTROL_TRANS_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_EX9_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_MUL_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_DIV_REMAINDER_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_LOAD_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_STORE_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_ADD_SUB_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_MUL_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_FUSED_MULADD_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_FLOAT_DIV_SQUARE_ROOT_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_OTHER_FLOAT_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_INT_MUL_AND_SUB_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_RETIRED_OP,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_ILM_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DLM_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_ICACHE_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_ICACHE_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_LOAD_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_LOAD_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_STORE_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_STORE_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_DCACHE_WB,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_ICACHE_FILL,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_DCACHE_FILL,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_UNCACHED_IFETCH_FROM_BUS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_UNCACHED_LOAD_FROM_BUS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_UNCACHED_IFETCH,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_UNCACHED_LOAD,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MAIN_ITLB_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MAIN_ITLB_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MAIN_DTLB_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MAIN_DTLB_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_CYCLE_WAIT_ITLB_FILL,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_PIPE_STALL_CYCLE_DTLB_MISS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_HW_PREFETCH_BUS_ACCESS,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MISPREDICT_CONDITION_BR,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MISPREDICT_TAKE_CONDITION_BR,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ {
+ .select = ANDES_MISPREDICT_TARGET_RET_INST,
+ .select_mask = ANDES_RAW_EVENT_MASK,
+ .ctr_map = ANDES_MHPM_MAP
+ },
+ { /* sentinel */ }
+};
+
+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match)
+{
+ /*
+ * At the moment, simply create mapping for any 45-series core
+ * based on marchid, we may check and differentiate the mapping
+ * by mimpid.
+ */
+ if (is_andes(45))
+ return fdt_add_pmu_mappings(fdt, andes45_hw_evt_selects,
+ andes45_hw_evt_counters,
+ andes45_raw_evt_counters);
+
+ return 0;
+}
diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
index 6a8c66c..57caaf6 100644
--- a/platform/generic/andes/objects.mk
+++ b/platform/generic/andes/objects.mk
@@ -8,3 +8,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
+platform-objs-$(CONFIG_ANDES_HPM) += andes/andes_hpm.o
diff --git a/platform/generic/include/andes/andes_hpm.h b/platform/generic/include/andes/andes_hpm.h
new file mode 100644
index 0000000..0f301db
--- /dev/null
+++ b/platform/generic/include/andes/andes_hpm.h
@@ -0,0 +1,83 @@
+/*
+ * SPDX-License-Identifier: BSD-2-Clause
+ *
+ * Copyright (c) 2023 Andes Technology Corporation
+ */
+
+#ifndef _ANDES_HPM_H_
+#define _ANDES_HPM_H_
+
+#include <sbi_utils/fdt/fdt_helper.h>
+
+#define ANDES_MHPM_MAP 0x78
+#define ANDES_RAW_EVENT_MASK ~0ULL
+
+/* Event code for instruction commit events */
+#define ANDES_CYCLES 0x10
+#define ANDES_INSTRET 0x20
+#define ANDES_INT_LOAD_INST 0x30
+#define ANDES_INT_STORE_INST 0x40
+#define ANDES_ATOMIC_INST 0x50
+#define ANDES_SYS_INST 0x60
+#define ANDES_INT_COMPUTE_INST 0x70
+#define ANDES_CONDITION_BR 0x80
+#define ANDES_TAKEN_CONDITION_BR 0x90
+#define ANDES_JAL_INST 0xA0
+#define ANDES_JALR_INST 0xB0
+#define ANDES_RET_INST 0xC0
+#define ANDES_CONTROL_TRANS_INST 0xD0
+#define ANDES_EX9_INST 0xE0
+#define ANDES_INT_MUL_INST 0xF0
+#define ANDES_INT_DIV_REMAINDER_INST 0x100
+#define ANDES_FLOAT_LOAD_INST 0x110
+#define ANDES_FLOAT_STORE_INST 0x120
+#define ANDES_FLOAT_ADD_SUB_INST 0x130
+#define ANDES_FLOAT_MUL_INST 0x140
+#define ANDES_FLOAT_FUSED_MULADD_INST 0x150
+#define ANDES_FLOAT_DIV_SQUARE_ROOT_INST 0x160
+#define ANDES_OTHER_FLOAT_INST 0x170
+#define ANDES_INT_MUL_AND_SUB_INST 0x180
+#define ANDES_RETIRED_OP 0x190
+
+/* Event code for memory system events */
+#define ANDES_ILM_ACCESS 0x01
+#define ANDES_DLM_ACCESS 0x11
+#define ANDES_ICACHE_ACCESS 0x21
+#define ANDES_ICACHE_MISS 0x31
+#define ANDES_DCACHE_ACCESS 0x41
+#define ANDES_DCACHE_MISS 0x51
+#define ANDES_DCACHE_LOAD_ACCESS 0x61
+#define ANDES_DCACHE_LOAD_MISS 0x71
+#define ANDES_DCACHE_STORE_ACCESS 0x81
+#define ANDES_DCACHE_STORE_MISS 0x91
+#define ANDES_DCACHE_WB 0xA1
+#define ANDES_CYCLE_WAIT_ICACHE_FILL 0xB1
+#define ANDES_CYCLE_WAIT_DCACHE_FILL 0xC1
+#define ANDES_UNCACHED_IFETCH_FROM_BUS 0xD1
+#define ANDES_UNCACHED_LOAD_FROM_BUS 0xE1
+#define ANDES_CYCLE_WAIT_UNCACHED_IFETCH 0xF1
+#define ANDES_CYCLE_WAIT_UNCACHED_LOAD 0x101
+#define ANDES_MAIN_ITLB_ACCESS 0x111
+#define ANDES_MAIN_ITLB_MISS 0x121
+#define ANDES_MAIN_DTLB_ACCESS 0x131
+#define ANDES_MAIN_DTLB_MISS 0x141
+#define ANDES_CYCLE_WAIT_ITLB_FILL 0x151
+#define ANDES_PIPE_STALL_CYCLE_DTLB_MISS 0x161
+#define ANDES_HW_PREFETCH_BUS_ACCESS 0x171
+
+/* Event code for microarchitecture events */
+#define ANDES_MISPREDICT_CONDITION_BR 0x02
+#define ANDES_MISPREDICT_TAKE_CONDITION_BR 0x12
+#define ANDES_MISPREDICT_TARGET_RET_INST 0x22
+
+#ifdef CONFIG_ANDES_HPM
+
+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match);
+
+#else
+
+int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match) { return 0; }
+
+#endif /* CONFIG_ANDES_HPM */
+
+#endif /* _ANDES_HPM_H_ */
diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
index 2f772c8..fafbff0 100644
--- a/platform/generic/renesas/rzfive/rzfive.c
+++ b/platform/generic/renesas/rzfive/rzfive.c
@@ -5,6 +5,7 @@
*/
#include <andes/andes45_pma.h>
+#include <andes/andes_hpm.h>
#include <andes/andes_pmu.h>
#include <andes/andes_sbi.h>
#include <platform_override.h>
@@ -69,6 +70,7 @@ const struct platform_override renesas_rzfive = {
.match_table = renesas_rzfive_match,
.early_init = renesas_rzfive_early_init,
.final_init = renesas_rzfive_final_init,
+ .fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
.vendor_ext_provider = andes_sbi_vendor_ext_provider,
.extensions_init = renesas_rzfive_extensions_init,
};
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override
2023-10-19 11:37 ` [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override Yu Chien Peter Lin
@ 2023-11-16 6:58 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 6:58 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:11?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Implement the andes_fdt_add_pmu_mappings() callback, which creates PMU
> node properties that will later be populated with mapping tables.
>
> Currently we only support 45-series event mappings.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> ---
> Changes v1 -> v2:
> - New patch
> ---
> include/sbi/sbi_ecall_interface.h | 5 +
> platform/generic/Kconfig | 2 +
> platform/generic/andes/Kconfig | 7 +
> platform/generic/andes/ae350.c | 2 +
> platform/generic/andes/andes_hpm.c | 381 +++++++++++++++++++++
> platform/generic/andes/objects.mk | 1 +
> platform/generic/include/andes/andes_hpm.h | 83 +++++
> platform/generic/renesas/rzfive/rzfive.c | 2 +
> 8 files changed, 483 insertions(+)
> create mode 100644 platform/generic/andes/andes_hpm.c
> create mode 100644 platform/generic/include/andes/andes_hpm.h
>
> diff --git a/include/sbi/sbi_ecall_interface.h b/include/sbi/sbi_ecall_interface.h
> index 1fe469e..89187e7 100644
> --- a/include/sbi/sbi_ecall_interface.h
> +++ b/include/sbi/sbi_ecall_interface.h
> @@ -155,6 +155,11 @@ enum sbi_pmu_hw_cache_op_result_id {
> SBI_PMU_HW_CACHE_RESULT_MAX,
> };
>
> +#define SBI_PMU_HW_CACHE_EVENT_IDX(id, op, res) \
> + (SBI_PMU_EVENT_TYPE_HW_CACHE << SBI_PMU_EVENT_IDX_TYPE_OFFSET | \
> + SBI_PMU_HW_CACHE_##id << 3 | SBI_PMU_HW_CACHE_OP_##op << 1 | \
> + SBI_PMU_HW_CACHE_RESULT_##res)
> +
> /**
> * Special "firmware" events provided by the OpenSBI, even if the hardware
> * does not support performance events. These events are encoded as a raw
> diff --git a/platform/generic/Kconfig b/platform/generic/Kconfig
> index d6dafef..fbcd870 100644
> --- a/platform/generic/Kconfig
> +++ b/platform/generic/Kconfig
> @@ -31,6 +31,7 @@ config PLATFORM_ALLWINNER_D1
> config PLATFORM_ANDES_AE350
> bool "Andes AE350 support"
> select SYS_ATCSMU
> + select ANDES_HPM
> select ANDES_PMU
> default n
>
> @@ -38,6 +39,7 @@ config PLATFORM_RENESAS_RZFIVE
> bool "Renesas RZ/Five support"
> select ANDES45_PMA
> select ANDES_SBI
> + select ANDES_HPM
> select ANDES_PMU
> default n
>
> diff --git a/platform/generic/andes/Kconfig b/platform/generic/andes/Kconfig
> index 555e4fe..8af2704 100644
> --- a/platform/generic/andes/Kconfig
> +++ b/platform/generic/andes/Kconfig
> @@ -8,6 +8,13 @@ config ANDES_SBI
> bool "Andes SBI support"
> default n
>
> +config ANDES_HPM
> + bool "Andes HPM support"
> + default n
> + help
> + This provides Andes platform override for creating
> + event to counter mappings in pmu node.
> +
> config ANDES_PMU
> bool "Andes custom PMU extension support"
> default n
> diff --git a/platform/generic/andes/ae350.c b/platform/generic/andes/ae350.c
> index 80cd294..28c187e 100644
> --- a/platform/generic/andes/ae350.c
> +++ b/platform/generic/andes/ae350.c
> @@ -19,6 +19,7 @@
> #include <sbi/sbi_ipi.h>
> #include <sbi/sbi_init.h>
> #include <andes/andes45.h>
> +#include <andes/andes_hpm.h>
>
> static struct smu_data smu = { 0 };
> extern void __ae350_enable_coherency_warmboot(void);
> @@ -128,5 +129,6 @@ static const struct fdt_match andes_ae350_match[] = {
> const struct platform_override andes_ae350 = {
> .match_table = andes_ae350_match,
> .final_init = ae350_final_init,
> + .fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> .extensions_init = ae350_extensions_init,
> };
> diff --git a/platform/generic/andes/andes_hpm.c b/platform/generic/andes/andes_hpm.c
> new file mode 100644
> index 0000000..f9e6d2e
> --- /dev/null
> +++ b/platform/generic/andes/andes_hpm.c
> @@ -0,0 +1,381 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2023 Andes Technology Corporation
> + */
> +
> +#include <andes/andes45.h>
> +#include <andes/andes_hpm.h>
> +#include <sbi/riscv_asm.h>
> +#include <sbi/sbi_ecall_interface.h>
> +#include <sbi_utils/fdt/fdt_fixup.h>
> +
> +static const struct sbi_pmu_event_select_map andes45_hw_evt_selects[] = {
> + /* Hardware general events (Type #0) */
> + {
> + /* perf: cycles (eidx: 0x1) */
> + .eidx = SBI_PMU_HW_CPU_CYCLES,
> + .select = ANDES_CYCLES
> + },
> + {
> + /* perf: instructions (eidx: 0x2) */
> + .eidx = SBI_PMU_HW_INSTRUCTIONS,
> + .select = ANDES_INSTRET
> + },
> + {
> + /* perf: cache-references (eidx: 0x3) */
> + .eidx = SBI_PMU_HW_CACHE_REFERENCES,
> + .select = ANDES_DCACHE_ACCESS
> + },
> + {
> + /* perf: cache-misses (eidx: 0x4) */
> + .eidx = SBI_PMU_HW_CACHE_MISSES,
> + .select = ANDES_DCACHE_MISS
> + },
> + {
> + /* perf: branches (eidx: 0x5) */
> + .eidx = SBI_PMU_HW_BRANCH_INSTRUCTIONS,
> + .select = ANDES_CONDITION_BR,
> + },
> + {
> + /* perf: branch-misses (eidx: 0x6) */
> + .eidx = SBI_PMU_HW_BRANCH_MISSES,
> + .select = ANDES_MISPREDICT_CONDITION_BR,
> + },
> + /* Hardware cache events (Type #1) */
> + {
> + /* perf: L1-dcache-loads (eidx: 0x10000) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
> + .select = ANDES_DCACHE_LOAD_ACCESS
> + },
> + {
> + /* perf: L1-dcache-loads-misses (eidx: 0x10001) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, MISS),
> + .select = ANDES_DCACHE_LOAD_MISS
> + },
> + {
> + /* perf: L1-dcache-stores (eidx: 0x10002) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, ACCESS),
> + .select = ANDES_DCACHE_STORE_ACCESS
> + },
> + {
> + /* perf: L1-dcache-store-misses (eidx: 0x10003) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
> + .select = ANDES_DCACHE_STORE_MISS
> + },
> + {
> + /* perf: L1-icache-load (eidx: 0x10008) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
> + .select = ANDES_ICACHE_ACCESS
> + },
> + {
> + /* perf: L1-icache-load-misses (eidx: 0x10009) */
> + .eidx = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
> + .select = ANDES_ICACHE_MISS
> + },
> + { /* sentinel */ }
> +};
> +
> +static const struct sbi_pmu_event_counter_map andes45_hw_evt_counters[] = {
> + {
> + /* perf: cycles (eidx: 0x1) */
> + .eidx_start = SBI_PMU_HW_CPU_CYCLES,
> + /* perf: branch-misses (eidx: 0x6) */
> + .eidx_end = SBI_PMU_HW_BRANCH_MISSES,
> + .ctr_map = ANDES_MHPM_MAP,
> + },
> + {
> + /* perf: L1-dcache-loads (eidx: 0x10000) */
> + .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, READ, ACCESS),
> + /* perf: L1-dcache-store-misses (eidx: 0x10003) */
> + .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1D, WRITE, MISS),
> + .ctr_map = ANDES_MHPM_MAP,
> + },
> + {
> + /* perf: L1-icache-load (eidx: 0x10008) */
> + .eidx_start = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, ACCESS),
> + /* perf: L1-icache-load-misses (eidx: 0x10009) */
> + .eidx_end = SBI_PMU_HW_CACHE_EVENT_IDX(L1I, READ, MISS),
> + .ctr_map = ANDES_MHPM_MAP,
> + },
> + { /* sentinel */ }
> +};
> +
> +static const struct sbi_pmu_raw_event_counter_map andes45_raw_evt_counters[] = {
> + {
> + .select = ANDES_CYCLES,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INSTRET,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_LOAD_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_STORE_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_ATOMIC_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_SYS_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_COMPUTE_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CONDITION_BR,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_TAKEN_CONDITION_BR,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_JAL_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_JALR_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_RET_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CONTROL_TRANS_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_EX9_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_MUL_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_DIV_REMAINDER_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_LOAD_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_STORE_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_ADD_SUB_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_MUL_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_FUSED_MULADD_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_FLOAT_DIV_SQUARE_ROOT_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_OTHER_FLOAT_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_INT_MUL_AND_SUB_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_RETIRED_OP,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_ILM_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DLM_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_ICACHE_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_ICACHE_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_LOAD_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_LOAD_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_STORE_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_STORE_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_DCACHE_WB,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_ICACHE_FILL,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_DCACHE_FILL,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_UNCACHED_IFETCH_FROM_BUS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_UNCACHED_LOAD_FROM_BUS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_UNCACHED_IFETCH,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_UNCACHED_LOAD,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MAIN_ITLB_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MAIN_ITLB_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MAIN_DTLB_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MAIN_DTLB_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_CYCLE_WAIT_ITLB_FILL,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_PIPE_STALL_CYCLE_DTLB_MISS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_HW_PREFETCH_BUS_ACCESS,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MISPREDICT_CONDITION_BR,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MISPREDICT_TAKE_CONDITION_BR,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + {
> + .select = ANDES_MISPREDICT_TARGET_RET_INST,
> + .select_mask = ANDES_RAW_EVENT_MASK,
> + .ctr_map = ANDES_MHPM_MAP
> + },
> + { /* sentinel */ }
> +};
> +
> +int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match)
> +{
> + /*
> + * At the moment, simply create mapping for any 45-series core
> + * based on marchid, we may check and differentiate the mapping
> + * by mimpid.
> + */
> + if (is_andes(45))
> + return fdt_add_pmu_mappings(fdt, andes45_hw_evt_selects,
> + andes45_hw_evt_counters,
> + andes45_raw_evt_counters);
This approach is an overkill because you are creating an FDT node at
boot-time which is later parsed by fdt_pmu_setup().
Instead, I would suggest to:
1) Drop PATCH7
2) Directly populate HW counters and event mappings over here
in the same way as fdt_pmu_setup() for your andes 45-series
> +
> + return 0;
> +}
> diff --git a/platform/generic/andes/objects.mk b/platform/generic/andes/objects.mk
> index 6a8c66c..57caaf6 100644
> --- a/platform/generic/andes/objects.mk
> +++ b/platform/generic/andes/objects.mk
> @@ -8,3 +8,4 @@ platform-objs-$(CONFIG_PLATFORM_ANDES_AE350) += andes/ae350.o andes/sleep.o
> platform-objs-$(CONFIG_ANDES45_PMA) += andes/andes45-pma.o
> platform-objs-$(CONFIG_ANDES_SBI) += andes/andes_sbi.o
> platform-objs-$(CONFIG_ANDES_PMU) += andes/andes_pmu.o
> +platform-objs-$(CONFIG_ANDES_HPM) += andes/andes_hpm.o
> diff --git a/platform/generic/include/andes/andes_hpm.h b/platform/generic/include/andes/andes_hpm.h
> new file mode 100644
> index 0000000..0f301db
> --- /dev/null
> +++ b/platform/generic/include/andes/andes_hpm.h
> @@ -0,0 +1,83 @@
> +/*
> + * SPDX-License-Identifier: BSD-2-Clause
> + *
> + * Copyright (c) 2023 Andes Technology Corporation
> + */
> +
> +#ifndef _ANDES_HPM_H_
> +#define _ANDES_HPM_H_
> +
> +#include <sbi_utils/fdt/fdt_helper.h>
> +
> +#define ANDES_MHPM_MAP 0x78
> +#define ANDES_RAW_EVENT_MASK ~0ULL
> +
> +/* Event code for instruction commit events */
> +#define ANDES_CYCLES 0x10
> +#define ANDES_INSTRET 0x20
> +#define ANDES_INT_LOAD_INST 0x30
> +#define ANDES_INT_STORE_INST 0x40
> +#define ANDES_ATOMIC_INST 0x50
> +#define ANDES_SYS_INST 0x60
> +#define ANDES_INT_COMPUTE_INST 0x70
> +#define ANDES_CONDITION_BR 0x80
> +#define ANDES_TAKEN_CONDITION_BR 0x90
> +#define ANDES_JAL_INST 0xA0
> +#define ANDES_JALR_INST 0xB0
> +#define ANDES_RET_INST 0xC0
> +#define ANDES_CONTROL_TRANS_INST 0xD0
> +#define ANDES_EX9_INST 0xE0
> +#define ANDES_INT_MUL_INST 0xF0
> +#define ANDES_INT_DIV_REMAINDER_INST 0x100
> +#define ANDES_FLOAT_LOAD_INST 0x110
> +#define ANDES_FLOAT_STORE_INST 0x120
> +#define ANDES_FLOAT_ADD_SUB_INST 0x130
> +#define ANDES_FLOAT_MUL_INST 0x140
> +#define ANDES_FLOAT_FUSED_MULADD_INST 0x150
> +#define ANDES_FLOAT_DIV_SQUARE_ROOT_INST 0x160
> +#define ANDES_OTHER_FLOAT_INST 0x170
> +#define ANDES_INT_MUL_AND_SUB_INST 0x180
> +#define ANDES_RETIRED_OP 0x190
> +
> +/* Event code for memory system events */
> +#define ANDES_ILM_ACCESS 0x01
> +#define ANDES_DLM_ACCESS 0x11
> +#define ANDES_ICACHE_ACCESS 0x21
> +#define ANDES_ICACHE_MISS 0x31
> +#define ANDES_DCACHE_ACCESS 0x41
> +#define ANDES_DCACHE_MISS 0x51
> +#define ANDES_DCACHE_LOAD_ACCESS 0x61
> +#define ANDES_DCACHE_LOAD_MISS 0x71
> +#define ANDES_DCACHE_STORE_ACCESS 0x81
> +#define ANDES_DCACHE_STORE_MISS 0x91
> +#define ANDES_DCACHE_WB 0xA1
> +#define ANDES_CYCLE_WAIT_ICACHE_FILL 0xB1
> +#define ANDES_CYCLE_WAIT_DCACHE_FILL 0xC1
> +#define ANDES_UNCACHED_IFETCH_FROM_BUS 0xD1
> +#define ANDES_UNCACHED_LOAD_FROM_BUS 0xE1
> +#define ANDES_CYCLE_WAIT_UNCACHED_IFETCH 0xF1
> +#define ANDES_CYCLE_WAIT_UNCACHED_LOAD 0x101
> +#define ANDES_MAIN_ITLB_ACCESS 0x111
> +#define ANDES_MAIN_ITLB_MISS 0x121
> +#define ANDES_MAIN_DTLB_ACCESS 0x131
> +#define ANDES_MAIN_DTLB_MISS 0x141
> +#define ANDES_CYCLE_WAIT_ITLB_FILL 0x151
> +#define ANDES_PIPE_STALL_CYCLE_DTLB_MISS 0x161
> +#define ANDES_HW_PREFETCH_BUS_ACCESS 0x171
> +
> +/* Event code for microarchitecture events */
> +#define ANDES_MISPREDICT_CONDITION_BR 0x02
> +#define ANDES_MISPREDICT_TAKE_CONDITION_BR 0x12
> +#define ANDES_MISPREDICT_TARGET_RET_INST 0x22
> +
> +#ifdef CONFIG_ANDES_HPM
> +
> +int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match);
> +
> +#else
> +
> +int andes_fdt_add_pmu_mappings(void *fdt, const struct fdt_match *match) { return 0; }
> +
> +#endif /* CONFIG_ANDES_HPM */
> +
> +#endif /* _ANDES_HPM_H_ */
> diff --git a/platform/generic/renesas/rzfive/rzfive.c b/platform/generic/renesas/rzfive/rzfive.c
> index 2f772c8..fafbff0 100644
> --- a/platform/generic/renesas/rzfive/rzfive.c
> +++ b/platform/generic/renesas/rzfive/rzfive.c
> @@ -5,6 +5,7 @@
> */
>
> #include <andes/andes45_pma.h>
> +#include <andes/andes_hpm.h>
> #include <andes/andes_pmu.h>
> #include <andes/andes_sbi.h>
> #include <platform_override.h>
> @@ -69,6 +70,7 @@ const struct platform_override renesas_rzfive = {
> .match_table = renesas_rzfive_match,
> .early_init = renesas_rzfive_early_init,
> .final_init = renesas_rzfive_final_init,
> + .fdt_add_pmu_mappings = andes_fdt_add_pmu_mappings,
> .vendor_ext_provider = andes_sbi_vendor_ext_provider,
> .extensions_init = renesas_rzfive_extensions_init,
> };
> --
> 2.34.1
>
Regards,
Anup
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 11/11] docs: pmu: Add Andes PMU node example
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
` (9 preceding siblings ...)
2023-10-19 11:37 ` [PATCH v2 10/11] platform: andes: Implement andes_fdt_add_pmu_mappings platform override Yu Chien Peter Lin
@ 2023-10-19 11:37 ` Yu Chien Peter Lin
2023-11-16 7:00 ` Anup Patel
2023-11-16 7:01 ` [PATCH v2 00/11] Add Andes PMU extension support Anup Patel
11 siblings, 1 reply; 27+ messages in thread
From: Yu Chien Peter Lin @ 2023-10-19 11:37 UTC (permalink / raw)
To: opensbi
Add PMU node example for event index to counter index mapping
and selector value translation of Andes' CPUs.
Currently, there are 4 HPM counters that can be used to monitor
all of the events for each hart.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Reviewed-by: Locus Wei-Han Chen <locus84@andestech.com>
Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---
Changes v1 -> v2:
- sync up with datasheet
---
docs/pmu_support.md | 82 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 82 insertions(+)
diff --git a/docs/pmu_support.md b/docs/pmu_support.md
index 8cfa08c..9b48f1e 100644
--- a/docs/pmu_support.md
+++ b/docs/pmu_support.md
@@ -125,3 +125,85 @@ pmu {
<0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
};
```
+
+### Example 3
+
+```
+/*
+ * For Andes 45-series platforms. The encodings can be found in the
+ * "Machine Performance Monitoring Event Selector" section
+ * http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+ */
+pmu {
+ compatible = "riscv,pmu";
+ riscv,event-to-mhpmevent =
+ <0x1 0x0000 0x10>, /* CPU_CYCLES -> Cycle count */
+ <0x2 0x0000 0x20>, /* INSTRUCTIONS -> Retired instruction count */
+ <0x3 0x0000 0x41>, /* CACHE_REFERENCES -> D-Cache access */
+ <0x4 0x0000 0x51>, /* CACHE_MISSES -> D-Cache miss */
+ <0x5 0x0000 0x80>, /* BRANCH_INSTRUCTIONS -> Conditional branch instruction count */
+ <0x6 0x0000 0x02>, /* BRANCH_MISSES -> Misprediction of conditional branches */
+ <0x10000 0x0000 0x61>, /* L1D_READ_ACCESS -> D-Cache load access */
+ <0x10001 0x0000 0x71>, /* L1D_READ_MISS -> D-Cache load miss */
+ <0x10002 0x0000 0x81>, /* L1D_WRITE_ACCESS -> D-Cache store access */
+ <0x10003 0x0000 0x91>, /* L1D_WRITE_MISS -> D-Cache store miss */
+ <0x10008 0x0000 0x21>, /* L1I_READ_ACCESS -> I-Cache access */
+ <0x10009 0x0000 0x31>; /* L1I_READ_MISS -> I-Cache miss */
+ riscv,event-to-mhpmcounters = <0x1 0x6 0x78>,
+ <0x10000 0x10003 0x78>,
+ <0x10008 0x10009 0x78>;
+ riscv,raw-event-to-mhpmcounters =
+ <0x0 0x10 0xffffffff 0xffffffff 0x78>, /* Cycle count */
+ <0x0 0x20 0xffffffff 0xffffffff 0x78>, /* Retired instruction count */
+ <0x0 0x30 0xffffffff 0xffffffff 0x78>, /* Integer load instruction count */
+ <0x0 0x40 0xffffffff 0xffffffff 0x78>, /* Integer store instruction count */
+ <0x0 0x50 0xffffffff 0xffffffff 0x78>, /* Atomic instruction count */
+ <0x0 0x60 0xffffffff 0xffffffff 0x78>, /* System instruction count */
+ <0x0 0x70 0xffffffff 0xffffffff 0x78>, /* Integer computational instruction count */
+ <0x0 0x80 0xffffffff 0xffffffff 0x78>, /* Conditional branch instruction count */
+ <0x0 0x90 0xffffffff 0xffffffff 0x78>, /* Taken conditional branch instruction count */
+ <0x0 0xA0 0xffffffff 0xffffffff 0x78>, /* JAL instruction count */
+ <0x0 0xB0 0xffffffff 0xffffffff 0x78>, /* JALR instruction count */
+ <0x0 0xC0 0xffffffff 0xffffffff 0x78>, /* Return instruction count */
+ <0x0 0xD0 0xffffffff 0xffffffff 0x78>, /* Control transfer instruction count */
+ <0x0 0xE0 0xffffffff 0xffffffff 0x78>, /* EXEC.IT instruction count */
+ <0x0 0xF0 0xffffffff 0xffffffff 0x78>, /* Integer multiplication instruction count */
+ <0x0 0x100 0xffffffff 0xffffffff 0x78>, /* Integer division instruction count */
+ <0x0 0x110 0xffffffff 0xffffffff 0x78>, /* Floating-point load instruction count */
+ <0x0 0x120 0xffffffff 0xffffffff 0x78>, /* Floating-point store instruction count */
+ <0x0 0x130 0xffffffff 0xffffffff 0x78>, /* Floating-point addition/subtraction instruction count */
+ <0x0 0x140 0xffffffff 0xffffffff 0x78>, /* Floating-point multiplication instruction count */
+ <0x0 0x150 0xffffffff 0xffffffff 0x78>, /* Floating-point fused multiply-add instruction count */
+ <0x0 0x160 0xffffffff 0xffffffff 0x78>, /* Floating-point division or square-root instruction count */
+ <0x0 0x170 0xffffffff 0xffffffff 0x78>, /* Other floating-point instruction count */
+ <0x0 0x180 0xffffffff 0xffffffff 0x78>, /* Integer multiplication and add/sub instruction count */
+ <0x0 0x190 0xffffffff 0xffffffff 0x78>, /* Retired operation count */
+ <0x0 0x01 0xffffffff 0xffffffff 0x78>, /* ILM access */
+ <0x0 0x11 0xffffffff 0xffffffff 0x78>, /* DLM access */
+ <0x0 0x21 0xffffffff 0xffffffff 0x78>, /* I-Cache access */
+ <0x0 0x31 0xffffffff 0xffffffff 0x78>, /* I-Cache miss */
+ <0x0 0x41 0xffffffff 0xffffffff 0x78>, /* D-Cache access */
+ <0x0 0x51 0xffffffff 0xffffffff 0x78>, /* D-Cache miss */
+ <0x0 0x61 0xffffffff 0xffffffff 0x78>, /* D-Cache load access */
+ <0x0 0x71 0xffffffff 0xffffffff 0x78>, /* D-Cache load miss */
+ <0x0 0x81 0xffffffff 0xffffffff 0x78>, /* D-Cache store access */
+ <0x0 0x91 0xffffffff 0xffffffff 0x78>, /* D-Cache store miss */
+ <0x0 0xA1 0xffffffff 0xffffffff 0x78>, /* D-Cache writeback */
+ <0x0 0xB1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for I-Cache fill data */
+ <0x0 0xC1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for D-Cache fill data */
+ <0x0 0xD1 0xffffffff 0xffffffff 0x78>, /* Uncached fetch data access from bus */
+ <0x0 0xE1 0xffffffff 0xffffffff 0x78>, /* Uncached load data access from bus */
+ <0x0 0xF1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached fetch data from bus */
+ <0x0 0x101 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached load data from bus */
+ <0x0 0x111 0xffffffff 0xffffffff 0x78>, /* Main ITLB access */
+ <0x0 0x121 0xffffffff 0xffffffff 0x78>, /* Main ITLB miss */
+ <0x0 0x131 0xffffffff 0xffffffff 0x78>, /* Main DTLB access */
+ <0x0 0x141 0xffffffff 0xffffffff 0x78>, /* Main DTLB miss */
+ <0x0 0x151 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for Main ITLB fill data */
+ <0x0 0x161 0xffffffff 0xffffffff 0x78>, /* Pipeline stall cycles caused by Main DTLB miss */
+ <0x0 0x171 0xffffffff 0xffffffff 0x78>, /* Hardware prefetch bus access */
+ <0x0 0x02 0xffffffff 0xffffffff 0x78>, /* Misprediction of conditional branches */
+ <0x0 0x12 0xffffffff 0xffffffff 0x78>, /* Misprediction of taken conditional branches */
+ <0x0 0x22 0xffffffff 0xffffffff 0x78>; /* Misprediction of targets of Return instructions */
+};
+```
--
2.34.1
^ permalink raw reply related [flat|nested] 27+ messages in thread* [PATCH v2 11/11] docs: pmu: Add Andes PMU node example
2023-10-19 11:37 ` [PATCH v2 11/11] docs: pmu: Add Andes PMU node example Yu Chien Peter Lin
@ 2023-11-16 7:00 ` Anup Patel
0 siblings, 0 replies; 27+ messages in thread
From: Anup Patel @ 2023-11-16 7:00 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:11?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> Add PMU node example for event index to counter index mapping
> and selector value translation of Andes' CPUs.
>
> Currently, there are 4 HPM counters that can be used to monitor
> all of the events for each hart.
>
> Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> Reviewed-by: Locus Wei-Han Chen <locus84@andestech.com>
> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Looks good to me.
Reviewed-by: Anup Patel <anup@brainfault.org>
Regards,
Anup
> ---
> Changes v1 -> v2:
> - sync up with datasheet
> ---
> docs/pmu_support.md | 82 +++++++++++++++++++++++++++++++++++++++++++++
> 1 file changed, 82 insertions(+)
>
> diff --git a/docs/pmu_support.md b/docs/pmu_support.md
> index 8cfa08c..9b48f1e 100644
> --- a/docs/pmu_support.md
> +++ b/docs/pmu_support.md
> @@ -125,3 +125,85 @@ pmu {
> <0x0 0x2 0xffffffff 0xffffe0ff 0x18>;
> };
> ```
> +
> +### Example 3
> +
> +```
> +/*
> + * For Andes 45-series platforms. The encodings can be found in the
> + * "Machine Performance Monitoring Event Selector" section
> + * http://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
> + */
> +pmu {
> + compatible = "riscv,pmu";
> + riscv,event-to-mhpmevent =
> + <0x1 0x0000 0x10>, /* CPU_CYCLES -> Cycle count */
> + <0x2 0x0000 0x20>, /* INSTRUCTIONS -> Retired instruction count */
> + <0x3 0x0000 0x41>, /* CACHE_REFERENCES -> D-Cache access */
> + <0x4 0x0000 0x51>, /* CACHE_MISSES -> D-Cache miss */
> + <0x5 0x0000 0x80>, /* BRANCH_INSTRUCTIONS -> Conditional branch instruction count */
> + <0x6 0x0000 0x02>, /* BRANCH_MISSES -> Misprediction of conditional branches */
> + <0x10000 0x0000 0x61>, /* L1D_READ_ACCESS -> D-Cache load access */
> + <0x10001 0x0000 0x71>, /* L1D_READ_MISS -> D-Cache load miss */
> + <0x10002 0x0000 0x81>, /* L1D_WRITE_ACCESS -> D-Cache store access */
> + <0x10003 0x0000 0x91>, /* L1D_WRITE_MISS -> D-Cache store miss */
> + <0x10008 0x0000 0x21>, /* L1I_READ_ACCESS -> I-Cache access */
> + <0x10009 0x0000 0x31>; /* L1I_READ_MISS -> I-Cache miss */
> + riscv,event-to-mhpmcounters = <0x1 0x6 0x78>,
> + <0x10000 0x10003 0x78>,
> + <0x10008 0x10009 0x78>;
> + riscv,raw-event-to-mhpmcounters =
> + <0x0 0x10 0xffffffff 0xffffffff 0x78>, /* Cycle count */
> + <0x0 0x20 0xffffffff 0xffffffff 0x78>, /* Retired instruction count */
> + <0x0 0x30 0xffffffff 0xffffffff 0x78>, /* Integer load instruction count */
> + <0x0 0x40 0xffffffff 0xffffffff 0x78>, /* Integer store instruction count */
> + <0x0 0x50 0xffffffff 0xffffffff 0x78>, /* Atomic instruction count */
> + <0x0 0x60 0xffffffff 0xffffffff 0x78>, /* System instruction count */
> + <0x0 0x70 0xffffffff 0xffffffff 0x78>, /* Integer computational instruction count */
> + <0x0 0x80 0xffffffff 0xffffffff 0x78>, /* Conditional branch instruction count */
> + <0x0 0x90 0xffffffff 0xffffffff 0x78>, /* Taken conditional branch instruction count */
> + <0x0 0xA0 0xffffffff 0xffffffff 0x78>, /* JAL instruction count */
> + <0x0 0xB0 0xffffffff 0xffffffff 0x78>, /* JALR instruction count */
> + <0x0 0xC0 0xffffffff 0xffffffff 0x78>, /* Return instruction count */
> + <0x0 0xD0 0xffffffff 0xffffffff 0x78>, /* Control transfer instruction count */
> + <0x0 0xE0 0xffffffff 0xffffffff 0x78>, /* EXEC.IT instruction count */
> + <0x0 0xF0 0xffffffff 0xffffffff 0x78>, /* Integer multiplication instruction count */
> + <0x0 0x100 0xffffffff 0xffffffff 0x78>, /* Integer division instruction count */
> + <0x0 0x110 0xffffffff 0xffffffff 0x78>, /* Floating-point load instruction count */
> + <0x0 0x120 0xffffffff 0xffffffff 0x78>, /* Floating-point store instruction count */
> + <0x0 0x130 0xffffffff 0xffffffff 0x78>, /* Floating-point addition/subtraction instruction count */
> + <0x0 0x140 0xffffffff 0xffffffff 0x78>, /* Floating-point multiplication instruction count */
> + <0x0 0x150 0xffffffff 0xffffffff 0x78>, /* Floating-point fused multiply-add instruction count */
> + <0x0 0x160 0xffffffff 0xffffffff 0x78>, /* Floating-point division or square-root instruction count */
> + <0x0 0x170 0xffffffff 0xffffffff 0x78>, /* Other floating-point instruction count */
> + <0x0 0x180 0xffffffff 0xffffffff 0x78>, /* Integer multiplication and add/sub instruction count */
> + <0x0 0x190 0xffffffff 0xffffffff 0x78>, /* Retired operation count */
> + <0x0 0x01 0xffffffff 0xffffffff 0x78>, /* ILM access */
> + <0x0 0x11 0xffffffff 0xffffffff 0x78>, /* DLM access */
> + <0x0 0x21 0xffffffff 0xffffffff 0x78>, /* I-Cache access */
> + <0x0 0x31 0xffffffff 0xffffffff 0x78>, /* I-Cache miss */
> + <0x0 0x41 0xffffffff 0xffffffff 0x78>, /* D-Cache access */
> + <0x0 0x51 0xffffffff 0xffffffff 0x78>, /* D-Cache miss */
> + <0x0 0x61 0xffffffff 0xffffffff 0x78>, /* D-Cache load access */
> + <0x0 0x71 0xffffffff 0xffffffff 0x78>, /* D-Cache load miss */
> + <0x0 0x81 0xffffffff 0xffffffff 0x78>, /* D-Cache store access */
> + <0x0 0x91 0xffffffff 0xffffffff 0x78>, /* D-Cache store miss */
> + <0x0 0xA1 0xffffffff 0xffffffff 0x78>, /* D-Cache writeback */
> + <0x0 0xB1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for I-Cache fill data */
> + <0x0 0xC1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for D-Cache fill data */
> + <0x0 0xD1 0xffffffff 0xffffffff 0x78>, /* Uncached fetch data access from bus */
> + <0x0 0xE1 0xffffffff 0xffffffff 0x78>, /* Uncached load data access from bus */
> + <0x0 0xF1 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached fetch data from bus */
> + <0x0 0x101 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for uncached load data from bus */
> + <0x0 0x111 0xffffffff 0xffffffff 0x78>, /* Main ITLB access */
> + <0x0 0x121 0xffffffff 0xffffffff 0x78>, /* Main ITLB miss */
> + <0x0 0x131 0xffffffff 0xffffffff 0x78>, /* Main DTLB access */
> + <0x0 0x141 0xffffffff 0xffffffff 0x78>, /* Main DTLB miss */
> + <0x0 0x151 0xffffffff 0xffffffff 0x78>, /* Cycles waiting for Main ITLB fill data */
> + <0x0 0x161 0xffffffff 0xffffffff 0x78>, /* Pipeline stall cycles caused by Main DTLB miss */
> + <0x0 0x171 0xffffffff 0xffffffff 0x78>, /* Hardware prefetch bus access */
> + <0x0 0x02 0xffffffff 0xffffffff 0x78>, /* Misprediction of conditional branches */
> + <0x0 0x12 0xffffffff 0xffffffff 0x78>, /* Misprediction of taken conditional branches */
> + <0x0 0x22 0xffffffff 0xffffffff 0x78>; /* Misprediction of targets of Return instructions */
> +};
> +```
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread
* [PATCH v2 00/11] Add Andes PMU extension support
2023-10-19 11:37 [PATCH v2 00/11] Add Andes PMU extension support Yu Chien Peter Lin
` (10 preceding siblings ...)
2023-10-19 11:37 ` [PATCH v2 11/11] docs: pmu: Add Andes PMU node example Yu Chien Peter Lin
@ 2023-11-16 7:01 ` Anup Patel
2023-11-21 7:44 ` Yu-Chien Peter Lin
11 siblings, 1 reply; 27+ messages in thread
From: Anup Patel @ 2023-11-16 7:01 UTC (permalink / raw)
To: opensbi
On Thu, Oct 19, 2023 at 5:10?PM Yu Chien Peter Lin
<peterlin@andestech.com> wrote:
>
> This patch series enables perf tool to utilize Andes PMU
> extension via PMU SBI calls, provides PMU device callbacks
> to achieve event sampling and mode filtering.
>
> This version also introduces a platform override fdt_add_pmu_mappings()
> to create event mappings before PMU setup if a valid PMU node
> is missing.
>
> The last patch provides a PMU node example used on AX45MP cores.
>
> The OpenSBI and Linux patches can be found on Andes Technology GitHub
> - https://github.com/andestech/opensbi/commits/andes-pmu-support-v2
> - https://github.com/andestech/linux/commits/andes-pmu-support-v2
>
> Yu Chien Peter Lin (11):
> sbi: sbi_pmu: Improve sbi_pmu_init() error handling
> sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
> platform: include: andes45: Add PMU related CSR defines
> platform: andes: Add Andes custom PMU support
> platform: andes: Enable Andes PMU for AE350
> platform: rzfive: Enable Andes PMU for RZ/Five
> lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function
> lib: utils: fdt_fixup: Allow preserving PMU properties
> platform: andes: Factor out is_andes() helper
> platform: andes: Implement andes_fdt_add_pmu_mappings platform
> override
> docs: pmu: Add Andes PMU node example
It would be great to have v3 sooner because next month we
have OpenSBI v1.4 release.
Regards,
Anup
>
> docs/pmu_support.md | 82 ++++
> include/sbi/sbi_ecall_interface.h | 5 +
> include/sbi/sbi_pmu.h | 6 +
> include/sbi/sbi_scratch.h | 2 +
> include/sbi_utils/fdt/fdt_fixup.h | 48 +++
> lib/sbi/sbi_pmu.c | 10 +-
> lib/utils/fdt/fdt_fixup.c | 101 ++++-
> lib/utils/fdt/fdt_pmu.c | 2 +-
> platform/generic/Kconfig | 4 +
> platform/generic/andes/Kconfig | 11 +
> platform/generic/andes/ae350.c | 31 +-
> platform/generic/andes/andes_hpm.c | 381 +++++++++++++++++++
> platform/generic/andes/andes_pmu.c | 81 ++++
> platform/generic/andes/objects.mk | 2 +
> platform/generic/include/andes/andes45.h | 32 ++
> platform/generic/include/andes/andes_hpm.h | 83 ++++
> platform/generic/include/andes/andes_pmu.h | 8 +
> platform/generic/include/platform_override.h | 1 +
> platform/generic/platform.c | 16 +-
> platform/generic/renesas/rzfive/rzfive.c | 18 +-
> 20 files changed, 909 insertions(+), 15 deletions(-)
> create mode 100644 platform/generic/andes/andes_hpm.c
> create mode 100644 platform/generic/andes/andes_pmu.c
> create mode 100644 platform/generic/include/andes/andes_hpm.h
> create mode 100644 platform/generic/include/andes/andes_pmu.h
>
> --
> 2.34.1
>
^ permalink raw reply [flat|nested] 27+ messages in thread* [PATCH v2 00/11] Add Andes PMU extension support
2023-11-16 7:01 ` [PATCH v2 00/11] Add Andes PMU extension support Anup Patel
@ 2023-11-21 7:44 ` Yu-Chien Peter Lin
0 siblings, 0 replies; 27+ messages in thread
From: Yu-Chien Peter Lin @ 2023-11-21 7:44 UTC (permalink / raw)
To: opensbi
Hi Anup,
On Thu, Nov 16, 2023 at 12:31:03PM +0530, Anup Patel wrote:
> On Thu, Oct 19, 2023 at 5:10?PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > This patch series enables perf tool to utilize Andes PMU
> > extension via PMU SBI calls, provides PMU device callbacks
> > to achieve event sampling and mode filtering.
> >
> > This version also introduces a platform override fdt_add_pmu_mappings()
> > to create event mappings before PMU setup if a valid PMU node
> > is missing.
> >
> > The last patch provides a PMU node example used on AX45MP cores.
> >
> > The OpenSBI and Linux patches can be found on Andes Technology GitHub
> > - https://github.com/andestech/opensbi/commits/andes-pmu-support-v2
> > - https://github.com/andestech/linux/commits/andes-pmu-support-v2
> >
> > Yu Chien Peter Lin (11):
> > sbi: sbi_pmu: Improve sbi_pmu_init() error handling
> > sbi: sbi_pmu: Add hw_counter_filter_mode() to pmu device
> > platform: include: andes45: Add PMU related CSR defines
> > platform: andes: Add Andes custom PMU support
> > platform: andes: Enable Andes PMU for AE350
> > platform: rzfive: Enable Andes PMU for RZ/Five
> > lib: utils: fdt_fixup: Add fdt_add_pmu_mappings() helper function
> > lib: utils: fdt_fixup: Allow preserving PMU properties
> > platform: andes: Factor out is_andes() helper
> > platform: andes: Implement andes_fdt_add_pmu_mappings platform
> > override
> > docs: pmu: Add Andes PMU node example
>
> It would be great to have v3 sooner because next month we
> have OpenSBI v1.4 release.
>
> Regards,
> Anup
Thanks for the comments on the series, I will update accordingly
and submit the next version soon.
Best regards,
Peter Lin
> >
> > docs/pmu_support.md | 82 ++++
> > include/sbi/sbi_ecall_interface.h | 5 +
> > include/sbi/sbi_pmu.h | 6 +
> > include/sbi/sbi_scratch.h | 2 +
> > include/sbi_utils/fdt/fdt_fixup.h | 48 +++
> > lib/sbi/sbi_pmu.c | 10 +-
> > lib/utils/fdt/fdt_fixup.c | 101 ++++-
> > lib/utils/fdt/fdt_pmu.c | 2 +-
> > platform/generic/Kconfig | 4 +
> > platform/generic/andes/Kconfig | 11 +
> > platform/generic/andes/ae350.c | 31 +-
> > platform/generic/andes/andes_hpm.c | 381 +++++++++++++++++++
> > platform/generic/andes/andes_pmu.c | 81 ++++
> > platform/generic/andes/objects.mk | 2 +
> > platform/generic/include/andes/andes45.h | 32 ++
> > platform/generic/include/andes/andes_hpm.h | 83 ++++
> > platform/generic/include/andes/andes_pmu.h | 8 +
> > platform/generic/include/platform_override.h | 1 +
> > platform/generic/platform.c | 16 +-
> > platform/generic/renesas/rzfive/rzfive.c | 18 +-
> > 20 files changed, 909 insertions(+), 15 deletions(-)
> > create mode 100644 platform/generic/andes/andes_hpm.c
> > create mode 100644 platform/generic/andes/andes_pmu.c
> > create mode 100644 platform/generic/include/andes/andes_hpm.h
> > create mode 100644 platform/generic/include/andes/andes_pmu.h
> >
> > --
> > 2.34.1
> >
^ permalink raw reply [flat|nested] 27+ messages in thread