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From: Wolfram Sang <wsa@kernel.org>
To: Camel Guo <camel.guo@axis.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Alim Akhtar <alim.akhtar@samsung.com>,
	linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	kernel@axis.com
Subject: Re: [PATCH] i2c: exynos5: Calculate t_scl_l, t_scl_h according to i2c spec
Date: Mon, 23 Oct 2023 17:12:40 +0200	[thread overview]
Message-ID: <ZTaNaH8qo3Ho+yvL@ninjato> (raw)
In-Reply-To: <20220912085943.1098651-1-camel.guo@axis.com>

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On Mon, Sep 12, 2022 at 10:59:43AM +0200, Camel Guo wrote:
> Previously the duty cycle was divided equally into h_scl_l, t_scl_h.
> This makes the low period of the SCL clock in Fast Mode is only 1.25us
> which is way lower than the minimal value (1.3) specified in i2c
> specification. In order to make sure t_scl_l, t_scl_h always fullfill
> i2c specification, this commit calculates t_scl_l using this formula:
> 
> t_scl_l = clk_cycle *
>     ((t_low_min + (scl_clock - t_low_min - t_high_min) / 2) / scl_clock)
> 
> where:
> t_low_min is the minimal value of low period of the SCL clock in us;
> t_high_min is the minimal value of high period of the SCL clock in us;
> scl_clock is converted from SCL clock frequency into us.
> 
> Signed-off-by: Camel Guo <camel.guo@axis.com>

Applied to for-next, thanks!


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WARNING: multiple messages have this Message-ID (diff)
From: Wolfram Sang <wsa@kernel.org>
To: Camel Guo <camel.guo@axis.com>
Cc: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>,
	Alim Akhtar <alim.akhtar@samsung.com>,
	linux-i2c@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	linux-samsung-soc@vger.kernel.org, linux-kernel@vger.kernel.org,
	kernel@axis.com
Subject: Re: [PATCH] i2c: exynos5: Calculate t_scl_l, t_scl_h according to i2c spec
Date: Mon, 23 Oct 2023 17:12:40 +0200	[thread overview]
Message-ID: <ZTaNaH8qo3Ho+yvL@ninjato> (raw)
In-Reply-To: <20220912085943.1098651-1-camel.guo@axis.com>


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On Mon, Sep 12, 2022 at 10:59:43AM +0200, Camel Guo wrote:
> Previously the duty cycle was divided equally into h_scl_l, t_scl_h.
> This makes the low period of the SCL clock in Fast Mode is only 1.25us
> which is way lower than the minimal value (1.3) specified in i2c
> specification. In order to make sure t_scl_l, t_scl_h always fullfill
> i2c specification, this commit calculates t_scl_l using this formula:
> 
> t_scl_l = clk_cycle *
>     ((t_low_min + (scl_clock - t_low_min - t_high_min) / 2) / scl_clock)
> 
> where:
> t_low_min is the minimal value of low period of the SCL clock in us;
> t_high_min is the minimal value of high period of the SCL clock in us;
> scl_clock is converted from SCL clock frequency into us.
> 
> Signed-off-by: Camel Guo <camel.guo@axis.com>

Applied to for-next, thanks!


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  parent reply	other threads:[~2023-10-23 15:12 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <CGME20231023103421eucas1p2f1415d69dd979036ef8bcb1a2dc88978@eucas1p2.samsung.com>
2022-09-12  8:59 ` [PATCH] i2c: exynos5: Calculate t_scl_l, t_scl_h according to i2c spec Camel Guo
2022-09-12  8:59   ` Camel Guo
2023-10-23 10:34   ` Marek Szyprowski
2023-10-23 10:34     ` Marek Szyprowski
2023-10-23 14:06     ` Jesper Nilsson
2023-10-23 14:06       ` Jesper Nilsson
2023-10-23 15:11       ` Wolfram Sang
2023-10-23 15:11         ` Wolfram Sang
2023-10-23 15:12   ` Wolfram Sang [this message]
2023-10-23 15:12     ` Wolfram Sang

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