* [PATCH] riscv: dts: thead: convert isa detection to new properties
@ 2023-10-22 15:41 ` Jisheng Zhang
0 siblings, 0 replies; 7+ messages in thread
From: Jisheng Zhang @ 2023-10-22 15:41 UTC (permalink / raw)
To: soc; +Cc: linux-riscv, Conor Dooley, Guo Ren
From: Conor Dooley <conor.dooley@microchip.com>
Convert the th1520 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Hi Arnd,
This is the only one thead patch for v6.7, could you please apply it
directly?
Thanks in advance
arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ce708183b6f6..723f65487246 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -41,6 +44,9 @@ c910_1: cpu@1 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -62,6 +68,9 @@ c910_2: cpu@2 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -83,6 +92,9 @@ c910_3: cpu@3 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
--
2.40.0
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 7+ messages in thread* [PATCH] riscv: dts: thead: convert isa detection to new properties
@ 2023-10-22 15:41 ` Jisheng Zhang
0 siblings, 0 replies; 7+ messages in thread
From: Jisheng Zhang @ 2023-10-22 15:41 UTC (permalink / raw)
To: soc; +Cc: linux-riscv, Conor Dooley, Guo Ren
From: Conor Dooley <conor.dooley@microchip.com>
Convert the th1520 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
Acked-by: Guo Ren <guoren@kernel.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
Hi Arnd,
This is the only one thead patch for v6.7, could you please apply it
directly?
Thanks in advance
arch/riscv/boot/dts/thead/th1520.dtsi | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/arch/riscv/boot/dts/thead/th1520.dtsi b/arch/riscv/boot/dts/thead/th1520.dtsi
index ce708183b6f6..723f65487246 100644
--- a/arch/riscv/boot/dts/thead/th1520.dtsi
+++ b/arch/riscv/boot/dts/thead/th1520.dtsi
@@ -20,6 +20,9 @@ c910_0: cpu@0 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <0>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -41,6 +44,9 @@ c910_1: cpu@1 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <1>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -62,6 +68,9 @@ c910_2: cpu@2 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <2>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
@@ -83,6 +92,9 @@ c910_3: cpu@3 {
compatible = "thead,c910", "riscv";
device_type = "cpu";
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
reg = <3>;
i-cache-block-size = <64>;
i-cache-size = <65536>;
--
2.40.0
^ permalink raw reply related [flat|nested] 7+ messages in thread* Re: [PATCH] riscv: dts: thead: convert isa detection to new properties
2023-10-22 15:41 ` Jisheng Zhang
@ 2023-10-23 8:27 ` Conor Dooley
-1 siblings, 0 replies; 7+ messages in thread
From: Conor Dooley @ 2023-10-23 8:27 UTC (permalink / raw)
To: Jisheng Zhang; +Cc: soc, linux-riscv, Conor Dooley, Guo Ren
[-- Attachment #1.1: Type: text/plain, Size: 647 bytes --]
On Sun, Oct 22, 2023 at 11:41:35PM +0800, Jisheng Zhang wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Convert the th1520 devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
>
> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> Acked-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>
> Hi Arnd,
>
> This is the only one thead patch for v6.7, could you please apply it
> directly?
FYI, this is missing your signoff, since you are resending my patch.
Cheers,
Conor.
[-- Attachment #1.2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
[-- Attachment #2: Type: text/plain, Size: 161 bytes --]
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv: dts: thead: convert isa detection to new properties
@ 2023-10-23 8:27 ` Conor Dooley
0 siblings, 0 replies; 7+ messages in thread
From: Conor Dooley @ 2023-10-23 8:27 UTC (permalink / raw)
To: Jisheng Zhang; +Cc: soc, linux-riscv, Conor Dooley, Guo Ren
[-- Attachment #1: Type: text/plain, Size: 647 bytes --]
On Sun, Oct 22, 2023 at 11:41:35PM +0800, Jisheng Zhang wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Convert the th1520 devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
>
> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> Acked-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> ---
>
> Hi Arnd,
>
> This is the only one thead patch for v6.7, could you please apply it
> directly?
FYI, this is missing your signoff, since you are resending my patch.
Cheers,
Conor.
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv: dts: thead: convert isa detection to new properties
2023-10-23 8:27 ` Conor Dooley
@ 2023-10-23 16:48 ` Jisheng Zhang
-1 siblings, 0 replies; 7+ messages in thread
From: Jisheng Zhang @ 2023-10-23 16:48 UTC (permalink / raw)
To: Conor Dooley; +Cc: soc, linux-riscv, Conor Dooley, Guo Ren
On Mon, Oct 23, 2023 at 09:27:07AM +0100, Conor Dooley wrote:
> On Sun, Oct 22, 2023 at 11:41:35PM +0800, Jisheng Zhang wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > Convert the th1520 devicetrees to use the new properties
> > "riscv,isa-base" & "riscv,isa-extensions".
> > For compatibility with other projects, "riscv,isa" remains.
> >
> > Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> > Acked-by: Guo Ren <guoren@kernel.org>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >
> > Hi Arnd,
> >
> > This is the only one thead patch for v6.7, could you please apply it
> > directly?
>
> FYI, this is missing your signoff, since you are resending my patch.
>
Hi Conor,
Today I noticed that Arnd has tagged for-next for 6.7, so I guess I
missed the 6.7 PR, sorry. And I also noticed that Arnd has queued the
thead dma-noncoherent patch for 6.7(which is expected in rc7 :) because
I didn't explictly mark the target. I will take care this kind of
PR/directly_merge target in future.
I expected a large dt and driver changes in the comming development window,
for example, usb/eth/emmc and so on, so I'll queue your patch into my
for-next tree once linux6.7-rc1 is released.
Thanks
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv: dts: thead: convert isa detection to new properties
@ 2023-10-23 16:48 ` Jisheng Zhang
0 siblings, 0 replies; 7+ messages in thread
From: Jisheng Zhang @ 2023-10-23 16:48 UTC (permalink / raw)
To: Conor Dooley; +Cc: soc, linux-riscv, Conor Dooley, Guo Ren
On Mon, Oct 23, 2023 at 09:27:07AM +0100, Conor Dooley wrote:
> On Sun, Oct 22, 2023 at 11:41:35PM +0800, Jisheng Zhang wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> >
> > Convert the th1520 devicetrees to use the new properties
> > "riscv,isa-base" & "riscv,isa-extensions".
> > For compatibility with other projects, "riscv,isa" remains.
> >
> > Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> > Acked-by: Guo Ren <guoren@kernel.org>
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> >
> > Hi Arnd,
> >
> > This is the only one thead patch for v6.7, could you please apply it
> > directly?
>
> FYI, this is missing your signoff, since you are resending my patch.
>
Hi Conor,
Today I noticed that Arnd has tagged for-next for 6.7, so I guess I
missed the 6.7 PR, sorry. And I also noticed that Arnd has queued the
thead dma-noncoherent patch for 6.7(which is expected in rc7 :) because
I didn't explictly mark the target. I will take care this kind of
PR/directly_merge target in future.
I expected a large dt and driver changes in the comming development window,
for example, usb/eth/emmc and so on, so I'll queue your patch into my
for-next tree once linux6.7-rc1 is released.
Thanks
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [PATCH] riscv: dts: thead: convert isa detection to new properties
2023-10-22 15:41 ` Jisheng Zhang
(?)
(?)
@ 2023-10-23 19:30 ` patchwork-bot+linux-soc
-1 siblings, 0 replies; 7+ messages in thread
From: patchwork-bot+linux-soc @ 2023-10-23 19:30 UTC (permalink / raw)
To: Jisheng Zhang; +Cc: soc
Hello:
This patch was applied to soc/soc.git (for-next)
by Arnd Bergmann <arnd@arndb.de>:
On Sun, 22 Oct 2023 23:41:35 +0800 you wrote:
> From: Conor Dooley <conor.dooley@microchip.com>
>
> Convert the th1520 devicetrees to use the new properties
> "riscv,isa-base" & "riscv,isa-extensions".
> For compatibility with other projects, "riscv,isa" remains.
>
> Reviewed-by: Jisheng Zhang <jszhang@kernel.org>
> Acked-by: Guo Ren <guoren@kernel.org>
> Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
>
> [...]
Here is the summary with links:
- riscv: dts: thead: convert isa detection to new properties
https://git.kernel.org/soc/soc/c/0804f3bec9e9
You are awesome, thank you!
--
Deet-doot-dot, I am a bot.
https://korg.docs.kernel.org/patchwork/pwbot.html
^ permalink raw reply [flat|nested] 7+ messages in thread
end of thread, other threads:[~2023-10-23 19:30 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-22 15:41 [PATCH] riscv: dts: thead: convert isa detection to new properties Jisheng Zhang
2023-10-22 15:41 ` Jisheng Zhang
2023-10-23 8:27 ` Conor Dooley
2023-10-23 8:27 ` Conor Dooley
2023-10-23 16:48 ` Jisheng Zhang
2023-10-23 16:48 ` Jisheng Zhang
2023-10-23 19:30 ` patchwork-bot+linux-soc
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