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From: "Roger Pau Monné" <roger.pau@citrix.com>
To: Jan Beulich <jbeulich@suse.com>
Cc: "xen-devel@lists.xenproject.org" <xen-devel@lists.xenproject.org>,
	Andrew Cooper <andrew.cooper3@citrix.com>, Wei Liu <wl@xen.org>
Subject: Re: [PATCH 2/7] x86: don't allow Dom0 access to port 92
Date: Wed, 25 Oct 2023 14:49:44 +0200	[thread overview]
Message-ID: <ZTkO6FZBlUDDKJKU@macbook> (raw)
In-Reply-To: <ba1de950-185e-8d8e-e313-aef54b18a097@suse.com>

On Thu, May 11, 2023 at 02:05:45PM +0200, Jan Beulich wrote:
> Somewhat like port CF9 this may have a bit controlling the CPU's INIT#
> signal, and it also may have a bit involved in the driving of A20M#.
> Neither of these - just like CF9 - we want to allow Dom0 to drive.
> 
> Signed-off-by: Jan Beulich <jbeulich@suse.com>

Acked-by: Roger Pau Monné <roger.pau@citrix.com>

I'm kind of concerned that such ports might be used for other stuff
not described in the specifications I'm looking at, I guess we will
find out.

> 
> --- a/xen/arch/x86/dom0_build.c
> +++ b/xen/arch/x86/dom0_build.c
> @@ -500,6 +500,10 @@ int __init dom0_setup_permissions(struct
>      rc |= ioports_deny_access(d, 0x40, 0x43);
>      /* PIT Channel 2 / PC Speaker Control. */
>      rc |= ioports_deny_access(d, 0x61, 0x61);
> +
> +    /* INIT# and alternative A20M# control. */
> +    rc |= ioports_deny_access(d, 0x92, 0x92);

I do wonder whether it would make sense to create an array of [start,
end] IO ports to deny access to, so that we could loop over them and
code a single call to ioports_deny_access().  Maybe that's over
engineering it.

Thanks, Roger.


  reply	other threads:[~2023-10-25 12:50 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-05-11 12:03 [PATCH 0/7] x86: Dom0 I/O port access permissions Jan Beulich
2023-05-11 12:05 ` [PATCH 1/7] x86: don't allow Dom0 access to port CF9 Jan Beulich
2023-10-25 12:36   ` Roger Pau Monné
2023-10-25 13:59     ` Jan Beulich
2023-05-11 12:05 ` [PATCH 2/7] x86: don't allow Dom0 access to port 92 Jan Beulich
2023-10-25 12:49   ` Roger Pau Monné [this message]
2023-10-25 14:11     ` Jan Beulich
2023-05-11 12:06 ` [PATCH 3/7] x86/PVH: deny Dom0 access to the ISA DMA controller Jan Beulich
2023-10-25 13:22   ` Roger Pau Monné
2023-05-11 12:06 ` [PATCH 4/7] x86: detect PIC aliasing on ports other than 0x[2A][01] Jan Beulich
2023-10-26  8:34   ` Roger Pau Monné
2023-10-26  9:03     ` Jan Beulich
2023-10-26 13:24       ` Roger Pau Monné
2023-10-26 15:07         ` Jan Beulich
2023-10-26 15:19           ` Roger Pau Monné
2023-10-30 12:24             ` Jan Beulich
2023-10-30 15:14               ` Roger Pau Monné
2023-10-30 15:19                 ` Jan Beulich
2023-10-30 15:23                   ` Roger Pau Monné
2023-10-30 15:35                     ` Jan Beulich
2023-10-30 16:25                       ` Roger Pau Monné
2023-05-11 12:07 ` [PATCH 5/7] x86: detect PIT aliasing on ports other than 0x4[0-3] Jan Beulich
2023-10-26 10:25   ` Roger Pau Monné
2023-10-26 12:31     ` Jan Beulich
2023-10-26 13:57       ` Roger Pau Monné
2023-10-26 15:10         ` Jan Beulich
2023-10-26 15:13           ` Roger Pau Monné
2023-10-30 12:50             ` Jan Beulich
2023-05-11 12:07 ` [PATCH 6/7] x86: don't allow Dom0 (direct) access to port F0 Jan Beulich
2023-10-26 10:48   ` Roger Pau Monné
2023-05-11 12:08 ` [PATCH 7/7] x86: don't allow Dom0 access to ELCR ports Jan Beulich
2023-10-26 11:02   ` Roger Pau Monné
2023-10-26 12:51     ` Jan Beulich

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