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From: Jisheng Zhang <jszhang@kernel.org>
To: Chen Wang <unicorn_wang@outlook.com>
Cc: Conor Dooley <conor@kernel.org>,
	linux-riscv@lists.infradead.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Chao Wei <chao.wei@sophgo.com>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] riscv: dts: sophgo: remove address-cells from intc node
Date: Wed, 25 Oct 2023 23:13:39 +0800	[thread overview]
Message-ID: <ZTkwo/u6S9Atp2u3@xhacker> (raw)
In-Reply-To: <MA0P287MB0332C00AB091FD7139560E25FEDEA@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM>

On Wed, Oct 25, 2023 at 08:48:57AM +0800, Chen Wang wrote:
> 
> On 2023/10/24 16:20, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> > 
> > A recent submission [1] from Rob has added additionalProperties: false
> > to the interrupt-controller child node of RISC-V cpus, highlighting that
> > the new cv1800b DT has been incorrectly using #address-cells.
> > It has no child nodes, so #address-cells is not needed. Remove it.
> > 
> > Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1]
> > Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Nice catch!

Reviewed-by: Jisheng Zhang <jszhang@kernel.org>


> > ---
> > CC: Chao Wei <chao.wei@sophgo.com>
> > CC: Chen Wang <unicorn_wang@outlook.com>
> > CC: Rob Herring <robh+dt@kernel.org>
> > CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> > CC: Paul Walmsley <paul.walmsley@sifive.com>
> > CC: Palmer Dabbelt <palmer@dabbelt.com>
> > CC: Albert Ou <aou@eecs.berkeley.edu>
> > CC: devicetree@vger.kernel.org
> > CC: linux-riscv@lists.infradead.org
> > CC: linux-kernel@vger.kernel.org
> > ---
> >   arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
> >   1 file changed, 1 deletion(-)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > index df40e87ee063..aec6401a467b 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > @@ -34,7 +34,6 @@ cpu0: cpu@0 {
> >   			cpu0_intc: interrupt-controller {
> >   				compatible = "riscv,cpu-intc";
> >   				interrupt-controller;
> > -				#address-cells = <0>;
> >   				#interrupt-cells = <1>;
> >   			};
> >   		};
> 
> Acked-by: Chen Wang <unicorn_wang@outlook.com>
> 
> Thanks，btw, will it be merged in 6.7?

Don't worry, this is a fix, I think Conor will submit fix PR once rc1 is out.

> 
> Looping Jisheng who is working on Duo/cv1800b.
> 

_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Jisheng Zhang <jszhang@kernel.org>
To: Chen Wang <unicorn_wang@outlook.com>
Cc: Conor Dooley <conor@kernel.org>,
	linux-riscv@lists.infradead.org,
	Conor Dooley <conor.dooley@microchip.com>,
	Chao Wei <chao.wei@sophgo.com>, Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v1] riscv: dts: sophgo: remove address-cells from intc node
Date: Wed, 25 Oct 2023 23:13:39 +0800	[thread overview]
Message-ID: <ZTkwo/u6S9Atp2u3@xhacker> (raw)
In-Reply-To: <MA0P287MB0332C00AB091FD7139560E25FEDEA@MA0P287MB0332.INDP287.PROD.OUTLOOK.COM>

On Wed, Oct 25, 2023 at 08:48:57AM +0800, Chen Wang wrote:
> 
> On 2023/10/24 16:20, Conor Dooley wrote:
> > From: Conor Dooley <conor.dooley@microchip.com>
> > 
> > A recent submission [1] from Rob has added additionalProperties: false
> > to the interrupt-controller child node of RISC-V cpus, highlighting that
> > the new cv1800b DT has been incorrectly using #address-cells.
> > It has no child nodes, so #address-cells is not needed. Remove it.
> > 
> > Link: https://patchwork.kernel.org/project/linux-riscv/patch/20230915201946.4184468-1-robh@kernel.org/ [1]
> > Fixes: c3dffa879cca ("riscv: dts: sophgo: add initial CV1800B SoC device tree")
> > Signed-off-by: Conor Dooley <conor.dooley@microchip.com>

Nice catch!

Reviewed-by: Jisheng Zhang <jszhang@kernel.org>


> > ---
> > CC: Chao Wei <chao.wei@sophgo.com>
> > CC: Chen Wang <unicorn_wang@outlook.com>
> > CC: Rob Herring <robh+dt@kernel.org>
> > CC: Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>
> > CC: Paul Walmsley <paul.walmsley@sifive.com>
> > CC: Palmer Dabbelt <palmer@dabbelt.com>
> > CC: Albert Ou <aou@eecs.berkeley.edu>
> > CC: devicetree@vger.kernel.org
> > CC: linux-riscv@lists.infradead.org
> > CC: linux-kernel@vger.kernel.org
> > ---
> >   arch/riscv/boot/dts/sophgo/cv1800b.dtsi | 1 -
> >   1 file changed, 1 deletion(-)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > index df40e87ee063..aec6401a467b 100644
> > --- a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi
> > @@ -34,7 +34,6 @@ cpu0: cpu@0 {
> >   			cpu0_intc: interrupt-controller {
> >   				compatible = "riscv,cpu-intc";
> >   				interrupt-controller;
> > -				#address-cells = <0>;
> >   				#interrupt-cells = <1>;
> >   			};
> >   		};
> 
> Acked-by: Chen Wang <unicorn_wang@outlook.com>
> 
> Thanks，btw, will it be merged in 6.7?

Don't worry, this is a fix, I think Conor will submit fix PR once rc1 is out.

> 
> Looping Jisheng who is working on Duo/cv1800b.
> 

  reply	other threads:[~2023-10-25 15:26 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-24  8:20 [PATCH v1] riscv: dts: sophgo: remove address-cells from intc node Conor Dooley
2023-10-24  8:20 ` Conor Dooley
2023-10-25  0:48 ` Chen Wang
2023-10-25  0:48   ` Chen Wang
2023-10-25 15:13   ` Jisheng Zhang [this message]
2023-10-25 15:13     ` Jisheng Zhang
2023-10-26 13:07     ` Conor Dooley
2023-10-26 13:07       ` Conor Dooley
2024-01-20 21:09 ` patchwork-bot+linux-riscv
2024-01-20 21:09   ` patchwork-bot+linux-riscv

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