* [Intel-gfx] [PATCH] drm/i915/display: Only fail fastset on PSR2
@ 2023-10-31 23:21 ` Paz Zcharya
0 siblings, 0 replies; 11+ messages in thread
From: Paz Zcharya @ 2023-10-31 23:21 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin
Cc: dri-devel, Luca Coelho, Andrzej Hajda, David Airlie,
Subrata Banik, intel-gfx, Sean Paul, Matt Roper, Paz Zcharya,
Paz Zcharya, linux-kernel, Daniel Vetter, Drew Davenport
Currently, i915 fails fastset if both the sink and the source support
any version of PSR and regardless of the configuration setting of the
driver (i.e., i915.enable_psr kernel argument). However, the
implementation of PSR1 enable sequence is already seamless
and works smoothly with fastset. Accordingly, do not fail fastset
if PSR2 is not enabled.
Signed-off-by: Paz Zcharya <pazz@google.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e0e4cb529284..a1af96e31518 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
fastset = false;
}
- if (CAN_PSR(intel_dp)) {
- drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
+ if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
+ drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to PSR2\n",
encoder->base.base.id, encoder->base.name);
crtc_state->uapi.mode_changed = true;
fastset = false;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 97d5eef10130..388bc3246db9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp *intel_dp)
}
}
-static bool psr2_global_enabled(struct intel_dp *intel_dp)
+bool psr2_global_enabled(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 0b95e8aa615f..6f3c36389cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -21,6 +21,7 @@ struct intel_encoder;
struct intel_plane;
struct intel_plane_state;
+bool psr2_global_enabled(struct intel_dp *intel_dp);
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
--
2.42.0.820.g83a721a137-goog
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] drm/i915/display: Only fail fastset on PSR2
@ 2023-10-31 23:21 ` Paz Zcharya
0 siblings, 0 replies; 11+ messages in thread
From: Paz Zcharya @ 2023-10-31 23:21 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin
Cc: dri-devel, Luca Coelho, Andrzej Hajda, Stanislav Lisovskiy,
Uma Shankar, Mika Kahola, Jouni Högander, Ankit Nautiyal,
Suraj Kandpal, Subrata Banik, intel-gfx, Manasi Navare, Sean Paul,
José Roberto de Souza, Matt Roper, Paz Zcharya, Paz Zcharya,
linux-kernel, Drew Davenport, Khaled Almahallawy
Currently, i915 fails fastset if both the sink and the source support
any version of PSR and regardless of the configuration setting of the
driver (i.e., i915.enable_psr kernel argument). However, the
implementation of PSR1 enable sequence is already seamless
and works smoothly with fastset. Accordingly, do not fail fastset
if PSR2 is not enabled.
Signed-off-by: Paz Zcharya <pazz@google.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e0e4cb529284..a1af96e31518 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
fastset = false;
}
- if (CAN_PSR(intel_dp)) {
- drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
+ if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
+ drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to PSR2\n",
encoder->base.base.id, encoder->base.name);
crtc_state->uapi.mode_changed = true;
fastset = false;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 97d5eef10130..388bc3246db9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp *intel_dp)
}
}
-static bool psr2_global_enabled(struct intel_dp *intel_dp)
+bool psr2_global_enabled(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 0b95e8aa615f..6f3c36389cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -21,6 +21,7 @@ struct intel_encoder;
struct intel_plane;
struct intel_plane_state;
+bool psr2_global_enabled(struct intel_dp *intel_dp);
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
--
2.42.0.820.g83a721a137-goog
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH] drm/i915/display: Only fail fastset on PSR2
@ 2023-10-31 23:21 ` Paz Zcharya
0 siblings, 0 replies; 11+ messages in thread
From: Paz Zcharya @ 2023-10-31 23:21 UTC (permalink / raw)
To: Jani Nikula, Joonas Lahtinen, Rodrigo Vivi, Tvrtko Ursulin
Cc: Subrata Banik, Drew Davenport, Sean Paul, Manasi Navare,
Paz Zcharya, Paz Zcharya, Andrzej Hajda, Ankit Nautiyal,
Daniel Vetter, David Airlie, José Roberto de Souza,
Jouni Högander, Khaled Almahallawy, Luca Coelho, Matt Roper,
Mika Kahola, Stanislav Lisovskiy, Suraj Kandpal, Uma Shankar,
Ville Syrjälä, dri-devel, intel-gfx, linux-kernel
Currently, i915 fails fastset if both the sink and the source support
any version of PSR and regardless of the configuration setting of the
driver (i.e., i915.enable_psr kernel argument). However, the
implementation of PSR1 enable sequence is already seamless
and works smoothly with fastset. Accordingly, do not fail fastset
if PSR2 is not enabled.
Signed-off-by: Paz Zcharya <pazz@google.com>
---
drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
drivers/gpu/drm/i915/display/intel_psr.h | 1 +
3 files changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c
index e0e4cb529284..a1af96e31518 100644
--- a/drivers/gpu/drm/i915/display/intel_dp.c
+++ b/drivers/gpu/drm/i915/display/intel_dp.c
@@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct intel_encoder *encoder,
fastset = false;
}
- if (CAN_PSR(intel_dp)) {
- drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset to compute PSR state\n",
+ if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
+ drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full modeset due to PSR2\n",
encoder->base.base.id, encoder->base.name);
crtc_state->uapi.mode_changed = true;
fastset = false;
diff --git a/drivers/gpu/drm/i915/display/intel_psr.c b/drivers/gpu/drm/i915/display/intel_psr.c
index 97d5eef10130..388bc3246db9 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.c
+++ b/drivers/gpu/drm/i915/display/intel_psr.c
@@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp *intel_dp)
}
}
-static bool psr2_global_enabled(struct intel_dp *intel_dp)
+bool psr2_global_enabled(struct intel_dp *intel_dp)
{
struct drm_i915_private *i915 = dp_to_i915(intel_dp);
diff --git a/drivers/gpu/drm/i915/display/intel_psr.h b/drivers/gpu/drm/i915/display/intel_psr.h
index 0b95e8aa615f..6f3c36389cd3 100644
--- a/drivers/gpu/drm/i915/display/intel_psr.h
+++ b/drivers/gpu/drm/i915/display/intel_psr.h
@@ -21,6 +21,7 @@ struct intel_encoder;
struct intel_plane;
struct intel_plane_state;
+bool psr2_global_enabled(struct intel_dp *intel_dp);
void intel_psr_init_dpcd(struct intel_dp *intel_dp);
void intel_psr_pre_plane_update(struct intel_atomic_state *state,
struct intel_crtc *crtc);
--
2.42.0.820.g83a721a137-goog
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/display: Only fail fastset on PSR2
2023-10-31 23:21 ` Paz Zcharya
(?)
(?)
@ 2023-11-01 0:04 ` Patchwork
-1 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2023-11-01 0:04 UTC (permalink / raw)
To: Paz Zcharya; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/display: Only fail fastset on PSR2
URL : https://patchwork.freedesktop.org/series/125829/
State : warning
== Summary ==
Error: dim checkpatch failed
7cb5d81d8463 drm/i915/display: Only fail fastset on PSR2
-:54: WARNING:FROM_SIGN_OFF_MISMATCH: From:/Signed-off-by: email address mismatch: 'From: Paz Zcharya <pazz@chromium.org>' != 'Signed-off-by: Paz Zcharya <pazz@google.com>'
total: 0 errors, 1 warnings, 0 checks, 25 lines checked
^ permalink raw reply [flat|nested] 11+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915/display: Only fail fastset on PSR2
2023-10-31 23:21 ` Paz Zcharya
` (2 preceding siblings ...)
(?)
@ 2023-11-01 0:23 ` Patchwork
-1 siblings, 0 replies; 11+ messages in thread
From: Patchwork @ 2023-11-01 0:23 UTC (permalink / raw)
To: Paz Zcharya; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 16065 bytes --]
== Series Details ==
Series: drm/i915/display: Only fail fastset on PSR2
URL : https://patchwork.freedesktop.org/series/125829/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_13823 -> Patchwork_125829v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_125829v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_125829v1, please notify your bug team (lgci.bug.filing@intel.com) to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/index.html
Participating hosts (35 -> 36)
------------------------------
Additional (4): fi-kbl-soraka bat-adlm-1 bat-adlp-11 bat-mtlp-8
Missing (3): bat-dg2-9 fi-snb-2520m bat-dg1-5
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_125829v1:
### IGT changes ###
#### Possible regressions ####
* igt@kms_addfb_basic@invalid-set-prop-any:
- fi-kbl-soraka: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/fi-kbl-soraka/igt@kms_addfb_basic@invalid-set-prop-any.html
Known issues
------------
Here are the changes found in Patchwork_125829v1 that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- bat-jsl-1: [FAIL][2] ([i915#8293]) -> [PASS][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13823/bat-jsl-1/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-jsl-1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@debugfs_test@basic-hwmon:
- bat-adlm-1: NOTRUN -> [SKIP][4] ([i915#3826])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@debugfs_test@basic-hwmon.html
- bat-jsl-1: NOTRUN -> [SKIP][5] ([i915#9318])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-jsl-1/igt@debugfs_test@basic-hwmon.html
- bat-mtlp-8: NOTRUN -> [SKIP][6] ([i915#9318])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@debugfs_test@basic-hwmon.html
- bat-adlp-11: NOTRUN -> [SKIP][7] ([i915#9318])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlp-11/igt@debugfs_test@basic-hwmon.html
* igt@fbdev@info:
- bat-adlm-1: NOTRUN -> [SKIP][8] ([i915#1849] / [i915#2582])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@fbdev@info.html
* igt@fbdev@read:
- bat-adlm-1: NOTRUN -> [SKIP][9] ([i915#2582]) +3 other tests skip
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@fbdev@read.html
* igt@gem_huc_copy@huc-copy:
- fi-kbl-soraka: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#2190])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/fi-kbl-soraka/igt@gem_huc_copy@huc-copy.html
- bat-jsl-1: NOTRUN -> [SKIP][11] ([i915#2190])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-jsl-1/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- fi-kbl-soraka: NOTRUN -> [SKIP][12] ([fdo#109271] / [i915#4613]) +3 other tests skip
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/fi-kbl-soraka/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@parallel-random-engines:
- bat-adlm-1: NOTRUN -> [SKIP][13] ([i915#4613]) +3 other tests skip
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@gem_lmem_swapping@parallel-random-engines.html
- bat-mtlp-8: NOTRUN -> [SKIP][14] ([i915#4613]) +3 other tests skip
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@gem_lmem_swapping@parallel-random-engines.html
- bat-jsl-1: NOTRUN -> [SKIP][15] ([i915#4613]) +3 other tests skip
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-jsl-1/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][16] ([i915#4083])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@gem_mmap@basic.html
* igt@gem_render_tiled_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][17] ([i915#4079]) +1 other test skip
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@gem_render_tiled_blits@basic.html
* igt@gem_tiled_fence_blits@basic:
- bat-mtlp-8: NOTRUN -> [SKIP][18] ([i915#4077]) +3 other tests skip
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@gem_tiled_fence_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-adlp-11: NOTRUN -> [SKIP][19] ([i915#3282])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlp-11/igt@gem_tiled_pread_basic.html
- bat-adlm-1: NOTRUN -> [SKIP][20] ([i915#3282])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@gem_tiled_pread_basic.html
* igt@i915_pm_rps@basic-api:
- bat-mtlp-8: NOTRUN -> [SKIP][21] ([i915#6621])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@i915_pm_rps@basic-api.html
- bat-adlm-1: NOTRUN -> [SKIP][22] ([i915#6621])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@gt_heartbeat:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][23] ([i915#5334] / [i915#7872])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/fi-kbl-soraka/igt@i915_selftest@live@gt_heartbeat.html
* igt@i915_selftest@live@gt_pm:
- fi-kbl-soraka: NOTRUN -> [DMESG-FAIL][24] ([i915#1886])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/fi-kbl-soraka/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@basic-s3-without-i915:
- bat-mtlp-8: NOTRUN -> [SKIP][25] ([i915#6645])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@i915_suspend@basic-s3-without-i915.html
* igt@kms_addfb_basic@addfb25-y-tiled-small-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][26] ([i915#5190])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@kms_addfb_basic@addfb25-y-tiled-small-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][27] ([i915#4212]) +8 other tests skip
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-kbl-soraka: NOTRUN -> [SKIP][28] ([fdo#109271]) +9 other tests skip
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/fi-kbl-soraka/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- bat-mtlp-8: NOTRUN -> [SKIP][29] ([i915#4213]) +1 other test skip
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-jsl-1: NOTRUN -> [SKIP][30] ([i915#4103]) +1 other test skip
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-jsl-1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-adlp-11: NOTRUN -> [SKIP][31] ([i915#4103] / [i915#5608]) +1 other test skip
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlp-11/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size:
- bat-adlm-1: NOTRUN -> [SKIP][32] ([i915#1845]) +17 other tests skip
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@kms_cursor_legacy@basic-flip-after-cursor-varying-size.html
* igt@kms_dsc@dsc-basic:
- bat-adlp-11: NOTRUN -> [SKIP][33] ([i915#3555] / [i915#3840])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlp-11/igt@kms_dsc@dsc-basic.html
- bat-mtlp-8: NOTRUN -> [SKIP][34] ([i915#3555] / [i915#3840] / [i915#9159])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@kms_dsc@dsc-basic.html
- bat-jsl-1: NOTRUN -> [SKIP][35] ([i915#3555]) +1 other test skip
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-jsl-1/igt@kms_dsc@dsc-basic.html
* igt@kms_flip@basic-flip-vs-wf_vblank:
- bat-adlm-1: NOTRUN -> [SKIP][36] ([i915#3637]) +3 other tests skip
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@kms_flip@basic-flip-vs-wf_vblank.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-adlm-1: NOTRUN -> [SKIP][37] ([fdo#109285])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@kms_force_connector_basic@force-load-detect.html
- bat-mtlp-8: NOTRUN -> [SKIP][38] ([fdo#109285])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@kms_force_connector_basic@force-load-detect.html
- bat-jsl-1: NOTRUN -> [SKIP][39] ([fdo#109285])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-jsl-1/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-11: NOTRUN -> [SKIP][40] ([i915#4093]) +3 other tests skip
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlp-11/igt@kms_force_connector_basic@prune-stale-modes.html
- bat-mtlp-8: NOTRUN -> [SKIP][41] ([i915#5274])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_frontbuffer_tracking@basic:
- bat-adlm-1: NOTRUN -> [SKIP][42] ([i915#1849])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_hdmi_inject@inject-audio:
- fi-kbl-guc: [PASS][43] -> [FAIL][44] ([IGT#3])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13823/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/fi-kbl-guc/igt@kms_hdmi_inject@inject-audio.html
- bat-adlp-11: NOTRUN -> [SKIP][45] ([i915#4369])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlp-11/igt@kms_hdmi_inject@inject-audio.html
* igt@kms_psr@cursor_plane_move:
- bat-adlm-1: NOTRUN -> [SKIP][46] ([i915#1072]) +3 other tests skip
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@kms_psr@cursor_plane_move.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-mtlp-8: NOTRUN -> [SKIP][47] ([i915#3555] / [i915#8809])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@kms_setmode@basic-clone-single-crtc.html
- bat-adlm-1: NOTRUN -> [SKIP][48] ([i915#3555])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-adlm-1: NOTRUN -> [SKIP][49] ([i915#1845] / [i915#3708])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-read:
- bat-mtlp-8: NOTRUN -> [SKIP][50] ([i915#3708]) +2 other tests skip
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-gtt:
- bat-mtlp-8: NOTRUN -> [SKIP][51] ([i915#3708] / [i915#4077]) +1 other test skip
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-mtlp-8/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-write:
- bat-adlm-1: NOTRUN -> [SKIP][52] ([i915#3708]) +2 other tests skip
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/bat-adlm-1/igt@prime_vgem@basic-write.html
#### Possible fixes ####
* igt@i915_selftest@live@hangcheck:
- fi-hsw-4770: [INCOMPLETE][53] -> [PASS][54]
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_13823/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[IGT#3]: https://gitlab.freedesktop.org/drm/igt-gpu-tools/issues/3
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3546]: https://gitlab.freedesktop.org/drm/intel/issues/3546
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5334]: https://gitlab.freedesktop.org/drm/intel/issues/5334
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5608]: https://gitlab.freedesktop.org/drm/intel/issues/5608
[i915#6621]: https://gitlab.freedesktop.org/drm/intel/issues/6621
[i915#6645]: https://gitlab.freedesktop.org/drm/intel/issues/6645
[i915#7872]: https://gitlab.freedesktop.org/drm/intel/issues/7872
[i915#8293]: https://gitlab.freedesktop.org/drm/intel/issues/8293
[i915#8668]: https://gitlab.freedesktop.org/drm/intel/issues/8668
[i915#8809]: https://gitlab.freedesktop.org/drm/intel/issues/8809
[i915#9159]: https://gitlab.freedesktop.org/drm/intel/issues/9159
[i915#9318]: https://gitlab.freedesktop.org/drm/intel/issues/9318
Build changes
-------------
* Linux: CI_DRM_13823 -> Patchwork_125829v1
CI-20190529: 20190529
CI_DRM_13823: 3f4656949887086d179f7d5c78aa8b749efa20dc @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_7566: 7566
Patchwork_125829v1: 3f4656949887086d179f7d5c78aa8b749efa20dc @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
9498ea1c3f1d drm/i915/display: Only fail fastset on PSR2
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_125829v1/index.html
[-- Attachment #2: Type: text/html, Size: 19310 bytes --]
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display: Only fail fastset on PSR2
2023-10-31 23:21 ` Paz Zcharya
(?)
@ 2023-11-01 6:26 ` Hogander, Jouni
-1 siblings, 0 replies; 11+ messages in thread
From: Hogander, Jouni @ 2023-11-01 6:26 UTC (permalink / raw)
To: pazz@chromium.org, joonas.lahtinen@linux.intel.com, Vivi, Rodrigo,
tvrtko.ursulin@linux.intel.com, jani.nikula@linux.intel.com
Cc: Zcharya, Paz, Hajda, Andrzej, Banik, Subrata, airlied@gmail.com,
intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org,
dri-devel@lists.freedesktop.org, Coelho, Luciano, daniel@ffwll.ch,
ddavenport@chromium.org, seanpaul@chromium.org, Roper, Matthew D
On Tue, 2023-10-31 at 23:21 +0000, Paz Zcharya wrote:
> Currently, i915 fails fastset if both the sink and the source support
> any version of PSR and regardless of the configuration setting of the
> driver (i.e., i915.enable_psr kernel argument). However, the
> implementation of PSR1 enable sequence is already seamless
> and works smoothly with fastset. Accordingly, do not fail fastset
> if PSR2 is not enabled.
Thank you for the patch. Check similar patch I sent some time ago to
trybot:
https://patchwork.freedesktop.org/series/125392/
If we want to temporarily do this only for psr1 I think you could check
what I've done in drivers/gpu/drm/i915/display/intel_display.c in my
patch and modify your patch accordingly. Otherwise e.g. our IGT
testcases which are toggling PSR enable/disable/psr1/psr2 are to my
understanding performing full modeset and possible issues are not
revealed.
After modifying drivers/gpu/drm/i915/display/intel_display.c you can
also verify it is really seamless and smooth by toggling different PSR
states via /sys/kernel/debug/dri/0/i915_edp_psr_debug. That interface
is performing atomic commit when PSR mode is changed.
BR,
Jouni Högander
>
> Signed-off-by: Paz Zcharya <pazz@google.com>
> ---
>
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> 3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e0e4cb529284..a1af96e31518 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
> fastset = false;
> }
>
> - if (CAN_PSR(intel_dp)) {
> - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> modeset to compute PSR state\n",
> + if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
> + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> modeset due to PSR2\n",
> encoder->base.base.id, encoder-
> >base.name);
> crtc_state->uapi.mode_changed = true;
> fastset = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 97d5eef10130..388bc3246db9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp
> *intel_dp)
> }
> }
>
> -static bool psr2_global_enabled(struct intel_dp *intel_dp)
> +bool psr2_global_enabled(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 0b95e8aa615f..6f3c36389cd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -21,6 +21,7 @@ struct intel_encoder;
> struct intel_plane;
> struct intel_plane_state;
>
> +bool psr2_global_enabled(struct intel_dp *intel_dp);
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/display: Only fail fastset on PSR2
@ 2023-11-01 6:26 ` Hogander, Jouni
0 siblings, 0 replies; 11+ messages in thread
From: Hogander, Jouni @ 2023-11-01 6:26 UTC (permalink / raw)
To: pazz@chromium.org, joonas.lahtinen@linux.intel.com, Vivi, Rodrigo,
tvrtko.ursulin@linux.intel.com, jani.nikula@linux.intel.com
Cc: Kandpal, Suraj, Zcharya, Paz, Hajda, Andrzej, Banik, Subrata,
Kahola, Mika, intel-gfx@lists.freedesktop.org,
linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org,
navaremanasi@chromium.org, Lisovskiy, Stanislav, Shankar, Uma,
Coelho, Luciano, Souza, Jose, ddavenport@chromium.org,
seanpaul@chromium.org, Nautiyal, Ankit K, Roper, Matthew D,
Almahallawy, Khaled
On Tue, 2023-10-31 at 23:21 +0000, Paz Zcharya wrote:
> Currently, i915 fails fastset if both the sink and the source support
> any version of PSR and regardless of the configuration setting of the
> driver (i.e., i915.enable_psr kernel argument). However, the
> implementation of PSR1 enable sequence is already seamless
> and works smoothly with fastset. Accordingly, do not fail fastset
> if PSR2 is not enabled.
Thank you for the patch. Check similar patch I sent some time ago to
trybot:
https://patchwork.freedesktop.org/series/125392/
If we want to temporarily do this only for psr1 I think you could check
what I've done in drivers/gpu/drm/i915/display/intel_display.c in my
patch and modify your patch accordingly. Otherwise e.g. our IGT
testcases which are toggling PSR enable/disable/psr1/psr2 are to my
understanding performing full modeset and possible issues are not
revealed.
After modifying drivers/gpu/drm/i915/display/intel_display.c you can
also verify it is really seamless and smooth by toggling different PSR
states via /sys/kernel/debug/dri/0/i915_edp_psr_debug. That interface
is performing atomic commit when PSR mode is changed.
BR,
Jouni Högander
>
> Signed-off-by: Paz Zcharya <pazz@google.com>
> ---
>
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> 3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e0e4cb529284..a1af96e31518 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
> fastset = false;
> }
>
> - if (CAN_PSR(intel_dp)) {
> - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> modeset to compute PSR state\n",
> + if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
> + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> modeset due to PSR2\n",
> encoder->base.base.id, encoder-
> >base.name);
> crtc_state->uapi.mode_changed = true;
> fastset = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 97d5eef10130..388bc3246db9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp
> *intel_dp)
> }
> }
>
> -static bool psr2_global_enabled(struct intel_dp *intel_dp)
> +bool psr2_global_enabled(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 0b95e8aa615f..6f3c36389cd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -21,6 +21,7 @@ struct intel_encoder;
> struct intel_plane;
> struct intel_plane_state;
>
> +bool psr2_global_enabled(struct intel_dp *intel_dp);
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/display: Only fail fastset on PSR2
@ 2023-11-01 6:26 ` Hogander, Jouni
0 siblings, 0 replies; 11+ messages in thread
From: Hogander, Jouni @ 2023-11-01 6:26 UTC (permalink / raw)
To: pazz@chromium.org, joonas.lahtinen@linux.intel.com, Vivi, Rodrigo,
tvrtko.ursulin@linux.intel.com, jani.nikula@linux.intel.com
Cc: navaremanasi@chromium.org, Almahallawy, Khaled, Banik, Subrata,
Kandpal, Suraj, Coelho, Luciano, Roper, Matthew D,
ville.syrjala@linux.intel.com, seanpaul@chromium.org,
daniel@ffwll.ch, dri-devel@lists.freedesktop.org, Hajda, Andrzej,
ddavenport@chromium.org, intel-gfx@lists.freedesktop.org,
linux-kernel@vger.kernel.org, Lisovskiy, Stanislav,
Nautiyal, Ankit K, Shankar, Uma, Zcharya, Paz, Souza, Jose,
Kahola, Mika, airlied@gmail.com
On Tue, 2023-10-31 at 23:21 +0000, Paz Zcharya wrote:
> Currently, i915 fails fastset if both the sink and the source support
> any version of PSR and regardless of the configuration setting of the
> driver (i.e., i915.enable_psr kernel argument). However, the
> implementation of PSR1 enable sequence is already seamless
> and works smoothly with fastset. Accordingly, do not fail fastset
> if PSR2 is not enabled.
Thank you for the patch. Check similar patch I sent some time ago to
trybot:
https://patchwork.freedesktop.org/series/125392/
If we want to temporarily do this only for psr1 I think you could check
what I've done in drivers/gpu/drm/i915/display/intel_display.c in my
patch and modify your patch accordingly. Otherwise e.g. our IGT
testcases which are toggling PSR enable/disable/psr1/psr2 are to my
understanding performing full modeset and possible issues are not
revealed.
After modifying drivers/gpu/drm/i915/display/intel_display.c you can
also verify it is really seamless and smooth by toggling different PSR
states via /sys/kernel/debug/dri/0/i915_edp_psr_debug. That interface
is performing atomic commit when PSR mode is changed.
BR,
Jouni Högander
>
> Signed-off-by: Paz Zcharya <pazz@google.com>
> ---
>
> drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> 3 files changed, 4 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> b/drivers/gpu/drm/i915/display/intel_dp.c
> index e0e4cb529284..a1af96e31518 100644
> --- a/drivers/gpu/drm/i915/display/intel_dp.c
> +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> @@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct
> intel_encoder *encoder,
> fastset = false;
> }
>
> - if (CAN_PSR(intel_dp)) {
> - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> modeset to compute PSR state\n",
> + if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
> + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> modeset due to PSR2\n",
> encoder->base.base.id, encoder-
> >base.name);
> crtc_state->uapi.mode_changed = true;
> fastset = false;
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> b/drivers/gpu/drm/i915/display/intel_psr.c
> index 97d5eef10130..388bc3246db9 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.c
> +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> @@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp
> *intel_dp)
> }
> }
>
> -static bool psr2_global_enabled(struct intel_dp *intel_dp)
> +bool psr2_global_enabled(struct intel_dp *intel_dp)
> {
> struct drm_i915_private *i915 = dp_to_i915(intel_dp);
>
> diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> b/drivers/gpu/drm/i915/display/intel_psr.h
> index 0b95e8aa615f..6f3c36389cd3 100644
> --- a/drivers/gpu/drm/i915/display/intel_psr.h
> +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> @@ -21,6 +21,7 @@ struct intel_encoder;
> struct intel_plane;
> struct intel_plane_state;
>
> +bool psr2_global_enabled(struct intel_dp *intel_dp);
> void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> struct intel_crtc *crtc);
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915/display: Only fail fastset on PSR2
2023-11-01 6:26 ` Hogander, Jouni
(?)
@ 2023-11-01 15:45 ` Paz Zcharya
-1 siblings, 0 replies; 11+ messages in thread
From: Paz Zcharya @ 2023-11-01 15:45 UTC (permalink / raw)
To: Hogander, Jouni
Cc: Coelho, Luciano, Hajda, Andrzej, airlied@gmail.com,
Banik, Subrata, intel-gfx@lists.freedesktop.org,
seanpaul@chromium.org, dri-devel@lists.freedesktop.org,
Vivi, Rodrigo, Roper, Matthew D, linux-kernel@vger.kernel.org,
daniel@ffwll.ch, ddavenport@chromium.org
On Wed, Nov 01, 2023 at 06:26:47AM +0000, Hogander, Jouni wrote:
> On Tue, 2023-10-31 at 23:21 +0000, Paz Zcharya wrote:
> > Currently, i915 fails fastset if both the sink and the source support
> > any version of PSR and regardless of the configuration setting of the
> > driver (i.e., i915.enable_psr kernel argument). However, the
> > implementation of PSR1 enable sequence is already seamless
> > and works smoothly with fastset. Accordingly, do not fail fastset
> > if PSR2 is not enabled.
>
> Thank you for the patch. Check similar patch I sent some time ago to
> trybot:
>
> https://patchwork.freedesktop.org/series/125392/
>
I missed this patch. I apologize!
This is great work and exactly what we (Google ChromeOS) need.
I think your patch is better than mine, so let's abort my patch
and continue the discussion at series/125392.
By the way, we have verified your patch on two Meteor Lake devices
running ChromeOS and it works smoothly (no flickering or modesets).
I'll comment on the other patch as well.
> If we want to temporarily do this only for psr1 I think you could check
> what I've done in drivers/gpu/drm/i915/display/intel_display.c in my
> patch and modify your patch accordingly. Otherwise e.g. our IGT
> testcases which are toggling PSR enable/disable/psr1/psr2 are to my
> understanding performing full modeset and possible issues are not
> revealed.
>
> After modifying drivers/gpu/drm/i915/display/intel_display.c you can
> also verify it is really seamless and smooth by toggling different PSR
> states via /sys/kernel/debug/dri/0/i915_edp_psr_debug. That interface
> is performing atomic commit when PSR mode is changed.
>
> BR,
>
> Jouni Högander
> >
> > Signed-off-by: Paz Zcharya <pazz@google.com>
> > ---
> >
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> > drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > 3 files changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index e0e4cb529284..a1af96e31518 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct
> > intel_encoder *encoder,
> > fastset = false;
> > }
> >
> > - if (CAN_PSR(intel_dp)) {
> > - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> > modeset to compute PSR state\n",
> > + if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
> > + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> > modeset due to PSR2\n",
> > encoder->base.base.id, encoder-
> > >base.name);
> > crtc_state->uapi.mode_changed = true;
> > fastset = false;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 97d5eef10130..388bc3246db9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp
> > *intel_dp)
> > }
> > }
> >
> > -static bool psr2_global_enabled(struct intel_dp *intel_dp)
> > +bool psr2_global_enabled(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 0b95e8aa615f..6f3c36389cd3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -21,6 +21,7 @@ struct intel_encoder;
> > struct intel_plane;
> > struct intel_plane_state;
> >
> > +bool psr2_global_enabled(struct intel_dp *intel_dp);
> > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
>
.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/display: Only fail fastset on PSR2
@ 2023-11-01 15:45 ` Paz Zcharya
0 siblings, 0 replies; 11+ messages in thread
From: Paz Zcharya @ 2023-11-01 15:45 UTC (permalink / raw)
To: Hogander, Jouni
Cc: Souza, Jose, Coelho, Luciano, Hajda, Andrzej,
Lisovskiy, Stanislav, Shankar, Uma, Kahola, Mika,
Nautiyal, Ankit K, Kandpal, Suraj, Banik, Subrata,
intel-gfx@lists.freedesktop.org, navaremanasi@chromium.org,
seanpaul@chromium.org, dri-devel@lists.freedesktop.org,
Vivi, Rodrigo, Roper, Matthew D, tvrtko.ursulin@linux.intel.com,
linux-kernel@vger.kernel.org, ddavenport@chromium.org,
Almahallawy, Khaled
On Wed, Nov 01, 2023 at 06:26:47AM +0000, Hogander, Jouni wrote:
> On Tue, 2023-10-31 at 23:21 +0000, Paz Zcharya wrote:
> > Currently, i915 fails fastset if both the sink and the source support
> > any version of PSR and regardless of the configuration setting of the
> > driver (i.e., i915.enable_psr kernel argument). However, the
> > implementation of PSR1 enable sequence is already seamless
> > and works smoothly with fastset. Accordingly, do not fail fastset
> > if PSR2 is not enabled.
>
> Thank you for the patch. Check similar patch I sent some time ago to
> trybot:
>
> https://patchwork.freedesktop.org/series/125392/
>
I missed this patch. I apologize!
This is great work and exactly what we (Google ChromeOS) need.
I think your patch is better than mine, so let's abort my patch
and continue the discussion at series/125392.
By the way, we have verified your patch on two Meteor Lake devices
running ChromeOS and it works smoothly (no flickering or modesets).
I'll comment on the other patch as well.
> If we want to temporarily do this only for psr1 I think you could check
> what I've done in drivers/gpu/drm/i915/display/intel_display.c in my
> patch and modify your patch accordingly. Otherwise e.g. our IGT
> testcases which are toggling PSR enable/disable/psr1/psr2 are to my
> understanding performing full modeset and possible issues are not
> revealed.
>
> After modifying drivers/gpu/drm/i915/display/intel_display.c you can
> also verify it is really seamless and smooth by toggling different PSR
> states via /sys/kernel/debug/dri/0/i915_edp_psr_debug. That interface
> is performing atomic commit when PSR mode is changed.
>
> BR,
>
> Jouni Högander
> >
> > Signed-off-by: Paz Zcharya <pazz@google.com>
> > ---
> >
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> > drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > 3 files changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index e0e4cb529284..a1af96e31518 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct
> > intel_encoder *encoder,
> > fastset = false;
> > }
> >
> > - if (CAN_PSR(intel_dp)) {
> > - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> > modeset to compute PSR state\n",
> > + if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
> > + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> > modeset due to PSR2\n",
> > encoder->base.base.id, encoder-
> > >base.name);
> > crtc_state->uapi.mode_changed = true;
> > fastset = false;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 97d5eef10130..388bc3246db9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp
> > *intel_dp)
> > }
> > }
> >
> > -static bool psr2_global_enabled(struct intel_dp *intel_dp)
> > +bool psr2_global_enabled(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 0b95e8aa615f..6f3c36389cd3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -21,6 +21,7 @@ struct intel_encoder;
> > struct intel_plane;
> > struct intel_plane_state;
> >
> > +bool psr2_global_enabled(struct intel_dp *intel_dp);
> > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
>
.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH] drm/i915/display: Only fail fastset on PSR2
@ 2023-11-01 15:45 ` Paz Zcharya
0 siblings, 0 replies; 11+ messages in thread
From: Paz Zcharya @ 2023-11-01 15:45 UTC (permalink / raw)
To: Hogander, Jouni
Cc: joonas.lahtinen@linux.intel.com, Vivi, Rodrigo,
tvrtko.ursulin@linux.intel.com, jani.nikula@linux.intel.com,
navaremanasi@chromium.org, Almahallawy, Khaled, Banik, Subrata,
Kandpal, Suraj, Coelho, Luciano, Roper, Matthew D,
ville.syrjala@linux.intel.com, seanpaul@chromium.org,
daniel@ffwll.ch, dri-devel@lists.freedesktop.org, Hajda, Andrzej,
ddavenport@chromium.org, intel-gfx@lists.freedesktop.org,
linux-kernel@vger.kernel.org, Lisovskiy, Stanislav,
Nautiyal, Ankit K, Shankar, Uma, Souza, Jose, Kahola, Mika,
airlied@gmail.com
On Wed, Nov 01, 2023 at 06:26:47AM +0000, Hogander, Jouni wrote:
> On Tue, 2023-10-31 at 23:21 +0000, Paz Zcharya wrote:
> > Currently, i915 fails fastset if both the sink and the source support
> > any version of PSR and regardless of the configuration setting of the
> > driver (i.e., i915.enable_psr kernel argument). However, the
> > implementation of PSR1 enable sequence is already seamless
> > and works smoothly with fastset. Accordingly, do not fail fastset
> > if PSR2 is not enabled.
>
> Thank you for the patch. Check similar patch I sent some time ago to
> trybot:
>
> https://patchwork.freedesktop.org/series/125392/
>
I missed this patch. I apologize!
This is great work and exactly what we (Google ChromeOS) need.
I think your patch is better than mine, so let's abort my patch
and continue the discussion at series/125392.
By the way, we have verified your patch on two Meteor Lake devices
running ChromeOS and it works smoothly (no flickering or modesets).
I'll comment on the other patch as well.
> If we want to temporarily do this only for psr1 I think you could check
> what I've done in drivers/gpu/drm/i915/display/intel_display.c in my
> patch and modify your patch accordingly. Otherwise e.g. our IGT
> testcases which are toggling PSR enable/disable/psr1/psr2 are to my
> understanding performing full modeset and possible issues are not
> revealed.
>
> After modifying drivers/gpu/drm/i915/display/intel_display.c you can
> also verify it is really seamless and smooth by toggling different PSR
> states via /sys/kernel/debug/dri/0/i915_edp_psr_debug. That interface
> is performing atomic commit when PSR mode is changed.
>
> BR,
>
> Jouni Högander
> >
> > Signed-off-by: Paz Zcharya <pazz@google.com>
> > ---
> >
> > drivers/gpu/drm/i915/display/intel_dp.c | 4 ++--
> > drivers/gpu/drm/i915/display/intel_psr.c | 2 +-
> > drivers/gpu/drm/i915/display/intel_psr.h | 1 +
> > 3 files changed, 4 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_dp.c
> > b/drivers/gpu/drm/i915/display/intel_dp.c
> > index e0e4cb529284..a1af96e31518 100644
> > --- a/drivers/gpu/drm/i915/display/intel_dp.c
> > +++ b/drivers/gpu/drm/i915/display/intel_dp.c
> > @@ -2584,8 +2584,8 @@ bool intel_dp_initial_fastset_check(struct
> > intel_encoder *encoder,
> > fastset = false;
> > }
> >
> > - if (CAN_PSR(intel_dp)) {
> > - drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> > modeset to compute PSR state\n",
> > + if (CAN_PSR(intel_dp) && psr2_global_enabled(intel_dp)) {
> > + drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Forcing full
> > modeset due to PSR2\n",
> > encoder->base.base.id, encoder-
> > >base.name);
> > crtc_state->uapi.mode_changed = true;
> > fastset = false;
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.c
> > b/drivers/gpu/drm/i915/display/intel_psr.c
> > index 97d5eef10130..388bc3246db9 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.c
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.c
> > @@ -187,7 +187,7 @@ static bool psr_global_enabled(struct intel_dp
> > *intel_dp)
> > }
> > }
> >
> > -static bool psr2_global_enabled(struct intel_dp *intel_dp)
> > +bool psr2_global_enabled(struct intel_dp *intel_dp)
> > {
> > struct drm_i915_private *i915 = dp_to_i915(intel_dp);
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_psr.h
> > b/drivers/gpu/drm/i915/display/intel_psr.h
> > index 0b95e8aa615f..6f3c36389cd3 100644
> > --- a/drivers/gpu/drm/i915/display/intel_psr.h
> > +++ b/drivers/gpu/drm/i915/display/intel_psr.h
> > @@ -21,6 +21,7 @@ struct intel_encoder;
> > struct intel_plane;
> > struct intel_plane_state;
> >
> > +bool psr2_global_enabled(struct intel_dp *intel_dp);
> > void intel_psr_init_dpcd(struct intel_dp *intel_dp);
> > void intel_psr_pre_plane_update(struct intel_atomic_state *state,
> > struct intel_crtc *crtc);
>
.
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-11-02 8:35 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-10-31 23:21 [Intel-gfx] [PATCH] drm/i915/display: Only fail fastset on PSR2 Paz Zcharya
2023-10-31 23:21 ` Paz Zcharya
2023-10-31 23:21 ` Paz Zcharya
2023-11-01 0:04 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2023-11-01 0:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2023-11-01 6:26 ` [Intel-gfx] [PATCH] " Hogander, Jouni
2023-11-01 6:26 ` Hogander, Jouni
2023-11-01 6:26 ` Hogander, Jouni
2023-11-01 15:45 ` [Intel-gfx] " Paz Zcharya
2023-11-01 15:45 ` Paz Zcharya
2023-11-01 15:45 ` Paz Zcharya
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