From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>
Subject: Re: [Intel-gfx] [PATCH 2/4] drm/i915: Adjust LUT rounding rules
Date: Mon, 20 Nov 2023 16:26:38 +0200 [thread overview]
Message-ID: <ZVtsnsLQ22ImaiFz@intel.com> (raw)
In-Reply-To: <SJ1PR11MB612921FEBAC75CFA6407F14CB9B4A@SJ1PR11MB6129.namprd11.prod.outlook.com>
On Mon, Nov 20, 2023 at 06:08:57AM +0000, Borah, Chaitanya Kumar wrote:
> Hello Ville,
>
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Friday, October 13, 2023 6:44 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org
> > Subject: [PATCH 2/4] drm/i915: Adjust LUT rounding rules
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > drm_color_lut_extract() rounding was changed to follow the OpenGL int<-
> > >float conversion rules. Adjust intel_color_lut_pack() to match.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 14 ++++++--------
> > 1 file changed, 6 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 2a2a163ea652..b01f463af861 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -785,14 +785,12 @@ static void chv_assign_csc(struct intel_crtc_state
> > *crtc_state)
> > /* convert hw value with given bit_precision to lut property val */ static u32
> > intel_color_lut_pack(u32 val, int bit_precision) {
>
> Is this operation unique to Intel. Should there be a drm helper for this?
If some other driver gains gamma readout support they
could probably use something like this. The other option
would be to rework the current helper to allow conversions
both ways.
>
> Regards
>
> Chaitanya
>
> > - u32 max = 0xffff >> (16 - bit_precision);
> > -
> > - val = clamp_val(val, 0, max);
> > -
> > - if (bit_precision < 16)
> > - val <<= 16 - bit_precision;
> > -
> > - return val;
> > + if (bit_precision > 16)
> > + return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(val, (1 << 16)
> > - 1),
> > + (1 << bit_precision) - 1);
> > + else
> > + return DIV_ROUND_CLOSEST(val * ((1 << 16) - 1),
> > + (1 << bit_precision) - 1);
> > }
> >
> > static u32 i9xx_lut_8(const struct drm_color_lut *color)
> > --
> > 2.41.0
>
--
Ville Syrjälä
Intel
WARNING: multiple messages have this Message-ID (diff)
From: "Ville Syrjälä" <ville.syrjala@linux.intel.com>
To: "Borah, Chaitanya Kumar" <chaitanya.kumar.borah@intel.com>
Cc: "intel-gfx@lists.freedesktop.org"
<intel-gfx@lists.freedesktop.org>,
"dri-devel@lists.freedesktop.org"
<dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH 2/4] drm/i915: Adjust LUT rounding rules
Date: Mon, 20 Nov 2023 16:26:38 +0200 [thread overview]
Message-ID: <ZVtsnsLQ22ImaiFz@intel.com> (raw)
In-Reply-To: <SJ1PR11MB612921FEBAC75CFA6407F14CB9B4A@SJ1PR11MB6129.namprd11.prod.outlook.com>
On Mon, Nov 20, 2023 at 06:08:57AM +0000, Borah, Chaitanya Kumar wrote:
> Hello Ville,
>
> > -----Original Message-----
> > From: dri-devel <dri-devel-bounces@lists.freedesktop.org> On Behalf Of Ville
> > Syrjala
> > Sent: Friday, October 13, 2023 6:44 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: dri-devel@lists.freedesktop.org
> > Subject: [PATCH 2/4] drm/i915: Adjust LUT rounding rules
> >
> > From: Ville Syrjälä <ville.syrjala@linux.intel.com>
> >
> > drm_color_lut_extract() rounding was changed to follow the OpenGL int<-
> > >float conversion rules. Adjust intel_color_lut_pack() to match.
> >
> > Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
> > ---
> > drivers/gpu/drm/i915/display/intel_color.c | 14 ++++++--------
> > 1 file changed, 6 insertions(+), 8 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/i915/display/intel_color.c
> > b/drivers/gpu/drm/i915/display/intel_color.c
> > index 2a2a163ea652..b01f463af861 100644
> > --- a/drivers/gpu/drm/i915/display/intel_color.c
> > +++ b/drivers/gpu/drm/i915/display/intel_color.c
> > @@ -785,14 +785,12 @@ static void chv_assign_csc(struct intel_crtc_state
> > *crtc_state)
> > /* convert hw value with given bit_precision to lut property val */ static u32
> > intel_color_lut_pack(u32 val, int bit_precision) {
>
> Is this operation unique to Intel. Should there be a drm helper for this?
If some other driver gains gamma readout support they
could probably use something like this. The other option
would be to rework the current helper to allow conversions
both ways.
>
> Regards
>
> Chaitanya
>
> > - u32 max = 0xffff >> (16 - bit_precision);
> > -
> > - val = clamp_val(val, 0, max);
> > -
> > - if (bit_precision < 16)
> > - val <<= 16 - bit_precision;
> > -
> > - return val;
> > + if (bit_precision > 16)
> > + return DIV_ROUND_CLOSEST_ULL(mul_u32_u32(val, (1 << 16)
> > - 1),
> > + (1 << bit_precision) - 1);
> > + else
> > + return DIV_ROUND_CLOSEST(val * ((1 << 16) - 1),
> > + (1 << bit_precision) - 1);
> > }
> >
> > static u32 i9xx_lut_8(const struct drm_color_lut *color)
> > --
> > 2.41.0
>
--
Ville Syrjälä
Intel
next prev parent reply other threads:[~2023-11-20 14:26 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-13 13:13 [Intel-gfx] [PATCH 0/4] drm/i915: Fix LUT rounding Ville Syrjala
2023-10-13 13:13 ` Ville Syrjala
2023-10-13 13:13 ` [Intel-gfx] [PATCH 1/4] drm: Fix color " Ville Syrjala
2023-10-13 13:13 ` Ville Syrjala
2023-10-31 9:15 ` [Intel-gfx] " Jani Nikula
2023-10-31 16:06 ` Ville Syrjälä
2023-11-20 13:03 ` Borah, Chaitanya Kumar
2023-11-20 13:03 ` Borah, Chaitanya Kumar
2023-11-20 13:17 ` Borah, Chaitanya Kumar
2023-11-20 13:17 ` Borah, Chaitanya Kumar
2023-11-20 14:27 ` Ville Syrjälä
2023-10-13 13:14 ` [Intel-gfx] [PATCH 2/4] drm/i915: Adjust LUT rounding rules Ville Syrjala
2023-10-13 13:14 ` Ville Syrjala
2023-11-20 6:08 ` [Intel-gfx] " Borah, Chaitanya Kumar
2023-11-20 6:08 ` Borah, Chaitanya Kumar
2023-11-20 14:26 ` Ville Syrjälä [this message]
2023-11-20 14:26 ` Ville Syrjälä
2023-11-21 6:15 ` [Intel-gfx] " Borah, Chaitanya Kumar
2023-11-21 6:15 ` Borah, Chaitanya Kumar
2023-10-13 13:14 ` [Intel-gfx] [PATCH 3/4] drm/i915: s/clamp()/min()/ in i965_lut_11p6_max_pack() Ville Syrjala
2023-10-13 13:14 ` Ville Syrjala
2023-11-03 4:39 ` [Intel-gfx] " Borah, Chaitanya Kumar
2023-11-03 4:39 ` Borah, Chaitanya Kumar
2023-10-13 13:14 ` [Intel-gfx] [PATCH 4/4] drm/i915: Fix glk+ degamma LUT conversions Ville Syrjala
2023-10-13 13:14 ` Ville Syrjala
2023-11-20 6:13 ` [Intel-gfx] " Borah, Chaitanya Kumar
2023-11-20 6:13 ` Borah, Chaitanya Kumar
2023-10-13 20:27 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix LUT rounding Patchwork
2023-10-13 20:27 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
2023-10-13 20:41 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-10-15 1:55 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-11-13 17:37 ` [Intel-gfx] [PATCH 0/4] " Jani Nikula
2023-11-20 14:30 ` Ville Syrjälä
2023-11-20 14:30 ` Ville Syrjälä
2023-11-21 10:51 ` [Intel-gfx] " Maxime Ripard
2023-11-21 10:51 ` Maxime Ripard
2023-11-23 17:35 ` [Intel-gfx] " Ville Syrjälä
2023-11-23 17:35 ` Ville Syrjälä
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