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* [Intel-gfx] [PATCH 0/8] drm/i915: cdclk/voltage_level cleanups and fixes
@ 2023-11-28 11:51 Ville Syrjala
  2023-11-28 11:51 ` [Intel-gfx] [PATCH 1/8] drm/i915/cdclk: s/-1/~0/ when dealing with unsigned values Ville Syrjala
                   ` (14 more replies)
  0 siblings, 15 replies; 29+ messages in thread
From: Ville Syrjala @ 2023-11-28 11:51 UTC (permalink / raw)
  To: intel-gfx

From: Ville Syrjälä <ville.syrjala@linux.intel.com>

A bit of refactoring around the cdclk/voltage_level stuff.

I also spotted that we were miscalculating the voltage level
on MTL in two different places, so included fixes (or rather
power optimizations) for those.

Ville Syrjälä (8):
  drm/i915/cdclk: s/-1/~0/ when dealing with unsigned values
  drm/i915/cdclk: Give the squash waveform length a name
  drm/i915/cdclk: Remove the assumption that cd2x div==2 when using
    squashing
  drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tables
  drm/i915/mtl: Fix voltage_level for cdclk==480MHz
  drm/i915: Split intel_ddi_compute_min_voltage_level() into platform
    variants
  drm/i915/mtl: Calculate the correct voltage level from port_clock
  drm/i915: Simplify intel_ddi_compute_min_voltage_level()

 drivers/gpu/drm/i915/display/intel_cdclk.c  | 101 ++++++++++++--------
 drivers/gpu/drm/i915/display/intel_ddi.c    |  50 +++++++---
 drivers/gpu/drm/i915/display/intel_ddi.h    |   3 +-
 drivers/gpu/drm/i915/display/intel_dp_mst.c |   2 +-
 4 files changed, 102 insertions(+), 54 deletions(-)

-- 
2.41.0


^ permalink raw reply	[flat|nested] 29+ messages in thread

end of thread, other threads:[~2023-12-12  0:36 UTC | newest]

Thread overview: 29+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-11-28 11:51 [Intel-gfx] [PATCH 0/8] drm/i915: cdclk/voltage_level cleanups and fixes Ville Syrjala
2023-11-28 11:51 ` [Intel-gfx] [PATCH 1/8] drm/i915/cdclk: s/-1/~0/ when dealing with unsigned values Ville Syrjala
2023-12-01 19:54   ` Gustavo Sousa
2023-11-28 11:51 ` [Intel-gfx] [PATCH 2/8] drm/i915/cdclk: Give the squash waveform length a name Ville Syrjala
2023-12-01 19:56   ` Gustavo Sousa
2023-11-28 11:51 ` [Intel-gfx] [PATCH 3/8] drm/i915/cdclk: Remove the assumption that cd2x div==2 when using squashing Ville Syrjala
2023-12-01 20:13   ` Gustavo Sousa
2023-12-04 20:05     ` Ville Syrjälä
2023-12-04 20:46       ` Gustavo Sousa
2023-12-05 14:50         ` Ville Syrjälä
2023-12-11 22:16   ` [PATCH v2 3/8] drm/i915/cdclk: Remove the assumption that cdclk divider==2 " Ville Syrjala
2023-11-28 11:51 ` [Intel-gfx] [PATCH 4/8] drm/i915/cdclk: Rewrite cdclk->voltage_level selection to use tables Ville Syrjala
2023-12-01 21:25   ` Gustavo Sousa
2023-12-11 22:17   ` [PATCH v2 " Ville Syrjala
2023-11-28 11:51 ` [Intel-gfx] [PATCH 5/8] drm/i915/mtl: Fix voltage_level for cdclk==480MHz Ville Syrjala
2023-12-01 21:29   ` Gustavo Sousa
2023-11-28 11:51 ` [Intel-gfx] [PATCH 6/8] drm/i915: Split intel_ddi_compute_min_voltage_level() into platform variants Ville Syrjala
2023-12-01 21:37   ` Gustavo Sousa
2023-11-28 11:51 ` [Intel-gfx] [PATCH 7/8] drm/i915/mtl: Calculate the correct voltage level from port_clock Ville Syrjala
2023-12-01 21:39   ` Gustavo Sousa
2023-11-28 11:51 ` [Intel-gfx] [PATCH 8/8] drm/i915: Simplify intel_ddi_compute_min_voltage_level() Ville Syrjala
2023-12-01 21:44   ` Gustavo Sousa
2023-11-29  0:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: cdclk/voltage_level cleanups and fixes Patchwork
2023-11-29  1:06 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2023-11-29  7:28 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2023-12-11 23:30 ` ✗ Fi.CI.CHECKPATCH: warning for drm/i915: cdclk/voltage_level cleanups and fixes (rev3) Patchwork
2023-12-11 23:30 ` ✗ Fi.CI.SPARSE: " Patchwork
2023-12-11 23:37 ` ✓ Fi.CI.BAT: success " Patchwork
2023-12-12  0:36 ` ✗ Fi.CI.IGT: failure " Patchwork

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