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From: Leo Liang <ycliang@andestech.com>
To: <trini@konsulko.com>
Cc: <u-boot@lists.denx.de>, <rick@andestech.com>, <ycliang@andestech.com>
Subject: [GIT PULL] u-boot-riscv/next
Date: Thu, 28 Dec 2023 13:38:11 +0800	[thread overview]
Message-ID: <ZY0Jwxaqw6bGOvBI@swlinux02> (raw)

Hi Tom,

The following changes since commit 4b151562bb8e54160adedbc6a1c0c749c00a2f84:

  bootmeth: pass size to efi_binary_run() (2023-12-22 10:36:50 -0500)

are available in the Git repository at:

  https://source.denx.de/u-boot/custodians/u-boot-riscv.git next

for you to fetch changes up to 9924d44dbcd47bd3664fa9f1f9f24044d83eaebf:

  andes: ae350: Enable MISC_INIT_R for ae350 platform (2023-12-27 17:29:11 +0800)

CI result shows no issue: https://source.denx.de/u-boot/custodians/u-boot-riscv/-/pipelines/19106
----------------------------------------------------------------
- Andes: Enable Andes CPU memboost and ECC feature by default 
- Sifive: Add private L2 cache driver
----------------------------------------------------------------
Leo Yu-Chi Liang (6):
      andes: csr.h: Clean up CSR definition
      andes: ae350: Implement cache switch via Kconfig
      andes: cpu: Enable memboost feature
      andes: cpu: Enable cache and TLB ECC support
      andes: ae350: Save cpu name to env
      andes: ae350: Enable MISC_INIT_R for ae350 platform

Michal Simek (1):
      riscv: Extend board compatible string with "qemu,mbv"

Zong Li (2):
      cache: add sifive private L2 cache driver
      riscv: cache: support cache enable in SPL stage

 arch/riscv/cpu/andesv5/cpu.c            | 33 ++++++++++++++++++-------
 arch/riscv/dts/xilinx-mbv32.dts         |  2 +-
 arch/riscv/include/asm/arch-andes/csr.h | 29 +++++++++++++---------
 arch/riscv/include/asm/csr.h            |  1 +
 arch/riscv/lib/sifive_cache.c           | 21 ++++++++++++++++
 board/AndesTech/ae350/ae350.c           | 26 ++++++++++++++++++-
 configs/ae350_rv32_defconfig            |  5 ++--
 configs/ae350_rv32_spl_defconfig        |  5 ++--
 configs/ae350_rv32_spl_xip_defconfig    |  5 ++--
 configs/ae350_rv32_xip_defconfig        |  5 ++--
 configs/ae350_rv64_defconfig            |  5 ++--
 configs/ae350_rv64_spl_defconfig        |  5 ++--
 configs/ae350_rv64_spl_xip_defconfig    |  5 ++--
 configs/ae350_rv64_xip_defconfig        |  5 ++--
 drivers/cache/Kconfig                   |  7 ++++++
 drivers/cache/Makefile                  |  1 +
 drivers/cache/cache-sifive-pl2.c        | 44 +++++++++++++++++++++++++++++++++
 17 files changed, 165 insertions(+), 39 deletions(-)
 create mode 100644 drivers/cache/cache-sifive-pl2.c

Best regards,
Leo

             reply	other threads:[~2023-12-28  5:38 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-12-28  5:38 Leo Liang [this message]
2023-12-28 16:55 ` [GIT PULL] u-boot-riscv/next Tom Rini
  -- strict thread matches above, loose matches on Subject: below --
2026-03-17  6:01 Leo Yu-Chi Liang
2026-03-18 17:05 ` Tom Rini
2026-03-23 19:20 ` E Shattow
2026-03-23 20:07   ` Tom Rini
2026-03-13  2:06 [GIT,PULL] u-boot-riscv/next Leo Liang
2026-03-13 16:52 ` Tom Rini
2026-03-13 22:59   ` E Shattow
2026-03-16 12:23     ` Leo Liang
2025-12-08  6:19 [GIT PULL] u-boot-riscv/next Leo Liang
2025-12-08 22:09 ` Tom Rini
2025-09-20 10:20 [GIT,PULL] u-boot-riscv/next Leo Liang
2025-09-20 17:47 ` Tom Rini
2025-09-25  2:07   ` E Shattow
2025-09-25  3:39     ` E Shattow
2025-09-25  4:57       ` Yao Zi
2025-09-25  6:36         ` E Shattow
2025-07-03 14:09 [GIT PULL] u-boot-riscv/next Leo Liang
2025-07-03 16:29 ` Tom Rini
2025-03-25 10:55 Leo Liang
2025-03-25 20:17 ` Tom Rini
2024-12-18  7:49 Leo Liang
2024-12-18 17:40 ` Tom Rini
2024-10-28 12:25 Leo Liang
2024-10-28 15:20 ` Tom Rini
2024-10-29  9:35   ` Leo Liang
2024-10-29 13:01     ` Michal Simek
2023-12-18 11:44 Leo Liang
2023-12-18 16:59 ` Tom Rini

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